1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 27 #include "dm_services.h" 28 #include "dm_helpers.h" 29 #include "core_types.h" 30 #include "resource.h" 31 #include "dccg.h" 32 #include "dce/dce_hwseq.h" 33 #include "clk_mgr.h" 34 #include "reg_helper.h" 35 #include "abm.h" 36 #include "hubp.h" 37 #include "dchubbub.h" 38 #include "timing_generator.h" 39 #include "opp.h" 40 #include "ipp.h" 41 #include "mpc.h" 42 #include "mcif_wb.h" 43 #include "dc_dmub_srv.h" 44 #include "dcn31_hwseq.h" 45 #include "link_hwss.h" 46 #include "dpcd_defs.h" 47 #include "dce/dmub_outbox.h" 48 #include "dc_link_dp.h" 49 #include "inc/link_dpcd.h" 50 #include "dcn10/dcn10_hw_sequencer.h" 51 #include "inc/link_enc_cfg.h" 52 #include "dcn30/dcn30_vpg.h" 53 #include "dce/dce_i2c_hw.h" 54 55 #define DC_LOGGER_INIT(logger) 56 57 #define CTX \ 58 hws->ctx 59 #define REG(reg)\ 60 hws->regs->reg 61 #define DC_LOGGER \ 62 dc->ctx->logger 63 64 65 #undef FN 66 #define FN(reg_name, field_name) \ 67 hws->shifts->field_name, hws->masks->field_name 68 69 static void enable_memory_low_power(struct dc *dc) 70 { 71 struct dce_hwseq *hws = dc->hwseq; 72 int i; 73 74 if (dc->debug.enable_mem_low_power.bits.dmcu) { 75 // Force ERAM to shutdown if DMCU is not enabled 76 if (dc->debug.disable_dmcu || dc->config.disable_dmcu) { 77 REG_UPDATE(DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, 3); 78 } 79 } 80 81 // Set default OPTC memory power states 82 if (dc->debug.enable_mem_low_power.bits.optc) { 83 // Shutdown when unassigned and light sleep in VBLANK 84 REG_SET_2(ODM_MEM_PWR_CTRL3, 0, ODM_MEM_UNASSIGNED_PWR_MODE, 3, ODM_MEM_VBLANK_PWR_MODE, 1); 85 } 86 87 if (dc->debug.enable_mem_low_power.bits.vga) { 88 // Power down VGA memory 89 REG_UPDATE(MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, 1); 90 } 91 92 if (dc->debug.enable_mem_low_power.bits.mpc) 93 dc->res_pool->mpc->funcs->set_mpc_mem_lp_mode(dc->res_pool->mpc); 94 95 96 if (dc->debug.enable_mem_low_power.bits.vpg && dc->res_pool->stream_enc[0]->vpg->funcs->vpg_powerdown) { 97 // Power down VPGs 98 for (i = 0; i < dc->res_pool->stream_enc_count; i++) 99 dc->res_pool->stream_enc[i]->vpg->funcs->vpg_powerdown(dc->res_pool->stream_enc[i]->vpg); 100 #if defined(CONFIG_DRM_AMD_DC_DCN) 101 for (i = 0; i < dc->res_pool->hpo_dp_stream_enc_count; i++) 102 dc->res_pool->hpo_dp_stream_enc[i]->vpg->funcs->vpg_powerdown(dc->res_pool->hpo_dp_stream_enc[i]->vpg); 103 #endif 104 } 105 106 } 107 108 void dcn31_init_hw(struct dc *dc) 109 { 110 struct abm **abms = dc->res_pool->multiple_abms; 111 struct dce_hwseq *hws = dc->hwseq; 112 struct dc_bios *dcb = dc->ctx->dc_bios; 113 struct resource_pool *res_pool = dc->res_pool; 114 uint32_t backlight = MAX_BACKLIGHT_LEVEL; 115 int i; 116 117 if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks) 118 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr); 119 120 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { 121 122 REG_WRITE(REFCLK_CNTL, 0); 123 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1); 124 REG_WRITE(DIO_MEM_PWR_CTRL, 0); 125 126 if (!dc->debug.disable_clock_gate) { 127 /* enable all DCN clock gating */ 128 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); 129 130 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); 131 132 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); 133 } 134 135 //Enable ability to power gate / don't force power on permanently 136 if (hws->funcs.enable_power_gating_plane) 137 hws->funcs.enable_power_gating_plane(hws, true); 138 139 return; 140 } 141 142 if (!dcb->funcs->is_accelerated_mode(dcb)) { 143 hws->funcs.bios_golden_init(dc); 144 hws->funcs.disable_vga(dc->hwseq); 145 } 146 // Initialize the dccg 147 if (res_pool->dccg->funcs->dccg_init) 148 res_pool->dccg->funcs->dccg_init(res_pool->dccg); 149 150 enable_memory_low_power(dc); 151 152 if (dc->ctx->dc_bios->fw_info_valid) { 153 res_pool->ref_clocks.xtalin_clock_inKhz = 154 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency; 155 156 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { 157 if (res_pool->dccg && res_pool->hubbub) { 158 159 (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg, 160 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency, 161 &res_pool->ref_clocks.dccg_ref_clock_inKhz); 162 163 (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub, 164 res_pool->ref_clocks.dccg_ref_clock_inKhz, 165 &res_pool->ref_clocks.dchub_ref_clock_inKhz); 166 } else { 167 // Not all ASICs have DCCG sw component 168 res_pool->ref_clocks.dccg_ref_clock_inKhz = 169 res_pool->ref_clocks.xtalin_clock_inKhz; 170 res_pool->ref_clocks.dchub_ref_clock_inKhz = 171 res_pool->ref_clocks.xtalin_clock_inKhz; 172 } 173 } 174 } else 175 ASSERT_CRITICAL(false); 176 177 for (i = 0; i < dc->link_count; i++) { 178 /* Power up AND update implementation according to the 179 * required signal (which may be different from the 180 * default signal on connector). 181 */ 182 struct dc_link *link = dc->links[i]; 183 184 if (link->ep_type != DISPLAY_ENDPOINT_PHY) 185 continue; 186 187 link->link_enc->funcs->hw_init(link->link_enc); 188 189 /* Check for enabled DIG to identify enabled display */ 190 if (link->link_enc->funcs->is_dig_enabled && 191 link->link_enc->funcs->is_dig_enabled(link->link_enc)) 192 link->link_status.link_active = true; 193 } 194 195 /* Enables outbox notifications for usb4 dpia */ 196 if (dc->res_pool->usb4_dpia_count) 197 dmub_enable_outbox_notification(dc->ctx->dmub_srv); 198 199 /* we want to turn off all dp displays before doing detection */ 200 dc_link_blank_all_dp_displays(dc); 201 202 /* If taking control over from VBIOS, we may want to optimize our first 203 * mode set, so we need to skip powering down pipes until we know which 204 * pipes we want to use. 205 * Otherwise, if taking control is not possible, we need to power 206 * everything down. 207 */ 208 if (dcb->funcs->is_accelerated_mode(dcb) || !dc->config.seamless_boot_edp_requested) { 209 hws->funcs.init_pipes(dc, dc->current_state); 210 if (dc->res_pool->hubbub->funcs->allow_self_refresh_control) 211 dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, 212 !dc->res_pool->hubbub->ctx->dc->debug.disable_stutter); 213 } 214 215 for (i = 0; i < res_pool->audio_count; i++) { 216 struct audio *audio = res_pool->audios[i]; 217 218 audio->funcs->hw_init(audio); 219 } 220 221 for (i = 0; i < dc->link_count; i++) { 222 struct dc_link *link = dc->links[i]; 223 224 if (link->panel_cntl) 225 backlight = link->panel_cntl->funcs->hw_init(link->panel_cntl); 226 } 227 228 for (i = 0; i < dc->res_pool->pipe_count; i++) { 229 if (abms[i] != NULL) 230 abms[i]->funcs->abm_init(abms[i], backlight); 231 } 232 233 /* power AFMT HDMI memory TODO: may move to dis/en output save power*/ 234 REG_WRITE(DIO_MEM_PWR_CTRL, 0); 235 236 // Set i2c to light sleep until engine is setup 237 if (dc->debug.enable_mem_low_power.bits.i2c) 238 REG_UPDATE(DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, 1); 239 240 if (hws->funcs.setup_hpo_hw_control) 241 hws->funcs.setup_hpo_hw_control(hws, false); 242 243 if (!dc->debug.disable_clock_gate) { 244 /* enable all DCN clock gating */ 245 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); 246 247 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); 248 249 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); 250 } 251 if (hws->funcs.enable_power_gating_plane) 252 hws->funcs.enable_power_gating_plane(dc->hwseq, true); 253 254 if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks) 255 dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub); 256 257 if (dc->clk_mgr->funcs->notify_wm_ranges) 258 dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr); 259 260 if (dc->clk_mgr->funcs->set_hard_max_memclk) 261 dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr); 262 263 if (dc->res_pool->hubbub->funcs->force_pstate_change_control) 264 dc->res_pool->hubbub->funcs->force_pstate_change_control( 265 dc->res_pool->hubbub, false, false); 266 #if defined(CONFIG_DRM_AMD_DC_DCN) 267 if (dc->res_pool->hubbub->funcs->init_crb) 268 dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub); 269 #endif 270 } 271 272 void dcn31_dsc_pg_control( 273 struct dce_hwseq *hws, 274 unsigned int dsc_inst, 275 bool power_on) 276 { 277 uint32_t power_gate = power_on ? 0 : 1; 278 uint32_t pwr_status = power_on ? 0 : 2; 279 uint32_t org_ip_request_cntl = 0; 280 281 if (hws->ctx->dc->debug.disable_dsc_power_gate) 282 return; 283 284 if (hws->ctx->dc->debug.root_clock_optimization.bits.dsc && 285 hws->ctx->dc->res_pool->dccg->funcs->enable_dsc && 286 power_on) 287 hws->ctx->dc->res_pool->dccg->funcs->enable_dsc( 288 hws->ctx->dc->res_pool->dccg, dsc_inst); 289 290 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); 291 if (org_ip_request_cntl == 0) 292 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); 293 294 switch (dsc_inst) { 295 case 0: /* DSC0 */ 296 REG_UPDATE(DOMAIN16_PG_CONFIG, 297 DOMAIN_POWER_GATE, power_gate); 298 299 REG_WAIT(DOMAIN16_PG_STATUS, 300 DOMAIN_PGFSM_PWR_STATUS, pwr_status, 301 1, 1000); 302 break; 303 case 1: /* DSC1 */ 304 REG_UPDATE(DOMAIN17_PG_CONFIG, 305 DOMAIN_POWER_GATE, power_gate); 306 307 REG_WAIT(DOMAIN17_PG_STATUS, 308 DOMAIN_PGFSM_PWR_STATUS, pwr_status, 309 1, 1000); 310 break; 311 case 2: /* DSC2 */ 312 REG_UPDATE(DOMAIN18_PG_CONFIG, 313 DOMAIN_POWER_GATE, power_gate); 314 315 REG_WAIT(DOMAIN18_PG_STATUS, 316 DOMAIN_PGFSM_PWR_STATUS, pwr_status, 317 1, 1000); 318 break; 319 default: 320 BREAK_TO_DEBUGGER(); 321 break; 322 } 323 324 if (org_ip_request_cntl == 0) 325 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); 326 327 if (hws->ctx->dc->debug.root_clock_optimization.bits.dsc) { 328 if (hws->ctx->dc->res_pool->dccg->funcs->disable_dsc && !power_on) 329 hws->ctx->dc->res_pool->dccg->funcs->disable_dsc( 330 hws->ctx->dc->res_pool->dccg, dsc_inst); 331 } 332 333 } 334 335 336 void dcn31_enable_power_gating_plane( 337 struct dce_hwseq *hws, 338 bool enable) 339 { 340 bool force_on = true; /* disable power gating */ 341 342 if (enable && !hws->ctx->dc->debug.disable_hubp_power_gate) 343 force_on = false; 344 345 /* DCHUBP0/1/2/3/4/5 */ 346 REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 347 REG_WAIT(DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, force_on, 1, 1000); 348 REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 349 REG_WAIT(DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, force_on, 1, 1000); 350 /* DPP0/1/2/3/4/5 */ 351 REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 352 REG_WAIT(DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, force_on, 1, 1000); 353 REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 354 REG_WAIT(DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, force_on, 1, 1000); 355 356 force_on = true; /* disable power gating */ 357 if (enable && !hws->ctx->dc->debug.disable_dsc_power_gate) 358 force_on = false; 359 360 /* DCS0/1/2/3/4/5 */ 361 REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 362 REG_WAIT(DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, force_on, 1, 1000); 363 REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 364 REG_WAIT(DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, force_on, 1, 1000); 365 REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 366 REG_WAIT(DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, force_on, 1, 1000); 367 } 368 369 void dcn31_update_info_frame(struct pipe_ctx *pipe_ctx) 370 { 371 bool is_hdmi_tmds; 372 bool is_dp; 373 374 ASSERT(pipe_ctx->stream); 375 376 if (pipe_ctx->stream_res.stream_enc == NULL) 377 return; /* this is not root pipe */ 378 379 is_hdmi_tmds = dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal); 380 is_dp = dc_is_dp_signal(pipe_ctx->stream->signal); 381 382 if (!is_hdmi_tmds && !is_dp) 383 return; 384 385 if (is_hdmi_tmds) 386 pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets( 387 pipe_ctx->stream_res.stream_enc, 388 &pipe_ctx->stream_res.encoder_info_frame); 389 else { 390 pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets( 391 pipe_ctx->stream_res.stream_enc, 392 &pipe_ctx->stream_res.encoder_info_frame); 393 } 394 } 395 void dcn31_z10_save_init(struct dc *dc) 396 { 397 union dmub_rb_cmd cmd; 398 399 memset(&cmd, 0, sizeof(cmd)); 400 cmd.dcn_restore.header.type = DMUB_CMD__IDLE_OPT; 401 cmd.dcn_restore.header.sub_type = DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT; 402 403 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd); 404 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv); 405 dc_dmub_srv_wait_idle(dc->ctx->dmub_srv); 406 } 407 408 void dcn31_z10_restore(const struct dc *dc) 409 { 410 union dmub_rb_cmd cmd; 411 412 /* 413 * DMUB notifies whether restore is required. 414 * Optimization to avoid sending commands when not required. 415 */ 416 if (!dc_dmub_srv_is_restore_required(dc->ctx->dmub_srv)) 417 return; 418 419 memset(&cmd, 0, sizeof(cmd)); 420 cmd.dcn_restore.header.type = DMUB_CMD__IDLE_OPT; 421 cmd.dcn_restore.header.sub_type = DMUB_CMD__IDLE_OPT_DCN_RESTORE; 422 423 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd); 424 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv); 425 dc_dmub_srv_wait_idle(dc->ctx->dmub_srv); 426 } 427 428 void dcn31_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on) 429 { 430 uint32_t power_gate = power_on ? 0 : 1; 431 uint32_t pwr_status = power_on ? 0 : 2; 432 uint32_t org_ip_request_cntl; 433 if (hws->ctx->dc->debug.disable_hubp_power_gate) 434 return; 435 436 if (REG(DOMAIN0_PG_CONFIG) == 0) 437 return; 438 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); 439 if (org_ip_request_cntl == 0) 440 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); 441 442 switch (hubp_inst) { 443 case 0: 444 REG_SET(DOMAIN0_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 445 REG_WAIT(DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 446 break; 447 case 1: 448 REG_SET(DOMAIN1_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 449 REG_WAIT(DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 450 break; 451 case 2: 452 REG_SET(DOMAIN2_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 453 REG_WAIT(DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 454 break; 455 case 3: 456 REG_SET(DOMAIN3_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 457 REG_WAIT(DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 458 break; 459 default: 460 BREAK_TO_DEBUGGER(); 461 break; 462 } 463 if (org_ip_request_cntl == 0) 464 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); 465 } 466 467 int dcn31_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config) 468 { 469 struct dcn_hubbub_phys_addr_config config; 470 471 config.system_aperture.fb_top = pa_config->system_aperture.fb_top; 472 config.system_aperture.fb_offset = pa_config->system_aperture.fb_offset; 473 config.system_aperture.fb_base = pa_config->system_aperture.fb_base; 474 config.system_aperture.agp_top = pa_config->system_aperture.agp_top; 475 config.system_aperture.agp_bot = pa_config->system_aperture.agp_bot; 476 config.system_aperture.agp_base = pa_config->system_aperture.agp_base; 477 config.gart_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr; 478 config.gart_config.page_table_end_addr = pa_config->gart_config.page_table_end_addr; 479 480 if (pa_config->gart_config.base_addr_is_mc_addr) { 481 /* Convert from MC address to offset into FB */ 482 config.gart_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr - 483 pa_config->system_aperture.fb_base + 484 pa_config->system_aperture.fb_offset; 485 } else 486 config.gart_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr; 487 488 return dc->res_pool->hubbub->funcs->init_dchub_sys_ctx(dc->res_pool->hubbub, &config); 489 } 490 491 static void dcn31_reset_back_end_for_pipe( 492 struct dc *dc, 493 struct pipe_ctx *pipe_ctx, 494 struct dc_state *context) 495 { 496 struct dc_link *link; 497 498 DC_LOGGER_INIT(dc->ctx->logger); 499 if (pipe_ctx->stream_res.stream_enc == NULL) { 500 pipe_ctx->stream = NULL; 501 return; 502 } 503 ASSERT(!pipe_ctx->top_pipe); 504 505 dc->hwss.set_abm_immediate_disable(pipe_ctx); 506 507 pipe_ctx->stream_res.tg->funcs->set_dsc_config( 508 pipe_ctx->stream_res.tg, 509 OPTC_DSC_DISABLED, 0, 0); 510 pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg); 511 512 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false); 513 if (pipe_ctx->stream_res.tg->funcs->set_odm_bypass) 514 pipe_ctx->stream_res.tg->funcs->set_odm_bypass( 515 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); 516 517 if (pipe_ctx->stream_res.tg->funcs->set_drr) 518 pipe_ctx->stream_res.tg->funcs->set_drr( 519 pipe_ctx->stream_res.tg, NULL); 520 521 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { 522 link = pipe_ctx->stream->link; 523 /* DPMS may already disable or */ 524 /* dpms_off status is incorrect due to fastboot 525 * feature. When system resume from S4 with second 526 * screen only, the dpms_off would be true but 527 * VBIOS lit up eDP, so check link status too. 528 */ 529 if (!pipe_ctx->stream->dpms_off || link->link_status.link_active) 530 core_link_disable_stream(pipe_ctx); 531 else if (pipe_ctx->stream_res.audio) 532 dc->hwss.disable_audio_stream(pipe_ctx); 533 534 /* free acquired resources */ 535 if (pipe_ctx->stream_res.audio) { 536 /*disable az_endpoint*/ 537 pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio); 538 539 /*free audio*/ 540 if (dc->caps.dynamic_audio == true) { 541 /*we have to dynamic arbitrate the audio endpoints*/ 542 /*we free the resource, need reset is_audio_acquired*/ 543 update_audio_usage(&dc->current_state->res_ctx, dc->res_pool, 544 pipe_ctx->stream_res.audio, false); 545 pipe_ctx->stream_res.audio = NULL; 546 } 547 } 548 } else if (pipe_ctx->stream_res.dsc) { 549 dp_set_dsc_enable(pipe_ctx, false); 550 } 551 552 pipe_ctx->stream = NULL; 553 DC_LOG_DEBUG("Reset back end for pipe %d, tg:%d\n", 554 pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst); 555 } 556 557 void dcn31_reset_hw_ctx_wrap( 558 struct dc *dc, 559 struct dc_state *context) 560 { 561 int i; 562 struct dce_hwseq *hws = dc->hwseq; 563 564 /* Reset Back End*/ 565 for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) { 566 struct pipe_ctx *pipe_ctx_old = 567 &dc->current_state->res_ctx.pipe_ctx[i]; 568 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 569 570 if (!pipe_ctx_old->stream) 571 continue; 572 573 if (pipe_ctx_old->top_pipe || pipe_ctx_old->prev_odm_pipe) 574 continue; 575 576 if (!pipe_ctx->stream || 577 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) { 578 struct clock_source *old_clk = pipe_ctx_old->clock_source; 579 580 dcn31_reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state); 581 if (hws->funcs.enable_stream_gating) 582 hws->funcs.enable_stream_gating(dc, pipe_ctx_old); 583 if (old_clk) 584 old_clk->funcs->cs_power_down(old_clk); 585 } 586 } 587 588 /* New dc_state in the process of being applied to hardware. */ 589 dc->current_state->res_ctx.link_enc_cfg_ctx.mode = LINK_ENC_CFG_TRANSIENT; 590 } 591 592 void dcn31_setup_hpo_hw_control(const struct dce_hwseq *hws, bool enable) 593 { 594 if (hws->ctx->dc->debug.hpo_optimization) 595 REG_UPDATE(HPO_TOP_HW_CONTROL, HPO_IO_EN, !!enable); 596 } 597