1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 27 #include "dm_services.h" 28 #include "dm_helpers.h" 29 #include "core_types.h" 30 #include "resource.h" 31 #include "dccg.h" 32 #include "dce/dce_hwseq.h" 33 #include "clk_mgr.h" 34 #include "reg_helper.h" 35 #include "abm.h" 36 #include "hubp.h" 37 #include "dchubbub.h" 38 #include "timing_generator.h" 39 #include "opp.h" 40 #include "ipp.h" 41 #include "mpc.h" 42 #include "mcif_wb.h" 43 #include "dc_dmub_srv.h" 44 #include "dcn31_hwseq.h" 45 #include "link_hwss.h" 46 #include "dpcd_defs.h" 47 #include "dce/dmub_outbox.h" 48 #include "dc_link_dp.h" 49 #include "inc/link_dpcd.h" 50 #include "dcn10/dcn10_hw_sequencer.h" 51 52 #define DC_LOGGER_INIT(logger) 53 54 #define CTX \ 55 hws->ctx 56 #define REG(reg)\ 57 hws->regs->reg 58 #define DC_LOGGER \ 59 dc->ctx->logger 60 61 62 #undef FN 63 #define FN(reg_name, field_name) \ 64 hws->shifts->field_name, hws->masks->field_name 65 66 void dcn31_init_hw(struct dc *dc) 67 { 68 struct abm **abms = dc->res_pool->multiple_abms; 69 struct dce_hwseq *hws = dc->hwseq; 70 struct dc_bios *dcb = dc->ctx->dc_bios; 71 struct resource_pool *res_pool = dc->res_pool; 72 uint32_t backlight = MAX_BACKLIGHT_LEVEL; 73 int i, j; 74 int edp_num; 75 76 if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks) 77 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr); 78 79 // Initialize the dccg 80 if (res_pool->dccg->funcs->dccg_init) 81 res_pool->dccg->funcs->dccg_init(res_pool->dccg); 82 83 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { 84 85 REG_WRITE(REFCLK_CNTL, 0); 86 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1); 87 REG_WRITE(DIO_MEM_PWR_CTRL, 0); 88 89 if (!dc->debug.disable_clock_gate) { 90 /* enable all DCN clock gating */ 91 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); 92 93 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); 94 95 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); 96 } 97 98 //Enable ability to power gate / don't force power on permanently 99 if (hws->funcs.enable_power_gating_plane) 100 hws->funcs.enable_power_gating_plane(hws, true); 101 102 return; 103 } 104 105 if (!dcb->funcs->is_accelerated_mode(dcb)) { 106 hws->funcs.bios_golden_init(dc); 107 hws->funcs.disable_vga(dc->hwseq); 108 } 109 110 if (dc->debug.enable_mem_low_power.bits.dmcu) { 111 // Force ERAM to shutdown if DMCU is not enabled 112 if (dc->debug.disable_dmcu || dc->config.disable_dmcu) { 113 REG_UPDATE(DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, 3); 114 } 115 } 116 117 // Set default OPTC memory power states 118 if (dc->debug.enable_mem_low_power.bits.optc) { 119 // Shutdown when unassigned and light sleep in VBLANK 120 REG_SET_2(ODM_MEM_PWR_CTRL3, 0, ODM_MEM_UNASSIGNED_PWR_MODE, 3, ODM_MEM_VBLANK_PWR_MODE, 1); 121 } 122 123 if (dc->debug.enable_mem_low_power.bits.vga) { 124 // Power down VGA memory 125 REG_UPDATE(MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, 1); 126 } 127 128 if (dc->ctx->dc_bios->fw_info_valid) { 129 res_pool->ref_clocks.xtalin_clock_inKhz = 130 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency; 131 132 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { 133 if (res_pool->dccg && res_pool->hubbub) { 134 135 (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg, 136 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency, 137 &res_pool->ref_clocks.dccg_ref_clock_inKhz); 138 139 (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub, 140 res_pool->ref_clocks.dccg_ref_clock_inKhz, 141 &res_pool->ref_clocks.dchub_ref_clock_inKhz); 142 } else { 143 // Not all ASICs have DCCG sw component 144 res_pool->ref_clocks.dccg_ref_clock_inKhz = 145 res_pool->ref_clocks.xtalin_clock_inKhz; 146 res_pool->ref_clocks.dchub_ref_clock_inKhz = 147 res_pool->ref_clocks.xtalin_clock_inKhz; 148 } 149 } 150 } else 151 ASSERT_CRITICAL(false); 152 153 for (i = 0; i < dc->link_count; i++) { 154 /* Power up AND update implementation according to the 155 * required signal (which may be different from the 156 * default signal on connector). 157 */ 158 struct dc_link *link = dc->links[i]; 159 160 if (link->ep_type != DISPLAY_ENDPOINT_PHY) 161 continue; 162 163 link->link_enc->funcs->hw_init(link->link_enc); 164 165 /* Check for enabled DIG to identify enabled display */ 166 if (link->link_enc->funcs->is_dig_enabled && 167 link->link_enc->funcs->is_dig_enabled(link->link_enc)) 168 link->link_status.link_active = true; 169 } 170 171 /* Power gate DSCs */ 172 for (i = 0; i < res_pool->res_cap->num_dsc; i++) 173 if (hws->funcs.dsc_pg_control != NULL) 174 hws->funcs.dsc_pg_control(hws, res_pool->dscs[i]->inst, false); 175 176 /* we want to turn off all dp displays before doing detection */ 177 if (dc->config.power_down_display_on_boot) { 178 uint8_t dpcd_power_state = '\0'; 179 enum dc_status status = DC_ERROR_UNEXPECTED; 180 181 for (i = 0; i < dc->link_count; i++) { 182 if (dc->links[i]->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) 183 continue; 184 185 /* if any of the displays are lit up turn them off */ 186 status = core_link_read_dpcd(dc->links[i], DP_SET_POWER, 187 &dpcd_power_state, sizeof(dpcd_power_state)); 188 if (status == DC_OK && dpcd_power_state == DP_POWER_STATE_D0) { 189 /* blank dp stream before power off receiver*/ 190 if (dc->links[i]->ep_type == DISPLAY_ENDPOINT_PHY && 191 dc->links[i]->link_enc->funcs->get_dig_frontend) { 192 unsigned int fe; 193 194 fe = dc->links[i]->link_enc->funcs->get_dig_frontend( 195 dc->links[i]->link_enc); 196 if (fe == ENGINE_ID_UNKNOWN) 197 continue; 198 199 for (j = 0; j < dc->res_pool->stream_enc_count; j++) { 200 if (fe == dc->res_pool->stream_enc[j]->id) { 201 dc->res_pool->stream_enc[j]->funcs->dp_blank(dc->links[i], 202 dc->res_pool->stream_enc[j]); 203 break; 204 } 205 } 206 } 207 dp_receiver_power_ctrl(dc->links[i], false); 208 } 209 } 210 } 211 212 /* If taking control over from VBIOS, we may want to optimize our first 213 * mode set, so we need to skip powering down pipes until we know which 214 * pipes we want to use. 215 * Otherwise, if taking control is not possible, we need to power 216 * everything down. 217 */ 218 if (dcb->funcs->is_accelerated_mode(dcb) || dc->config.power_down_display_on_boot) { 219 hws->funcs.init_pipes(dc, dc->current_state); 220 if (dc->res_pool->hubbub->funcs->allow_self_refresh_control) 221 dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, 222 !dc->res_pool->hubbub->ctx->dc->debug.disable_stutter); 223 } 224 225 /* In headless boot cases, DIG may be turned 226 * on which causes HW/SW discrepancies. 227 * To avoid this, power down hardware on boot 228 * if DIG is turned on and seamless boot not enabled 229 */ 230 if (dc->config.power_down_display_on_boot) { 231 struct dc_link *edp_links[MAX_NUM_EDP]; 232 struct dc_link *edp_link; 233 bool power_down = false; 234 235 get_edp_links(dc, edp_links, &edp_num); 236 if (edp_num) { 237 for (i = 0; i < edp_num; i++) { 238 edp_link = edp_links[i]; 239 if (edp_link->link_enc->funcs->is_dig_enabled && 240 edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc) && 241 dc->hwss.edp_backlight_control && 242 dc->hwss.power_down && 243 dc->hwss.edp_power_control) { 244 dc->hwss.edp_backlight_control(edp_link, false); 245 dc->hwss.power_down(dc); 246 dc->hwss.edp_power_control(edp_link, false); 247 power_down = true; 248 } 249 } 250 } 251 if (!power_down) { 252 for (i = 0; i < dc->link_count; i++) { 253 struct dc_link *link = dc->links[i]; 254 255 if (link->ep_type == DISPLAY_ENDPOINT_PHY && 256 link->link_enc->funcs->is_dig_enabled && 257 link->link_enc->funcs->is_dig_enabled(link->link_enc) && 258 dc->hwss.power_down) { 259 dc->hwss.power_down(dc); 260 break; 261 } 262 263 } 264 } 265 } 266 267 for (i = 0; i < res_pool->audio_count; i++) { 268 struct audio *audio = res_pool->audios[i]; 269 270 audio->funcs->hw_init(audio); 271 } 272 273 for (i = 0; i < dc->link_count; i++) { 274 struct dc_link *link = dc->links[i]; 275 276 if (link->panel_cntl) 277 backlight = link->panel_cntl->funcs->hw_init(link->panel_cntl); 278 } 279 280 for (i = 0; i < dc->res_pool->pipe_count; i++) { 281 if (abms[i] != NULL) 282 abms[i]->funcs->abm_init(abms[i], backlight); 283 } 284 285 /* power AFMT HDMI memory TODO: may move to dis/en output save power*/ 286 REG_WRITE(DIO_MEM_PWR_CTRL, 0); 287 288 if (!dc->debug.disable_clock_gate) { 289 /* enable all DCN clock gating */ 290 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); 291 292 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); 293 294 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); 295 } 296 if (hws->funcs.enable_power_gating_plane) 297 hws->funcs.enable_power_gating_plane(dc->hwseq, true); 298 299 if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks) 300 dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub); 301 302 if (dc->clk_mgr->funcs->notify_wm_ranges) 303 dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr); 304 305 if (dc->clk_mgr->funcs->set_hard_max_memclk) 306 dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr); 307 308 if (dc->res_pool->hubbub->funcs->force_pstate_change_control) 309 dc->res_pool->hubbub->funcs->force_pstate_change_control( 310 dc->res_pool->hubbub, false, false); 311 if (dc->res_pool->hubbub->funcs->init_crb) 312 dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub); 313 } 314 315 void dcn31_dsc_pg_control( 316 struct dce_hwseq *hws, 317 unsigned int dsc_inst, 318 bool power_on) 319 { 320 uint32_t power_gate = power_on ? 0 : 1; 321 uint32_t pwr_status = power_on ? 0 : 2; 322 uint32_t org_ip_request_cntl = 0; 323 324 if (hws->ctx->dc->debug.disable_dsc_power_gate) 325 return; 326 327 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); 328 if (org_ip_request_cntl == 0) 329 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); 330 331 switch (dsc_inst) { 332 case 0: /* DSC0 */ 333 REG_UPDATE(DOMAIN16_PG_CONFIG, 334 DOMAIN_POWER_GATE, power_gate); 335 336 REG_WAIT(DOMAIN16_PG_STATUS, 337 DOMAIN_PGFSM_PWR_STATUS, pwr_status, 338 1, 1000); 339 break; 340 case 1: /* DSC1 */ 341 REG_UPDATE(DOMAIN17_PG_CONFIG, 342 DOMAIN_POWER_GATE, power_gate); 343 344 REG_WAIT(DOMAIN17_PG_STATUS, 345 DOMAIN_PGFSM_PWR_STATUS, pwr_status, 346 1, 1000); 347 break; 348 case 2: /* DSC2 */ 349 REG_UPDATE(DOMAIN18_PG_CONFIG, 350 DOMAIN_POWER_GATE, power_gate); 351 352 REG_WAIT(DOMAIN18_PG_STATUS, 353 DOMAIN_PGFSM_PWR_STATUS, pwr_status, 354 1, 1000); 355 break; 356 default: 357 BREAK_TO_DEBUGGER(); 358 break; 359 } 360 361 if (org_ip_request_cntl == 0) 362 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); 363 } 364 365 366 void dcn31_enable_power_gating_plane( 367 struct dce_hwseq *hws, 368 bool enable) 369 { 370 bool force_on = true; /* disable power gating */ 371 372 if (enable) 373 force_on = false; 374 375 /* DCHUBP0/1/2/3/4/5 */ 376 REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 377 REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 378 379 /* DPP0/1/2/3/4/5 */ 380 REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 381 REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 382 383 /* DCS0/1/2/3/4/5 */ 384 REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 385 REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 386 REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 387 } 388 389 void dcn31_update_info_frame(struct pipe_ctx *pipe_ctx) 390 { 391 bool is_hdmi_tmds; 392 bool is_dp; 393 394 ASSERT(pipe_ctx->stream); 395 396 if (pipe_ctx->stream_res.stream_enc == NULL) 397 return; /* this is not root pipe */ 398 399 is_hdmi_tmds = dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal); 400 is_dp = dc_is_dp_signal(pipe_ctx->stream->signal); 401 402 if (!is_hdmi_tmds && !is_dp) 403 return; 404 405 if (is_hdmi_tmds) 406 pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets( 407 pipe_ctx->stream_res.stream_enc, 408 &pipe_ctx->stream_res.encoder_info_frame); 409 else { 410 pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets( 411 pipe_ctx->stream_res.stream_enc, 412 &pipe_ctx->stream_res.encoder_info_frame); 413 } 414 } 415 void dcn31_z10_save_init(struct dc *dc) 416 { 417 union dmub_rb_cmd cmd; 418 419 memset(&cmd, 0, sizeof(cmd)); 420 cmd.dcn_restore.header.type = DMUB_CMD__IDLE_OPT; 421 cmd.dcn_restore.header.sub_type = DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT; 422 423 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd); 424 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv); 425 dc_dmub_srv_wait_idle(dc->ctx->dmub_srv); 426 } 427 428 void dcn31_z10_restore(struct dc *dc) 429 { 430 union dmub_rb_cmd cmd; 431 432 /* 433 * DMUB notifies whether restore is required. 434 * Optimization to avoid sending commands when not required. 435 */ 436 if (!dc_dmub_srv_is_restore_required(dc->ctx->dmub_srv)) 437 return; 438 439 memset(&cmd, 0, sizeof(cmd)); 440 cmd.dcn_restore.header.type = DMUB_CMD__IDLE_OPT; 441 cmd.dcn_restore.header.sub_type = DMUB_CMD__IDLE_OPT_DCN_RESTORE; 442 443 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd); 444 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv); 445 dc_dmub_srv_wait_idle(dc->ctx->dmub_srv); 446 } 447 448 void dcn31_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on) 449 { 450 uint32_t power_gate = power_on ? 0 : 1; 451 uint32_t pwr_status = power_on ? 0 : 2; 452 453 if (hws->ctx->dc->debug.disable_hubp_power_gate) 454 return; 455 456 if (REG(DOMAIN0_PG_CONFIG) == 0) 457 return; 458 459 switch (hubp_inst) { 460 case 0: 461 REG_SET(DOMAIN0_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 462 REG_WAIT(DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 463 break; 464 case 1: 465 REG_SET(DOMAIN1_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 466 REG_WAIT(DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 467 break; 468 case 2: 469 REG_SET(DOMAIN2_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 470 REG_WAIT(DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 471 break; 472 case 3: 473 REG_SET(DOMAIN3_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 474 REG_WAIT(DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 475 break; 476 default: 477 BREAK_TO_DEBUGGER(); 478 break; 479 } 480 } 481 482 int dcn31_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config) 483 { 484 struct dcn_hubbub_phys_addr_config config; 485 486 config.system_aperture.fb_top = pa_config->system_aperture.fb_top; 487 config.system_aperture.fb_offset = pa_config->system_aperture.fb_offset; 488 config.system_aperture.fb_base = pa_config->system_aperture.fb_base; 489 config.system_aperture.agp_top = pa_config->system_aperture.agp_top; 490 config.system_aperture.agp_bot = pa_config->system_aperture.agp_bot; 491 config.system_aperture.agp_base = pa_config->system_aperture.agp_base; 492 config.gart_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr; 493 config.gart_config.page_table_end_addr = pa_config->gart_config.page_table_end_addr; 494 495 if (pa_config->gart_config.base_addr_is_mc_addr) { 496 /* Convert from MC address to offset into FB */ 497 config.gart_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr - 498 pa_config->system_aperture.fb_base + 499 pa_config->system_aperture.fb_offset; 500 } else 501 config.gart_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr; 502 503 return dc->res_pool->hubbub->funcs->init_dchub_sys_ctx(dc->res_pool->hubbub, &config); 504 } 505 506 static void dcn31_reset_back_end_for_pipe( 507 struct dc *dc, 508 struct pipe_ctx *pipe_ctx, 509 struct dc_state *context) 510 { 511 struct dc_link *link; 512 513 DC_LOGGER_INIT(dc->ctx->logger); 514 if (pipe_ctx->stream_res.stream_enc == NULL) { 515 pipe_ctx->stream = NULL; 516 return; 517 } 518 ASSERT(!pipe_ctx->top_pipe); 519 520 dc->hwss.set_abm_immediate_disable(pipe_ctx); 521 522 pipe_ctx->stream_res.tg->funcs->set_dsc_config( 523 pipe_ctx->stream_res.tg, 524 OPTC_DSC_DISABLED, 0, 0); 525 pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg); 526 527 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false); 528 if (pipe_ctx->stream_res.tg->funcs->set_odm_bypass) 529 pipe_ctx->stream_res.tg->funcs->set_odm_bypass( 530 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); 531 532 if (pipe_ctx->stream_res.tg->funcs->set_drr) 533 pipe_ctx->stream_res.tg->funcs->set_drr( 534 pipe_ctx->stream_res.tg, NULL); 535 536 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { 537 link = pipe_ctx->stream->link; 538 /* DPMS may already disable or */ 539 /* dpms_off status is incorrect due to fastboot 540 * feature. When system resume from S4 with second 541 * screen only, the dpms_off would be true but 542 * VBIOS lit up eDP, so check link status too. 543 */ 544 if (!pipe_ctx->stream->dpms_off || link->link_status.link_active) 545 core_link_disable_stream(pipe_ctx); 546 else if (pipe_ctx->stream_res.audio) 547 dc->hwss.disable_audio_stream(pipe_ctx); 548 549 /* free acquired resources */ 550 if (pipe_ctx->stream_res.audio) { 551 /*disable az_endpoint*/ 552 pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio); 553 554 /*free audio*/ 555 if (dc->caps.dynamic_audio == true) { 556 /*we have to dynamic arbitrate the audio endpoints*/ 557 /*we free the resource, need reset is_audio_acquired*/ 558 update_audio_usage(&dc->current_state->res_ctx, dc->res_pool, 559 pipe_ctx->stream_res.audio, false); 560 pipe_ctx->stream_res.audio = NULL; 561 } 562 } 563 } else if (pipe_ctx->stream_res.dsc) { 564 dp_set_dsc_enable(pipe_ctx, false); 565 } 566 567 pipe_ctx->stream = NULL; 568 DC_LOG_DEBUG("Reset back end for pipe %d, tg:%d\n", 569 pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst); 570 } 571 572 void dcn31_reset_hw_ctx_wrap( 573 struct dc *dc, 574 struct dc_state *context) 575 { 576 int i; 577 struct dce_hwseq *hws = dc->hwseq; 578 579 /* Reset Back End*/ 580 for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) { 581 struct pipe_ctx *pipe_ctx_old = 582 &dc->current_state->res_ctx.pipe_ctx[i]; 583 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 584 585 if (!pipe_ctx_old->stream) 586 continue; 587 588 if (pipe_ctx_old->top_pipe || pipe_ctx_old->prev_odm_pipe) 589 continue; 590 591 if (!pipe_ctx->stream || 592 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) { 593 struct clock_source *old_clk = pipe_ctx_old->clock_source; 594 595 dcn31_reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state); 596 if (hws->funcs.enable_stream_gating) 597 hws->funcs.enable_stream_gating(dc, pipe_ctx); 598 if (old_clk) 599 old_clk->funcs->cs_power_down(old_clk); 600 } 601 } 602 } 603