1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 27 #include "dm_services.h" 28 #include "dm_helpers.h" 29 #include "core_types.h" 30 #include "resource.h" 31 #include "dccg.h" 32 #include "dce/dce_hwseq.h" 33 #include "clk_mgr.h" 34 #include "reg_helper.h" 35 #include "abm.h" 36 #include "hubp.h" 37 #include "dchubbub.h" 38 #include "timing_generator.h" 39 #include "opp.h" 40 #include "ipp.h" 41 #include "mpc.h" 42 #include "mcif_wb.h" 43 #include "dc_dmub_srv.h" 44 #include "dcn31_hwseq.h" 45 #include "link_hwss.h" 46 #include "dpcd_defs.h" 47 #include "dce/dmub_outbox.h" 48 #include "dc_link_dp.h" 49 #include "inc/link_dpcd.h" 50 #include "dcn10/dcn10_hw_sequencer.h" 51 #include "inc/link_enc_cfg.h" 52 #include "dcn30/dcn30_vpg.h" 53 #include "dce/dce_i2c_hw.h" 54 55 #define DC_LOGGER_INIT(logger) 56 57 #define CTX \ 58 hws->ctx 59 #define REG(reg)\ 60 hws->regs->reg 61 #define DC_LOGGER \ 62 dc->ctx->logger 63 64 65 #undef FN 66 #define FN(reg_name, field_name) \ 67 hws->shifts->field_name, hws->masks->field_name 68 69 void dcn31_init_hw(struct dc *dc) 70 { 71 struct abm **abms = dc->res_pool->multiple_abms; 72 struct dce_hwseq *hws = dc->hwseq; 73 struct dc_bios *dcb = dc->ctx->dc_bios; 74 struct resource_pool *res_pool = dc->res_pool; 75 uint32_t backlight = MAX_BACKLIGHT_LEVEL; 76 int i, j; 77 78 if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks) 79 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr); 80 81 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { 82 83 REG_WRITE(REFCLK_CNTL, 0); 84 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1); 85 REG_WRITE(DIO_MEM_PWR_CTRL, 0); 86 87 if (!dc->debug.disable_clock_gate) { 88 /* enable all DCN clock gating */ 89 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); 90 91 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); 92 93 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); 94 } 95 96 //Enable ability to power gate / don't force power on permanently 97 if (hws->funcs.enable_power_gating_plane) 98 hws->funcs.enable_power_gating_plane(hws, true); 99 100 return; 101 } 102 103 if (!dcb->funcs->is_accelerated_mode(dcb)) { 104 hws->funcs.bios_golden_init(dc); 105 hws->funcs.disable_vga(dc->hwseq); 106 } 107 // Initialize the dccg 108 if (res_pool->dccg->funcs->dccg_init) 109 res_pool->dccg->funcs->dccg_init(res_pool->dccg); 110 111 if (dc->debug.enable_mem_low_power.bits.dmcu) { 112 // Force ERAM to shutdown if DMCU is not enabled 113 if (dc->debug.disable_dmcu || dc->config.disable_dmcu) { 114 REG_UPDATE(DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, 3); 115 } 116 } 117 118 // Set default OPTC memory power states 119 if (dc->debug.enable_mem_low_power.bits.optc) { 120 // Shutdown when unassigned and light sleep in VBLANK 121 REG_SET_2(ODM_MEM_PWR_CTRL3, 0, ODM_MEM_UNASSIGNED_PWR_MODE, 3, ODM_MEM_VBLANK_PWR_MODE, 1); 122 } 123 124 if (dc->debug.enable_mem_low_power.bits.vga) { 125 // Power down VGA memory 126 REG_UPDATE(MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, 1); 127 } 128 129 #if defined(CONFIG_DRM_AMD_DC_DCN) 130 if (dc->debug.enable_mem_low_power.bits.vpg && dc->res_pool->stream_enc[0]->vpg->funcs->vpg_powerdown) { 131 // Power down VPGs 132 for (i = 0; i < dc->res_pool->stream_enc_count; i++) 133 dc->res_pool->stream_enc[i]->vpg->funcs->vpg_powerdown(dc->res_pool->stream_enc[i]->vpg); 134 #if defined(CONFIG_DRM_AMD_DC_DP2_0) 135 for (i = 0; i < dc->res_pool->hpo_dp_stream_enc_count; i++) 136 dc->res_pool->hpo_dp_stream_enc[i]->vpg->funcs->vpg_powerdown(dc->res_pool->hpo_dp_stream_enc[i]->vpg); 137 #endif 138 } 139 #endif 140 141 if (dc->ctx->dc_bios->fw_info_valid) { 142 res_pool->ref_clocks.xtalin_clock_inKhz = 143 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency; 144 145 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { 146 if (res_pool->dccg && res_pool->hubbub) { 147 148 (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg, 149 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency, 150 &res_pool->ref_clocks.dccg_ref_clock_inKhz); 151 152 (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub, 153 res_pool->ref_clocks.dccg_ref_clock_inKhz, 154 &res_pool->ref_clocks.dchub_ref_clock_inKhz); 155 } else { 156 // Not all ASICs have DCCG sw component 157 res_pool->ref_clocks.dccg_ref_clock_inKhz = 158 res_pool->ref_clocks.xtalin_clock_inKhz; 159 res_pool->ref_clocks.dchub_ref_clock_inKhz = 160 res_pool->ref_clocks.xtalin_clock_inKhz; 161 } 162 } 163 } else 164 ASSERT_CRITICAL(false); 165 166 for (i = 0; i < dc->link_count; i++) { 167 /* Power up AND update implementation according to the 168 * required signal (which may be different from the 169 * default signal on connector). 170 */ 171 struct dc_link *link = dc->links[i]; 172 173 if (link->ep_type != DISPLAY_ENDPOINT_PHY) 174 continue; 175 176 link->link_enc->funcs->hw_init(link->link_enc); 177 178 /* Check for enabled DIG to identify enabled display */ 179 if (link->link_enc->funcs->is_dig_enabled && 180 link->link_enc->funcs->is_dig_enabled(link->link_enc)) 181 link->link_status.link_active = true; 182 } 183 184 /* Power gate DSCs */ 185 for (i = 0; i < res_pool->res_cap->num_dsc; i++) 186 if (hws->funcs.dsc_pg_control != NULL) 187 hws->funcs.dsc_pg_control(hws, res_pool->dscs[i]->inst, false); 188 189 /* Enables outbox notifications for usb4 dpia */ 190 if (dc->res_pool->usb4_dpia_count) 191 dmub_enable_outbox_notification(dc); 192 193 /* we want to turn off all dp displays before doing detection */ 194 if (dc->config.power_down_display_on_boot) { 195 uint8_t dpcd_power_state = '\0'; 196 enum dc_status status = DC_ERROR_UNEXPECTED; 197 198 for (i = 0; i < dc->link_count; i++) { 199 if (dc->links[i]->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) 200 continue; 201 202 /* if any of the displays are lit up turn them off */ 203 status = core_link_read_dpcd(dc->links[i], DP_SET_POWER, 204 &dpcd_power_state, sizeof(dpcd_power_state)); 205 if (status == DC_OK && dpcd_power_state == DP_POWER_STATE_D0) { 206 /* blank dp stream before power off receiver*/ 207 if (dc->links[i]->ep_type == DISPLAY_ENDPOINT_PHY && 208 dc->links[i]->link_enc->funcs->get_dig_frontend) { 209 unsigned int fe; 210 211 fe = dc->links[i]->link_enc->funcs->get_dig_frontend( 212 dc->links[i]->link_enc); 213 if (fe == ENGINE_ID_UNKNOWN) 214 continue; 215 216 for (j = 0; j < dc->res_pool->stream_enc_count; j++) { 217 if (fe == dc->res_pool->stream_enc[j]->id) { 218 dc->res_pool->stream_enc[j]->funcs->dp_blank(dc->links[i], 219 dc->res_pool->stream_enc[j]); 220 break; 221 } 222 } 223 } 224 dp_receiver_power_ctrl(dc->links[i], false); 225 } 226 } 227 } 228 229 /* If taking control over from VBIOS, we may want to optimize our first 230 * mode set, so we need to skip powering down pipes until we know which 231 * pipes we want to use. 232 * Otherwise, if taking control is not possible, we need to power 233 * everything down. 234 */ 235 if (dcb->funcs->is_accelerated_mode(dcb) || dc->config.power_down_display_on_boot) { 236 hws->funcs.init_pipes(dc, dc->current_state); 237 if (dc->res_pool->hubbub->funcs->allow_self_refresh_control) 238 dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, 239 !dc->res_pool->hubbub->ctx->dc->debug.disable_stutter); 240 } 241 242 for (i = 0; i < res_pool->audio_count; i++) { 243 struct audio *audio = res_pool->audios[i]; 244 245 audio->funcs->hw_init(audio); 246 } 247 248 for (i = 0; i < dc->link_count; i++) { 249 struct dc_link *link = dc->links[i]; 250 251 if (link->panel_cntl) 252 backlight = link->panel_cntl->funcs->hw_init(link->panel_cntl); 253 } 254 255 for (i = 0; i < dc->res_pool->pipe_count; i++) { 256 if (abms[i] != NULL) 257 abms[i]->funcs->abm_init(abms[i], backlight); 258 } 259 260 /* power AFMT HDMI memory TODO: may move to dis/en output save power*/ 261 REG_WRITE(DIO_MEM_PWR_CTRL, 0); 262 263 // Set i2c to light sleep until engine is setup 264 if (dc->debug.enable_mem_low_power.bits.i2c) 265 REG_UPDATE(DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, 1); 266 267 if (!dc->debug.disable_clock_gate) { 268 /* enable all DCN clock gating */ 269 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); 270 271 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); 272 273 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); 274 } 275 if (hws->funcs.enable_power_gating_plane) 276 hws->funcs.enable_power_gating_plane(dc->hwseq, true); 277 278 if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks) 279 dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub); 280 281 if (dc->clk_mgr->funcs->notify_wm_ranges) 282 dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr); 283 284 if (dc->clk_mgr->funcs->set_hard_max_memclk) 285 dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr); 286 287 if (dc->res_pool->hubbub->funcs->force_pstate_change_control) 288 dc->res_pool->hubbub->funcs->force_pstate_change_control( 289 dc->res_pool->hubbub, false, false); 290 #if defined(CONFIG_DRM_AMD_DC_DCN) 291 if (dc->res_pool->hubbub->funcs->init_crb) 292 dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub); 293 #endif 294 } 295 296 void dcn31_dsc_pg_control( 297 struct dce_hwseq *hws, 298 unsigned int dsc_inst, 299 bool power_on) 300 { 301 uint32_t power_gate = power_on ? 0 : 1; 302 uint32_t pwr_status = power_on ? 0 : 2; 303 uint32_t org_ip_request_cntl = 0; 304 305 if (hws->ctx->dc->debug.disable_dsc_power_gate) 306 return; 307 308 if (hws->ctx->dc->debug.root_clock_optimization.bits.dsc && 309 hws->ctx->dc->res_pool->dccg->funcs->enable_dsc && 310 power_on) 311 hws->ctx->dc->res_pool->dccg->funcs->enable_dsc( 312 hws->ctx->dc->res_pool->dccg, dsc_inst); 313 314 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); 315 if (org_ip_request_cntl == 0) 316 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); 317 318 switch (dsc_inst) { 319 case 0: /* DSC0 */ 320 REG_UPDATE(DOMAIN16_PG_CONFIG, 321 DOMAIN_POWER_GATE, power_gate); 322 323 REG_WAIT(DOMAIN16_PG_STATUS, 324 DOMAIN_PGFSM_PWR_STATUS, pwr_status, 325 1, 1000); 326 break; 327 case 1: /* DSC1 */ 328 REG_UPDATE(DOMAIN17_PG_CONFIG, 329 DOMAIN_POWER_GATE, power_gate); 330 331 REG_WAIT(DOMAIN17_PG_STATUS, 332 DOMAIN_PGFSM_PWR_STATUS, pwr_status, 333 1, 1000); 334 break; 335 case 2: /* DSC2 */ 336 REG_UPDATE(DOMAIN18_PG_CONFIG, 337 DOMAIN_POWER_GATE, power_gate); 338 339 REG_WAIT(DOMAIN18_PG_STATUS, 340 DOMAIN_PGFSM_PWR_STATUS, pwr_status, 341 1, 1000); 342 break; 343 default: 344 BREAK_TO_DEBUGGER(); 345 break; 346 } 347 348 if (org_ip_request_cntl == 0) 349 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); 350 351 if (hws->ctx->dc->debug.root_clock_optimization.bits.dsc) { 352 if (hws->ctx->dc->res_pool->dccg->funcs->disable_dsc && !power_on) 353 hws->ctx->dc->res_pool->dccg->funcs->disable_dsc( 354 hws->ctx->dc->res_pool->dccg, dsc_inst); 355 } 356 357 } 358 359 360 void dcn31_enable_power_gating_plane( 361 struct dce_hwseq *hws, 362 bool enable) 363 { 364 bool force_on = true; /* disable power gating */ 365 366 if (enable) 367 force_on = false; 368 369 /* DCHUBP0/1/2/3/4/5 */ 370 REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 371 REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 372 373 /* DPP0/1/2/3/4/5 */ 374 REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 375 REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 376 377 /* DCS0/1/2/3/4/5 */ 378 REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 379 REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 380 REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 381 } 382 383 void dcn31_update_info_frame(struct pipe_ctx *pipe_ctx) 384 { 385 bool is_hdmi_tmds; 386 bool is_dp; 387 388 ASSERT(pipe_ctx->stream); 389 390 if (pipe_ctx->stream_res.stream_enc == NULL) 391 return; /* this is not root pipe */ 392 393 is_hdmi_tmds = dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal); 394 is_dp = dc_is_dp_signal(pipe_ctx->stream->signal); 395 396 if (!is_hdmi_tmds && !is_dp) 397 return; 398 399 if (is_hdmi_tmds) 400 pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets( 401 pipe_ctx->stream_res.stream_enc, 402 &pipe_ctx->stream_res.encoder_info_frame); 403 else { 404 pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets( 405 pipe_ctx->stream_res.stream_enc, 406 &pipe_ctx->stream_res.encoder_info_frame); 407 } 408 } 409 void dcn31_z10_save_init(struct dc *dc) 410 { 411 union dmub_rb_cmd cmd; 412 413 memset(&cmd, 0, sizeof(cmd)); 414 cmd.dcn_restore.header.type = DMUB_CMD__IDLE_OPT; 415 cmd.dcn_restore.header.sub_type = DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT; 416 417 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd); 418 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv); 419 dc_dmub_srv_wait_idle(dc->ctx->dmub_srv); 420 } 421 422 void dcn31_z10_restore(const struct dc *dc) 423 { 424 union dmub_rb_cmd cmd; 425 426 /* 427 * DMUB notifies whether restore is required. 428 * Optimization to avoid sending commands when not required. 429 */ 430 if (!dc_dmub_srv_is_restore_required(dc->ctx->dmub_srv)) 431 return; 432 433 memset(&cmd, 0, sizeof(cmd)); 434 cmd.dcn_restore.header.type = DMUB_CMD__IDLE_OPT; 435 cmd.dcn_restore.header.sub_type = DMUB_CMD__IDLE_OPT_DCN_RESTORE; 436 437 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd); 438 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv); 439 dc_dmub_srv_wait_idle(dc->ctx->dmub_srv); 440 } 441 442 void dcn31_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on) 443 { 444 uint32_t power_gate = power_on ? 0 : 1; 445 uint32_t pwr_status = power_on ? 0 : 2; 446 447 if (hws->ctx->dc->debug.disable_hubp_power_gate) 448 return; 449 450 if (REG(DOMAIN0_PG_CONFIG) == 0) 451 return; 452 453 switch (hubp_inst) { 454 case 0: 455 REG_SET(DOMAIN0_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 456 REG_WAIT(DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 457 break; 458 case 1: 459 REG_SET(DOMAIN1_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 460 REG_WAIT(DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 461 break; 462 case 2: 463 REG_SET(DOMAIN2_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 464 REG_WAIT(DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 465 break; 466 case 3: 467 REG_SET(DOMAIN3_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 468 REG_WAIT(DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 469 break; 470 default: 471 BREAK_TO_DEBUGGER(); 472 break; 473 } 474 } 475 476 int dcn31_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config) 477 { 478 struct dcn_hubbub_phys_addr_config config; 479 480 config.system_aperture.fb_top = pa_config->system_aperture.fb_top; 481 config.system_aperture.fb_offset = pa_config->system_aperture.fb_offset; 482 config.system_aperture.fb_base = pa_config->system_aperture.fb_base; 483 config.system_aperture.agp_top = pa_config->system_aperture.agp_top; 484 config.system_aperture.agp_bot = pa_config->system_aperture.agp_bot; 485 config.system_aperture.agp_base = pa_config->system_aperture.agp_base; 486 config.gart_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr; 487 config.gart_config.page_table_end_addr = pa_config->gart_config.page_table_end_addr; 488 489 if (pa_config->gart_config.base_addr_is_mc_addr) { 490 /* Convert from MC address to offset into FB */ 491 config.gart_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr - 492 pa_config->system_aperture.fb_base + 493 pa_config->system_aperture.fb_offset; 494 } else 495 config.gart_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr; 496 497 return dc->res_pool->hubbub->funcs->init_dchub_sys_ctx(dc->res_pool->hubbub, &config); 498 } 499 500 static void dcn31_reset_back_end_for_pipe( 501 struct dc *dc, 502 struct pipe_ctx *pipe_ctx, 503 struct dc_state *context) 504 { 505 struct dc_link *link; 506 507 DC_LOGGER_INIT(dc->ctx->logger); 508 if (pipe_ctx->stream_res.stream_enc == NULL) { 509 pipe_ctx->stream = NULL; 510 return; 511 } 512 ASSERT(!pipe_ctx->top_pipe); 513 514 dc->hwss.set_abm_immediate_disable(pipe_ctx); 515 516 pipe_ctx->stream_res.tg->funcs->set_dsc_config( 517 pipe_ctx->stream_res.tg, 518 OPTC_DSC_DISABLED, 0, 0); 519 pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg); 520 521 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false); 522 if (pipe_ctx->stream_res.tg->funcs->set_odm_bypass) 523 pipe_ctx->stream_res.tg->funcs->set_odm_bypass( 524 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); 525 526 if (pipe_ctx->stream_res.tg->funcs->set_drr) 527 pipe_ctx->stream_res.tg->funcs->set_drr( 528 pipe_ctx->stream_res.tg, NULL); 529 530 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { 531 link = pipe_ctx->stream->link; 532 /* DPMS may already disable or */ 533 /* dpms_off status is incorrect due to fastboot 534 * feature. When system resume from S4 with second 535 * screen only, the dpms_off would be true but 536 * VBIOS lit up eDP, so check link status too. 537 */ 538 if (!pipe_ctx->stream->dpms_off || link->link_status.link_active) 539 core_link_disable_stream(pipe_ctx); 540 else if (pipe_ctx->stream_res.audio) 541 dc->hwss.disable_audio_stream(pipe_ctx); 542 543 /* free acquired resources */ 544 if (pipe_ctx->stream_res.audio) { 545 /*disable az_endpoint*/ 546 pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio); 547 548 /*free audio*/ 549 if (dc->caps.dynamic_audio == true) { 550 /*we have to dynamic arbitrate the audio endpoints*/ 551 /*we free the resource, need reset is_audio_acquired*/ 552 update_audio_usage(&dc->current_state->res_ctx, dc->res_pool, 553 pipe_ctx->stream_res.audio, false); 554 pipe_ctx->stream_res.audio = NULL; 555 } 556 } 557 } else if (pipe_ctx->stream_res.dsc) { 558 dp_set_dsc_enable(pipe_ctx, false); 559 } 560 561 pipe_ctx->stream = NULL; 562 DC_LOG_DEBUG("Reset back end for pipe %d, tg:%d\n", 563 pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst); 564 } 565 566 void dcn31_reset_hw_ctx_wrap( 567 struct dc *dc, 568 struct dc_state *context) 569 { 570 int i; 571 struct dce_hwseq *hws = dc->hwseq; 572 573 /* Reset Back End*/ 574 for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) { 575 struct pipe_ctx *pipe_ctx_old = 576 &dc->current_state->res_ctx.pipe_ctx[i]; 577 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 578 579 if (!pipe_ctx_old->stream) 580 continue; 581 582 if (pipe_ctx_old->top_pipe || pipe_ctx_old->prev_odm_pipe) 583 continue; 584 585 if (!pipe_ctx->stream || 586 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) { 587 struct clock_source *old_clk = pipe_ctx_old->clock_source; 588 589 dcn31_reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state); 590 if (hws->funcs.enable_stream_gating) 591 hws->funcs.enable_stream_gating(dc, pipe_ctx); 592 if (old_clk) 593 old_clk->funcs->cs_power_down(old_clk); 594 } 595 } 596 597 /* New dc_state in the process of being applied to hardware. */ 598 dc->current_state->res_ctx.link_enc_cfg_ctx.mode = LINK_ENC_CFG_TRANSIENT; 599 } 600