1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 27 #include "dm_services.h" 28 #include "dm_helpers.h" 29 #include "core_types.h" 30 #include "resource.h" 31 #include "dccg.h" 32 #include "dce/dce_hwseq.h" 33 #include "clk_mgr.h" 34 #include "reg_helper.h" 35 #include "abm.h" 36 #include "clk_mgr.h" 37 #include "hubp.h" 38 #include "dchubbub.h" 39 #include "timing_generator.h" 40 #include "opp.h" 41 #include "ipp.h" 42 #include "mpc.h" 43 #include "mcif_wb.h" 44 #include "dc_dmub_srv.h" 45 #include "dcn31_hwseq.h" 46 #include "link_hwss.h" 47 #include "dpcd_defs.h" 48 #include "dce/dmub_outbox.h" 49 #include "dc_link_dp.h" 50 51 #define DC_LOGGER_INIT(logger) 52 53 #define CTX \ 54 hws->ctx 55 #define REG(reg)\ 56 hws->regs->reg 57 #define DC_LOGGER \ 58 dc->ctx->logger 59 60 61 #undef FN 62 #define FN(reg_name, field_name) \ 63 hws->shifts->field_name, hws->masks->field_name 64 65 void dcn31_init_hw(struct dc *dc) 66 { 67 struct abm **abms = dc->res_pool->multiple_abms; 68 struct dce_hwseq *hws = dc->hwseq; 69 struct dc_bios *dcb = dc->ctx->dc_bios; 70 struct resource_pool *res_pool = dc->res_pool; 71 uint32_t backlight = MAX_BACKLIGHT_LEVEL; 72 int i, j; 73 int edp_num; 74 75 if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks) 76 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr); 77 78 // Initialize the dccg 79 if (res_pool->dccg->funcs->dccg_init) 80 res_pool->dccg->funcs->dccg_init(res_pool->dccg); 81 82 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { 83 84 REG_WRITE(REFCLK_CNTL, 0); 85 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1); 86 REG_WRITE(DIO_MEM_PWR_CTRL, 0); 87 88 if (!dc->debug.disable_clock_gate) { 89 /* enable all DCN clock gating */ 90 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); 91 92 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); 93 94 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); 95 } 96 97 //Enable ability to power gate / don't force power on permanently 98 if (hws->funcs.enable_power_gating_plane) 99 hws->funcs.enable_power_gating_plane(hws, true); 100 101 return; 102 } 103 104 if (!dcb->funcs->is_accelerated_mode(dcb)) { 105 hws->funcs.bios_golden_init(dc); 106 hws->funcs.disable_vga(dc->hwseq); 107 } 108 109 if (dc->debug.enable_mem_low_power.bits.dmcu) { 110 // Force ERAM to shutdown if DMCU is not enabled 111 if (dc->debug.disable_dmcu || dc->config.disable_dmcu) { 112 REG_UPDATE(DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, 3); 113 } 114 } 115 116 // Set default OPTC memory power states 117 if (dc->debug.enable_mem_low_power.bits.optc) { 118 // Shutdown when unassigned and light sleep in VBLANK 119 REG_SET_2(ODM_MEM_PWR_CTRL3, 0, ODM_MEM_UNASSIGNED_PWR_MODE, 3, ODM_MEM_VBLANK_PWR_MODE, 1); 120 } 121 122 if (dc->debug.enable_mem_low_power.bits.vga) { 123 // Power down VGA memory 124 REG_UPDATE(MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, 1); 125 } 126 127 if (dc->ctx->dc_bios->fw_info_valid) { 128 res_pool->ref_clocks.xtalin_clock_inKhz = 129 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency; 130 131 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { 132 if (res_pool->dccg && res_pool->hubbub) { 133 134 (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg, 135 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency, 136 &res_pool->ref_clocks.dccg_ref_clock_inKhz); 137 138 (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub, 139 res_pool->ref_clocks.dccg_ref_clock_inKhz, 140 &res_pool->ref_clocks.dchub_ref_clock_inKhz); 141 } else { 142 // Not all ASICs have DCCG sw component 143 res_pool->ref_clocks.dccg_ref_clock_inKhz = 144 res_pool->ref_clocks.xtalin_clock_inKhz; 145 res_pool->ref_clocks.dchub_ref_clock_inKhz = 146 res_pool->ref_clocks.xtalin_clock_inKhz; 147 } 148 } 149 } else 150 ASSERT_CRITICAL(false); 151 152 for (i = 0; i < dc->link_count; i++) { 153 /* Power up AND update implementation according to the 154 * required signal (which may be different from the 155 * default signal on connector). 156 */ 157 struct dc_link *link = dc->links[i]; 158 159 link->link_enc->funcs->hw_init(link->link_enc); 160 161 /* Check for enabled DIG to identify enabled display */ 162 if (link->link_enc->funcs->is_dig_enabled && 163 link->link_enc->funcs->is_dig_enabled(link->link_enc)) 164 link->link_status.link_active = true; 165 } 166 167 /* Power gate DSCs */ 168 for (i = 0; i < res_pool->res_cap->num_dsc; i++) 169 if (hws->funcs.dsc_pg_control != NULL) 170 hws->funcs.dsc_pg_control(hws, res_pool->dscs[i]->inst, false); 171 172 /* we want to turn off all dp displays before doing detection */ 173 if (dc->config.power_down_display_on_boot) { 174 uint8_t dpcd_power_state = '\0'; 175 enum dc_status status = DC_ERROR_UNEXPECTED; 176 177 for (i = 0; i < dc->link_count; i++) { 178 if (dc->links[i]->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) 179 continue; 180 181 /* if any of the displays are lit up turn them off */ 182 status = core_link_read_dpcd(dc->links[i], DP_SET_POWER, 183 &dpcd_power_state, sizeof(dpcd_power_state)); 184 if (status == DC_OK && dpcd_power_state == DP_POWER_STATE_D0) { 185 /* blank dp stream before power off receiver*/ 186 if (dc->links[i]->link_enc->funcs->get_dig_frontend) { 187 unsigned int fe; 188 189 fe = dc->links[i]->link_enc->funcs->get_dig_frontend( 190 dc->links[i]->link_enc); 191 if (fe == ENGINE_ID_UNKNOWN) 192 continue; 193 194 for (j = 0; j < dc->res_pool->stream_enc_count; j++) { 195 if (fe == dc->res_pool->stream_enc[j]->id) { 196 dc->res_pool->stream_enc[j]->funcs->dp_blank( 197 dc->res_pool->stream_enc[j]); 198 break; 199 } 200 } 201 } 202 dp_receiver_power_ctrl(dc->links[i], false); 203 } 204 } 205 } 206 207 /* If taking control over from VBIOS, we may want to optimize our first 208 * mode set, so we need to skip powering down pipes until we know which 209 * pipes we want to use. 210 * Otherwise, if taking control is not possible, we need to power 211 * everything down. 212 */ 213 if (dcb->funcs->is_accelerated_mode(dcb) || dc->config.power_down_display_on_boot) { 214 hws->funcs.init_pipes(dc, dc->current_state); 215 if (dc->res_pool->hubbub->funcs->allow_self_refresh_control) 216 dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, 217 !dc->res_pool->hubbub->ctx->dc->debug.disable_stutter); 218 } 219 220 /* In headless boot cases, DIG may be turned 221 * on which causes HW/SW discrepancies. 222 * To avoid this, power down hardware on boot 223 * if DIG is turned on and seamless boot not enabled 224 */ 225 if (dc->config.power_down_display_on_boot) { 226 struct dc_link *edp_links[MAX_NUM_EDP]; 227 struct dc_link *edp_link; 228 229 get_edp_links(dc, edp_links, &edp_num); 230 if (edp_num) { 231 for (i = 0; i < edp_num; i++) { 232 edp_link = edp_links[i]; 233 if (edp_link->link_enc->funcs->is_dig_enabled && 234 edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc) && 235 dc->hwss.edp_backlight_control && 236 dc->hwss.power_down && 237 dc->hwss.edp_power_control) { 238 dc->hwss.edp_backlight_control(edp_link, false); 239 dc->hwss.power_down(dc); 240 dc->hwss.edp_power_control(edp_link, false); 241 } 242 } 243 } else { 244 for (i = 0; i < dc->link_count; i++) { 245 struct dc_link *link = dc->links[i]; 246 247 if (link->link_enc->funcs->is_dig_enabled && 248 link->link_enc->funcs->is_dig_enabled(link->link_enc) && 249 dc->hwss.power_down) { 250 dc->hwss.power_down(dc); 251 break; 252 } 253 254 } 255 } 256 } 257 258 for (i = 0; i < res_pool->audio_count; i++) { 259 struct audio *audio = res_pool->audios[i]; 260 261 audio->funcs->hw_init(audio); 262 } 263 264 for (i = 0; i < dc->link_count; i++) { 265 struct dc_link *link = dc->links[i]; 266 267 if (link->panel_cntl) 268 backlight = link->panel_cntl->funcs->hw_init(link->panel_cntl); 269 } 270 271 for (i = 0; i < dc->res_pool->pipe_count; i++) { 272 if (abms[i] != NULL) 273 abms[i]->funcs->abm_init(abms[i], backlight); 274 } 275 276 /* power AFMT HDMI memory TODO: may move to dis/en output save power*/ 277 REG_WRITE(DIO_MEM_PWR_CTRL, 0); 278 279 if (!dc->debug.disable_clock_gate) { 280 /* enable all DCN clock gating */ 281 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); 282 283 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); 284 285 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); 286 } 287 if (hws->funcs.enable_power_gating_plane) 288 hws->funcs.enable_power_gating_plane(dc->hwseq, true); 289 290 if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks) 291 dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub); 292 293 if (dc->clk_mgr->funcs->notify_wm_ranges) 294 dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr); 295 296 if (dc->clk_mgr->funcs->set_hard_max_memclk) 297 dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr); 298 299 if (dc->res_pool->hubbub->funcs->force_pstate_change_control) 300 dc->res_pool->hubbub->funcs->force_pstate_change_control( 301 dc->res_pool->hubbub, false, false); 302 #if defined(CONFIG_DRM_AMD_DC_DCN3_1) 303 if (dc->res_pool->hubbub->funcs->init_crb) 304 dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub); 305 #endif 306 } 307 308 void dcn31_dsc_pg_control( 309 struct dce_hwseq *hws, 310 unsigned int dsc_inst, 311 bool power_on) 312 { 313 uint32_t power_gate = power_on ? 0 : 1; 314 uint32_t pwr_status = power_on ? 0 : 2; 315 uint32_t org_ip_request_cntl = 0; 316 317 if (hws->ctx->dc->debug.disable_dsc_power_gate) 318 return; 319 320 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); 321 if (org_ip_request_cntl == 0) 322 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); 323 324 switch (dsc_inst) { 325 case 0: /* DSC0 */ 326 REG_UPDATE(DOMAIN16_PG_CONFIG, 327 DOMAIN_POWER_GATE, power_gate); 328 329 REG_WAIT(DOMAIN16_PG_STATUS, 330 DOMAIN_PGFSM_PWR_STATUS, pwr_status, 331 1, 1000); 332 break; 333 case 1: /* DSC1 */ 334 REG_UPDATE(DOMAIN17_PG_CONFIG, 335 DOMAIN_POWER_GATE, power_gate); 336 337 REG_WAIT(DOMAIN17_PG_STATUS, 338 DOMAIN_PGFSM_PWR_STATUS, pwr_status, 339 1, 1000); 340 break; 341 case 2: /* DSC2 */ 342 REG_UPDATE(DOMAIN18_PG_CONFIG, 343 DOMAIN_POWER_GATE, power_gate); 344 345 REG_WAIT(DOMAIN18_PG_STATUS, 346 DOMAIN_PGFSM_PWR_STATUS, pwr_status, 347 1, 1000); 348 break; 349 default: 350 BREAK_TO_DEBUGGER(); 351 break; 352 } 353 354 if (org_ip_request_cntl == 0) 355 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); 356 } 357 358 359 void dcn31_enable_power_gating_plane( 360 struct dce_hwseq *hws, 361 bool enable) 362 { 363 bool force_on = true; /* disable power gating */ 364 365 if (enable) 366 force_on = false; 367 368 /* DCHUBP0/1/2/3/4/5 */ 369 REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 370 REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 371 372 /* DPP0/1/2/3/4/5 */ 373 REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 374 REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 375 376 /* DCS0/1/2/3/4/5 */ 377 REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 378 REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 379 REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 380 } 381 382 void dcn31_update_info_frame(struct pipe_ctx *pipe_ctx) 383 { 384 bool is_hdmi_tmds; 385 bool is_dp; 386 387 ASSERT(pipe_ctx->stream); 388 389 if (pipe_ctx->stream_res.stream_enc == NULL) 390 return; /* this is not root pipe */ 391 392 is_hdmi_tmds = dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal); 393 is_dp = dc_is_dp_signal(pipe_ctx->stream->signal); 394 395 if (!is_hdmi_tmds) 396 return; 397 398 if (is_hdmi_tmds) 399 pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets( 400 pipe_ctx->stream_res.stream_enc, 401 &pipe_ctx->stream_res.encoder_info_frame); 402 else { 403 pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets( 404 pipe_ctx->stream_res.stream_enc, 405 &pipe_ctx->stream_res.encoder_info_frame); 406 } 407 } 408 409 void dcn31_z10_restore(struct dc *dc) 410 { 411 union dmub_rb_cmd cmd; 412 413 /* 414 * DMUB notifies whether restore is required. 415 * Optimization to avoid sending commands when not required. 416 */ 417 if (!dc_dmub_srv_is_restore_required(dc->ctx->dmub_srv)) 418 return; 419 420 memset(&cmd, 0, sizeof(cmd)); 421 cmd.dcn_restore.header.type = DMUB_CMD__IDLE_OPT; 422 cmd.dcn_restore.header.sub_type = DMUB_CMD__IDLE_OPT_DCN_RESTORE; 423 424 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd); 425 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv); 426 dc_dmub_srv_wait_idle(dc->ctx->dmub_srv); 427 } 428 429 void dcn31_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on) 430 { 431 uint32_t power_gate = power_on ? 0 : 1; 432 uint32_t pwr_status = power_on ? 0 : 2; 433 434 if (hws->ctx->dc->debug.disable_hubp_power_gate) 435 return; 436 437 if (REG(DOMAIN0_PG_CONFIG) == 0) 438 return; 439 440 switch (hubp_inst) { 441 case 0: 442 REG_SET(DOMAIN0_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 443 REG_WAIT(DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 444 break; 445 case 1: 446 REG_SET(DOMAIN1_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 447 REG_WAIT(DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 448 break; 449 case 2: 450 REG_SET(DOMAIN2_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 451 REG_WAIT(DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 452 break; 453 case 3: 454 REG_SET(DOMAIN3_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 455 REG_WAIT(DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 456 break; 457 default: 458 BREAK_TO_DEBUGGER(); 459 break; 460 } 461 } 462 463 int dcn31_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config) 464 { 465 struct dcn_hubbub_phys_addr_config config; 466 467 config.system_aperture.fb_top = pa_config->system_aperture.fb_top; 468 config.system_aperture.fb_offset = pa_config->system_aperture.fb_offset; 469 config.system_aperture.fb_base = pa_config->system_aperture.fb_base; 470 config.system_aperture.agp_top = pa_config->system_aperture.agp_top; 471 config.system_aperture.agp_bot = pa_config->system_aperture.agp_bot; 472 config.system_aperture.agp_base = pa_config->system_aperture.agp_base; 473 config.gart_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr; 474 config.gart_config.page_table_end_addr = pa_config->gart_config.page_table_end_addr; 475 476 if (pa_config->gart_config.base_addr_is_mc_addr) { 477 /* Convert from MC address to offset into FB */ 478 config.gart_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr - 479 pa_config->system_aperture.fb_base + 480 pa_config->system_aperture.fb_offset; 481 } else 482 config.gart_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr; 483 484 return dc->res_pool->hubbub->funcs->init_dchub_sys_ctx(dc->res_pool->hubbub, &config); 485 } 486 487 static void dcn31_reset_back_end_for_pipe( 488 struct dc *dc, 489 struct pipe_ctx *pipe_ctx, 490 struct dc_state *context) 491 { 492 struct dc_link *link; 493 494 DC_LOGGER_INIT(dc->ctx->logger); 495 if (pipe_ctx->stream_res.stream_enc == NULL) { 496 pipe_ctx->stream = NULL; 497 return; 498 } 499 ASSERT(!pipe_ctx->top_pipe); 500 501 dc->hwss.set_abm_immediate_disable(pipe_ctx); 502 503 pipe_ctx->stream_res.tg->funcs->set_dsc_config( 504 pipe_ctx->stream_res.tg, 505 OPTC_DSC_DISABLED, 0, 0); 506 pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg); 507 508 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false); 509 if (pipe_ctx->stream_res.tg->funcs->set_odm_bypass) 510 pipe_ctx->stream_res.tg->funcs->set_odm_bypass( 511 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); 512 513 if (pipe_ctx->stream_res.tg->funcs->set_drr) 514 pipe_ctx->stream_res.tg->funcs->set_drr( 515 pipe_ctx->stream_res.tg, NULL); 516 517 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { 518 link = pipe_ctx->stream->link; 519 /* DPMS may already disable or */ 520 /* dpms_off status is incorrect due to fastboot 521 * feature. When system resume from S4 with second 522 * screen only, the dpms_off would be true but 523 * VBIOS lit up eDP, so check link status too. 524 */ 525 if (!pipe_ctx->stream->dpms_off || link->link_status.link_active) 526 core_link_disable_stream(pipe_ctx); 527 else if (pipe_ctx->stream_res.audio) 528 dc->hwss.disable_audio_stream(pipe_ctx); 529 530 /* free acquired resources */ 531 if (pipe_ctx->stream_res.audio) { 532 /*disable az_endpoint*/ 533 pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio); 534 535 /*free audio*/ 536 if (dc->caps.dynamic_audio == true) { 537 /*we have to dynamic arbitrate the audio endpoints*/ 538 /*we free the resource, need reset is_audio_acquired*/ 539 update_audio_usage(&dc->current_state->res_ctx, dc->res_pool, 540 pipe_ctx->stream_res.audio, false); 541 pipe_ctx->stream_res.audio = NULL; 542 } 543 } 544 } else if (pipe_ctx->stream_res.dsc) { 545 dp_set_dsc_enable(pipe_ctx, false); 546 } 547 548 pipe_ctx->stream = NULL; 549 DC_LOG_DEBUG("Reset back end for pipe %d, tg:%d\n", 550 pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst); 551 } 552 553 void dcn31_reset_hw_ctx_wrap( 554 struct dc *dc, 555 struct dc_state *context) 556 { 557 int i; 558 struct dce_hwseq *hws = dc->hwseq; 559 560 /* Reset Back End*/ 561 for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) { 562 struct pipe_ctx *pipe_ctx_old = 563 &dc->current_state->res_ctx.pipe_ctx[i]; 564 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 565 566 if (!pipe_ctx_old->stream) 567 continue; 568 569 if (pipe_ctx_old->top_pipe || pipe_ctx_old->prev_odm_pipe) 570 continue; 571 572 if (!pipe_ctx->stream || 573 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) { 574 struct clock_source *old_clk = pipe_ctx_old->clock_source; 575 576 dcn31_reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state); 577 if (hws->funcs.enable_stream_gating) 578 hws->funcs.enable_stream_gating(dc, pipe_ctx); 579 if (old_clk) 580 old_clk->funcs->cs_power_down(old_clk); 581 } 582 } 583 } 584 585 bool dcn31_is_abm_supported(struct dc *dc, 586 struct dc_state *context, struct dc_stream_state *stream) 587 { 588 int i; 589 590 for (i = 0; i < dc->res_pool->pipe_count; i++) { 591 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 592 593 if (pipe_ctx->stream == stream && 594 (pipe_ctx->prev_odm_pipe == NULL && pipe_ctx->next_odm_pipe == NULL)) 595 return true; 596 } 597 return false; 598 } 599