1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 27 #include "dm_services.h" 28 #include "dm_helpers.h" 29 #include "core_types.h" 30 #include "resource.h" 31 #include "dccg.h" 32 #include "dce/dce_hwseq.h" 33 #include "clk_mgr.h" 34 #include "reg_helper.h" 35 #include "abm.h" 36 #include "hubp.h" 37 #include "dchubbub.h" 38 #include "timing_generator.h" 39 #include "opp.h" 40 #include "ipp.h" 41 #include "mpc.h" 42 #include "mcif_wb.h" 43 #include "dc_dmub_srv.h" 44 #include "dcn31_hwseq.h" 45 #include "link_hwss.h" 46 #include "dpcd_defs.h" 47 #include "dce/dmub_outbox.h" 48 #include "link.h" 49 #include "dcn10/dcn10_hw_sequencer.h" 50 #include "inc/link_enc_cfg.h" 51 #include "dcn30/dcn30_vpg.h" 52 #include "dce/dce_i2c_hw.h" 53 54 #define DC_LOGGER_INIT(logger) 55 56 #define CTX \ 57 hws->ctx 58 #define REG(reg)\ 59 hws->regs->reg 60 #define DC_LOGGER \ 61 dc->ctx->logger 62 63 64 #undef FN 65 #define FN(reg_name, field_name) \ 66 hws->shifts->field_name, hws->masks->field_name 67 68 static void enable_memory_low_power(struct dc *dc) 69 { 70 struct dce_hwseq *hws = dc->hwseq; 71 int i; 72 73 if (dc->debug.enable_mem_low_power.bits.dmcu) { 74 // Force ERAM to shutdown if DMCU is not enabled 75 if (dc->debug.disable_dmcu || dc->config.disable_dmcu) { 76 REG_UPDATE(DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, 3); 77 } 78 } 79 80 // Set default OPTC memory power states 81 if (dc->debug.enable_mem_low_power.bits.optc) { 82 // Shutdown when unassigned and light sleep in VBLANK 83 REG_SET_2(ODM_MEM_PWR_CTRL3, 0, ODM_MEM_UNASSIGNED_PWR_MODE, 3, ODM_MEM_VBLANK_PWR_MODE, 1); 84 } 85 86 if (dc->debug.enable_mem_low_power.bits.vga) { 87 // Power down VGA memory 88 REG_UPDATE(MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, 1); 89 } 90 91 if (dc->debug.enable_mem_low_power.bits.mpc && 92 dc->res_pool->mpc->funcs->set_mpc_mem_lp_mode) 93 dc->res_pool->mpc->funcs->set_mpc_mem_lp_mode(dc->res_pool->mpc); 94 95 96 if (dc->debug.enable_mem_low_power.bits.vpg && dc->res_pool->stream_enc[0]->vpg->funcs->vpg_powerdown) { 97 // Power down VPGs 98 for (i = 0; i < dc->res_pool->stream_enc_count; i++) 99 dc->res_pool->stream_enc[i]->vpg->funcs->vpg_powerdown(dc->res_pool->stream_enc[i]->vpg); 100 #if defined(CONFIG_DRM_AMD_DC_DCN) 101 for (i = 0; i < dc->res_pool->hpo_dp_stream_enc_count; i++) 102 dc->res_pool->hpo_dp_stream_enc[i]->vpg->funcs->vpg_powerdown(dc->res_pool->hpo_dp_stream_enc[i]->vpg); 103 #endif 104 } 105 106 } 107 108 void dcn31_init_hw(struct dc *dc) 109 { 110 struct abm **abms = dc->res_pool->multiple_abms; 111 struct dce_hwseq *hws = dc->hwseq; 112 struct dc_bios *dcb = dc->ctx->dc_bios; 113 struct resource_pool *res_pool = dc->res_pool; 114 uint32_t backlight = MAX_BACKLIGHT_LEVEL; 115 int i; 116 117 if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks) 118 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr); 119 120 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { 121 122 REG_WRITE(REFCLK_CNTL, 0); 123 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1); 124 REG_WRITE(DIO_MEM_PWR_CTRL, 0); 125 126 if (!dc->debug.disable_clock_gate) { 127 /* enable all DCN clock gating */ 128 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); 129 130 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); 131 132 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); 133 } 134 135 //Enable ability to power gate / don't force power on permanently 136 if (hws->funcs.enable_power_gating_plane) 137 hws->funcs.enable_power_gating_plane(hws, true); 138 139 return; 140 } 141 142 if (!dcb->funcs->is_accelerated_mode(dcb)) { 143 hws->funcs.bios_golden_init(dc); 144 if (hws->funcs.disable_vga) 145 hws->funcs.disable_vga(dc->hwseq); 146 } 147 // Initialize the dccg 148 if (res_pool->dccg->funcs->dccg_init) 149 res_pool->dccg->funcs->dccg_init(res_pool->dccg); 150 151 enable_memory_low_power(dc); 152 153 if (dc->ctx->dc_bios->fw_info_valid) { 154 res_pool->ref_clocks.xtalin_clock_inKhz = 155 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency; 156 157 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { 158 if (res_pool->dccg && res_pool->hubbub) { 159 160 (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg, 161 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency, 162 &res_pool->ref_clocks.dccg_ref_clock_inKhz); 163 164 (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub, 165 res_pool->ref_clocks.dccg_ref_clock_inKhz, 166 &res_pool->ref_clocks.dchub_ref_clock_inKhz); 167 } else { 168 // Not all ASICs have DCCG sw component 169 res_pool->ref_clocks.dccg_ref_clock_inKhz = 170 res_pool->ref_clocks.xtalin_clock_inKhz; 171 res_pool->ref_clocks.dchub_ref_clock_inKhz = 172 res_pool->ref_clocks.xtalin_clock_inKhz; 173 } 174 } 175 } else 176 ASSERT_CRITICAL(false); 177 178 for (i = 0; i < dc->link_count; i++) { 179 /* Power up AND update implementation according to the 180 * required signal (which may be different from the 181 * default signal on connector). 182 */ 183 struct dc_link *link = dc->links[i]; 184 185 if (link->ep_type != DISPLAY_ENDPOINT_PHY) 186 continue; 187 188 link->link_enc->funcs->hw_init(link->link_enc); 189 190 /* Check for enabled DIG to identify enabled display */ 191 if (link->link_enc->funcs->is_dig_enabled && 192 link->link_enc->funcs->is_dig_enabled(link->link_enc)) { 193 link->link_status.link_active = true; 194 if (link->link_enc->funcs->fec_is_active && 195 link->link_enc->funcs->fec_is_active(link->link_enc)) 196 link->fec_state = dc_link_fec_enabled; 197 } 198 } 199 200 /* Enables outbox notifications for usb4 dpia */ 201 if (dc->res_pool->usb4_dpia_count) 202 dmub_enable_outbox_notification(dc->ctx->dmub_srv); 203 204 /* we want to turn off all dp displays before doing detection */ 205 link_blank_all_dp_displays(dc); 206 207 if (hws->funcs.enable_power_gating_plane) 208 hws->funcs.enable_power_gating_plane(dc->hwseq, true); 209 210 /* If taking control over from VBIOS, we may want to optimize our first 211 * mode set, so we need to skip powering down pipes until we know which 212 * pipes we want to use. 213 * Otherwise, if taking control is not possible, we need to power 214 * everything down. 215 */ 216 if (dcb->funcs->is_accelerated_mode(dcb) || !dc->config.seamless_boot_edp_requested) { 217 218 // we want to turn off edp displays if odm is enabled and no seamless boot 219 if (!dc->caps.seamless_odm) { 220 for (i = 0; i < dc->res_pool->timing_generator_count; i++) { 221 struct timing_generator *tg = dc->res_pool->timing_generators[i]; 222 uint32_t num_opps, opp_id_src0, opp_id_src1; 223 224 num_opps = 1; 225 if (tg) { 226 if (tg->funcs->is_tg_enabled(tg) && tg->funcs->get_optc_source) { 227 tg->funcs->get_optc_source(tg, &num_opps, 228 &opp_id_src0, &opp_id_src1); 229 } 230 } 231 232 if (num_opps > 1) { 233 link_blank_all_edp_displays(dc); 234 break; 235 } 236 } 237 } 238 239 hws->funcs.init_pipes(dc, dc->current_state); 240 if (dc->res_pool->hubbub->funcs->allow_self_refresh_control) 241 dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, 242 !dc->res_pool->hubbub->ctx->dc->debug.disable_stutter); 243 } 244 245 for (i = 0; i < res_pool->audio_count; i++) { 246 struct audio *audio = res_pool->audios[i]; 247 248 audio->funcs->hw_init(audio); 249 } 250 251 for (i = 0; i < dc->link_count; i++) { 252 struct dc_link *link = dc->links[i]; 253 254 if (link->panel_cntl) 255 backlight = link->panel_cntl->funcs->hw_init(link->panel_cntl); 256 } 257 258 for (i = 0; i < dc->res_pool->pipe_count; i++) { 259 if (abms[i] != NULL) 260 abms[i]->funcs->abm_init(abms[i], backlight); 261 } 262 263 /* power AFMT HDMI memory TODO: may move to dis/en output save power*/ 264 REG_WRITE(DIO_MEM_PWR_CTRL, 0); 265 266 // Set i2c to light sleep until engine is setup 267 if (dc->debug.enable_mem_low_power.bits.i2c) 268 REG_UPDATE(DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, 1); 269 270 if (hws->funcs.setup_hpo_hw_control) 271 hws->funcs.setup_hpo_hw_control(hws, false); 272 273 if (!dc->debug.disable_clock_gate) { 274 /* enable all DCN clock gating */ 275 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); 276 277 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); 278 279 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); 280 } 281 282 if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks) 283 dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub); 284 285 if (dc->clk_mgr->funcs->notify_wm_ranges) 286 dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr); 287 288 if (dc->clk_mgr->funcs->set_hard_max_memclk) 289 dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr); 290 291 if (dc->res_pool->hubbub->funcs->force_pstate_change_control) 292 dc->res_pool->hubbub->funcs->force_pstate_change_control( 293 dc->res_pool->hubbub, false, false); 294 #if defined(CONFIG_DRM_AMD_DC_DCN) 295 if (dc->res_pool->hubbub->funcs->init_crb) 296 dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub); 297 #endif 298 } 299 300 void dcn31_dsc_pg_control( 301 struct dce_hwseq *hws, 302 unsigned int dsc_inst, 303 bool power_on) 304 { 305 uint32_t power_gate = power_on ? 0 : 1; 306 uint32_t pwr_status = power_on ? 0 : 2; 307 uint32_t org_ip_request_cntl = 0; 308 309 if (hws->ctx->dc->debug.disable_dsc_power_gate) 310 return; 311 312 if (hws->ctx->dc->debug.root_clock_optimization.bits.dsc && 313 hws->ctx->dc->res_pool->dccg->funcs->enable_dsc && 314 power_on) 315 hws->ctx->dc->res_pool->dccg->funcs->enable_dsc( 316 hws->ctx->dc->res_pool->dccg, dsc_inst); 317 318 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); 319 if (org_ip_request_cntl == 0) 320 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); 321 322 switch (dsc_inst) { 323 case 0: /* DSC0 */ 324 REG_UPDATE(DOMAIN16_PG_CONFIG, 325 DOMAIN_POWER_GATE, power_gate); 326 327 REG_WAIT(DOMAIN16_PG_STATUS, 328 DOMAIN_PGFSM_PWR_STATUS, pwr_status, 329 1, 1000); 330 break; 331 case 1: /* DSC1 */ 332 REG_UPDATE(DOMAIN17_PG_CONFIG, 333 DOMAIN_POWER_GATE, power_gate); 334 335 REG_WAIT(DOMAIN17_PG_STATUS, 336 DOMAIN_PGFSM_PWR_STATUS, pwr_status, 337 1, 1000); 338 break; 339 case 2: /* DSC2 */ 340 REG_UPDATE(DOMAIN18_PG_CONFIG, 341 DOMAIN_POWER_GATE, power_gate); 342 343 REG_WAIT(DOMAIN18_PG_STATUS, 344 DOMAIN_PGFSM_PWR_STATUS, pwr_status, 345 1, 1000); 346 break; 347 default: 348 BREAK_TO_DEBUGGER(); 349 break; 350 } 351 352 if (org_ip_request_cntl == 0) 353 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); 354 355 if (hws->ctx->dc->debug.root_clock_optimization.bits.dsc) { 356 if (hws->ctx->dc->res_pool->dccg->funcs->disable_dsc && !power_on) 357 hws->ctx->dc->res_pool->dccg->funcs->disable_dsc( 358 hws->ctx->dc->res_pool->dccg, dsc_inst); 359 } 360 361 } 362 363 364 void dcn31_enable_power_gating_plane( 365 struct dce_hwseq *hws, 366 bool enable) 367 { 368 bool force_on = true; /* disable power gating */ 369 uint32_t org_ip_request_cntl = 0; 370 371 if (enable && !hws->ctx->dc->debug.disable_hubp_power_gate) 372 force_on = false; 373 374 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); 375 if (org_ip_request_cntl == 0) 376 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); 377 /* DCHUBP0/1/2/3/4/5 */ 378 REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 379 REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 380 /* DPP0/1/2/3/4/5 */ 381 REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 382 REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 383 384 force_on = true; /* disable power gating */ 385 if (enable && !hws->ctx->dc->debug.disable_dsc_power_gate) 386 force_on = false; 387 388 /* DCS0/1/2/3/4/5 */ 389 REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 390 REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 391 REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 392 393 if (org_ip_request_cntl == 0) 394 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); 395 } 396 397 void dcn31_update_info_frame(struct pipe_ctx *pipe_ctx) 398 { 399 bool is_hdmi_tmds; 400 bool is_dp; 401 402 ASSERT(pipe_ctx->stream); 403 404 if (pipe_ctx->stream_res.stream_enc == NULL) 405 return; /* this is not root pipe */ 406 407 is_hdmi_tmds = dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal); 408 is_dp = dc_is_dp_signal(pipe_ctx->stream->signal); 409 410 if (!is_hdmi_tmds && !is_dp) 411 return; 412 413 if (is_hdmi_tmds) 414 pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets( 415 pipe_ctx->stream_res.stream_enc, 416 &pipe_ctx->stream_res.encoder_info_frame); 417 else if (link_is_dp_128b_132b_signal(pipe_ctx)) { 418 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->update_dp_info_packets( 419 pipe_ctx->stream_res.hpo_dp_stream_enc, 420 &pipe_ctx->stream_res.encoder_info_frame); 421 return; 422 } else { 423 if (pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets_sdp_line_num) 424 pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets_sdp_line_num( 425 pipe_ctx->stream_res.stream_enc, 426 &pipe_ctx->stream_res.encoder_info_frame); 427 428 pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets( 429 pipe_ctx->stream_res.stream_enc, 430 &pipe_ctx->stream_res.encoder_info_frame); 431 } 432 } 433 void dcn31_z10_save_init(struct dc *dc) 434 { 435 union dmub_rb_cmd cmd; 436 437 memset(&cmd, 0, sizeof(cmd)); 438 cmd.dcn_restore.header.type = DMUB_CMD__IDLE_OPT; 439 cmd.dcn_restore.header.sub_type = DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT; 440 441 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd); 442 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv); 443 dc_dmub_srv_wait_idle(dc->ctx->dmub_srv); 444 } 445 446 void dcn31_z10_restore(const struct dc *dc) 447 { 448 union dmub_rb_cmd cmd; 449 450 /* 451 * DMUB notifies whether restore is required. 452 * Optimization to avoid sending commands when not required. 453 */ 454 if (!dc_dmub_srv_is_restore_required(dc->ctx->dmub_srv)) 455 return; 456 457 memset(&cmd, 0, sizeof(cmd)); 458 cmd.dcn_restore.header.type = DMUB_CMD__IDLE_OPT; 459 cmd.dcn_restore.header.sub_type = DMUB_CMD__IDLE_OPT_DCN_RESTORE; 460 461 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd); 462 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv); 463 dc_dmub_srv_wait_idle(dc->ctx->dmub_srv); 464 } 465 466 void dcn31_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on) 467 { 468 uint32_t power_gate = power_on ? 0 : 1; 469 uint32_t pwr_status = power_on ? 0 : 2; 470 uint32_t org_ip_request_cntl; 471 if (hws->ctx->dc->debug.disable_hubp_power_gate) 472 return; 473 474 if (REG(DOMAIN0_PG_CONFIG) == 0) 475 return; 476 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); 477 if (org_ip_request_cntl == 0) 478 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); 479 480 switch (hubp_inst) { 481 case 0: 482 REG_SET(DOMAIN0_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 483 REG_WAIT(DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 484 break; 485 case 1: 486 REG_SET(DOMAIN1_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 487 REG_WAIT(DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 488 break; 489 case 2: 490 REG_SET(DOMAIN2_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 491 REG_WAIT(DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 492 break; 493 case 3: 494 REG_SET(DOMAIN3_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 495 REG_WAIT(DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 496 break; 497 default: 498 BREAK_TO_DEBUGGER(); 499 break; 500 } 501 if (org_ip_request_cntl == 0) 502 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); 503 } 504 505 int dcn31_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config) 506 { 507 struct dcn_hubbub_phys_addr_config config; 508 509 config.system_aperture.fb_top = pa_config->system_aperture.fb_top; 510 config.system_aperture.fb_offset = pa_config->system_aperture.fb_offset; 511 config.system_aperture.fb_base = pa_config->system_aperture.fb_base; 512 config.system_aperture.agp_top = pa_config->system_aperture.agp_top; 513 config.system_aperture.agp_bot = pa_config->system_aperture.agp_bot; 514 config.system_aperture.agp_base = pa_config->system_aperture.agp_base; 515 config.gart_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr; 516 config.gart_config.page_table_end_addr = pa_config->gart_config.page_table_end_addr; 517 518 if (pa_config->gart_config.base_addr_is_mc_addr) { 519 /* Convert from MC address to offset into FB */ 520 config.gart_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr - 521 pa_config->system_aperture.fb_base + 522 pa_config->system_aperture.fb_offset; 523 } else 524 config.gart_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr; 525 526 return dc->res_pool->hubbub->funcs->init_dchub_sys_ctx(dc->res_pool->hubbub, &config); 527 } 528 529 static void dcn31_reset_back_end_for_pipe( 530 struct dc *dc, 531 struct pipe_ctx *pipe_ctx, 532 struct dc_state *context) 533 { 534 struct dc_link *link; 535 536 DC_LOGGER_INIT(dc->ctx->logger); 537 if (pipe_ctx->stream_res.stream_enc == NULL) { 538 pipe_ctx->stream = NULL; 539 return; 540 } 541 ASSERT(!pipe_ctx->top_pipe); 542 543 dc->hwss.set_abm_immediate_disable(pipe_ctx); 544 545 pipe_ctx->stream_res.tg->funcs->set_dsc_config( 546 pipe_ctx->stream_res.tg, 547 OPTC_DSC_DISABLED, 0, 0); 548 pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg); 549 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false); 550 if (pipe_ctx->stream_res.tg->funcs->set_odm_bypass) 551 pipe_ctx->stream_res.tg->funcs->set_odm_bypass( 552 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); 553 pipe_ctx->stream->link->phy_state.symclk_ref_cnts.otg = 0; 554 555 if (pipe_ctx->stream_res.tg->funcs->set_drr) 556 pipe_ctx->stream_res.tg->funcs->set_drr( 557 pipe_ctx->stream_res.tg, NULL); 558 559 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { 560 link = pipe_ctx->stream->link; 561 /* DPMS may already disable or */ 562 /* dpms_off status is incorrect due to fastboot 563 * feature. When system resume from S4 with second 564 * screen only, the dpms_off would be true but 565 * VBIOS lit up eDP, so check link status too. 566 */ 567 if (!pipe_ctx->stream->dpms_off || link->link_status.link_active) 568 link_set_dpms_off(pipe_ctx); 569 else if (pipe_ctx->stream_res.audio) 570 dc->hwss.disable_audio_stream(pipe_ctx); 571 572 /* free acquired resources */ 573 if (pipe_ctx->stream_res.audio) { 574 /*disable az_endpoint*/ 575 pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio); 576 577 /*free audio*/ 578 if (dc->caps.dynamic_audio == true) { 579 /*we have to dynamic arbitrate the audio endpoints*/ 580 /*we free the resource, need reset is_audio_acquired*/ 581 update_audio_usage(&dc->current_state->res_ctx, dc->res_pool, 582 pipe_ctx->stream_res.audio, false); 583 pipe_ctx->stream_res.audio = NULL; 584 } 585 } 586 } else if (pipe_ctx->stream_res.dsc) { 587 link_set_dsc_enable(pipe_ctx, false); 588 } 589 590 pipe_ctx->stream = NULL; 591 DC_LOG_DEBUG("Reset back end for pipe %d, tg:%d\n", 592 pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst); 593 } 594 595 void dcn31_reset_hw_ctx_wrap( 596 struct dc *dc, 597 struct dc_state *context) 598 { 599 int i; 600 struct dce_hwseq *hws = dc->hwseq; 601 602 /* Reset Back End*/ 603 for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) { 604 struct pipe_ctx *pipe_ctx_old = 605 &dc->current_state->res_ctx.pipe_ctx[i]; 606 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 607 608 if (!pipe_ctx_old->stream) 609 continue; 610 611 if (pipe_ctx_old->top_pipe || pipe_ctx_old->prev_odm_pipe) 612 continue; 613 614 if (!pipe_ctx->stream || 615 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) { 616 struct clock_source *old_clk = pipe_ctx_old->clock_source; 617 618 dcn31_reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state); 619 if (hws->funcs.enable_stream_gating) 620 hws->funcs.enable_stream_gating(dc, pipe_ctx_old); 621 if (old_clk) 622 old_clk->funcs->cs_power_down(old_clk); 623 } 624 } 625 626 /* New dc_state in the process of being applied to hardware. */ 627 link_enc_cfg_set_transient_mode(dc, dc->current_state, context); 628 } 629 630 void dcn31_setup_hpo_hw_control(const struct dce_hwseq *hws, bool enable) 631 { 632 if (hws->ctx->dc->debug.hpo_optimization) 633 REG_UPDATE(HPO_TOP_HW_CONTROL, HPO_IO_EN, !!enable); 634 } 635