1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 27 #include "dm_services.h" 28 #include "dm_helpers.h" 29 #include "core_types.h" 30 #include "resource.h" 31 #include "dccg.h" 32 #include "dce/dce_hwseq.h" 33 #include "clk_mgr.h" 34 #include "reg_helper.h" 35 #include "abm.h" 36 #include "hubp.h" 37 #include "dchubbub.h" 38 #include "timing_generator.h" 39 #include "opp.h" 40 #include "ipp.h" 41 #include "mpc.h" 42 #include "mcif_wb.h" 43 #include "dc_dmub_srv.h" 44 #include "dcn31_hwseq.h" 45 #include "link_hwss.h" 46 #include "dpcd_defs.h" 47 #include "dce/dmub_outbox.h" 48 #include "dc_link_dp.h" 49 #include "inc/link_dpcd.h" 50 #include "dcn10/dcn10_hw_sequencer.h" 51 #include "inc/link_enc_cfg.h" 52 #include "dcn30/dcn30_vpg.h" 53 #include "dce/dce_i2c_hw.h" 54 55 #define DC_LOGGER_INIT(logger) 56 57 #define CTX \ 58 hws->ctx 59 #define REG(reg)\ 60 hws->regs->reg 61 #define DC_LOGGER \ 62 dc->ctx->logger 63 64 65 #undef FN 66 #define FN(reg_name, field_name) \ 67 hws->shifts->field_name, hws->masks->field_name 68 69 static void enable_memory_low_power(struct dc *dc) 70 { 71 struct dce_hwseq *hws = dc->hwseq; 72 int i; 73 74 if (dc->debug.enable_mem_low_power.bits.dmcu) { 75 // Force ERAM to shutdown if DMCU is not enabled 76 if (dc->debug.disable_dmcu || dc->config.disable_dmcu) { 77 REG_UPDATE(DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, 3); 78 } 79 } 80 81 // Set default OPTC memory power states 82 if (dc->debug.enable_mem_low_power.bits.optc) { 83 // Shutdown when unassigned and light sleep in VBLANK 84 REG_SET_2(ODM_MEM_PWR_CTRL3, 0, ODM_MEM_UNASSIGNED_PWR_MODE, 3, ODM_MEM_VBLANK_PWR_MODE, 1); 85 } 86 87 if (dc->debug.enable_mem_low_power.bits.vga) { 88 // Power down VGA memory 89 REG_UPDATE(MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, 1); 90 } 91 92 if (dc->debug.enable_mem_low_power.bits.mpc) 93 dc->res_pool->mpc->funcs->set_mpc_mem_lp_mode(dc->res_pool->mpc); 94 95 96 if (dc->debug.enable_mem_low_power.bits.vpg && dc->res_pool->stream_enc[0]->vpg->funcs->vpg_powerdown) { 97 // Power down VPGs 98 for (i = 0; i < dc->res_pool->stream_enc_count; i++) 99 dc->res_pool->stream_enc[i]->vpg->funcs->vpg_powerdown(dc->res_pool->stream_enc[i]->vpg); 100 #if defined(CONFIG_DRM_AMD_DC_DCN) 101 for (i = 0; i < dc->res_pool->hpo_dp_stream_enc_count; i++) 102 dc->res_pool->hpo_dp_stream_enc[i]->vpg->funcs->vpg_powerdown(dc->res_pool->hpo_dp_stream_enc[i]->vpg); 103 #endif 104 } 105 106 } 107 108 void dcn31_init_hw(struct dc *dc) 109 { 110 struct abm **abms = dc->res_pool->multiple_abms; 111 struct dce_hwseq *hws = dc->hwseq; 112 struct dc_bios *dcb = dc->ctx->dc_bios; 113 struct resource_pool *res_pool = dc->res_pool; 114 uint32_t backlight = MAX_BACKLIGHT_LEVEL; 115 int i, j; 116 117 if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks) 118 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr); 119 120 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { 121 122 REG_WRITE(REFCLK_CNTL, 0); 123 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1); 124 REG_WRITE(DIO_MEM_PWR_CTRL, 0); 125 126 if (!dc->debug.disable_clock_gate) { 127 /* enable all DCN clock gating */ 128 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); 129 130 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); 131 132 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); 133 } 134 135 //Enable ability to power gate / don't force power on permanently 136 if (hws->funcs.enable_power_gating_plane) 137 hws->funcs.enable_power_gating_plane(hws, true); 138 139 return; 140 } 141 142 if (!dcb->funcs->is_accelerated_mode(dcb)) { 143 hws->funcs.bios_golden_init(dc); 144 hws->funcs.disable_vga(dc->hwseq); 145 } 146 // Initialize the dccg 147 if (res_pool->dccg->funcs->dccg_init) 148 res_pool->dccg->funcs->dccg_init(res_pool->dccg); 149 150 enable_memory_low_power(dc); 151 152 if (dc->ctx->dc_bios->fw_info_valid) { 153 res_pool->ref_clocks.xtalin_clock_inKhz = 154 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency; 155 156 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { 157 if (res_pool->dccg && res_pool->hubbub) { 158 159 (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg, 160 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency, 161 &res_pool->ref_clocks.dccg_ref_clock_inKhz); 162 163 (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub, 164 res_pool->ref_clocks.dccg_ref_clock_inKhz, 165 &res_pool->ref_clocks.dchub_ref_clock_inKhz); 166 } else { 167 // Not all ASICs have DCCG sw component 168 res_pool->ref_clocks.dccg_ref_clock_inKhz = 169 res_pool->ref_clocks.xtalin_clock_inKhz; 170 res_pool->ref_clocks.dchub_ref_clock_inKhz = 171 res_pool->ref_clocks.xtalin_clock_inKhz; 172 } 173 } 174 } else 175 ASSERT_CRITICAL(false); 176 177 for (i = 0; i < dc->link_count; i++) { 178 /* Power up AND update implementation according to the 179 * required signal (which may be different from the 180 * default signal on connector). 181 */ 182 struct dc_link *link = dc->links[i]; 183 184 if (link->ep_type != DISPLAY_ENDPOINT_PHY) 185 continue; 186 187 link->link_enc->funcs->hw_init(link->link_enc); 188 189 /* Check for enabled DIG to identify enabled display */ 190 if (link->link_enc->funcs->is_dig_enabled && 191 link->link_enc->funcs->is_dig_enabled(link->link_enc)) 192 link->link_status.link_active = true; 193 } 194 195 /* Power gate DSCs */ 196 for (i = 0; i < res_pool->res_cap->num_dsc; i++) 197 if (hws->funcs.dsc_pg_control != NULL) 198 hws->funcs.dsc_pg_control(hws, res_pool->dscs[i]->inst, false); 199 200 /* Enables outbox notifications for usb4 dpia */ 201 if (dc->res_pool->usb4_dpia_count) 202 dmub_enable_outbox_notification(dc); 203 204 /* we want to turn off all dp displays before doing detection */ 205 if (dc->config.power_down_display_on_boot) { 206 uint8_t dpcd_power_state = '\0'; 207 enum dc_status status = DC_ERROR_UNEXPECTED; 208 209 for (i = 0; i < dc->link_count; i++) { 210 if (dc->links[i]->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) 211 continue; 212 213 /* if any of the displays are lit up turn them off */ 214 status = core_link_read_dpcd(dc->links[i], DP_SET_POWER, 215 &dpcd_power_state, sizeof(dpcd_power_state)); 216 if (status == DC_OK && dpcd_power_state == DP_POWER_STATE_D0) { 217 /* blank dp stream before power off receiver*/ 218 if (dc->links[i]->ep_type == DISPLAY_ENDPOINT_PHY && 219 dc->links[i]->link_enc->funcs->get_dig_frontend) { 220 unsigned int fe; 221 222 fe = dc->links[i]->link_enc->funcs->get_dig_frontend( 223 dc->links[i]->link_enc); 224 if (fe == ENGINE_ID_UNKNOWN) 225 continue; 226 227 for (j = 0; j < dc->res_pool->stream_enc_count; j++) { 228 if (fe == dc->res_pool->stream_enc[j]->id) { 229 dc->res_pool->stream_enc[j]->funcs->dp_blank(dc->links[i], 230 dc->res_pool->stream_enc[j]); 231 break; 232 } 233 } 234 } 235 dp_receiver_power_ctrl(dc->links[i], false); 236 } 237 } 238 } 239 240 /* If taking control over from VBIOS, we may want to optimize our first 241 * mode set, so we need to skip powering down pipes until we know which 242 * pipes we want to use. 243 * Otherwise, if taking control is not possible, we need to power 244 * everything down. 245 */ 246 if (dcb->funcs->is_accelerated_mode(dcb) || dc->config.power_down_display_on_boot) { 247 hws->funcs.init_pipes(dc, dc->current_state); 248 if (dc->res_pool->hubbub->funcs->allow_self_refresh_control) 249 dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, 250 !dc->res_pool->hubbub->ctx->dc->debug.disable_stutter); 251 } 252 253 for (i = 0; i < res_pool->audio_count; i++) { 254 struct audio *audio = res_pool->audios[i]; 255 256 audio->funcs->hw_init(audio); 257 } 258 259 for (i = 0; i < dc->link_count; i++) { 260 struct dc_link *link = dc->links[i]; 261 262 if (link->panel_cntl) 263 backlight = link->panel_cntl->funcs->hw_init(link->panel_cntl); 264 } 265 266 for (i = 0; i < dc->res_pool->pipe_count; i++) { 267 if (abms[i] != NULL) 268 abms[i]->funcs->abm_init(abms[i], backlight); 269 } 270 271 /* power AFMT HDMI memory TODO: may move to dis/en output save power*/ 272 REG_WRITE(DIO_MEM_PWR_CTRL, 0); 273 274 // Set i2c to light sleep until engine is setup 275 if (dc->debug.enable_mem_low_power.bits.i2c) 276 REG_UPDATE(DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, 1); 277 278 if (hws->funcs.setup_hpo_hw_control) 279 hws->funcs.setup_hpo_hw_control(hws, false); 280 281 if (!dc->debug.disable_clock_gate) { 282 /* enable all DCN clock gating */ 283 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); 284 285 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); 286 287 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); 288 } 289 if (hws->funcs.enable_power_gating_plane) 290 hws->funcs.enable_power_gating_plane(dc->hwseq, true); 291 292 if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks) 293 dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub); 294 295 if (dc->clk_mgr->funcs->notify_wm_ranges) 296 dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr); 297 298 if (dc->clk_mgr->funcs->set_hard_max_memclk) 299 dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr); 300 301 if (dc->res_pool->hubbub->funcs->force_pstate_change_control) 302 dc->res_pool->hubbub->funcs->force_pstate_change_control( 303 dc->res_pool->hubbub, false, false); 304 #if defined(CONFIG_DRM_AMD_DC_DCN) 305 if (dc->res_pool->hubbub->funcs->init_crb) 306 dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub); 307 #endif 308 } 309 310 void dcn31_dsc_pg_control( 311 struct dce_hwseq *hws, 312 unsigned int dsc_inst, 313 bool power_on) 314 { 315 uint32_t power_gate = power_on ? 0 : 1; 316 uint32_t pwr_status = power_on ? 0 : 2; 317 uint32_t org_ip_request_cntl = 0; 318 319 if (hws->ctx->dc->debug.disable_dsc_power_gate) 320 return; 321 322 if (hws->ctx->dc->debug.root_clock_optimization.bits.dsc && 323 hws->ctx->dc->res_pool->dccg->funcs->enable_dsc && 324 power_on) 325 hws->ctx->dc->res_pool->dccg->funcs->enable_dsc( 326 hws->ctx->dc->res_pool->dccg, dsc_inst); 327 328 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); 329 if (org_ip_request_cntl == 0) 330 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); 331 332 switch (dsc_inst) { 333 case 0: /* DSC0 */ 334 REG_UPDATE(DOMAIN16_PG_CONFIG, 335 DOMAIN_POWER_GATE, power_gate); 336 337 REG_WAIT(DOMAIN16_PG_STATUS, 338 DOMAIN_PGFSM_PWR_STATUS, pwr_status, 339 1, 1000); 340 break; 341 case 1: /* DSC1 */ 342 REG_UPDATE(DOMAIN17_PG_CONFIG, 343 DOMAIN_POWER_GATE, power_gate); 344 345 REG_WAIT(DOMAIN17_PG_STATUS, 346 DOMAIN_PGFSM_PWR_STATUS, pwr_status, 347 1, 1000); 348 break; 349 case 2: /* DSC2 */ 350 REG_UPDATE(DOMAIN18_PG_CONFIG, 351 DOMAIN_POWER_GATE, power_gate); 352 353 REG_WAIT(DOMAIN18_PG_STATUS, 354 DOMAIN_PGFSM_PWR_STATUS, pwr_status, 355 1, 1000); 356 break; 357 default: 358 BREAK_TO_DEBUGGER(); 359 break; 360 } 361 362 if (org_ip_request_cntl == 0) 363 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); 364 365 if (hws->ctx->dc->debug.root_clock_optimization.bits.dsc) { 366 if (hws->ctx->dc->res_pool->dccg->funcs->disable_dsc && !power_on) 367 hws->ctx->dc->res_pool->dccg->funcs->disable_dsc( 368 hws->ctx->dc->res_pool->dccg, dsc_inst); 369 } 370 371 } 372 373 374 void dcn31_enable_power_gating_plane( 375 struct dce_hwseq *hws, 376 bool enable) 377 { 378 bool force_on = true; /* disable power gating */ 379 380 if (enable) 381 force_on = false; 382 383 /* DCHUBP0/1/2/3/4/5 */ 384 REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 385 REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 386 387 /* DPP0/1/2/3/4/5 */ 388 REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 389 REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 390 391 /* DCS0/1/2/3/4/5 */ 392 REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 393 REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 394 REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 395 } 396 397 void dcn31_update_info_frame(struct pipe_ctx *pipe_ctx) 398 { 399 bool is_hdmi_tmds; 400 bool is_dp; 401 402 ASSERT(pipe_ctx->stream); 403 404 if (pipe_ctx->stream_res.stream_enc == NULL) 405 return; /* this is not root pipe */ 406 407 is_hdmi_tmds = dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal); 408 is_dp = dc_is_dp_signal(pipe_ctx->stream->signal); 409 410 if (!is_hdmi_tmds && !is_dp) 411 return; 412 413 if (is_hdmi_tmds) 414 pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets( 415 pipe_ctx->stream_res.stream_enc, 416 &pipe_ctx->stream_res.encoder_info_frame); 417 else { 418 pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets( 419 pipe_ctx->stream_res.stream_enc, 420 &pipe_ctx->stream_res.encoder_info_frame); 421 } 422 } 423 void dcn31_z10_save_init(struct dc *dc) 424 { 425 union dmub_rb_cmd cmd; 426 427 memset(&cmd, 0, sizeof(cmd)); 428 cmd.dcn_restore.header.type = DMUB_CMD__IDLE_OPT; 429 cmd.dcn_restore.header.sub_type = DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT; 430 431 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd); 432 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv); 433 dc_dmub_srv_wait_idle(dc->ctx->dmub_srv); 434 } 435 436 void dcn31_z10_restore(const struct dc *dc) 437 { 438 union dmub_rb_cmd cmd; 439 440 /* 441 * DMUB notifies whether restore is required. 442 * Optimization to avoid sending commands when not required. 443 */ 444 if (!dc_dmub_srv_is_restore_required(dc->ctx->dmub_srv)) 445 return; 446 447 memset(&cmd, 0, sizeof(cmd)); 448 cmd.dcn_restore.header.type = DMUB_CMD__IDLE_OPT; 449 cmd.dcn_restore.header.sub_type = DMUB_CMD__IDLE_OPT_DCN_RESTORE; 450 451 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd); 452 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv); 453 dc_dmub_srv_wait_idle(dc->ctx->dmub_srv); 454 } 455 456 void dcn31_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on) 457 { 458 uint32_t power_gate = power_on ? 0 : 1; 459 uint32_t pwr_status = power_on ? 0 : 2; 460 461 if (hws->ctx->dc->debug.disable_hubp_power_gate) 462 return; 463 464 if (REG(DOMAIN0_PG_CONFIG) == 0) 465 return; 466 467 switch (hubp_inst) { 468 case 0: 469 REG_SET(DOMAIN0_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 470 REG_WAIT(DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 471 break; 472 case 1: 473 REG_SET(DOMAIN1_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 474 REG_WAIT(DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 475 break; 476 case 2: 477 REG_SET(DOMAIN2_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 478 REG_WAIT(DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 479 break; 480 case 3: 481 REG_SET(DOMAIN3_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 482 REG_WAIT(DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 483 break; 484 default: 485 BREAK_TO_DEBUGGER(); 486 break; 487 } 488 } 489 490 int dcn31_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config) 491 { 492 struct dcn_hubbub_phys_addr_config config; 493 494 config.system_aperture.fb_top = pa_config->system_aperture.fb_top; 495 config.system_aperture.fb_offset = pa_config->system_aperture.fb_offset; 496 config.system_aperture.fb_base = pa_config->system_aperture.fb_base; 497 config.system_aperture.agp_top = pa_config->system_aperture.agp_top; 498 config.system_aperture.agp_bot = pa_config->system_aperture.agp_bot; 499 config.system_aperture.agp_base = pa_config->system_aperture.agp_base; 500 config.gart_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr; 501 config.gart_config.page_table_end_addr = pa_config->gart_config.page_table_end_addr; 502 503 if (pa_config->gart_config.base_addr_is_mc_addr) { 504 /* Convert from MC address to offset into FB */ 505 config.gart_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr - 506 pa_config->system_aperture.fb_base + 507 pa_config->system_aperture.fb_offset; 508 } else 509 config.gart_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr; 510 511 return dc->res_pool->hubbub->funcs->init_dchub_sys_ctx(dc->res_pool->hubbub, &config); 512 } 513 514 static void dcn31_reset_back_end_for_pipe( 515 struct dc *dc, 516 struct pipe_ctx *pipe_ctx, 517 struct dc_state *context) 518 { 519 struct dc_link *link; 520 521 DC_LOGGER_INIT(dc->ctx->logger); 522 if (pipe_ctx->stream_res.stream_enc == NULL) { 523 pipe_ctx->stream = NULL; 524 return; 525 } 526 ASSERT(!pipe_ctx->top_pipe); 527 528 dc->hwss.set_abm_immediate_disable(pipe_ctx); 529 530 pipe_ctx->stream_res.tg->funcs->set_dsc_config( 531 pipe_ctx->stream_res.tg, 532 OPTC_DSC_DISABLED, 0, 0); 533 pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg); 534 535 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false); 536 if (pipe_ctx->stream_res.tg->funcs->set_odm_bypass) 537 pipe_ctx->stream_res.tg->funcs->set_odm_bypass( 538 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); 539 540 if (pipe_ctx->stream_res.tg->funcs->set_drr) 541 pipe_ctx->stream_res.tg->funcs->set_drr( 542 pipe_ctx->stream_res.tg, NULL); 543 544 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { 545 link = pipe_ctx->stream->link; 546 /* DPMS may already disable or */ 547 /* dpms_off status is incorrect due to fastboot 548 * feature. When system resume from S4 with second 549 * screen only, the dpms_off would be true but 550 * VBIOS lit up eDP, so check link status too. 551 */ 552 if (!pipe_ctx->stream->dpms_off || link->link_status.link_active) 553 core_link_disable_stream(pipe_ctx); 554 else if (pipe_ctx->stream_res.audio) 555 dc->hwss.disable_audio_stream(pipe_ctx); 556 557 /* free acquired resources */ 558 if (pipe_ctx->stream_res.audio) { 559 /*disable az_endpoint*/ 560 pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio); 561 562 /*free audio*/ 563 if (dc->caps.dynamic_audio == true) { 564 /*we have to dynamic arbitrate the audio endpoints*/ 565 /*we free the resource, need reset is_audio_acquired*/ 566 update_audio_usage(&dc->current_state->res_ctx, dc->res_pool, 567 pipe_ctx->stream_res.audio, false); 568 pipe_ctx->stream_res.audio = NULL; 569 } 570 } 571 } else if (pipe_ctx->stream_res.dsc) { 572 dp_set_dsc_enable(pipe_ctx, false); 573 } 574 575 pipe_ctx->stream = NULL; 576 DC_LOG_DEBUG("Reset back end for pipe %d, tg:%d\n", 577 pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst); 578 } 579 580 void dcn31_reset_hw_ctx_wrap( 581 struct dc *dc, 582 struct dc_state *context) 583 { 584 int i; 585 struct dce_hwseq *hws = dc->hwseq; 586 587 /* Reset Back End*/ 588 for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) { 589 struct pipe_ctx *pipe_ctx_old = 590 &dc->current_state->res_ctx.pipe_ctx[i]; 591 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 592 593 if (!pipe_ctx_old->stream) 594 continue; 595 596 if (pipe_ctx_old->top_pipe || pipe_ctx_old->prev_odm_pipe) 597 continue; 598 599 if (!pipe_ctx->stream || 600 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) { 601 struct clock_source *old_clk = pipe_ctx_old->clock_source; 602 603 dcn31_reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state); 604 if (hws->funcs.enable_stream_gating) 605 hws->funcs.enable_stream_gating(dc, pipe_ctx); 606 if (old_clk) 607 old_clk->funcs->cs_power_down(old_clk); 608 } 609 } 610 611 /* New dc_state in the process of being applied to hardware. */ 612 dc->current_state->res_ctx.link_enc_cfg_ctx.mode = LINK_ENC_CFG_TRANSIENT; 613 } 614 615 void dcn31_setup_hpo_hw_control(const struct dce_hwseq *hws, bool enable) 616 { 617 if (hws->ctx->dc->debug.hpo_optimization) 618 REG_UPDATE(HPO_TOP_HW_CONTROL, HPO_IO_EN, !!enable); 619 } 620