1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 27 #include "dm_services.h" 28 #include "dm_helpers.h" 29 #include "core_types.h" 30 #include "resource.h" 31 #include "dccg.h" 32 #include "dce/dce_hwseq.h" 33 #include "clk_mgr.h" 34 #include "reg_helper.h" 35 #include "abm.h" 36 #include "hubp.h" 37 #include "dchubbub.h" 38 #include "timing_generator.h" 39 #include "opp.h" 40 #include "ipp.h" 41 #include "mpc.h" 42 #include "mcif_wb.h" 43 #include "dc_dmub_srv.h" 44 #include "dcn31_hwseq.h" 45 #include "link_hwss.h" 46 #include "dpcd_defs.h" 47 #include "dce/dmub_outbox.h" 48 #include "dc_link_dp.h" 49 #include "inc/link_dpcd.h" 50 #include "dcn10/dcn10_hw_sequencer.h" 51 #include "inc/link_enc_cfg.h" 52 53 #define DC_LOGGER_INIT(logger) 54 55 #define CTX \ 56 hws->ctx 57 #define REG(reg)\ 58 hws->regs->reg 59 #define DC_LOGGER \ 60 dc->ctx->logger 61 62 63 #undef FN 64 #define FN(reg_name, field_name) \ 65 hws->shifts->field_name, hws->masks->field_name 66 67 void dcn31_init_hw(struct dc *dc) 68 { 69 struct abm **abms = dc->res_pool->multiple_abms; 70 struct dce_hwseq *hws = dc->hwseq; 71 struct dc_bios *dcb = dc->ctx->dc_bios; 72 struct resource_pool *res_pool = dc->res_pool; 73 uint32_t backlight = MAX_BACKLIGHT_LEVEL; 74 int i; 75 int edp_num; 76 77 if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks) 78 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr); 79 80 // Initialize the dccg 81 if (res_pool->dccg->funcs->dccg_init) 82 res_pool->dccg->funcs->dccg_init(res_pool->dccg); 83 84 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { 85 86 REG_WRITE(REFCLK_CNTL, 0); 87 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1); 88 REG_WRITE(DIO_MEM_PWR_CTRL, 0); 89 90 if (!dc->debug.disable_clock_gate) { 91 /* enable all DCN clock gating */ 92 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); 93 94 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); 95 96 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); 97 } 98 99 //Enable ability to power gate / don't force power on permanently 100 if (hws->funcs.enable_power_gating_plane) 101 hws->funcs.enable_power_gating_plane(hws, true); 102 103 return; 104 } 105 106 if (!dcb->funcs->is_accelerated_mode(dcb)) { 107 hws->funcs.bios_golden_init(dc); 108 hws->funcs.disable_vga(dc->hwseq); 109 } 110 111 if (dc->debug.enable_mem_low_power.bits.dmcu) { 112 // Force ERAM to shutdown if DMCU is not enabled 113 if (dc->debug.disable_dmcu || dc->config.disable_dmcu) { 114 REG_UPDATE(DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, 3); 115 } 116 } 117 118 // Set default OPTC memory power states 119 if (dc->debug.enable_mem_low_power.bits.optc) { 120 // Shutdown when unassigned and light sleep in VBLANK 121 REG_SET_2(ODM_MEM_PWR_CTRL3, 0, ODM_MEM_UNASSIGNED_PWR_MODE, 3, ODM_MEM_VBLANK_PWR_MODE, 1); 122 } 123 124 if (dc->debug.enable_mem_low_power.bits.vga) { 125 // Power down VGA memory 126 REG_UPDATE(MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, 1); 127 } 128 129 if (dc->ctx->dc_bios->fw_info_valid) { 130 res_pool->ref_clocks.xtalin_clock_inKhz = 131 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency; 132 133 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { 134 if (res_pool->dccg && res_pool->hubbub) { 135 136 (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg, 137 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency, 138 &res_pool->ref_clocks.dccg_ref_clock_inKhz); 139 140 (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub, 141 res_pool->ref_clocks.dccg_ref_clock_inKhz, 142 &res_pool->ref_clocks.dchub_ref_clock_inKhz); 143 } else { 144 // Not all ASICs have DCCG sw component 145 res_pool->ref_clocks.dccg_ref_clock_inKhz = 146 res_pool->ref_clocks.xtalin_clock_inKhz; 147 res_pool->ref_clocks.dchub_ref_clock_inKhz = 148 res_pool->ref_clocks.xtalin_clock_inKhz; 149 } 150 } 151 } else 152 ASSERT_CRITICAL(false); 153 154 for (i = 0; i < dc->link_count; i++) { 155 /* Power up AND update implementation according to the 156 * required signal (which may be different from the 157 * default signal on connector). 158 */ 159 struct dc_link *link = dc->links[i]; 160 161 if (link->ep_type != DISPLAY_ENDPOINT_PHY) 162 continue; 163 164 link->link_enc->funcs->hw_init(link->link_enc); 165 166 /* Check for enabled DIG to identify enabled display */ 167 if (link->link_enc->funcs->is_dig_enabled && 168 link->link_enc->funcs->is_dig_enabled(link->link_enc)) 169 link->link_status.link_active = true; 170 } 171 172 /* Power gate DSCs */ 173 for (i = 0; i < res_pool->res_cap->num_dsc; i++) 174 if (hws->funcs.dsc_pg_control != NULL) 175 hws->funcs.dsc_pg_control(hws, res_pool->dscs[i]->inst, false); 176 177 /* Enables outbox notifications for usb4 dpia */ 178 if (dc->res_pool->usb4_dpia_count) 179 dmub_enable_outbox_notification(dc); 180 181 /* we want to turn off all dp displays before doing detection */ 182 if (dc->config.power_down_display_on_boot) 183 blank_all_dp_displays(dc, true); 184 185 186 /* If taking control over from VBIOS, we may want to optimize our first 187 * mode set, so we need to skip powering down pipes until we know which 188 * pipes we want to use. 189 * Otherwise, if taking control is not possible, we need to power 190 * everything down. 191 */ 192 if (dcb->funcs->is_accelerated_mode(dcb) || dc->config.power_down_display_on_boot) { 193 hws->funcs.init_pipes(dc, dc->current_state); 194 if (dc->res_pool->hubbub->funcs->allow_self_refresh_control) 195 dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, 196 !dc->res_pool->hubbub->ctx->dc->debug.disable_stutter); 197 } 198 199 /* In headless boot cases, DIG may be turned 200 * on which causes HW/SW discrepancies. 201 * To avoid this, power down hardware on boot 202 * if DIG is turned on and seamless boot not enabled 203 */ 204 if (dc->config.power_down_display_on_boot) { 205 struct dc_link *edp_links[MAX_NUM_EDP]; 206 struct dc_link *edp_link; 207 bool power_down = false; 208 209 get_edp_links(dc, edp_links, &edp_num); 210 if (edp_num) { 211 for (i = 0; i < edp_num; i++) { 212 edp_link = edp_links[i]; 213 if (edp_link->link_enc->funcs->is_dig_enabled && 214 edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc) && 215 dc->hwss.edp_backlight_control && 216 dc->hwss.power_down && 217 dc->hwss.edp_power_control) { 218 dc->hwss.edp_backlight_control(edp_link, false); 219 dc->hwss.power_down(dc); 220 dc->hwss.edp_power_control(edp_link, false); 221 power_down = true; 222 } 223 } 224 } 225 if (!power_down) { 226 for (i = 0; i < dc->link_count; i++) { 227 struct dc_link *link = dc->links[i]; 228 229 if (link->ep_type == DISPLAY_ENDPOINT_PHY && 230 link->link_enc->funcs->is_dig_enabled && 231 link->link_enc->funcs->is_dig_enabled(link->link_enc) && 232 dc->hwss.power_down) { 233 dc->hwss.power_down(dc); 234 break; 235 } 236 237 } 238 } 239 } 240 241 for (i = 0; i < res_pool->audio_count; i++) { 242 struct audio *audio = res_pool->audios[i]; 243 244 audio->funcs->hw_init(audio); 245 } 246 247 for (i = 0; i < dc->link_count; i++) { 248 struct dc_link *link = dc->links[i]; 249 250 if (link->panel_cntl) 251 backlight = link->panel_cntl->funcs->hw_init(link->panel_cntl); 252 } 253 254 for (i = 0; i < dc->res_pool->pipe_count; i++) { 255 if (abms[i] != NULL) 256 abms[i]->funcs->abm_init(abms[i], backlight); 257 } 258 259 /* power AFMT HDMI memory TODO: may move to dis/en output save power*/ 260 REG_WRITE(DIO_MEM_PWR_CTRL, 0); 261 262 if (!dc->debug.disable_clock_gate) { 263 /* enable all DCN clock gating */ 264 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); 265 266 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); 267 268 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); 269 } 270 if (hws->funcs.enable_power_gating_plane) 271 hws->funcs.enable_power_gating_plane(dc->hwseq, true); 272 273 if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks) 274 dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub); 275 276 if (dc->clk_mgr->funcs->notify_wm_ranges) 277 dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr); 278 279 if (dc->clk_mgr->funcs->set_hard_max_memclk) 280 dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr); 281 282 if (dc->res_pool->hubbub->funcs->force_pstate_change_control) 283 dc->res_pool->hubbub->funcs->force_pstate_change_control( 284 dc->res_pool->hubbub, false, false); 285 #if defined(CONFIG_DRM_AMD_DC_DCN) 286 if (dc->res_pool->hubbub->funcs->init_crb) 287 dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub); 288 #endif 289 } 290 291 void dcn31_dsc_pg_control( 292 struct dce_hwseq *hws, 293 unsigned int dsc_inst, 294 bool power_on) 295 { 296 uint32_t power_gate = power_on ? 0 : 1; 297 uint32_t pwr_status = power_on ? 0 : 2; 298 uint32_t org_ip_request_cntl = 0; 299 300 if (hws->ctx->dc->debug.disable_dsc_power_gate) 301 return; 302 303 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); 304 if (org_ip_request_cntl == 0) 305 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); 306 307 switch (dsc_inst) { 308 case 0: /* DSC0 */ 309 REG_UPDATE(DOMAIN16_PG_CONFIG, 310 DOMAIN_POWER_GATE, power_gate); 311 312 REG_WAIT(DOMAIN16_PG_STATUS, 313 DOMAIN_PGFSM_PWR_STATUS, pwr_status, 314 1, 1000); 315 break; 316 case 1: /* DSC1 */ 317 REG_UPDATE(DOMAIN17_PG_CONFIG, 318 DOMAIN_POWER_GATE, power_gate); 319 320 REG_WAIT(DOMAIN17_PG_STATUS, 321 DOMAIN_PGFSM_PWR_STATUS, pwr_status, 322 1, 1000); 323 break; 324 case 2: /* DSC2 */ 325 REG_UPDATE(DOMAIN18_PG_CONFIG, 326 DOMAIN_POWER_GATE, power_gate); 327 328 REG_WAIT(DOMAIN18_PG_STATUS, 329 DOMAIN_PGFSM_PWR_STATUS, pwr_status, 330 1, 1000); 331 break; 332 default: 333 BREAK_TO_DEBUGGER(); 334 break; 335 } 336 337 if (org_ip_request_cntl == 0) 338 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); 339 } 340 341 342 void dcn31_enable_power_gating_plane( 343 struct dce_hwseq *hws, 344 bool enable) 345 { 346 bool force_on = true; /* disable power gating */ 347 348 if (enable) 349 force_on = false; 350 351 /* DCHUBP0/1/2/3/4/5 */ 352 REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 353 REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 354 355 /* DPP0/1/2/3/4/5 */ 356 REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 357 REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 358 359 /* DCS0/1/2/3/4/5 */ 360 REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 361 REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 362 REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 363 } 364 365 void dcn31_update_info_frame(struct pipe_ctx *pipe_ctx) 366 { 367 bool is_hdmi_tmds; 368 bool is_dp; 369 370 ASSERT(pipe_ctx->stream); 371 372 if (pipe_ctx->stream_res.stream_enc == NULL) 373 return; /* this is not root pipe */ 374 375 is_hdmi_tmds = dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal); 376 is_dp = dc_is_dp_signal(pipe_ctx->stream->signal); 377 378 if (!is_hdmi_tmds && !is_dp) 379 return; 380 381 if (is_hdmi_tmds) 382 pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets( 383 pipe_ctx->stream_res.stream_enc, 384 &pipe_ctx->stream_res.encoder_info_frame); 385 else { 386 pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets( 387 pipe_ctx->stream_res.stream_enc, 388 &pipe_ctx->stream_res.encoder_info_frame); 389 } 390 } 391 void dcn31_z10_save_init(struct dc *dc) 392 { 393 union dmub_rb_cmd cmd; 394 395 memset(&cmd, 0, sizeof(cmd)); 396 cmd.dcn_restore.header.type = DMUB_CMD__IDLE_OPT; 397 cmd.dcn_restore.header.sub_type = DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT; 398 399 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd); 400 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv); 401 dc_dmub_srv_wait_idle(dc->ctx->dmub_srv); 402 } 403 404 void dcn31_z10_restore(const struct dc *dc) 405 { 406 union dmub_rb_cmd cmd; 407 408 /* 409 * DMUB notifies whether restore is required. 410 * Optimization to avoid sending commands when not required. 411 */ 412 if (!dc_dmub_srv_is_restore_required(dc->ctx->dmub_srv)) 413 return; 414 415 memset(&cmd, 0, sizeof(cmd)); 416 cmd.dcn_restore.header.type = DMUB_CMD__IDLE_OPT; 417 cmd.dcn_restore.header.sub_type = DMUB_CMD__IDLE_OPT_DCN_RESTORE; 418 419 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd); 420 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv); 421 dc_dmub_srv_wait_idle(dc->ctx->dmub_srv); 422 } 423 424 void dcn31_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on) 425 { 426 uint32_t power_gate = power_on ? 0 : 1; 427 uint32_t pwr_status = power_on ? 0 : 2; 428 429 if (hws->ctx->dc->debug.disable_hubp_power_gate) 430 return; 431 432 if (REG(DOMAIN0_PG_CONFIG) == 0) 433 return; 434 435 switch (hubp_inst) { 436 case 0: 437 REG_SET(DOMAIN0_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 438 REG_WAIT(DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 439 break; 440 case 1: 441 REG_SET(DOMAIN1_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 442 REG_WAIT(DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 443 break; 444 case 2: 445 REG_SET(DOMAIN2_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 446 REG_WAIT(DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 447 break; 448 case 3: 449 REG_SET(DOMAIN3_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 450 REG_WAIT(DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 451 break; 452 default: 453 BREAK_TO_DEBUGGER(); 454 break; 455 } 456 } 457 458 int dcn31_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config) 459 { 460 struct dcn_hubbub_phys_addr_config config; 461 462 config.system_aperture.fb_top = pa_config->system_aperture.fb_top; 463 config.system_aperture.fb_offset = pa_config->system_aperture.fb_offset; 464 config.system_aperture.fb_base = pa_config->system_aperture.fb_base; 465 config.system_aperture.agp_top = pa_config->system_aperture.agp_top; 466 config.system_aperture.agp_bot = pa_config->system_aperture.agp_bot; 467 config.system_aperture.agp_base = pa_config->system_aperture.agp_base; 468 config.gart_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr; 469 config.gart_config.page_table_end_addr = pa_config->gart_config.page_table_end_addr; 470 471 if (pa_config->gart_config.base_addr_is_mc_addr) { 472 /* Convert from MC address to offset into FB */ 473 config.gart_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr - 474 pa_config->system_aperture.fb_base + 475 pa_config->system_aperture.fb_offset; 476 } else 477 config.gart_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr; 478 479 return dc->res_pool->hubbub->funcs->init_dchub_sys_ctx(dc->res_pool->hubbub, &config); 480 } 481 482 static void dcn31_reset_back_end_for_pipe( 483 struct dc *dc, 484 struct pipe_ctx *pipe_ctx, 485 struct dc_state *context) 486 { 487 struct dc_link *link; 488 489 DC_LOGGER_INIT(dc->ctx->logger); 490 if (pipe_ctx->stream_res.stream_enc == NULL) { 491 pipe_ctx->stream = NULL; 492 return; 493 } 494 ASSERT(!pipe_ctx->top_pipe); 495 496 dc->hwss.set_abm_immediate_disable(pipe_ctx); 497 498 pipe_ctx->stream_res.tg->funcs->set_dsc_config( 499 pipe_ctx->stream_res.tg, 500 OPTC_DSC_DISABLED, 0, 0); 501 pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg); 502 503 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false); 504 if (pipe_ctx->stream_res.tg->funcs->set_odm_bypass) 505 pipe_ctx->stream_res.tg->funcs->set_odm_bypass( 506 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); 507 508 if (pipe_ctx->stream_res.tg->funcs->set_drr) 509 pipe_ctx->stream_res.tg->funcs->set_drr( 510 pipe_ctx->stream_res.tg, NULL); 511 512 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { 513 link = pipe_ctx->stream->link; 514 /* DPMS may already disable or */ 515 /* dpms_off status is incorrect due to fastboot 516 * feature. When system resume from S4 with second 517 * screen only, the dpms_off would be true but 518 * VBIOS lit up eDP, so check link status too. 519 */ 520 if (!pipe_ctx->stream->dpms_off || link->link_status.link_active) 521 core_link_disable_stream(pipe_ctx); 522 else if (pipe_ctx->stream_res.audio) 523 dc->hwss.disable_audio_stream(pipe_ctx); 524 525 /* free acquired resources */ 526 if (pipe_ctx->stream_res.audio) { 527 /*disable az_endpoint*/ 528 pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio); 529 530 /*free audio*/ 531 if (dc->caps.dynamic_audio == true) { 532 /*we have to dynamic arbitrate the audio endpoints*/ 533 /*we free the resource, need reset is_audio_acquired*/ 534 update_audio_usage(&dc->current_state->res_ctx, dc->res_pool, 535 pipe_ctx->stream_res.audio, false); 536 pipe_ctx->stream_res.audio = NULL; 537 } 538 } 539 } else if (pipe_ctx->stream_res.dsc) { 540 dp_set_dsc_enable(pipe_ctx, false); 541 } 542 543 pipe_ctx->stream = NULL; 544 DC_LOG_DEBUG("Reset back end for pipe %d, tg:%d\n", 545 pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst); 546 } 547 548 void dcn31_reset_hw_ctx_wrap( 549 struct dc *dc, 550 struct dc_state *context) 551 { 552 int i; 553 struct dce_hwseq *hws = dc->hwseq; 554 555 /* Reset Back End*/ 556 for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) { 557 struct pipe_ctx *pipe_ctx_old = 558 &dc->current_state->res_ctx.pipe_ctx[i]; 559 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 560 561 if (!pipe_ctx_old->stream) 562 continue; 563 564 if (pipe_ctx_old->top_pipe || pipe_ctx_old->prev_odm_pipe) 565 continue; 566 567 if (!pipe_ctx->stream || 568 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) { 569 struct clock_source *old_clk = pipe_ctx_old->clock_source; 570 571 dcn31_reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state); 572 if (hws->funcs.enable_stream_gating) 573 hws->funcs.enable_stream_gating(dc, pipe_ctx); 574 if (old_clk) 575 old_clk->funcs->cs_power_down(old_clk); 576 } 577 } 578 579 /* New dc_state in the process of being applied to hardware. */ 580 dc->current_state->res_ctx.link_enc_cfg_ctx.mode = LINK_ENC_CFG_TRANSIENT; 581 } 582