1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 27 #include "dm_services.h" 28 #include "dm_helpers.h" 29 #include "core_types.h" 30 #include "resource.h" 31 #include "dccg.h" 32 #include "dce/dce_hwseq.h" 33 #include "clk_mgr.h" 34 #include "reg_helper.h" 35 #include "abm.h" 36 #include "hubp.h" 37 #include "dchubbub.h" 38 #include "timing_generator.h" 39 #include "opp.h" 40 #include "ipp.h" 41 #include "mpc.h" 42 #include "mcif_wb.h" 43 #include "dc_dmub_srv.h" 44 #include "dcn31_hwseq.h" 45 #include "link_hwss.h" 46 #include "dpcd_defs.h" 47 #include "dce/dmub_outbox.h" 48 #include "dc_link_dp.h" 49 #include "inc/link_dpcd.h" 50 #include "dcn10/dcn10_hw_sequencer.h" 51 #include "inc/link_enc_cfg.h" 52 #include "dcn30/dcn30_vpg.h" 53 #include "dce/dce_i2c_hw.h" 54 55 #define DC_LOGGER_INIT(logger) 56 57 #define CTX \ 58 hws->ctx 59 #define REG(reg)\ 60 hws->regs->reg 61 #define DC_LOGGER \ 62 dc->ctx->logger 63 64 65 #undef FN 66 #define FN(reg_name, field_name) \ 67 hws->shifts->field_name, hws->masks->field_name 68 69 static void enable_memory_low_power(struct dc *dc) 70 { 71 struct dce_hwseq *hws = dc->hwseq; 72 int i; 73 74 if (dc->debug.enable_mem_low_power.bits.dmcu) { 75 // Force ERAM to shutdown if DMCU is not enabled 76 if (dc->debug.disable_dmcu || dc->config.disable_dmcu) { 77 REG_UPDATE(DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, 3); 78 } 79 } 80 81 // Set default OPTC memory power states 82 if (dc->debug.enable_mem_low_power.bits.optc) { 83 // Shutdown when unassigned and light sleep in VBLANK 84 REG_SET_2(ODM_MEM_PWR_CTRL3, 0, ODM_MEM_UNASSIGNED_PWR_MODE, 3, ODM_MEM_VBLANK_PWR_MODE, 1); 85 } 86 87 if (dc->debug.enable_mem_low_power.bits.vga) { 88 // Power down VGA memory 89 REG_UPDATE(MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, 1); 90 } 91 92 if (dc->debug.enable_mem_low_power.bits.mpc) 93 dc->res_pool->mpc->funcs->set_mpc_mem_lp_mode(dc->res_pool->mpc); 94 95 96 if (dc->debug.enable_mem_low_power.bits.vpg && dc->res_pool->stream_enc[0]->vpg->funcs->vpg_powerdown) { 97 // Power down VPGs 98 for (i = 0; i < dc->res_pool->stream_enc_count; i++) 99 dc->res_pool->stream_enc[i]->vpg->funcs->vpg_powerdown(dc->res_pool->stream_enc[i]->vpg); 100 #if defined(CONFIG_DRM_AMD_DC_DCN) 101 for (i = 0; i < dc->res_pool->hpo_dp_stream_enc_count; i++) 102 dc->res_pool->hpo_dp_stream_enc[i]->vpg->funcs->vpg_powerdown(dc->res_pool->hpo_dp_stream_enc[i]->vpg); 103 #endif 104 } 105 106 } 107 108 void dcn31_init_hw(struct dc *dc) 109 { 110 struct abm **abms = dc->res_pool->multiple_abms; 111 struct dce_hwseq *hws = dc->hwseq; 112 struct dc_bios *dcb = dc->ctx->dc_bios; 113 struct resource_pool *res_pool = dc->res_pool; 114 uint32_t backlight = MAX_BACKLIGHT_LEVEL; 115 int i; 116 117 if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks) 118 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr); 119 120 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { 121 122 REG_WRITE(REFCLK_CNTL, 0); 123 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1); 124 REG_WRITE(DIO_MEM_PWR_CTRL, 0); 125 126 if (!dc->debug.disable_clock_gate) { 127 /* enable all DCN clock gating */ 128 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); 129 130 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); 131 132 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); 133 } 134 135 //Enable ability to power gate / don't force power on permanently 136 if (hws->funcs.enable_power_gating_plane) 137 hws->funcs.enable_power_gating_plane(hws, true); 138 139 return; 140 } 141 142 if (!dcb->funcs->is_accelerated_mode(dcb)) { 143 hws->funcs.bios_golden_init(dc); 144 hws->funcs.disable_vga(dc->hwseq); 145 } 146 // Initialize the dccg 147 if (res_pool->dccg->funcs->dccg_init) 148 res_pool->dccg->funcs->dccg_init(res_pool->dccg); 149 150 enable_memory_low_power(dc); 151 152 if (dc->ctx->dc_bios->fw_info_valid) { 153 res_pool->ref_clocks.xtalin_clock_inKhz = 154 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency; 155 156 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { 157 if (res_pool->dccg && res_pool->hubbub) { 158 159 (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg, 160 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency, 161 &res_pool->ref_clocks.dccg_ref_clock_inKhz); 162 163 (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub, 164 res_pool->ref_clocks.dccg_ref_clock_inKhz, 165 &res_pool->ref_clocks.dchub_ref_clock_inKhz); 166 } else { 167 // Not all ASICs have DCCG sw component 168 res_pool->ref_clocks.dccg_ref_clock_inKhz = 169 res_pool->ref_clocks.xtalin_clock_inKhz; 170 res_pool->ref_clocks.dchub_ref_clock_inKhz = 171 res_pool->ref_clocks.xtalin_clock_inKhz; 172 } 173 } 174 } else 175 ASSERT_CRITICAL(false); 176 177 for (i = 0; i < dc->link_count; i++) { 178 /* Power up AND update implementation according to the 179 * required signal (which may be different from the 180 * default signal on connector). 181 */ 182 struct dc_link *link = dc->links[i]; 183 184 if (link->ep_type != DISPLAY_ENDPOINT_PHY) 185 continue; 186 187 link->link_enc->funcs->hw_init(link->link_enc); 188 189 /* Check for enabled DIG to identify enabled display */ 190 if (link->link_enc->funcs->is_dig_enabled && 191 link->link_enc->funcs->is_dig_enabled(link->link_enc)) 192 link->link_status.link_active = true; 193 } 194 195 /* Enables outbox notifications for usb4 dpia */ 196 if (dc->res_pool->usb4_dpia_count) 197 dmub_enable_outbox_notification(dc); 198 199 /* we want to turn off all dp displays before doing detection */ 200 if (dc->config.power_down_display_on_boot) 201 dc_link_blank_all_dp_displays(dc); 202 203 /* If taking control over from VBIOS, we may want to optimize our first 204 * mode set, so we need to skip powering down pipes until we know which 205 * pipes we want to use. 206 * Otherwise, if taking control is not possible, we need to power 207 * everything down. 208 */ 209 if (dcb->funcs->is_accelerated_mode(dcb) || dc->config.power_down_display_on_boot) { 210 hws->funcs.init_pipes(dc, dc->current_state); 211 if (dc->res_pool->hubbub->funcs->allow_self_refresh_control) 212 dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, 213 !dc->res_pool->hubbub->ctx->dc->debug.disable_stutter); 214 } 215 216 for (i = 0; i < res_pool->audio_count; i++) { 217 struct audio *audio = res_pool->audios[i]; 218 219 audio->funcs->hw_init(audio); 220 } 221 222 for (i = 0; i < dc->link_count; i++) { 223 struct dc_link *link = dc->links[i]; 224 225 if (link->panel_cntl) 226 backlight = link->panel_cntl->funcs->hw_init(link->panel_cntl); 227 } 228 229 for (i = 0; i < dc->res_pool->pipe_count; i++) { 230 if (abms[i] != NULL) 231 abms[i]->funcs->abm_init(abms[i], backlight); 232 } 233 234 /* power AFMT HDMI memory TODO: may move to dis/en output save power*/ 235 REG_WRITE(DIO_MEM_PWR_CTRL, 0); 236 237 // Set i2c to light sleep until engine is setup 238 if (dc->debug.enable_mem_low_power.bits.i2c) 239 REG_UPDATE(DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, 1); 240 241 if (hws->funcs.setup_hpo_hw_control) 242 hws->funcs.setup_hpo_hw_control(hws, false); 243 244 if (!dc->debug.disable_clock_gate) { 245 /* enable all DCN clock gating */ 246 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); 247 248 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); 249 250 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); 251 } 252 if (hws->funcs.enable_power_gating_plane) 253 hws->funcs.enable_power_gating_plane(dc->hwseq, true); 254 255 if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks) 256 dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub); 257 258 if (dc->clk_mgr->funcs->notify_wm_ranges) 259 dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr); 260 261 if (dc->clk_mgr->funcs->set_hard_max_memclk) 262 dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr); 263 264 if (dc->res_pool->hubbub->funcs->force_pstate_change_control) 265 dc->res_pool->hubbub->funcs->force_pstate_change_control( 266 dc->res_pool->hubbub, false, false); 267 #if defined(CONFIG_DRM_AMD_DC_DCN) 268 if (dc->res_pool->hubbub->funcs->init_crb) 269 dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub); 270 #endif 271 } 272 273 void dcn31_dsc_pg_control( 274 struct dce_hwseq *hws, 275 unsigned int dsc_inst, 276 bool power_on) 277 { 278 uint32_t power_gate = power_on ? 0 : 1; 279 uint32_t pwr_status = power_on ? 0 : 2; 280 uint32_t org_ip_request_cntl = 0; 281 282 if (hws->ctx->dc->debug.disable_dsc_power_gate) 283 return; 284 285 if (hws->ctx->dc->debug.root_clock_optimization.bits.dsc && 286 hws->ctx->dc->res_pool->dccg->funcs->enable_dsc && 287 power_on) 288 hws->ctx->dc->res_pool->dccg->funcs->enable_dsc( 289 hws->ctx->dc->res_pool->dccg, dsc_inst); 290 291 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); 292 if (org_ip_request_cntl == 0) 293 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); 294 295 switch (dsc_inst) { 296 case 0: /* DSC0 */ 297 REG_UPDATE(DOMAIN16_PG_CONFIG, 298 DOMAIN_POWER_GATE, power_gate); 299 300 REG_WAIT(DOMAIN16_PG_STATUS, 301 DOMAIN_PGFSM_PWR_STATUS, pwr_status, 302 1, 1000); 303 break; 304 case 1: /* DSC1 */ 305 REG_UPDATE(DOMAIN17_PG_CONFIG, 306 DOMAIN_POWER_GATE, power_gate); 307 308 REG_WAIT(DOMAIN17_PG_STATUS, 309 DOMAIN_PGFSM_PWR_STATUS, pwr_status, 310 1, 1000); 311 break; 312 case 2: /* DSC2 */ 313 REG_UPDATE(DOMAIN18_PG_CONFIG, 314 DOMAIN_POWER_GATE, power_gate); 315 316 REG_WAIT(DOMAIN18_PG_STATUS, 317 DOMAIN_PGFSM_PWR_STATUS, pwr_status, 318 1, 1000); 319 break; 320 default: 321 BREAK_TO_DEBUGGER(); 322 break; 323 } 324 325 if (org_ip_request_cntl == 0) 326 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); 327 328 if (hws->ctx->dc->debug.root_clock_optimization.bits.dsc) { 329 if (hws->ctx->dc->res_pool->dccg->funcs->disable_dsc && !power_on) 330 hws->ctx->dc->res_pool->dccg->funcs->disable_dsc( 331 hws->ctx->dc->res_pool->dccg, dsc_inst); 332 } 333 334 } 335 336 337 void dcn31_enable_power_gating_plane( 338 struct dce_hwseq *hws, 339 bool enable) 340 { 341 bool force_on = true; /* disable power gating */ 342 343 if (enable) 344 force_on = false; 345 346 /* DCHUBP0/1/2/3/4/5 */ 347 REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 348 REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 349 350 /* DPP0/1/2/3/4/5 */ 351 REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 352 REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 353 354 /* DCS0/1/2/3/4/5 */ 355 REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 356 REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 357 REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 358 } 359 360 void dcn31_update_info_frame(struct pipe_ctx *pipe_ctx) 361 { 362 bool is_hdmi_tmds; 363 bool is_dp; 364 365 ASSERT(pipe_ctx->stream); 366 367 if (pipe_ctx->stream_res.stream_enc == NULL) 368 return; /* this is not root pipe */ 369 370 is_hdmi_tmds = dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal); 371 is_dp = dc_is_dp_signal(pipe_ctx->stream->signal); 372 373 if (!is_hdmi_tmds && !is_dp) 374 return; 375 376 if (is_hdmi_tmds) 377 pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets( 378 pipe_ctx->stream_res.stream_enc, 379 &pipe_ctx->stream_res.encoder_info_frame); 380 else { 381 pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets( 382 pipe_ctx->stream_res.stream_enc, 383 &pipe_ctx->stream_res.encoder_info_frame); 384 } 385 } 386 void dcn31_z10_save_init(struct dc *dc) 387 { 388 union dmub_rb_cmd cmd; 389 390 memset(&cmd, 0, sizeof(cmd)); 391 cmd.dcn_restore.header.type = DMUB_CMD__IDLE_OPT; 392 cmd.dcn_restore.header.sub_type = DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT; 393 394 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd); 395 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv); 396 dc_dmub_srv_wait_idle(dc->ctx->dmub_srv); 397 } 398 399 void dcn31_z10_restore(const struct dc *dc) 400 { 401 union dmub_rb_cmd cmd; 402 403 /* 404 * DMUB notifies whether restore is required. 405 * Optimization to avoid sending commands when not required. 406 */ 407 if (!dc_dmub_srv_is_restore_required(dc->ctx->dmub_srv)) 408 return; 409 410 memset(&cmd, 0, sizeof(cmd)); 411 cmd.dcn_restore.header.type = DMUB_CMD__IDLE_OPT; 412 cmd.dcn_restore.header.sub_type = DMUB_CMD__IDLE_OPT_DCN_RESTORE; 413 414 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd); 415 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv); 416 dc_dmub_srv_wait_idle(dc->ctx->dmub_srv); 417 } 418 419 void dcn31_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on) 420 { 421 uint32_t power_gate = power_on ? 0 : 1; 422 uint32_t pwr_status = power_on ? 0 : 2; 423 424 if (hws->ctx->dc->debug.disable_hubp_power_gate) 425 return; 426 427 if (REG(DOMAIN0_PG_CONFIG) == 0) 428 return; 429 430 switch (hubp_inst) { 431 case 0: 432 REG_SET(DOMAIN0_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 433 REG_WAIT(DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 434 break; 435 case 1: 436 REG_SET(DOMAIN1_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 437 REG_WAIT(DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 438 break; 439 case 2: 440 REG_SET(DOMAIN2_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 441 REG_WAIT(DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 442 break; 443 case 3: 444 REG_SET(DOMAIN3_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 445 REG_WAIT(DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 446 break; 447 default: 448 BREAK_TO_DEBUGGER(); 449 break; 450 } 451 } 452 453 int dcn31_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config) 454 { 455 struct dcn_hubbub_phys_addr_config config; 456 457 config.system_aperture.fb_top = pa_config->system_aperture.fb_top; 458 config.system_aperture.fb_offset = pa_config->system_aperture.fb_offset; 459 config.system_aperture.fb_base = pa_config->system_aperture.fb_base; 460 config.system_aperture.agp_top = pa_config->system_aperture.agp_top; 461 config.system_aperture.agp_bot = pa_config->system_aperture.agp_bot; 462 config.system_aperture.agp_base = pa_config->system_aperture.agp_base; 463 config.gart_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr; 464 config.gart_config.page_table_end_addr = pa_config->gart_config.page_table_end_addr; 465 466 if (pa_config->gart_config.base_addr_is_mc_addr) { 467 /* Convert from MC address to offset into FB */ 468 config.gart_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr - 469 pa_config->system_aperture.fb_base + 470 pa_config->system_aperture.fb_offset; 471 } else 472 config.gart_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr; 473 474 return dc->res_pool->hubbub->funcs->init_dchub_sys_ctx(dc->res_pool->hubbub, &config); 475 } 476 477 static void dcn31_reset_back_end_for_pipe( 478 struct dc *dc, 479 struct pipe_ctx *pipe_ctx, 480 struct dc_state *context) 481 { 482 struct dc_link *link; 483 484 DC_LOGGER_INIT(dc->ctx->logger); 485 if (pipe_ctx->stream_res.stream_enc == NULL) { 486 pipe_ctx->stream = NULL; 487 return; 488 } 489 ASSERT(!pipe_ctx->top_pipe); 490 491 dc->hwss.set_abm_immediate_disable(pipe_ctx); 492 493 pipe_ctx->stream_res.tg->funcs->set_dsc_config( 494 pipe_ctx->stream_res.tg, 495 OPTC_DSC_DISABLED, 0, 0); 496 pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg); 497 498 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false); 499 if (pipe_ctx->stream_res.tg->funcs->set_odm_bypass) 500 pipe_ctx->stream_res.tg->funcs->set_odm_bypass( 501 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); 502 503 if (pipe_ctx->stream_res.tg->funcs->set_drr) 504 pipe_ctx->stream_res.tg->funcs->set_drr( 505 pipe_ctx->stream_res.tg, NULL); 506 507 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { 508 link = pipe_ctx->stream->link; 509 /* DPMS may already disable or */ 510 /* dpms_off status is incorrect due to fastboot 511 * feature. When system resume from S4 with second 512 * screen only, the dpms_off would be true but 513 * VBIOS lit up eDP, so check link status too. 514 */ 515 if (!pipe_ctx->stream->dpms_off || link->link_status.link_active) 516 core_link_disable_stream(pipe_ctx); 517 else if (pipe_ctx->stream_res.audio) 518 dc->hwss.disable_audio_stream(pipe_ctx); 519 520 /* free acquired resources */ 521 if (pipe_ctx->stream_res.audio) { 522 /*disable az_endpoint*/ 523 pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio); 524 525 /*free audio*/ 526 if (dc->caps.dynamic_audio == true) { 527 /*we have to dynamic arbitrate the audio endpoints*/ 528 /*we free the resource, need reset is_audio_acquired*/ 529 update_audio_usage(&dc->current_state->res_ctx, dc->res_pool, 530 pipe_ctx->stream_res.audio, false); 531 pipe_ctx->stream_res.audio = NULL; 532 } 533 } 534 } else if (pipe_ctx->stream_res.dsc) { 535 dp_set_dsc_enable(pipe_ctx, false); 536 } 537 538 pipe_ctx->stream = NULL; 539 DC_LOG_DEBUG("Reset back end for pipe %d, tg:%d\n", 540 pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst); 541 } 542 543 void dcn31_reset_hw_ctx_wrap( 544 struct dc *dc, 545 struct dc_state *context) 546 { 547 int i; 548 struct dce_hwseq *hws = dc->hwseq; 549 550 /* Reset Back End*/ 551 for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) { 552 struct pipe_ctx *pipe_ctx_old = 553 &dc->current_state->res_ctx.pipe_ctx[i]; 554 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 555 556 if (!pipe_ctx_old->stream) 557 continue; 558 559 if (pipe_ctx_old->top_pipe || pipe_ctx_old->prev_odm_pipe) 560 continue; 561 562 if (!pipe_ctx->stream || 563 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) { 564 struct clock_source *old_clk = pipe_ctx_old->clock_source; 565 566 dcn31_reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state); 567 if (hws->funcs.enable_stream_gating) 568 hws->funcs.enable_stream_gating(dc, pipe_ctx_old); 569 if (old_clk) 570 old_clk->funcs->cs_power_down(old_clk); 571 } 572 } 573 574 /* New dc_state in the process of being applied to hardware. */ 575 dc->current_state->res_ctx.link_enc_cfg_ctx.mode = LINK_ENC_CFG_TRANSIENT; 576 } 577 578 void dcn31_setup_hpo_hw_control(const struct dce_hwseq *hws, bool enable) 579 { 580 if (hws->ctx->dc->debug.hpo_optimization) 581 REG_UPDATE(HPO_TOP_HW_CONTROL, HPO_IO_EN, !!enable); 582 } 583