1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 27 #include "dm_services.h" 28 #include "dm_helpers.h" 29 #include "core_types.h" 30 #include "resource.h" 31 #include "dccg.h" 32 #include "dce/dce_hwseq.h" 33 #include "clk_mgr.h" 34 #include "reg_helper.h" 35 #include "abm.h" 36 #include "hubp.h" 37 #include "dchubbub.h" 38 #include "timing_generator.h" 39 #include "opp.h" 40 #include "ipp.h" 41 #include "mpc.h" 42 #include "mcif_wb.h" 43 #include "dc_dmub_srv.h" 44 #include "dcn31_hwseq.h" 45 #include "link_hwss.h" 46 #include "dpcd_defs.h" 47 #include "dce/dmub_outbox.h" 48 #include "dc_link_dp.h" 49 #include "inc/link_dpcd.h" 50 #include "dcn10/dcn10_hw_sequencer.h" 51 #include "inc/link_enc_cfg.h" 52 #include "dcn30/dcn30_vpg.h" 53 #include "dce/dce_i2c_hw.h" 54 55 #define DC_LOGGER_INIT(logger) 56 57 #define CTX \ 58 hws->ctx 59 #define REG(reg)\ 60 hws->regs->reg 61 #define DC_LOGGER \ 62 dc->ctx->logger 63 64 65 #undef FN 66 #define FN(reg_name, field_name) \ 67 hws->shifts->field_name, hws->masks->field_name 68 69 static void enable_memory_low_power(struct dc *dc) 70 { 71 struct dce_hwseq *hws = dc->hwseq; 72 int i; 73 74 if (dc->debug.enable_mem_low_power.bits.dmcu) { 75 // Force ERAM to shutdown if DMCU is not enabled 76 if (dc->debug.disable_dmcu || dc->config.disable_dmcu) { 77 REG_UPDATE(DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, 3); 78 } 79 } 80 81 // Set default OPTC memory power states 82 if (dc->debug.enable_mem_low_power.bits.optc) { 83 // Shutdown when unassigned and light sleep in VBLANK 84 REG_SET_2(ODM_MEM_PWR_CTRL3, 0, ODM_MEM_UNASSIGNED_PWR_MODE, 3, ODM_MEM_VBLANK_PWR_MODE, 1); 85 } 86 87 if (dc->debug.enable_mem_low_power.bits.vga) { 88 // Power down VGA memory 89 REG_UPDATE(MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, 1); 90 } 91 92 if (dc->debug.enable_mem_low_power.bits.mpc) 93 dc->res_pool->mpc->funcs->set_mpc_mem_lp_mode(dc->res_pool->mpc); 94 95 96 if (dc->debug.enable_mem_low_power.bits.vpg && dc->res_pool->stream_enc[0]->vpg->funcs->vpg_powerdown) { 97 // Power down VPGs 98 for (i = 0; i < dc->res_pool->stream_enc_count; i++) 99 dc->res_pool->stream_enc[i]->vpg->funcs->vpg_powerdown(dc->res_pool->stream_enc[i]->vpg); 100 #if defined(CONFIG_DRM_AMD_DC_DCN) 101 for (i = 0; i < dc->res_pool->hpo_dp_stream_enc_count; i++) 102 dc->res_pool->hpo_dp_stream_enc[i]->vpg->funcs->vpg_powerdown(dc->res_pool->hpo_dp_stream_enc[i]->vpg); 103 #endif 104 } 105 106 } 107 108 void dcn31_init_hw(struct dc *dc) 109 { 110 struct abm **abms = dc->res_pool->multiple_abms; 111 struct dce_hwseq *hws = dc->hwseq; 112 struct dc_bios *dcb = dc->ctx->dc_bios; 113 struct resource_pool *res_pool = dc->res_pool; 114 uint32_t backlight = MAX_BACKLIGHT_LEVEL; 115 int i; 116 117 if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks) 118 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr); 119 120 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { 121 122 REG_WRITE(REFCLK_CNTL, 0); 123 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1); 124 REG_WRITE(DIO_MEM_PWR_CTRL, 0); 125 126 if (!dc->debug.disable_clock_gate) { 127 /* enable all DCN clock gating */ 128 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); 129 130 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); 131 132 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); 133 } 134 135 //Enable ability to power gate / don't force power on permanently 136 if (hws->funcs.enable_power_gating_plane) 137 hws->funcs.enable_power_gating_plane(hws, true); 138 139 return; 140 } 141 142 if (!dcb->funcs->is_accelerated_mode(dcb)) { 143 hws->funcs.bios_golden_init(dc); 144 hws->funcs.disable_vga(dc->hwseq); 145 } 146 // Initialize the dccg 147 if (res_pool->dccg->funcs->dccg_init) 148 res_pool->dccg->funcs->dccg_init(res_pool->dccg); 149 150 enable_memory_low_power(dc); 151 152 if (dc->ctx->dc_bios->fw_info_valid) { 153 res_pool->ref_clocks.xtalin_clock_inKhz = 154 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency; 155 156 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { 157 if (res_pool->dccg && res_pool->hubbub) { 158 159 (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg, 160 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency, 161 &res_pool->ref_clocks.dccg_ref_clock_inKhz); 162 163 (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub, 164 res_pool->ref_clocks.dccg_ref_clock_inKhz, 165 &res_pool->ref_clocks.dchub_ref_clock_inKhz); 166 } else { 167 // Not all ASICs have DCCG sw component 168 res_pool->ref_clocks.dccg_ref_clock_inKhz = 169 res_pool->ref_clocks.xtalin_clock_inKhz; 170 res_pool->ref_clocks.dchub_ref_clock_inKhz = 171 res_pool->ref_clocks.xtalin_clock_inKhz; 172 } 173 } 174 } else 175 ASSERT_CRITICAL(false); 176 177 for (i = 0; i < dc->link_count; i++) { 178 /* Power up AND update implementation according to the 179 * required signal (which may be different from the 180 * default signal on connector). 181 */ 182 struct dc_link *link = dc->links[i]; 183 184 if (link->ep_type != DISPLAY_ENDPOINT_PHY) 185 continue; 186 187 link->link_enc->funcs->hw_init(link->link_enc); 188 189 /* Check for enabled DIG to identify enabled display */ 190 if (link->link_enc->funcs->is_dig_enabled && 191 link->link_enc->funcs->is_dig_enabled(link->link_enc)) { 192 link->link_status.link_active = true; 193 if (link->link_enc->funcs->fec_is_active && 194 link->link_enc->funcs->fec_is_active(link->link_enc)) 195 link->fec_state = dc_link_fec_enabled; 196 } 197 } 198 199 /* Enables outbox notifications for usb4 dpia */ 200 if (dc->res_pool->usb4_dpia_count) 201 dmub_enable_outbox_notification(dc->ctx->dmub_srv); 202 203 /* we want to turn off all dp displays before doing detection */ 204 dc_link_blank_all_dp_displays(dc); 205 206 if (hws->funcs.enable_power_gating_plane) 207 hws->funcs.enable_power_gating_plane(dc->hwseq, true); 208 209 /* If taking control over from VBIOS, we may want to optimize our first 210 * mode set, so we need to skip powering down pipes until we know which 211 * pipes we want to use. 212 * Otherwise, if taking control is not possible, we need to power 213 * everything down. 214 */ 215 if (dcb->funcs->is_accelerated_mode(dcb) || !dc->config.seamless_boot_edp_requested) { 216 217 // we want to turn off edp displays if odm is enabled and no seamless boot 218 if (!dc->caps.seamless_odm) { 219 for (i = 0; i < dc->res_pool->timing_generator_count; i++) { 220 struct timing_generator *tg = dc->res_pool->timing_generators[i]; 221 uint32_t num_opps, opp_id_src0, opp_id_src1; 222 223 num_opps = 1; 224 if (tg) { 225 if (tg->funcs->is_tg_enabled(tg) && tg->funcs->get_optc_source) { 226 tg->funcs->get_optc_source(tg, &num_opps, 227 &opp_id_src0, &opp_id_src1); 228 } 229 } 230 231 if (num_opps > 1) { 232 dc_link_blank_all_edp_displays(dc); 233 break; 234 } 235 } 236 } 237 238 hws->funcs.init_pipes(dc, dc->current_state); 239 if (dc->res_pool->hubbub->funcs->allow_self_refresh_control) 240 dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, 241 !dc->res_pool->hubbub->ctx->dc->debug.disable_stutter); 242 } 243 244 for (i = 0; i < res_pool->audio_count; i++) { 245 struct audio *audio = res_pool->audios[i]; 246 247 audio->funcs->hw_init(audio); 248 } 249 250 for (i = 0; i < dc->link_count; i++) { 251 struct dc_link *link = dc->links[i]; 252 253 if (link->panel_cntl) 254 backlight = link->panel_cntl->funcs->hw_init(link->panel_cntl); 255 } 256 257 for (i = 0; i < dc->res_pool->pipe_count; i++) { 258 if (abms[i] != NULL) 259 abms[i]->funcs->abm_init(abms[i], backlight); 260 } 261 262 /* power AFMT HDMI memory TODO: may move to dis/en output save power*/ 263 REG_WRITE(DIO_MEM_PWR_CTRL, 0); 264 265 // Set i2c to light sleep until engine is setup 266 if (dc->debug.enable_mem_low_power.bits.i2c) 267 REG_UPDATE(DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, 1); 268 269 if (hws->funcs.setup_hpo_hw_control) 270 hws->funcs.setup_hpo_hw_control(hws, false); 271 272 if (!dc->debug.disable_clock_gate) { 273 /* enable all DCN clock gating */ 274 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); 275 276 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); 277 278 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); 279 } 280 281 if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks) 282 dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub); 283 284 if (dc->clk_mgr->funcs->notify_wm_ranges) 285 dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr); 286 287 if (dc->clk_mgr->funcs->set_hard_max_memclk) 288 dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr); 289 290 if (dc->res_pool->hubbub->funcs->force_pstate_change_control) 291 dc->res_pool->hubbub->funcs->force_pstate_change_control( 292 dc->res_pool->hubbub, false, false); 293 #if defined(CONFIG_DRM_AMD_DC_DCN) 294 if (dc->res_pool->hubbub->funcs->init_crb) 295 dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub); 296 #endif 297 } 298 299 void dcn31_dsc_pg_control( 300 struct dce_hwseq *hws, 301 unsigned int dsc_inst, 302 bool power_on) 303 { 304 uint32_t power_gate = power_on ? 0 : 1; 305 uint32_t pwr_status = power_on ? 0 : 2; 306 uint32_t org_ip_request_cntl = 0; 307 308 if (hws->ctx->dc->debug.disable_dsc_power_gate) 309 return; 310 311 if (hws->ctx->dc->debug.root_clock_optimization.bits.dsc && 312 hws->ctx->dc->res_pool->dccg->funcs->enable_dsc && 313 power_on) 314 hws->ctx->dc->res_pool->dccg->funcs->enable_dsc( 315 hws->ctx->dc->res_pool->dccg, dsc_inst); 316 317 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); 318 if (org_ip_request_cntl == 0) 319 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); 320 321 switch (dsc_inst) { 322 case 0: /* DSC0 */ 323 REG_UPDATE(DOMAIN16_PG_CONFIG, 324 DOMAIN_POWER_GATE, power_gate); 325 326 REG_WAIT(DOMAIN16_PG_STATUS, 327 DOMAIN_PGFSM_PWR_STATUS, pwr_status, 328 1, 1000); 329 break; 330 case 1: /* DSC1 */ 331 REG_UPDATE(DOMAIN17_PG_CONFIG, 332 DOMAIN_POWER_GATE, power_gate); 333 334 REG_WAIT(DOMAIN17_PG_STATUS, 335 DOMAIN_PGFSM_PWR_STATUS, pwr_status, 336 1, 1000); 337 break; 338 case 2: /* DSC2 */ 339 REG_UPDATE(DOMAIN18_PG_CONFIG, 340 DOMAIN_POWER_GATE, power_gate); 341 342 REG_WAIT(DOMAIN18_PG_STATUS, 343 DOMAIN_PGFSM_PWR_STATUS, pwr_status, 344 1, 1000); 345 break; 346 default: 347 BREAK_TO_DEBUGGER(); 348 break; 349 } 350 351 if (org_ip_request_cntl == 0) 352 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); 353 354 if (hws->ctx->dc->debug.root_clock_optimization.bits.dsc) { 355 if (hws->ctx->dc->res_pool->dccg->funcs->disable_dsc && !power_on) 356 hws->ctx->dc->res_pool->dccg->funcs->disable_dsc( 357 hws->ctx->dc->res_pool->dccg, dsc_inst); 358 } 359 360 } 361 362 363 void dcn31_enable_power_gating_plane( 364 struct dce_hwseq *hws, 365 bool enable) 366 { 367 bool force_on = true; /* disable power gating */ 368 uint32_t org_ip_request_cntl = 0; 369 370 if (enable && !hws->ctx->dc->debug.disable_hubp_power_gate) 371 force_on = false; 372 373 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); 374 if (org_ip_request_cntl == 0) 375 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); 376 /* DCHUBP0/1/2/3/4/5 */ 377 REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 378 REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 379 /* DPP0/1/2/3/4/5 */ 380 REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 381 REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 382 383 force_on = true; /* disable power gating */ 384 if (enable && !hws->ctx->dc->debug.disable_dsc_power_gate) 385 force_on = false; 386 387 /* DCS0/1/2/3/4/5 */ 388 REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 389 REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 390 REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 391 392 if (org_ip_request_cntl == 0) 393 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); 394 } 395 396 void dcn31_update_info_frame(struct pipe_ctx *pipe_ctx) 397 { 398 bool is_hdmi_tmds; 399 bool is_dp; 400 401 ASSERT(pipe_ctx->stream); 402 403 if (pipe_ctx->stream_res.stream_enc == NULL) 404 return; /* this is not root pipe */ 405 406 is_hdmi_tmds = dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal); 407 is_dp = dc_is_dp_signal(pipe_ctx->stream->signal); 408 409 if (!is_hdmi_tmds && !is_dp) 410 return; 411 412 if (is_hdmi_tmds) 413 pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets( 414 pipe_ctx->stream_res.stream_enc, 415 &pipe_ctx->stream_res.encoder_info_frame); 416 else { 417 pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets( 418 pipe_ctx->stream_res.stream_enc, 419 &pipe_ctx->stream_res.encoder_info_frame); 420 } 421 } 422 void dcn31_z10_save_init(struct dc *dc) 423 { 424 union dmub_rb_cmd cmd; 425 426 memset(&cmd, 0, sizeof(cmd)); 427 cmd.dcn_restore.header.type = DMUB_CMD__IDLE_OPT; 428 cmd.dcn_restore.header.sub_type = DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT; 429 430 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd); 431 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv); 432 dc_dmub_srv_wait_idle(dc->ctx->dmub_srv); 433 } 434 435 void dcn31_z10_restore(const struct dc *dc) 436 { 437 union dmub_rb_cmd cmd; 438 439 /* 440 * DMUB notifies whether restore is required. 441 * Optimization to avoid sending commands when not required. 442 */ 443 if (!dc_dmub_srv_is_restore_required(dc->ctx->dmub_srv)) 444 return; 445 446 memset(&cmd, 0, sizeof(cmd)); 447 cmd.dcn_restore.header.type = DMUB_CMD__IDLE_OPT; 448 cmd.dcn_restore.header.sub_type = DMUB_CMD__IDLE_OPT_DCN_RESTORE; 449 450 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd); 451 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv); 452 dc_dmub_srv_wait_idle(dc->ctx->dmub_srv); 453 } 454 455 void dcn31_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on) 456 { 457 uint32_t power_gate = power_on ? 0 : 1; 458 uint32_t pwr_status = power_on ? 0 : 2; 459 uint32_t org_ip_request_cntl; 460 if (hws->ctx->dc->debug.disable_hubp_power_gate) 461 return; 462 463 if (REG(DOMAIN0_PG_CONFIG) == 0) 464 return; 465 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); 466 if (org_ip_request_cntl == 0) 467 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); 468 469 switch (hubp_inst) { 470 case 0: 471 REG_SET(DOMAIN0_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 472 REG_WAIT(DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 473 break; 474 case 1: 475 REG_SET(DOMAIN1_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 476 REG_WAIT(DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 477 break; 478 case 2: 479 REG_SET(DOMAIN2_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 480 REG_WAIT(DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 481 break; 482 case 3: 483 REG_SET(DOMAIN3_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 484 REG_WAIT(DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 485 break; 486 default: 487 BREAK_TO_DEBUGGER(); 488 break; 489 } 490 if (org_ip_request_cntl == 0) 491 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); 492 } 493 494 int dcn31_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config) 495 { 496 struct dcn_hubbub_phys_addr_config config; 497 498 config.system_aperture.fb_top = pa_config->system_aperture.fb_top; 499 config.system_aperture.fb_offset = pa_config->system_aperture.fb_offset; 500 config.system_aperture.fb_base = pa_config->system_aperture.fb_base; 501 config.system_aperture.agp_top = pa_config->system_aperture.agp_top; 502 config.system_aperture.agp_bot = pa_config->system_aperture.agp_bot; 503 config.system_aperture.agp_base = pa_config->system_aperture.agp_base; 504 config.gart_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr; 505 config.gart_config.page_table_end_addr = pa_config->gart_config.page_table_end_addr; 506 507 if (pa_config->gart_config.base_addr_is_mc_addr) { 508 /* Convert from MC address to offset into FB */ 509 config.gart_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr - 510 pa_config->system_aperture.fb_base + 511 pa_config->system_aperture.fb_offset; 512 } else 513 config.gart_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr; 514 515 return dc->res_pool->hubbub->funcs->init_dchub_sys_ctx(dc->res_pool->hubbub, &config); 516 } 517 518 static void dcn31_reset_back_end_for_pipe( 519 struct dc *dc, 520 struct pipe_ctx *pipe_ctx, 521 struct dc_state *context) 522 { 523 struct dc_link *link; 524 525 DC_LOGGER_INIT(dc->ctx->logger); 526 if (pipe_ctx->stream_res.stream_enc == NULL) { 527 pipe_ctx->stream = NULL; 528 return; 529 } 530 ASSERT(!pipe_ctx->top_pipe); 531 532 dc->hwss.set_abm_immediate_disable(pipe_ctx); 533 534 pipe_ctx->stream_res.tg->funcs->set_dsc_config( 535 pipe_ctx->stream_res.tg, 536 OPTC_DSC_DISABLED, 0, 0); 537 pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg); 538 539 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false); 540 if (pipe_ctx->stream_res.tg->funcs->set_odm_bypass) 541 pipe_ctx->stream_res.tg->funcs->set_odm_bypass( 542 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); 543 544 if (pipe_ctx->stream_res.tg->funcs->set_drr) 545 pipe_ctx->stream_res.tg->funcs->set_drr( 546 pipe_ctx->stream_res.tg, NULL); 547 548 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { 549 link = pipe_ctx->stream->link; 550 /* DPMS may already disable or */ 551 /* dpms_off status is incorrect due to fastboot 552 * feature. When system resume from S4 with second 553 * screen only, the dpms_off would be true but 554 * VBIOS lit up eDP, so check link status too. 555 */ 556 if (!pipe_ctx->stream->dpms_off || link->link_status.link_active) 557 core_link_disable_stream(pipe_ctx); 558 else if (pipe_ctx->stream_res.audio) 559 dc->hwss.disable_audio_stream(pipe_ctx); 560 561 /* free acquired resources */ 562 if (pipe_ctx->stream_res.audio) { 563 /*disable az_endpoint*/ 564 pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio); 565 566 /*free audio*/ 567 if (dc->caps.dynamic_audio == true) { 568 /*we have to dynamic arbitrate the audio endpoints*/ 569 /*we free the resource, need reset is_audio_acquired*/ 570 update_audio_usage(&dc->current_state->res_ctx, dc->res_pool, 571 pipe_ctx->stream_res.audio, false); 572 pipe_ctx->stream_res.audio = NULL; 573 } 574 } 575 } else if (pipe_ctx->stream_res.dsc) { 576 dp_set_dsc_enable(pipe_ctx, false); 577 } 578 579 pipe_ctx->stream = NULL; 580 DC_LOG_DEBUG("Reset back end for pipe %d, tg:%d\n", 581 pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst); 582 } 583 584 void dcn31_reset_hw_ctx_wrap( 585 struct dc *dc, 586 struct dc_state *context) 587 { 588 int i; 589 struct dce_hwseq *hws = dc->hwseq; 590 591 /* Reset Back End*/ 592 for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) { 593 struct pipe_ctx *pipe_ctx_old = 594 &dc->current_state->res_ctx.pipe_ctx[i]; 595 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 596 597 if (!pipe_ctx_old->stream) 598 continue; 599 600 if (pipe_ctx_old->top_pipe || pipe_ctx_old->prev_odm_pipe) 601 continue; 602 603 if (!pipe_ctx->stream || 604 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) { 605 struct clock_source *old_clk = pipe_ctx_old->clock_source; 606 607 dcn31_reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state); 608 if (hws->funcs.enable_stream_gating) 609 hws->funcs.enable_stream_gating(dc, pipe_ctx_old); 610 if (old_clk) 611 old_clk->funcs->cs_power_down(old_clk); 612 } 613 } 614 615 /* New dc_state in the process of being applied to hardware. */ 616 link_enc_cfg_set_transient_mode(dc, dc->current_state, context); 617 } 618 619 void dcn31_setup_hpo_hw_control(const struct dce_hwseq *hws, bool enable) 620 { 621 if (hws->ctx->dc->debug.hpo_optimization) 622 REG_UPDATE(HPO_TOP_HW_CONTROL, HPO_IO_EN, !!enable); 623 } 624