1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 27 #include "dm_services.h" 28 #include "dm_helpers.h" 29 #include "core_types.h" 30 #include "resource.h" 31 #include "dccg.h" 32 #include "dce/dce_hwseq.h" 33 #include "clk_mgr.h" 34 #include "reg_helper.h" 35 #include "abm.h" 36 #include "hubp.h" 37 #include "dchubbub.h" 38 #include "timing_generator.h" 39 #include "opp.h" 40 #include "ipp.h" 41 #include "mpc.h" 42 #include "mcif_wb.h" 43 #include "dc_dmub_srv.h" 44 #include "dcn31_hwseq.h" 45 #include "link_hwss.h" 46 #include "dpcd_defs.h" 47 #include "dce/dmub_outbox.h" 48 #include "dc_link_dp.h" 49 #include "inc/link_dpcd.h" 50 #include "dcn10/dcn10_hw_sequencer.h" 51 #include "inc/link_enc_cfg.h" 52 #include "dcn30/dcn30_vpg.h" 53 #include "dce/dce_i2c_hw.h" 54 55 #define DC_LOGGER_INIT(logger) 56 57 #define CTX \ 58 hws->ctx 59 #define REG(reg)\ 60 hws->regs->reg 61 #define DC_LOGGER \ 62 dc->ctx->logger 63 64 65 #undef FN 66 #define FN(reg_name, field_name) \ 67 hws->shifts->field_name, hws->masks->field_name 68 69 static void enable_memory_low_power(struct dc *dc) 70 { 71 struct dce_hwseq *hws = dc->hwseq; 72 int i; 73 74 if (dc->debug.enable_mem_low_power.bits.dmcu) { 75 // Force ERAM to shutdown if DMCU is not enabled 76 if (dc->debug.disable_dmcu || dc->config.disable_dmcu) { 77 REG_UPDATE(DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, 3); 78 } 79 } 80 81 // Set default OPTC memory power states 82 if (dc->debug.enable_mem_low_power.bits.optc) { 83 // Shutdown when unassigned and light sleep in VBLANK 84 REG_SET_2(ODM_MEM_PWR_CTRL3, 0, ODM_MEM_UNASSIGNED_PWR_MODE, 3, ODM_MEM_VBLANK_PWR_MODE, 1); 85 } 86 87 if (dc->debug.enable_mem_low_power.bits.vga) { 88 // Power down VGA memory 89 REG_UPDATE(MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, 1); 90 } 91 92 if (dc->debug.enable_mem_low_power.bits.mpc) 93 dc->res_pool->mpc->funcs->set_mpc_mem_lp_mode(dc->res_pool->mpc); 94 95 96 if (dc->debug.enable_mem_low_power.bits.vpg && dc->res_pool->stream_enc[0]->vpg->funcs->vpg_powerdown) { 97 // Power down VPGs 98 for (i = 0; i < dc->res_pool->stream_enc_count; i++) 99 dc->res_pool->stream_enc[i]->vpg->funcs->vpg_powerdown(dc->res_pool->stream_enc[i]->vpg); 100 #if defined(CONFIG_DRM_AMD_DC_DCN) 101 for (i = 0; i < dc->res_pool->hpo_dp_stream_enc_count; i++) 102 dc->res_pool->hpo_dp_stream_enc[i]->vpg->funcs->vpg_powerdown(dc->res_pool->hpo_dp_stream_enc[i]->vpg); 103 #endif 104 } 105 106 } 107 108 void dcn31_init_hw(struct dc *dc) 109 { 110 struct abm **abms = dc->res_pool->multiple_abms; 111 struct dce_hwseq *hws = dc->hwseq; 112 struct dc_bios *dcb = dc->ctx->dc_bios; 113 struct resource_pool *res_pool = dc->res_pool; 114 uint32_t backlight = MAX_BACKLIGHT_LEVEL; 115 int i; 116 117 if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks) 118 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr); 119 120 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { 121 122 REG_WRITE(REFCLK_CNTL, 0); 123 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1); 124 REG_WRITE(DIO_MEM_PWR_CTRL, 0); 125 126 if (!dc->debug.disable_clock_gate) { 127 /* enable all DCN clock gating */ 128 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); 129 130 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); 131 132 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); 133 } 134 135 //Enable ability to power gate / don't force power on permanently 136 if (hws->funcs.enable_power_gating_plane) 137 hws->funcs.enable_power_gating_plane(hws, true); 138 139 return; 140 } 141 142 if (!dcb->funcs->is_accelerated_mode(dcb)) { 143 hws->funcs.bios_golden_init(dc); 144 hws->funcs.disable_vga(dc->hwseq); 145 } 146 // Initialize the dccg 147 if (res_pool->dccg->funcs->dccg_init) 148 res_pool->dccg->funcs->dccg_init(res_pool->dccg); 149 150 enable_memory_low_power(dc); 151 152 if (dc->ctx->dc_bios->fw_info_valid) { 153 res_pool->ref_clocks.xtalin_clock_inKhz = 154 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency; 155 156 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { 157 if (res_pool->dccg && res_pool->hubbub) { 158 159 (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg, 160 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency, 161 &res_pool->ref_clocks.dccg_ref_clock_inKhz); 162 163 (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub, 164 res_pool->ref_clocks.dccg_ref_clock_inKhz, 165 &res_pool->ref_clocks.dchub_ref_clock_inKhz); 166 } else { 167 // Not all ASICs have DCCG sw component 168 res_pool->ref_clocks.dccg_ref_clock_inKhz = 169 res_pool->ref_clocks.xtalin_clock_inKhz; 170 res_pool->ref_clocks.dchub_ref_clock_inKhz = 171 res_pool->ref_clocks.xtalin_clock_inKhz; 172 } 173 } 174 } else 175 ASSERT_CRITICAL(false); 176 177 for (i = 0; i < dc->link_count; i++) { 178 /* Power up AND update implementation according to the 179 * required signal (which may be different from the 180 * default signal on connector). 181 */ 182 struct dc_link *link = dc->links[i]; 183 184 if (link->ep_type != DISPLAY_ENDPOINT_PHY) 185 continue; 186 187 link->link_enc->funcs->hw_init(link->link_enc); 188 189 /* Check for enabled DIG to identify enabled display */ 190 if (link->link_enc->funcs->is_dig_enabled && 191 link->link_enc->funcs->is_dig_enabled(link->link_enc)) 192 link->link_status.link_active = true; 193 } 194 195 /* Enables outbox notifications for usb4 dpia */ 196 if (dc->res_pool->usb4_dpia_count) 197 dmub_enable_outbox_notification(dc->ctx->dmub_srv); 198 199 /* we want to turn off all dp displays before doing detection */ 200 dc_link_blank_all_dp_displays(dc); 201 202 if (hws->funcs.enable_power_gating_plane) 203 hws->funcs.enable_power_gating_plane(dc->hwseq, true); 204 205 /* If taking control over from VBIOS, we may want to optimize our first 206 * mode set, so we need to skip powering down pipes until we know which 207 * pipes we want to use. 208 * Otherwise, if taking control is not possible, we need to power 209 * everything down. 210 */ 211 if (dcb->funcs->is_accelerated_mode(dcb) || !dc->config.seamless_boot_edp_requested) { 212 hws->funcs.init_pipes(dc, dc->current_state); 213 if (dc->res_pool->hubbub->funcs->allow_self_refresh_control) 214 dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, 215 !dc->res_pool->hubbub->ctx->dc->debug.disable_stutter); 216 } 217 218 for (i = 0; i < res_pool->audio_count; i++) { 219 struct audio *audio = res_pool->audios[i]; 220 221 audio->funcs->hw_init(audio); 222 } 223 224 for (i = 0; i < dc->link_count; i++) { 225 struct dc_link *link = dc->links[i]; 226 227 if (link->panel_cntl) 228 backlight = link->panel_cntl->funcs->hw_init(link->panel_cntl); 229 } 230 231 for (i = 0; i < dc->res_pool->pipe_count; i++) { 232 if (abms[i] != NULL) 233 abms[i]->funcs->abm_init(abms[i], backlight); 234 } 235 236 /* power AFMT HDMI memory TODO: may move to dis/en output save power*/ 237 REG_WRITE(DIO_MEM_PWR_CTRL, 0); 238 239 // Set i2c to light sleep until engine is setup 240 if (dc->debug.enable_mem_low_power.bits.i2c) 241 REG_UPDATE(DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, 1); 242 243 if (hws->funcs.setup_hpo_hw_control) 244 hws->funcs.setup_hpo_hw_control(hws, false); 245 246 if (!dc->debug.disable_clock_gate) { 247 /* enable all DCN clock gating */ 248 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); 249 250 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); 251 252 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); 253 } 254 255 if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks) 256 dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub); 257 258 if (dc->clk_mgr->funcs->notify_wm_ranges) 259 dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr); 260 261 if (dc->clk_mgr->funcs->set_hard_max_memclk) 262 dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr); 263 264 if (dc->res_pool->hubbub->funcs->force_pstate_change_control) 265 dc->res_pool->hubbub->funcs->force_pstate_change_control( 266 dc->res_pool->hubbub, false, false); 267 #if defined(CONFIG_DRM_AMD_DC_DCN) 268 if (dc->res_pool->hubbub->funcs->init_crb) 269 dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub); 270 #endif 271 } 272 273 void dcn31_dsc_pg_control( 274 struct dce_hwseq *hws, 275 unsigned int dsc_inst, 276 bool power_on) 277 { 278 uint32_t power_gate = power_on ? 0 : 1; 279 uint32_t pwr_status = power_on ? 0 : 2; 280 uint32_t org_ip_request_cntl = 0; 281 282 if (hws->ctx->dc->debug.disable_dsc_power_gate) 283 return; 284 285 if (hws->ctx->dc->debug.root_clock_optimization.bits.dsc && 286 hws->ctx->dc->res_pool->dccg->funcs->enable_dsc && 287 power_on) 288 hws->ctx->dc->res_pool->dccg->funcs->enable_dsc( 289 hws->ctx->dc->res_pool->dccg, dsc_inst); 290 291 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); 292 if (org_ip_request_cntl == 0) 293 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); 294 295 switch (dsc_inst) { 296 case 0: /* DSC0 */ 297 REG_UPDATE(DOMAIN16_PG_CONFIG, 298 DOMAIN_POWER_GATE, power_gate); 299 300 REG_WAIT(DOMAIN16_PG_STATUS, 301 DOMAIN_PGFSM_PWR_STATUS, pwr_status, 302 1, 1000); 303 break; 304 case 1: /* DSC1 */ 305 REG_UPDATE(DOMAIN17_PG_CONFIG, 306 DOMAIN_POWER_GATE, power_gate); 307 308 REG_WAIT(DOMAIN17_PG_STATUS, 309 DOMAIN_PGFSM_PWR_STATUS, pwr_status, 310 1, 1000); 311 break; 312 case 2: /* DSC2 */ 313 REG_UPDATE(DOMAIN18_PG_CONFIG, 314 DOMAIN_POWER_GATE, power_gate); 315 316 REG_WAIT(DOMAIN18_PG_STATUS, 317 DOMAIN_PGFSM_PWR_STATUS, pwr_status, 318 1, 1000); 319 break; 320 default: 321 BREAK_TO_DEBUGGER(); 322 break; 323 } 324 325 if (org_ip_request_cntl == 0) 326 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); 327 328 if (hws->ctx->dc->debug.root_clock_optimization.bits.dsc) { 329 if (hws->ctx->dc->res_pool->dccg->funcs->disable_dsc && !power_on) 330 hws->ctx->dc->res_pool->dccg->funcs->disable_dsc( 331 hws->ctx->dc->res_pool->dccg, dsc_inst); 332 } 333 334 } 335 336 337 void dcn31_enable_power_gating_plane( 338 struct dce_hwseq *hws, 339 bool enable) 340 { 341 bool force_on = true; /* disable power gating */ 342 uint32_t org_ip_request_cntl = 0; 343 344 if (enable && !hws->ctx->dc->debug.disable_hubp_power_gate) 345 force_on = false; 346 347 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); 348 if (org_ip_request_cntl == 0) 349 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); 350 /* DCHUBP0/1/2/3/4/5 */ 351 REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 352 REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 353 /* DPP0/1/2/3/4/5 */ 354 REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 355 REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 356 357 force_on = true; /* disable power gating */ 358 if (enable && !hws->ctx->dc->debug.disable_dsc_power_gate) 359 force_on = false; 360 361 /* DCS0/1/2/3/4/5 */ 362 REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 363 REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 364 REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 365 366 if (org_ip_request_cntl == 0) 367 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); 368 } 369 370 void dcn31_update_info_frame(struct pipe_ctx *pipe_ctx) 371 { 372 bool is_hdmi_tmds; 373 bool is_dp; 374 375 ASSERT(pipe_ctx->stream); 376 377 if (pipe_ctx->stream_res.stream_enc == NULL) 378 return; /* this is not root pipe */ 379 380 is_hdmi_tmds = dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal); 381 is_dp = dc_is_dp_signal(pipe_ctx->stream->signal); 382 383 if (!is_hdmi_tmds && !is_dp) 384 return; 385 386 if (is_hdmi_tmds) 387 pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets( 388 pipe_ctx->stream_res.stream_enc, 389 &pipe_ctx->stream_res.encoder_info_frame); 390 else { 391 pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets( 392 pipe_ctx->stream_res.stream_enc, 393 &pipe_ctx->stream_res.encoder_info_frame); 394 } 395 } 396 void dcn31_z10_save_init(struct dc *dc) 397 { 398 union dmub_rb_cmd cmd; 399 400 memset(&cmd, 0, sizeof(cmd)); 401 cmd.dcn_restore.header.type = DMUB_CMD__IDLE_OPT; 402 cmd.dcn_restore.header.sub_type = DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT; 403 404 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd); 405 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv); 406 dc_dmub_srv_wait_idle(dc->ctx->dmub_srv); 407 } 408 409 void dcn31_z10_restore(const struct dc *dc) 410 { 411 union dmub_rb_cmd cmd; 412 413 /* 414 * DMUB notifies whether restore is required. 415 * Optimization to avoid sending commands when not required. 416 */ 417 if (!dc_dmub_srv_is_restore_required(dc->ctx->dmub_srv)) 418 return; 419 420 memset(&cmd, 0, sizeof(cmd)); 421 cmd.dcn_restore.header.type = DMUB_CMD__IDLE_OPT; 422 cmd.dcn_restore.header.sub_type = DMUB_CMD__IDLE_OPT_DCN_RESTORE; 423 424 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd); 425 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv); 426 dc_dmub_srv_wait_idle(dc->ctx->dmub_srv); 427 } 428 429 void dcn31_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on) 430 { 431 uint32_t power_gate = power_on ? 0 : 1; 432 uint32_t pwr_status = power_on ? 0 : 2; 433 uint32_t org_ip_request_cntl; 434 if (hws->ctx->dc->debug.disable_hubp_power_gate) 435 return; 436 437 if (REG(DOMAIN0_PG_CONFIG) == 0) 438 return; 439 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); 440 if (org_ip_request_cntl == 0) 441 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); 442 443 switch (hubp_inst) { 444 case 0: 445 REG_SET(DOMAIN0_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 446 REG_WAIT(DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 447 break; 448 case 1: 449 REG_SET(DOMAIN1_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 450 REG_WAIT(DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 451 break; 452 case 2: 453 REG_SET(DOMAIN2_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 454 REG_WAIT(DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 455 break; 456 case 3: 457 REG_SET(DOMAIN3_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 458 REG_WAIT(DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 459 break; 460 default: 461 BREAK_TO_DEBUGGER(); 462 break; 463 } 464 if (org_ip_request_cntl == 0) 465 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); 466 } 467 468 int dcn31_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config) 469 { 470 struct dcn_hubbub_phys_addr_config config; 471 472 config.system_aperture.fb_top = pa_config->system_aperture.fb_top; 473 config.system_aperture.fb_offset = pa_config->system_aperture.fb_offset; 474 config.system_aperture.fb_base = pa_config->system_aperture.fb_base; 475 config.system_aperture.agp_top = pa_config->system_aperture.agp_top; 476 config.system_aperture.agp_bot = pa_config->system_aperture.agp_bot; 477 config.system_aperture.agp_base = pa_config->system_aperture.agp_base; 478 config.gart_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr; 479 config.gart_config.page_table_end_addr = pa_config->gart_config.page_table_end_addr; 480 481 if (pa_config->gart_config.base_addr_is_mc_addr) { 482 /* Convert from MC address to offset into FB */ 483 config.gart_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr - 484 pa_config->system_aperture.fb_base + 485 pa_config->system_aperture.fb_offset; 486 } else 487 config.gart_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr; 488 489 return dc->res_pool->hubbub->funcs->init_dchub_sys_ctx(dc->res_pool->hubbub, &config); 490 } 491 492 static void dcn31_reset_back_end_for_pipe( 493 struct dc *dc, 494 struct pipe_ctx *pipe_ctx, 495 struct dc_state *context) 496 { 497 struct dc_link *link; 498 499 DC_LOGGER_INIT(dc->ctx->logger); 500 if (pipe_ctx->stream_res.stream_enc == NULL) { 501 pipe_ctx->stream = NULL; 502 return; 503 } 504 ASSERT(!pipe_ctx->top_pipe); 505 506 dc->hwss.set_abm_immediate_disable(pipe_ctx); 507 508 pipe_ctx->stream_res.tg->funcs->set_dsc_config( 509 pipe_ctx->stream_res.tg, 510 OPTC_DSC_DISABLED, 0, 0); 511 pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg); 512 513 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false); 514 if (pipe_ctx->stream_res.tg->funcs->set_odm_bypass) 515 pipe_ctx->stream_res.tg->funcs->set_odm_bypass( 516 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); 517 518 if (pipe_ctx->stream_res.tg->funcs->set_drr) 519 pipe_ctx->stream_res.tg->funcs->set_drr( 520 pipe_ctx->stream_res.tg, NULL); 521 522 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { 523 link = pipe_ctx->stream->link; 524 /* DPMS may already disable or */ 525 /* dpms_off status is incorrect due to fastboot 526 * feature. When system resume from S4 with second 527 * screen only, the dpms_off would be true but 528 * VBIOS lit up eDP, so check link status too. 529 */ 530 if (!pipe_ctx->stream->dpms_off || link->link_status.link_active) 531 core_link_disable_stream(pipe_ctx); 532 else if (pipe_ctx->stream_res.audio) 533 dc->hwss.disable_audio_stream(pipe_ctx); 534 535 /* free acquired resources */ 536 if (pipe_ctx->stream_res.audio) { 537 /*disable az_endpoint*/ 538 pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio); 539 540 /*free audio*/ 541 if (dc->caps.dynamic_audio == true) { 542 /*we have to dynamic arbitrate the audio endpoints*/ 543 /*we free the resource, need reset is_audio_acquired*/ 544 update_audio_usage(&dc->current_state->res_ctx, dc->res_pool, 545 pipe_ctx->stream_res.audio, false); 546 pipe_ctx->stream_res.audio = NULL; 547 } 548 } 549 } else if (pipe_ctx->stream_res.dsc) { 550 dp_set_dsc_enable(pipe_ctx, false); 551 } 552 553 pipe_ctx->stream = NULL; 554 DC_LOG_DEBUG("Reset back end for pipe %d, tg:%d\n", 555 pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst); 556 } 557 558 void dcn31_reset_hw_ctx_wrap( 559 struct dc *dc, 560 struct dc_state *context) 561 { 562 int i; 563 struct dce_hwseq *hws = dc->hwseq; 564 565 /* Reset Back End*/ 566 for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) { 567 struct pipe_ctx *pipe_ctx_old = 568 &dc->current_state->res_ctx.pipe_ctx[i]; 569 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 570 571 if (!pipe_ctx_old->stream) 572 continue; 573 574 if (pipe_ctx_old->top_pipe || pipe_ctx_old->prev_odm_pipe) 575 continue; 576 577 if (!pipe_ctx->stream || 578 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) { 579 struct clock_source *old_clk = pipe_ctx_old->clock_source; 580 581 dcn31_reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state); 582 if (hws->funcs.enable_stream_gating) 583 hws->funcs.enable_stream_gating(dc, pipe_ctx_old); 584 if (old_clk) 585 old_clk->funcs->cs_power_down(old_clk); 586 } 587 } 588 589 /* New dc_state in the process of being applied to hardware. */ 590 dc->current_state->res_ctx.link_enc_cfg_ctx.mode = LINK_ENC_CFG_TRANSIENT; 591 } 592 593 void dcn31_setup_hpo_hw_control(const struct dce_hwseq *hws, bool enable) 594 { 595 if (hws->ctx->dc->debug.hpo_optimization) 596 REG_UPDATE(HPO_TOP_HW_CONTROL, HPO_IO_EN, !!enable); 597 } 598