1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 27 #include "dm_services.h" 28 #include "dm_helpers.h" 29 #include "core_types.h" 30 #include "resource.h" 31 #include "dccg.h" 32 #include "dce/dce_hwseq.h" 33 #include "clk_mgr.h" 34 #include "reg_helper.h" 35 #include "abm.h" 36 #include "hubp.h" 37 #include "dchubbub.h" 38 #include "timing_generator.h" 39 #include "opp.h" 40 #include "ipp.h" 41 #include "mpc.h" 42 #include "mcif_wb.h" 43 #include "dc_dmub_srv.h" 44 #include "dcn31_hwseq.h" 45 #include "link_hwss.h" 46 #include "dpcd_defs.h" 47 #include "dce/dmub_outbox.h" 48 #include "dc_link_dp.h" 49 #include "inc/link_dpcd.h" 50 #include "dcn10/dcn10_hw_sequencer.h" 51 #include "inc/link_enc_cfg.h" 52 53 #define DC_LOGGER_INIT(logger) 54 55 #define CTX \ 56 hws->ctx 57 #define REG(reg)\ 58 hws->regs->reg 59 #define DC_LOGGER \ 60 dc->ctx->logger 61 62 63 #undef FN 64 #define FN(reg_name, field_name) \ 65 hws->shifts->field_name, hws->masks->field_name 66 67 void dcn31_init_hw(struct dc *dc) 68 { 69 struct abm **abms = dc->res_pool->multiple_abms; 70 struct dce_hwseq *hws = dc->hwseq; 71 struct dc_bios *dcb = dc->ctx->dc_bios; 72 struct resource_pool *res_pool = dc->res_pool; 73 uint32_t backlight = MAX_BACKLIGHT_LEVEL; 74 int i, j; 75 int edp_num; 76 77 if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks) 78 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr); 79 80 // Initialize the dccg 81 if (res_pool->dccg->funcs->dccg_init) 82 res_pool->dccg->funcs->dccg_init(res_pool->dccg); 83 84 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { 85 86 REG_WRITE(REFCLK_CNTL, 0); 87 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1); 88 REG_WRITE(DIO_MEM_PWR_CTRL, 0); 89 90 if (!dc->debug.disable_clock_gate) { 91 /* enable all DCN clock gating */ 92 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); 93 94 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); 95 96 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); 97 } 98 99 //Enable ability to power gate / don't force power on permanently 100 if (hws->funcs.enable_power_gating_plane) 101 hws->funcs.enable_power_gating_plane(hws, true); 102 103 return; 104 } 105 106 if (!dcb->funcs->is_accelerated_mode(dcb)) { 107 hws->funcs.bios_golden_init(dc); 108 hws->funcs.disable_vga(dc->hwseq); 109 } 110 111 if (dc->debug.enable_mem_low_power.bits.dmcu) { 112 // Force ERAM to shutdown if DMCU is not enabled 113 if (dc->debug.disable_dmcu || dc->config.disable_dmcu) { 114 REG_UPDATE(DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, 3); 115 } 116 } 117 118 // Set default OPTC memory power states 119 if (dc->debug.enable_mem_low_power.bits.optc) { 120 // Shutdown when unassigned and light sleep in VBLANK 121 REG_SET_2(ODM_MEM_PWR_CTRL3, 0, ODM_MEM_UNASSIGNED_PWR_MODE, 3, ODM_MEM_VBLANK_PWR_MODE, 1); 122 } 123 124 if (dc->debug.enable_mem_low_power.bits.vga) { 125 // Power down VGA memory 126 REG_UPDATE(MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, 1); 127 } 128 129 if (dc->ctx->dc_bios->fw_info_valid) { 130 res_pool->ref_clocks.xtalin_clock_inKhz = 131 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency; 132 133 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { 134 if (res_pool->dccg && res_pool->hubbub) { 135 136 (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg, 137 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency, 138 &res_pool->ref_clocks.dccg_ref_clock_inKhz); 139 140 (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub, 141 res_pool->ref_clocks.dccg_ref_clock_inKhz, 142 &res_pool->ref_clocks.dchub_ref_clock_inKhz); 143 } else { 144 // Not all ASICs have DCCG sw component 145 res_pool->ref_clocks.dccg_ref_clock_inKhz = 146 res_pool->ref_clocks.xtalin_clock_inKhz; 147 res_pool->ref_clocks.dchub_ref_clock_inKhz = 148 res_pool->ref_clocks.xtalin_clock_inKhz; 149 } 150 } 151 } else 152 ASSERT_CRITICAL(false); 153 154 for (i = 0; i < dc->link_count; i++) { 155 /* Power up AND update implementation according to the 156 * required signal (which may be different from the 157 * default signal on connector). 158 */ 159 struct dc_link *link = dc->links[i]; 160 161 if (link->ep_type != DISPLAY_ENDPOINT_PHY) 162 continue; 163 164 link->link_enc->funcs->hw_init(link->link_enc); 165 166 /* Check for enabled DIG to identify enabled display */ 167 if (link->link_enc->funcs->is_dig_enabled && 168 link->link_enc->funcs->is_dig_enabled(link->link_enc)) 169 link->link_status.link_active = true; 170 } 171 172 /* Power gate DSCs */ 173 for (i = 0; i < res_pool->res_cap->num_dsc; i++) 174 if (hws->funcs.dsc_pg_control != NULL) 175 hws->funcs.dsc_pg_control(hws, res_pool->dscs[i]->inst, false); 176 177 /* we want to turn off all dp displays before doing detection */ 178 if (dc->config.power_down_display_on_boot) { 179 uint8_t dpcd_power_state = '\0'; 180 enum dc_status status = DC_ERROR_UNEXPECTED; 181 182 for (i = 0; i < dc->link_count; i++) { 183 if (dc->links[i]->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) 184 continue; 185 186 /* if any of the displays are lit up turn them off */ 187 status = core_link_read_dpcd(dc->links[i], DP_SET_POWER, 188 &dpcd_power_state, sizeof(dpcd_power_state)); 189 if (status == DC_OK && dpcd_power_state == DP_POWER_STATE_D0) { 190 /* blank dp stream before power off receiver*/ 191 if (dc->links[i]->ep_type == DISPLAY_ENDPOINT_PHY && 192 dc->links[i]->link_enc->funcs->get_dig_frontend) { 193 unsigned int fe; 194 195 fe = dc->links[i]->link_enc->funcs->get_dig_frontend( 196 dc->links[i]->link_enc); 197 if (fe == ENGINE_ID_UNKNOWN) 198 continue; 199 200 for (j = 0; j < dc->res_pool->stream_enc_count; j++) { 201 if (fe == dc->res_pool->stream_enc[j]->id) { 202 dc->res_pool->stream_enc[j]->funcs->dp_blank(dc->links[i], 203 dc->res_pool->stream_enc[j]); 204 break; 205 } 206 } 207 } 208 dp_receiver_power_ctrl(dc->links[i], false); 209 } 210 } 211 } 212 213 /* If taking control over from VBIOS, we may want to optimize our first 214 * mode set, so we need to skip powering down pipes until we know which 215 * pipes we want to use. 216 * Otherwise, if taking control is not possible, we need to power 217 * everything down. 218 */ 219 if (dcb->funcs->is_accelerated_mode(dcb) || dc->config.power_down_display_on_boot) { 220 hws->funcs.init_pipes(dc, dc->current_state); 221 if (dc->res_pool->hubbub->funcs->allow_self_refresh_control) 222 dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, 223 !dc->res_pool->hubbub->ctx->dc->debug.disable_stutter); 224 } 225 226 /* In headless boot cases, DIG may be turned 227 * on which causes HW/SW discrepancies. 228 * To avoid this, power down hardware on boot 229 * if DIG is turned on and seamless boot not enabled 230 */ 231 if (dc->config.power_down_display_on_boot) { 232 struct dc_link *edp_links[MAX_NUM_EDP]; 233 struct dc_link *edp_link; 234 bool power_down = false; 235 236 get_edp_links(dc, edp_links, &edp_num); 237 if (edp_num) { 238 for (i = 0; i < edp_num; i++) { 239 edp_link = edp_links[i]; 240 if (edp_link->link_enc->funcs->is_dig_enabled && 241 edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc) && 242 dc->hwss.edp_backlight_control && 243 dc->hwss.power_down && 244 dc->hwss.edp_power_control) { 245 dc->hwss.edp_backlight_control(edp_link, false); 246 dc->hwss.power_down(dc); 247 dc->hwss.edp_power_control(edp_link, false); 248 power_down = true; 249 } 250 } 251 } 252 if (!power_down) { 253 for (i = 0; i < dc->link_count; i++) { 254 struct dc_link *link = dc->links[i]; 255 256 if (link->ep_type == DISPLAY_ENDPOINT_PHY && 257 link->link_enc->funcs->is_dig_enabled && 258 link->link_enc->funcs->is_dig_enabled(link->link_enc) && 259 dc->hwss.power_down) { 260 dc->hwss.power_down(dc); 261 break; 262 } 263 264 } 265 } 266 } 267 268 for (i = 0; i < res_pool->audio_count; i++) { 269 struct audio *audio = res_pool->audios[i]; 270 271 audio->funcs->hw_init(audio); 272 } 273 274 for (i = 0; i < dc->link_count; i++) { 275 struct dc_link *link = dc->links[i]; 276 277 if (link->panel_cntl) 278 backlight = link->panel_cntl->funcs->hw_init(link->panel_cntl); 279 } 280 281 for (i = 0; i < dc->res_pool->pipe_count; i++) { 282 if (abms[i] != NULL) 283 abms[i]->funcs->abm_init(abms[i], backlight); 284 } 285 286 /* power AFMT HDMI memory TODO: may move to dis/en output save power*/ 287 REG_WRITE(DIO_MEM_PWR_CTRL, 0); 288 289 if (!dc->debug.disable_clock_gate) { 290 /* enable all DCN clock gating */ 291 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); 292 293 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); 294 295 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); 296 } 297 if (hws->funcs.enable_power_gating_plane) 298 hws->funcs.enable_power_gating_plane(dc->hwseq, true); 299 300 if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks) 301 dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub); 302 303 if (dc->clk_mgr->funcs->notify_wm_ranges) 304 dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr); 305 306 if (dc->clk_mgr->funcs->set_hard_max_memclk) 307 dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr); 308 309 if (dc->res_pool->hubbub->funcs->force_pstate_change_control) 310 dc->res_pool->hubbub->funcs->force_pstate_change_control( 311 dc->res_pool->hubbub, false, false); 312 if (dc->res_pool->hubbub->funcs->init_crb) 313 dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub); 314 } 315 316 void dcn31_dsc_pg_control( 317 struct dce_hwseq *hws, 318 unsigned int dsc_inst, 319 bool power_on) 320 { 321 uint32_t power_gate = power_on ? 0 : 1; 322 uint32_t pwr_status = power_on ? 0 : 2; 323 uint32_t org_ip_request_cntl = 0; 324 325 if (hws->ctx->dc->debug.disable_dsc_power_gate) 326 return; 327 328 REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); 329 if (org_ip_request_cntl == 0) 330 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); 331 332 switch (dsc_inst) { 333 case 0: /* DSC0 */ 334 REG_UPDATE(DOMAIN16_PG_CONFIG, 335 DOMAIN_POWER_GATE, power_gate); 336 337 REG_WAIT(DOMAIN16_PG_STATUS, 338 DOMAIN_PGFSM_PWR_STATUS, pwr_status, 339 1, 1000); 340 break; 341 case 1: /* DSC1 */ 342 REG_UPDATE(DOMAIN17_PG_CONFIG, 343 DOMAIN_POWER_GATE, power_gate); 344 345 REG_WAIT(DOMAIN17_PG_STATUS, 346 DOMAIN_PGFSM_PWR_STATUS, pwr_status, 347 1, 1000); 348 break; 349 case 2: /* DSC2 */ 350 REG_UPDATE(DOMAIN18_PG_CONFIG, 351 DOMAIN_POWER_GATE, power_gate); 352 353 REG_WAIT(DOMAIN18_PG_STATUS, 354 DOMAIN_PGFSM_PWR_STATUS, pwr_status, 355 1, 1000); 356 break; 357 default: 358 BREAK_TO_DEBUGGER(); 359 break; 360 } 361 362 if (org_ip_request_cntl == 0) 363 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); 364 } 365 366 367 void dcn31_enable_power_gating_plane( 368 struct dce_hwseq *hws, 369 bool enable) 370 { 371 bool force_on = true; /* disable power gating */ 372 373 if (enable) 374 force_on = false; 375 376 /* DCHUBP0/1/2/3/4/5 */ 377 REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 378 REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 379 380 /* DPP0/1/2/3/4/5 */ 381 REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 382 REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 383 384 /* DCS0/1/2/3/4/5 */ 385 REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 386 REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 387 REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 388 } 389 390 void dcn31_update_info_frame(struct pipe_ctx *pipe_ctx) 391 { 392 bool is_hdmi_tmds; 393 bool is_dp; 394 395 ASSERT(pipe_ctx->stream); 396 397 if (pipe_ctx->stream_res.stream_enc == NULL) 398 return; /* this is not root pipe */ 399 400 is_hdmi_tmds = dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal); 401 is_dp = dc_is_dp_signal(pipe_ctx->stream->signal); 402 403 if (!is_hdmi_tmds && !is_dp) 404 return; 405 406 if (is_hdmi_tmds) 407 pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets( 408 pipe_ctx->stream_res.stream_enc, 409 &pipe_ctx->stream_res.encoder_info_frame); 410 else { 411 pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets( 412 pipe_ctx->stream_res.stream_enc, 413 &pipe_ctx->stream_res.encoder_info_frame); 414 } 415 } 416 void dcn31_z10_save_init(struct dc *dc) 417 { 418 union dmub_rb_cmd cmd; 419 420 memset(&cmd, 0, sizeof(cmd)); 421 cmd.dcn_restore.header.type = DMUB_CMD__IDLE_OPT; 422 cmd.dcn_restore.header.sub_type = DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT; 423 424 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd); 425 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv); 426 dc_dmub_srv_wait_idle(dc->ctx->dmub_srv); 427 } 428 429 void dcn31_z10_restore(const struct dc *dc) 430 { 431 union dmub_rb_cmd cmd; 432 433 /* 434 * DMUB notifies whether restore is required. 435 * Optimization to avoid sending commands when not required. 436 */ 437 if (!dc_dmub_srv_is_restore_required(dc->ctx->dmub_srv)) 438 return; 439 440 memset(&cmd, 0, sizeof(cmd)); 441 cmd.dcn_restore.header.type = DMUB_CMD__IDLE_OPT; 442 cmd.dcn_restore.header.sub_type = DMUB_CMD__IDLE_OPT_DCN_RESTORE; 443 444 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd); 445 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv); 446 dc_dmub_srv_wait_idle(dc->ctx->dmub_srv); 447 } 448 449 void dcn31_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on) 450 { 451 uint32_t power_gate = power_on ? 0 : 1; 452 uint32_t pwr_status = power_on ? 0 : 2; 453 454 if (hws->ctx->dc->debug.disable_hubp_power_gate) 455 return; 456 457 if (REG(DOMAIN0_PG_CONFIG) == 0) 458 return; 459 460 switch (hubp_inst) { 461 case 0: 462 REG_SET(DOMAIN0_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 463 REG_WAIT(DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 464 break; 465 case 1: 466 REG_SET(DOMAIN1_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 467 REG_WAIT(DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 468 break; 469 case 2: 470 REG_SET(DOMAIN2_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 471 REG_WAIT(DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 472 break; 473 case 3: 474 REG_SET(DOMAIN3_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 475 REG_WAIT(DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 476 break; 477 default: 478 BREAK_TO_DEBUGGER(); 479 break; 480 } 481 } 482 483 int dcn31_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config) 484 { 485 struct dcn_hubbub_phys_addr_config config; 486 487 config.system_aperture.fb_top = pa_config->system_aperture.fb_top; 488 config.system_aperture.fb_offset = pa_config->system_aperture.fb_offset; 489 config.system_aperture.fb_base = pa_config->system_aperture.fb_base; 490 config.system_aperture.agp_top = pa_config->system_aperture.agp_top; 491 config.system_aperture.agp_bot = pa_config->system_aperture.agp_bot; 492 config.system_aperture.agp_base = pa_config->system_aperture.agp_base; 493 config.gart_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr; 494 config.gart_config.page_table_end_addr = pa_config->gart_config.page_table_end_addr; 495 496 if (pa_config->gart_config.base_addr_is_mc_addr) { 497 /* Convert from MC address to offset into FB */ 498 config.gart_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr - 499 pa_config->system_aperture.fb_base + 500 pa_config->system_aperture.fb_offset; 501 } else 502 config.gart_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr; 503 504 return dc->res_pool->hubbub->funcs->init_dchub_sys_ctx(dc->res_pool->hubbub, &config); 505 } 506 507 static void dcn31_reset_back_end_for_pipe( 508 struct dc *dc, 509 struct pipe_ctx *pipe_ctx, 510 struct dc_state *context) 511 { 512 struct dc_link *link; 513 514 DC_LOGGER_INIT(dc->ctx->logger); 515 if (pipe_ctx->stream_res.stream_enc == NULL) { 516 pipe_ctx->stream = NULL; 517 return; 518 } 519 ASSERT(!pipe_ctx->top_pipe); 520 521 dc->hwss.set_abm_immediate_disable(pipe_ctx); 522 523 pipe_ctx->stream_res.tg->funcs->set_dsc_config( 524 pipe_ctx->stream_res.tg, 525 OPTC_DSC_DISABLED, 0, 0); 526 pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg); 527 528 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false); 529 if (pipe_ctx->stream_res.tg->funcs->set_odm_bypass) 530 pipe_ctx->stream_res.tg->funcs->set_odm_bypass( 531 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); 532 533 if (pipe_ctx->stream_res.tg->funcs->set_drr) 534 pipe_ctx->stream_res.tg->funcs->set_drr( 535 pipe_ctx->stream_res.tg, NULL); 536 537 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { 538 link = pipe_ctx->stream->link; 539 /* DPMS may already disable or */ 540 /* dpms_off status is incorrect due to fastboot 541 * feature. When system resume from S4 with second 542 * screen only, the dpms_off would be true but 543 * VBIOS lit up eDP, so check link status too. 544 */ 545 if (!pipe_ctx->stream->dpms_off || link->link_status.link_active) 546 core_link_disable_stream(pipe_ctx); 547 else if (pipe_ctx->stream_res.audio) 548 dc->hwss.disable_audio_stream(pipe_ctx); 549 550 /* free acquired resources */ 551 if (pipe_ctx->stream_res.audio) { 552 /*disable az_endpoint*/ 553 pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio); 554 555 /*free audio*/ 556 if (dc->caps.dynamic_audio == true) { 557 /*we have to dynamic arbitrate the audio endpoints*/ 558 /*we free the resource, need reset is_audio_acquired*/ 559 update_audio_usage(&dc->current_state->res_ctx, dc->res_pool, 560 pipe_ctx->stream_res.audio, false); 561 pipe_ctx->stream_res.audio = NULL; 562 } 563 } 564 } else if (pipe_ctx->stream_res.dsc) { 565 dp_set_dsc_enable(pipe_ctx, false); 566 } 567 568 pipe_ctx->stream = NULL; 569 DC_LOG_DEBUG("Reset back end for pipe %d, tg:%d\n", 570 pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst); 571 } 572 573 void dcn31_reset_hw_ctx_wrap( 574 struct dc *dc, 575 struct dc_state *context) 576 { 577 int i; 578 struct dce_hwseq *hws = dc->hwseq; 579 580 /* Reset Back End*/ 581 for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) { 582 struct pipe_ctx *pipe_ctx_old = 583 &dc->current_state->res_ctx.pipe_ctx[i]; 584 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 585 586 if (!pipe_ctx_old->stream) 587 continue; 588 589 if (pipe_ctx_old->top_pipe || pipe_ctx_old->prev_odm_pipe) 590 continue; 591 592 if (!pipe_ctx->stream || 593 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) { 594 struct clock_source *old_clk = pipe_ctx_old->clock_source; 595 596 dcn31_reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state); 597 if (hws->funcs.enable_stream_gating) 598 hws->funcs.enable_stream_gating(dc, pipe_ctx); 599 if (old_clk) 600 old_clk->funcs->cs_power_down(old_clk); 601 } 602 } 603 604 /* New dc_state in the process of being applied to hardware. */ 605 dc->current_state->res_ctx.link_enc_cfg_ctx.mode = LINK_ENC_CFG_TRANSIENT; 606 } 607