1 /*
2  * Copyright 2016 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 
27 #include "dm_services.h"
28 #include "dm_helpers.h"
29 #include "core_types.h"
30 #include "resource.h"
31 #include "dccg.h"
32 #include "dce/dce_hwseq.h"
33 #include "clk_mgr.h"
34 #include "reg_helper.h"
35 #include "abm.h"
36 #include "hubp.h"
37 #include "dchubbub.h"
38 #include "timing_generator.h"
39 #include "opp.h"
40 #include "ipp.h"
41 #include "mpc.h"
42 #include "mcif_wb.h"
43 #include "dc_dmub_srv.h"
44 #include "dcn31_hwseq.h"
45 #include "link_hwss.h"
46 #include "dpcd_defs.h"
47 #include "dce/dmub_outbox.h"
48 #include "link.h"
49 #include "dcn10/dcn10_hw_sequencer.h"
50 #include "inc/link_enc_cfg.h"
51 #include "dcn30/dcn30_vpg.h"
52 #include "dce/dce_i2c_hw.h"
53 
54 #define DC_LOGGER_INIT(logger)
55 
56 #define CTX \
57 	hws->ctx
58 #define REG(reg)\
59 	hws->regs->reg
60 #define DC_LOGGER \
61 		dc->ctx->logger
62 
63 
64 #undef FN
65 #define FN(reg_name, field_name) \
66 	hws->shifts->field_name, hws->masks->field_name
67 
68 static void enable_memory_low_power(struct dc *dc)
69 {
70 	struct dce_hwseq *hws = dc->hwseq;
71 	int i;
72 
73 	if (dc->debug.enable_mem_low_power.bits.dmcu) {
74 		// Force ERAM to shutdown if DMCU is not enabled
75 		if (dc->debug.disable_dmcu || dc->config.disable_dmcu) {
76 			REG_UPDATE(DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, 3);
77 		}
78 	}
79 
80 	// Set default OPTC memory power states
81 	if (dc->debug.enable_mem_low_power.bits.optc) {
82 		// Shutdown when unassigned and light sleep in VBLANK
83 		REG_SET_2(ODM_MEM_PWR_CTRL3, 0, ODM_MEM_UNASSIGNED_PWR_MODE, 3, ODM_MEM_VBLANK_PWR_MODE, 1);
84 	}
85 
86 	if (dc->debug.enable_mem_low_power.bits.vga) {
87 		// Power down VGA memory
88 		REG_UPDATE(MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, 1);
89 	}
90 
91 	if (dc->debug.enable_mem_low_power.bits.mpc &&
92 		dc->res_pool->mpc->funcs->set_mpc_mem_lp_mode)
93 		dc->res_pool->mpc->funcs->set_mpc_mem_lp_mode(dc->res_pool->mpc);
94 
95 
96 	if (dc->debug.enable_mem_low_power.bits.vpg && dc->res_pool->stream_enc[0]->vpg->funcs->vpg_powerdown) {
97 		// Power down VPGs
98 		for (i = 0; i < dc->res_pool->stream_enc_count; i++)
99 			dc->res_pool->stream_enc[i]->vpg->funcs->vpg_powerdown(dc->res_pool->stream_enc[i]->vpg);
100 #if defined(CONFIG_DRM_AMD_DC_FP)
101 		for (i = 0; i < dc->res_pool->hpo_dp_stream_enc_count; i++)
102 			dc->res_pool->hpo_dp_stream_enc[i]->vpg->funcs->vpg_powerdown(dc->res_pool->hpo_dp_stream_enc[i]->vpg);
103 #endif
104 	}
105 
106 }
107 
108 void dcn31_init_hw(struct dc *dc)
109 {
110 	struct abm **abms = dc->res_pool->multiple_abms;
111 	struct dce_hwseq *hws = dc->hwseq;
112 	struct dc_bios *dcb = dc->ctx->dc_bios;
113 	struct resource_pool *res_pool = dc->res_pool;
114 	uint32_t backlight = MAX_BACKLIGHT_LEVEL;
115 	int i;
116 
117 	if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)
118 		dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);
119 
120 	if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
121 
122 		REG_WRITE(REFCLK_CNTL, 0);
123 		REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1);
124 		REG_WRITE(DIO_MEM_PWR_CTRL, 0);
125 
126 		if (!dc->debug.disable_clock_gate) {
127 			/* enable all DCN clock gating */
128 			REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
129 
130 			REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
131 
132 			REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
133 		}
134 
135 		//Enable ability to power gate / don't force power on permanently
136 		if (hws->funcs.enable_power_gating_plane)
137 			hws->funcs.enable_power_gating_plane(hws, true);
138 
139 		return;
140 	}
141 
142 	if (!dcb->funcs->is_accelerated_mode(dcb)) {
143 		hws->funcs.bios_golden_init(dc);
144 		if (hws->funcs.disable_vga)
145 			hws->funcs.disable_vga(dc->hwseq);
146 	}
147 	// Initialize the dccg
148 	if (res_pool->dccg->funcs->dccg_init)
149 		res_pool->dccg->funcs->dccg_init(res_pool->dccg);
150 
151 	enable_memory_low_power(dc);
152 
153 	if (dc->ctx->dc_bios->fw_info_valid) {
154 		res_pool->ref_clocks.xtalin_clock_inKhz =
155 				dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
156 
157 		if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
158 			if (res_pool->dccg && res_pool->hubbub) {
159 
160 				(res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,
161 						dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,
162 						&res_pool->ref_clocks.dccg_ref_clock_inKhz);
163 
164 				(res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub,
165 						res_pool->ref_clocks.dccg_ref_clock_inKhz,
166 						&res_pool->ref_clocks.dchub_ref_clock_inKhz);
167 			} else {
168 				// Not all ASICs have DCCG sw component
169 				res_pool->ref_clocks.dccg_ref_clock_inKhz =
170 						res_pool->ref_clocks.xtalin_clock_inKhz;
171 				res_pool->ref_clocks.dchub_ref_clock_inKhz =
172 						res_pool->ref_clocks.xtalin_clock_inKhz;
173 			}
174 		}
175 	} else
176 		ASSERT_CRITICAL(false);
177 
178 	for (i = 0; i < dc->link_count; i++) {
179 		/* Power up AND update implementation according to the
180 		 * required signal (which may be different from the
181 		 * default signal on connector).
182 		 */
183 		struct dc_link *link = dc->links[i];
184 
185 		if (link->ep_type != DISPLAY_ENDPOINT_PHY)
186 			continue;
187 
188 		link->link_enc->funcs->hw_init(link->link_enc);
189 
190 		/* Check for enabled DIG to identify enabled display */
191 		if (link->link_enc->funcs->is_dig_enabled &&
192 			link->link_enc->funcs->is_dig_enabled(link->link_enc)) {
193 			link->link_status.link_active = true;
194 			if (link->link_enc->funcs->fec_is_active &&
195 					link->link_enc->funcs->fec_is_active(link->link_enc))
196 				link->fec_state = dc_link_fec_enabled;
197 		}
198 	}
199 
200 	/* Enables outbox notifications for usb4 dpia */
201 	if (dc->res_pool->usb4_dpia_count)
202 		dmub_enable_outbox_notification(dc->ctx->dmub_srv);
203 
204 	/* we want to turn off all dp displays before doing detection */
205 	dc->link_srv->blank_all_dp_displays(dc);
206 
207 	if (hws->funcs.enable_power_gating_plane)
208 		hws->funcs.enable_power_gating_plane(dc->hwseq, true);
209 
210 	/* If taking control over from VBIOS, we may want to optimize our first
211 	 * mode set, so we need to skip powering down pipes until we know which
212 	 * pipes we want to use.
213 	 * Otherwise, if taking control is not possible, we need to power
214 	 * everything down.
215 	 */
216 	if (dcb->funcs->is_accelerated_mode(dcb) || !dc->config.seamless_boot_edp_requested) {
217 
218 		// we want to turn off edp displays if odm is enabled and no seamless boot
219 		if (!dc->caps.seamless_odm) {
220 			for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
221 				struct timing_generator *tg = dc->res_pool->timing_generators[i];
222 				uint32_t num_opps, opp_id_src0, opp_id_src1;
223 
224 				num_opps = 1;
225 				if (tg) {
226 					if (tg->funcs->is_tg_enabled(tg) && tg->funcs->get_optc_source) {
227 						tg->funcs->get_optc_source(tg, &num_opps,
228 								&opp_id_src0, &opp_id_src1);
229 					}
230 				}
231 
232 				if (num_opps > 1) {
233 					dc->link_srv->blank_all_edp_displays(dc);
234 					break;
235 				}
236 			}
237 		}
238 
239 		hws->funcs.init_pipes(dc, dc->current_state);
240 		if (dc->res_pool->hubbub->funcs->allow_self_refresh_control)
241 			dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub,
242 					!dc->res_pool->hubbub->ctx->dc->debug.disable_stutter);
243 	}
244 
245 	for (i = 0; i < res_pool->audio_count; i++) {
246 		struct audio *audio = res_pool->audios[i];
247 
248 		audio->funcs->hw_init(audio);
249 	}
250 
251 	for (i = 0; i < dc->link_count; i++) {
252 		struct dc_link *link = dc->links[i];
253 
254 		if (link->panel_cntl)
255 			backlight = link->panel_cntl->funcs->hw_init(link->panel_cntl);
256 	}
257 
258 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
259 		if (abms[i] != NULL)
260 			abms[i]->funcs->abm_init(abms[i], backlight);
261 	}
262 
263 	/* power AFMT HDMI memory TODO: may move to dis/en output save power*/
264 	REG_WRITE(DIO_MEM_PWR_CTRL, 0);
265 
266 	// Set i2c to light sleep until engine is setup
267 	if (dc->debug.enable_mem_low_power.bits.i2c)
268 		REG_UPDATE(DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, 1);
269 
270 	if (hws->funcs.setup_hpo_hw_control)
271 		hws->funcs.setup_hpo_hw_control(hws, false);
272 
273 	if (!dc->debug.disable_clock_gate) {
274 		/* enable all DCN clock gating */
275 		REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
276 
277 		REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
278 
279 		REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
280 	}
281 
282 	if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks)
283 		dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub);
284 
285 	if (dc->clk_mgr->funcs->notify_wm_ranges)
286 		dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr);
287 
288 	if (dc->clk_mgr->funcs->set_hard_max_memclk && !dc->clk_mgr->dc_mode_softmax_enabled)
289 		dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);
290 
291 	if (dc->res_pool->hubbub->funcs->force_pstate_change_control)
292 		dc->res_pool->hubbub->funcs->force_pstate_change_control(
293 				dc->res_pool->hubbub, false, false);
294 #if defined(CONFIG_DRM_AMD_DC_FP)
295 	if (dc->res_pool->hubbub->funcs->init_crb)
296 		dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub);
297 #endif
298 
299 	// Get DMCUB capabilities
300 	dc_dmub_srv_query_caps_cmd(dc->ctx->dmub_srv->dmub);
301 	dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr;
302 }
303 
304 void dcn31_dsc_pg_control(
305 		struct dce_hwseq *hws,
306 		unsigned int dsc_inst,
307 		bool power_on)
308 {
309 	uint32_t power_gate = power_on ? 0 : 1;
310 	uint32_t pwr_status = power_on ? 0 : 2;
311 	uint32_t org_ip_request_cntl = 0;
312 
313 	if (hws->ctx->dc->debug.disable_dsc_power_gate)
314 		return;
315 
316 	if (hws->ctx->dc->debug.root_clock_optimization.bits.dsc &&
317 		hws->ctx->dc->res_pool->dccg->funcs->enable_dsc &&
318 		power_on)
319 		hws->ctx->dc->res_pool->dccg->funcs->enable_dsc(
320 			hws->ctx->dc->res_pool->dccg, dsc_inst);
321 
322 	REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);
323 	if (org_ip_request_cntl == 0)
324 		REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);
325 
326 	switch (dsc_inst) {
327 	case 0: /* DSC0 */
328 		REG_UPDATE(DOMAIN16_PG_CONFIG,
329 				DOMAIN_POWER_GATE, power_gate);
330 
331 		REG_WAIT(DOMAIN16_PG_STATUS,
332 				DOMAIN_PGFSM_PWR_STATUS, pwr_status,
333 				1, 1000);
334 		break;
335 	case 1: /* DSC1 */
336 		REG_UPDATE(DOMAIN17_PG_CONFIG,
337 				DOMAIN_POWER_GATE, power_gate);
338 
339 		REG_WAIT(DOMAIN17_PG_STATUS,
340 				DOMAIN_PGFSM_PWR_STATUS, pwr_status,
341 				1, 1000);
342 		break;
343 	case 2: /* DSC2 */
344 		REG_UPDATE(DOMAIN18_PG_CONFIG,
345 				DOMAIN_POWER_GATE, power_gate);
346 
347 		REG_WAIT(DOMAIN18_PG_STATUS,
348 				DOMAIN_PGFSM_PWR_STATUS, pwr_status,
349 				1, 1000);
350 		break;
351 	default:
352 		BREAK_TO_DEBUGGER();
353 		break;
354 	}
355 
356 	if (org_ip_request_cntl == 0)
357 		REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);
358 
359 	if (hws->ctx->dc->debug.root_clock_optimization.bits.dsc) {
360 		if (hws->ctx->dc->res_pool->dccg->funcs->disable_dsc && !power_on)
361 			hws->ctx->dc->res_pool->dccg->funcs->disable_dsc(
362 				hws->ctx->dc->res_pool->dccg, dsc_inst);
363 	}
364 
365 }
366 
367 
368 void dcn31_enable_power_gating_plane(
369 	struct dce_hwseq *hws,
370 	bool enable)
371 {
372 	bool force_on = true; /* disable power gating */
373 	uint32_t org_ip_request_cntl = 0;
374 
375 	if (enable && !hws->ctx->dc->debug.disable_hubp_power_gate)
376 		force_on = false;
377 
378 	REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);
379 	if (org_ip_request_cntl == 0)
380 		REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);
381 	/* DCHUBP0/1/2/3/4/5 */
382 	REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
383 	REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
384 	/* DPP0/1/2/3/4/5 */
385 	REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
386 	REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
387 
388 	force_on = true; /* disable power gating */
389 	if (enable && !hws->ctx->dc->debug.disable_dsc_power_gate)
390 		force_on = false;
391 
392 	/* DCS0/1/2/3/4/5 */
393 	REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
394 	REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
395 	REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
396 
397 	if (org_ip_request_cntl == 0)
398 		REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);
399 }
400 
401 void dcn31_update_info_frame(struct pipe_ctx *pipe_ctx)
402 {
403 	bool is_hdmi_tmds;
404 	bool is_dp;
405 
406 	ASSERT(pipe_ctx->stream);
407 
408 	if (pipe_ctx->stream_res.stream_enc == NULL)
409 		return;  /* this is not root pipe */
410 
411 	is_hdmi_tmds = dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal);
412 	is_dp = dc_is_dp_signal(pipe_ctx->stream->signal);
413 
414 	if (!is_hdmi_tmds && !is_dp)
415 		return;
416 
417 	if (is_hdmi_tmds)
418 		pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets(
419 			pipe_ctx->stream_res.stream_enc,
420 			&pipe_ctx->stream_res.encoder_info_frame);
421 	else if (pipe_ctx->stream->ctx->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {
422 		pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->update_dp_info_packets(
423 				pipe_ctx->stream_res.hpo_dp_stream_enc,
424 				&pipe_ctx->stream_res.encoder_info_frame);
425 		return;
426 	} else {
427 		if (pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets_sdp_line_num)
428 			pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets_sdp_line_num(
429 				pipe_ctx->stream_res.stream_enc,
430 				&pipe_ctx->stream_res.encoder_info_frame);
431 
432 		pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets(
433 			pipe_ctx->stream_res.stream_enc,
434 			&pipe_ctx->stream_res.encoder_info_frame);
435 	}
436 }
437 void dcn31_z10_save_init(struct dc *dc)
438 {
439 	union dmub_rb_cmd cmd;
440 
441 	memset(&cmd, 0, sizeof(cmd));
442 	cmd.dcn_restore.header.type = DMUB_CMD__IDLE_OPT;
443 	cmd.dcn_restore.header.sub_type = DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT;
444 
445 	dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd);
446 	dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv);
447 	dc_dmub_srv_wait_idle(dc->ctx->dmub_srv);
448 }
449 
450 void dcn31_z10_restore(const struct dc *dc)
451 {
452 	union dmub_rb_cmd cmd;
453 
454 	/*
455 	 * DMUB notifies whether restore is required.
456 	 * Optimization to avoid sending commands when not required.
457 	 */
458 	if (!dc_dmub_srv_is_restore_required(dc->ctx->dmub_srv))
459 		return;
460 
461 	memset(&cmd, 0, sizeof(cmd));
462 	cmd.dcn_restore.header.type = DMUB_CMD__IDLE_OPT;
463 	cmd.dcn_restore.header.sub_type = DMUB_CMD__IDLE_OPT_DCN_RESTORE;
464 
465 	dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd);
466 	dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv);
467 	dc_dmub_srv_wait_idle(dc->ctx->dmub_srv);
468 }
469 
470 void dcn31_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on)
471 {
472 	uint32_t power_gate = power_on ? 0 : 1;
473 	uint32_t pwr_status = power_on ? 0 : 2;
474 	uint32_t org_ip_request_cntl;
475 	if (hws->ctx->dc->debug.disable_hubp_power_gate)
476 		return;
477 
478 	if (REG(DOMAIN0_PG_CONFIG) == 0)
479 		return;
480 	REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);
481 	if (org_ip_request_cntl == 0)
482 		REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);
483 
484 	switch (hubp_inst) {
485 	case 0:
486 		REG_SET(DOMAIN0_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate);
487 		REG_WAIT(DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000);
488 		break;
489 	case 1:
490 		REG_SET(DOMAIN1_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate);
491 		REG_WAIT(DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000);
492 		break;
493 	case 2:
494 		REG_SET(DOMAIN2_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate);
495 		REG_WAIT(DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000);
496 		break;
497 	case 3:
498 		REG_SET(DOMAIN3_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate);
499 		REG_WAIT(DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000);
500 		break;
501 	default:
502 		BREAK_TO_DEBUGGER();
503 		break;
504 	}
505 	if (org_ip_request_cntl == 0)
506 		REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);
507 }
508 
509 int dcn31_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config)
510 {
511 	struct dcn_hubbub_phys_addr_config config;
512 
513 	config.system_aperture.fb_top = pa_config->system_aperture.fb_top;
514 	config.system_aperture.fb_offset = pa_config->system_aperture.fb_offset;
515 	config.system_aperture.fb_base = pa_config->system_aperture.fb_base;
516 	config.system_aperture.agp_top = pa_config->system_aperture.agp_top;
517 	config.system_aperture.agp_bot = pa_config->system_aperture.agp_bot;
518 	config.system_aperture.agp_base = pa_config->system_aperture.agp_base;
519 	config.gart_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr;
520 	config.gart_config.page_table_end_addr = pa_config->gart_config.page_table_end_addr;
521 
522 	if (pa_config->gart_config.base_addr_is_mc_addr) {
523 		/* Convert from MC address to offset into FB */
524 		config.gart_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr -
525 				pa_config->system_aperture.fb_base +
526 				pa_config->system_aperture.fb_offset;
527 	} else
528 		config.gart_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr;
529 
530 	return dc->res_pool->hubbub->funcs->init_dchub_sys_ctx(dc->res_pool->hubbub, &config);
531 }
532 
533 static void dcn31_reset_back_end_for_pipe(
534 		struct dc *dc,
535 		struct pipe_ctx *pipe_ctx,
536 		struct dc_state *context)
537 {
538 	struct dc_link *link;
539 
540 	DC_LOGGER_INIT(dc->ctx->logger);
541 	if (pipe_ctx->stream_res.stream_enc == NULL) {
542 		pipe_ctx->stream = NULL;
543 		return;
544 	}
545 	ASSERT(!pipe_ctx->top_pipe);
546 
547 	dc->hwss.set_abm_immediate_disable(pipe_ctx);
548 
549 	pipe_ctx->stream_res.tg->funcs->set_dsc_config(
550 			pipe_ctx->stream_res.tg,
551 			OPTC_DSC_DISABLED, 0, 0);
552 	pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg);
553 	pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false);
554 	if (pipe_ctx->stream_res.tg->funcs->set_odm_bypass)
555 		pipe_ctx->stream_res.tg->funcs->set_odm_bypass(
556 				pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
557 	pipe_ctx->stream->link->phy_state.symclk_ref_cnts.otg = 0;
558 
559 	if (pipe_ctx->stream_res.tg->funcs->set_drr)
560 		pipe_ctx->stream_res.tg->funcs->set_drr(
561 				pipe_ctx->stream_res.tg, NULL);
562 
563 	if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
564 		link = pipe_ctx->stream->link;
565 		/* DPMS may already disable or */
566 		/* dpms_off status is incorrect due to fastboot
567 		 * feature. When system resume from S4 with second
568 		 * screen only, the dpms_off would be true but
569 		 * VBIOS lit up eDP, so check link status too.
570 		 */
571 		if (!pipe_ctx->stream->dpms_off || link->link_status.link_active)
572 			dc->link_srv->set_dpms_off(pipe_ctx);
573 		else if (pipe_ctx->stream_res.audio)
574 			dc->hwss.disable_audio_stream(pipe_ctx);
575 
576 		/* free acquired resources */
577 		if (pipe_ctx->stream_res.audio) {
578 			/*disable az_endpoint*/
579 			pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio);
580 
581 			/*free audio*/
582 			if (dc->caps.dynamic_audio == true) {
583 				/*we have to dynamic arbitrate the audio endpoints*/
584 				/*we free the resource, need reset is_audio_acquired*/
585 				update_audio_usage(&dc->current_state->res_ctx, dc->res_pool,
586 						pipe_ctx->stream_res.audio, false);
587 				pipe_ctx->stream_res.audio = NULL;
588 			}
589 		}
590 	} else if (pipe_ctx->stream_res.dsc) {
591 		dc->link_srv->set_dsc_enable(pipe_ctx, false);
592 	}
593 
594 	pipe_ctx->stream = NULL;
595 	DC_LOG_DEBUG("Reset back end for pipe %d, tg:%d\n",
596 					pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst);
597 }
598 
599 void dcn31_reset_hw_ctx_wrap(
600 		struct dc *dc,
601 		struct dc_state *context)
602 {
603 	int i;
604 	struct dce_hwseq *hws = dc->hwseq;
605 
606 	/* Reset Back End*/
607 	for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {
608 		struct pipe_ctx *pipe_ctx_old =
609 			&dc->current_state->res_ctx.pipe_ctx[i];
610 		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
611 
612 		if (!pipe_ctx_old->stream)
613 			continue;
614 
615 		if (pipe_ctx_old->top_pipe || pipe_ctx_old->prev_odm_pipe)
616 			continue;
617 
618 		if (!pipe_ctx->stream ||
619 				pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {
620 			struct clock_source *old_clk = pipe_ctx_old->clock_source;
621 
622 			dcn31_reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state);
623 			if (hws->funcs.enable_stream_gating)
624 				hws->funcs.enable_stream_gating(dc, pipe_ctx_old);
625 			if (old_clk)
626 				old_clk->funcs->cs_power_down(old_clk);
627 		}
628 	}
629 
630 	/* New dc_state in the process of being applied to hardware. */
631 	link_enc_cfg_set_transient_mode(dc, dc->current_state, context);
632 }
633 
634 void dcn31_setup_hpo_hw_control(const struct dce_hwseq *hws, bool enable)
635 {
636 	if (hws->ctx->dc->debug.hpo_optimization)
637 		REG_UPDATE(HPO_TOP_HW_CONTROL, HPO_IO_EN, !!enable);
638 }
639