164b1d0e8SNicholas Kazlauskas /* 264b1d0e8SNicholas Kazlauskas * Copyright 2016 Advanced Micro Devices, Inc. 364b1d0e8SNicholas Kazlauskas * 464b1d0e8SNicholas Kazlauskas * Permission is hereby granted, free of charge, to any person obtaining a 564b1d0e8SNicholas Kazlauskas * copy of this software and associated documentation files (the "Software"), 664b1d0e8SNicholas Kazlauskas * to deal in the Software without restriction, including without limitation 764b1d0e8SNicholas Kazlauskas * the rights to use, copy, modify, merge, publish, distribute, sublicense, 864b1d0e8SNicholas Kazlauskas * and/or sell copies of the Software, and to permit persons to whom the 964b1d0e8SNicholas Kazlauskas * Software is furnished to do so, subject to the following conditions: 1064b1d0e8SNicholas Kazlauskas * 1164b1d0e8SNicholas Kazlauskas * The above copyright notice and this permission notice shall be included in 1264b1d0e8SNicholas Kazlauskas * all copies or substantial portions of the Software. 1364b1d0e8SNicholas Kazlauskas * 1464b1d0e8SNicholas Kazlauskas * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1564b1d0e8SNicholas Kazlauskas * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 1664b1d0e8SNicholas Kazlauskas * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 1764b1d0e8SNicholas Kazlauskas * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 1864b1d0e8SNicholas Kazlauskas * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 1964b1d0e8SNicholas Kazlauskas * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 2064b1d0e8SNicholas Kazlauskas * OTHER DEALINGS IN THE SOFTWARE. 2164b1d0e8SNicholas Kazlauskas * 2264b1d0e8SNicholas Kazlauskas * Authors: AMD 2364b1d0e8SNicholas Kazlauskas * 2464b1d0e8SNicholas Kazlauskas */ 2564b1d0e8SNicholas Kazlauskas 2664b1d0e8SNicholas Kazlauskas 2764b1d0e8SNicholas Kazlauskas #include "dm_services.h" 2864b1d0e8SNicholas Kazlauskas #include "dm_helpers.h" 2964b1d0e8SNicholas Kazlauskas #include "core_types.h" 3064b1d0e8SNicholas Kazlauskas #include "resource.h" 3164b1d0e8SNicholas Kazlauskas #include "dccg.h" 3264b1d0e8SNicholas Kazlauskas #include "dce/dce_hwseq.h" 3364b1d0e8SNicholas Kazlauskas #include "clk_mgr.h" 3464b1d0e8SNicholas Kazlauskas #include "reg_helper.h" 3564b1d0e8SNicholas Kazlauskas #include "abm.h" 3664b1d0e8SNicholas Kazlauskas #include "hubp.h" 3764b1d0e8SNicholas Kazlauskas #include "dchubbub.h" 3864b1d0e8SNicholas Kazlauskas #include "timing_generator.h" 3964b1d0e8SNicholas Kazlauskas #include "opp.h" 4064b1d0e8SNicholas Kazlauskas #include "ipp.h" 4164b1d0e8SNicholas Kazlauskas #include "mpc.h" 4264b1d0e8SNicholas Kazlauskas #include "mcif_wb.h" 4364b1d0e8SNicholas Kazlauskas #include "dc_dmub_srv.h" 4464b1d0e8SNicholas Kazlauskas #include "dcn31_hwseq.h" 4564b1d0e8SNicholas Kazlauskas #include "link_hwss.h" 4664b1d0e8SNicholas Kazlauskas #include "dpcd_defs.h" 4764b1d0e8SNicholas Kazlauskas #include "dce/dmub_outbox.h" 4864b1d0e8SNicholas Kazlauskas #include "dc_link_dp.h" 4930adeee5SWesley Chalmers #include "inc/link_dpcd.h" 5032f1d0cfSEric Yang #include "dcn10/dcn10_hw_sequencer.h" 510d4b4253SJimmy Kizito #include "inc/link_enc_cfg.h" 52fd8811e6SMichael Strauss #include "dcn30/dcn30_vpg.h" 535ffb5267SMichael Strauss #include "dce/dce_i2c_hw.h" 5464b1d0e8SNicholas Kazlauskas 5564b1d0e8SNicholas Kazlauskas #define DC_LOGGER_INIT(logger) 5664b1d0e8SNicholas Kazlauskas 5764b1d0e8SNicholas Kazlauskas #define CTX \ 5864b1d0e8SNicholas Kazlauskas hws->ctx 5964b1d0e8SNicholas Kazlauskas #define REG(reg)\ 6064b1d0e8SNicholas Kazlauskas hws->regs->reg 6164b1d0e8SNicholas Kazlauskas #define DC_LOGGER \ 6264b1d0e8SNicholas Kazlauskas dc->ctx->logger 6364b1d0e8SNicholas Kazlauskas 6464b1d0e8SNicholas Kazlauskas 6564b1d0e8SNicholas Kazlauskas #undef FN 6664b1d0e8SNicholas Kazlauskas #define FN(reg_name, field_name) \ 6764b1d0e8SNicholas Kazlauskas hws->shifts->field_name, hws->masks->field_name 6864b1d0e8SNicholas Kazlauskas 699959125aSJake Wang static void enable_memory_low_power(struct dc *dc) 709959125aSJake Wang { 719959125aSJake Wang struct dce_hwseq *hws = dc->hwseq; 729959125aSJake Wang int i; 739959125aSJake Wang 749959125aSJake Wang if (dc->debug.enable_mem_low_power.bits.dmcu) { 759959125aSJake Wang // Force ERAM to shutdown if DMCU is not enabled 769959125aSJake Wang if (dc->debug.disable_dmcu || dc->config.disable_dmcu) { 779959125aSJake Wang REG_UPDATE(DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, 3); 789959125aSJake Wang } 799959125aSJake Wang } 809959125aSJake Wang 819959125aSJake Wang // Set default OPTC memory power states 829959125aSJake Wang if (dc->debug.enable_mem_low_power.bits.optc) { 839959125aSJake Wang // Shutdown when unassigned and light sleep in VBLANK 849959125aSJake Wang REG_SET_2(ODM_MEM_PWR_CTRL3, 0, ODM_MEM_UNASSIGNED_PWR_MODE, 3, ODM_MEM_VBLANK_PWR_MODE, 1); 859959125aSJake Wang } 869959125aSJake Wang 879959125aSJake Wang if (dc->debug.enable_mem_low_power.bits.vga) { 889959125aSJake Wang // Power down VGA memory 899959125aSJake Wang REG_UPDATE(MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, 1); 909959125aSJake Wang } 919959125aSJake Wang 929959125aSJake Wang if (dc->debug.enable_mem_low_power.bits.mpc) 939959125aSJake Wang dc->res_pool->mpc->funcs->set_mpc_mem_lp_mode(dc->res_pool->mpc); 949959125aSJake Wang 959959125aSJake Wang 969959125aSJake Wang if (dc->debug.enable_mem_low_power.bits.vpg && dc->res_pool->stream_enc[0]->vpg->funcs->vpg_powerdown) { 979959125aSJake Wang // Power down VPGs 989959125aSJake Wang for (i = 0; i < dc->res_pool->stream_enc_count; i++) 999959125aSJake Wang dc->res_pool->stream_enc[i]->vpg->funcs->vpg_powerdown(dc->res_pool->stream_enc[i]->vpg); 1009959125aSJake Wang #if defined(CONFIG_DRM_AMD_DC_DCN) 1019959125aSJake Wang for (i = 0; i < dc->res_pool->hpo_dp_stream_enc_count; i++) 1029959125aSJake Wang dc->res_pool->hpo_dp_stream_enc[i]->vpg->funcs->vpg_powerdown(dc->res_pool->hpo_dp_stream_enc[i]->vpg); 1039959125aSJake Wang #endif 1049959125aSJake Wang } 1059959125aSJake Wang 1069959125aSJake Wang } 1079959125aSJake Wang 10864b1d0e8SNicholas Kazlauskas void dcn31_init_hw(struct dc *dc) 10964b1d0e8SNicholas Kazlauskas { 11064b1d0e8SNicholas Kazlauskas struct abm **abms = dc->res_pool->multiple_abms; 11164b1d0e8SNicholas Kazlauskas struct dce_hwseq *hws = dc->hwseq; 11264b1d0e8SNicholas Kazlauskas struct dc_bios *dcb = dc->ctx->dc_bios; 11364b1d0e8SNicholas Kazlauskas struct resource_pool *res_pool = dc->res_pool; 11464b1d0e8SNicholas Kazlauskas uint32_t backlight = MAX_BACKLIGHT_LEVEL; 115ebd1e719SLeo (Hanghong) Ma int i; 11664b1d0e8SNicholas Kazlauskas 11764b1d0e8SNicholas Kazlauskas if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks) 11864b1d0e8SNicholas Kazlauskas dc->clk_mgr->funcs->init_clocks(dc->clk_mgr); 11964b1d0e8SNicholas Kazlauskas 12064b1d0e8SNicholas Kazlauskas if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { 12164b1d0e8SNicholas Kazlauskas 12264b1d0e8SNicholas Kazlauskas REG_WRITE(REFCLK_CNTL, 0); 12364b1d0e8SNicholas Kazlauskas REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1); 12464b1d0e8SNicholas Kazlauskas REG_WRITE(DIO_MEM_PWR_CTRL, 0); 12564b1d0e8SNicholas Kazlauskas 12664b1d0e8SNicholas Kazlauskas if (!dc->debug.disable_clock_gate) { 12764b1d0e8SNicholas Kazlauskas /* enable all DCN clock gating */ 12864b1d0e8SNicholas Kazlauskas REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); 12964b1d0e8SNicholas Kazlauskas 13064b1d0e8SNicholas Kazlauskas REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); 13164b1d0e8SNicholas Kazlauskas 13264b1d0e8SNicholas Kazlauskas REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); 13364b1d0e8SNicholas Kazlauskas } 13464b1d0e8SNicholas Kazlauskas 13564b1d0e8SNicholas Kazlauskas //Enable ability to power gate / don't force power on permanently 13664b1d0e8SNicholas Kazlauskas if (hws->funcs.enable_power_gating_plane) 13764b1d0e8SNicholas Kazlauskas hws->funcs.enable_power_gating_plane(hws, true); 13864b1d0e8SNicholas Kazlauskas 13964b1d0e8SNicholas Kazlauskas return; 14064b1d0e8SNicholas Kazlauskas } 14164b1d0e8SNicholas Kazlauskas 14264b1d0e8SNicholas Kazlauskas if (!dcb->funcs->is_accelerated_mode(dcb)) { 14364b1d0e8SNicholas Kazlauskas hws->funcs.bios_golden_init(dc); 14464b1d0e8SNicholas Kazlauskas hws->funcs.disable_vga(dc->hwseq); 14564b1d0e8SNicholas Kazlauskas } 146f2949a51SJake Wang // Initialize the dccg 147f2949a51SJake Wang if (res_pool->dccg->funcs->dccg_init) 148f2949a51SJake Wang res_pool->dccg->funcs->dccg_init(res_pool->dccg); 14964b1d0e8SNicholas Kazlauskas 1509959125aSJake Wang enable_memory_low_power(dc); 151fd8811e6SMichael Strauss 15264b1d0e8SNicholas Kazlauskas if (dc->ctx->dc_bios->fw_info_valid) { 15364b1d0e8SNicholas Kazlauskas res_pool->ref_clocks.xtalin_clock_inKhz = 15464b1d0e8SNicholas Kazlauskas dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency; 15564b1d0e8SNicholas Kazlauskas 15664b1d0e8SNicholas Kazlauskas if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { 15764b1d0e8SNicholas Kazlauskas if (res_pool->dccg && res_pool->hubbub) { 15864b1d0e8SNicholas Kazlauskas 15964b1d0e8SNicholas Kazlauskas (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg, 16064b1d0e8SNicholas Kazlauskas dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency, 16164b1d0e8SNicholas Kazlauskas &res_pool->ref_clocks.dccg_ref_clock_inKhz); 16264b1d0e8SNicholas Kazlauskas 16364b1d0e8SNicholas Kazlauskas (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub, 16464b1d0e8SNicholas Kazlauskas res_pool->ref_clocks.dccg_ref_clock_inKhz, 16564b1d0e8SNicholas Kazlauskas &res_pool->ref_clocks.dchub_ref_clock_inKhz); 16664b1d0e8SNicholas Kazlauskas } else { 16764b1d0e8SNicholas Kazlauskas // Not all ASICs have DCCG sw component 16864b1d0e8SNicholas Kazlauskas res_pool->ref_clocks.dccg_ref_clock_inKhz = 16964b1d0e8SNicholas Kazlauskas res_pool->ref_clocks.xtalin_clock_inKhz; 17064b1d0e8SNicholas Kazlauskas res_pool->ref_clocks.dchub_ref_clock_inKhz = 17164b1d0e8SNicholas Kazlauskas res_pool->ref_clocks.xtalin_clock_inKhz; 17264b1d0e8SNicholas Kazlauskas } 17364b1d0e8SNicholas Kazlauskas } 17464b1d0e8SNicholas Kazlauskas } else 17564b1d0e8SNicholas Kazlauskas ASSERT_CRITICAL(false); 17664b1d0e8SNicholas Kazlauskas 17764b1d0e8SNicholas Kazlauskas for (i = 0; i < dc->link_count; i++) { 17864b1d0e8SNicholas Kazlauskas /* Power up AND update implementation according to the 17964b1d0e8SNicholas Kazlauskas * required signal (which may be different from the 18064b1d0e8SNicholas Kazlauskas * default signal on connector). 18164b1d0e8SNicholas Kazlauskas */ 18264b1d0e8SNicholas Kazlauskas struct dc_link *link = dc->links[i]; 18364b1d0e8SNicholas Kazlauskas 18464d283cbSJimmy Kizito if (link->ep_type != DISPLAY_ENDPOINT_PHY) 18564d283cbSJimmy Kizito continue; 18664d283cbSJimmy Kizito 18764b1d0e8SNicholas Kazlauskas link->link_enc->funcs->hw_init(link->link_enc); 18864b1d0e8SNicholas Kazlauskas 18964b1d0e8SNicholas Kazlauskas /* Check for enabled DIG to identify enabled display */ 19064b1d0e8SNicholas Kazlauskas if (link->link_enc->funcs->is_dig_enabled && 19164b1d0e8SNicholas Kazlauskas link->link_enc->funcs->is_dig_enabled(link->link_enc)) 19264b1d0e8SNicholas Kazlauskas link->link_status.link_active = true; 19364b1d0e8SNicholas Kazlauskas } 19464b1d0e8SNicholas Kazlauskas 1959fa0fb77SMeenakshikumar Somasundaram /* Enables outbox notifications for usb4 dpia */ 1969fa0fb77SMeenakshikumar Somasundaram if (dc->res_pool->usb4_dpia_count) 197ed720870SMeenakshikumar Somasundaram dmub_enable_outbox_notification(dc->ctx->dmub_srv); 1989fa0fb77SMeenakshikumar Somasundaram 19964b1d0e8SNicholas Kazlauskas /* we want to turn off all dp displays before doing detection */ 200ebd1e719SLeo (Hanghong) Ma dc_link_blank_all_dp_displays(dc); 20164b1d0e8SNicholas Kazlauskas 20264b1d0e8SNicholas Kazlauskas /* If taking control over from VBIOS, we may want to optimize our first 20364b1d0e8SNicholas Kazlauskas * mode set, so we need to skip powering down pipes until we know which 20464b1d0e8SNicholas Kazlauskas * pipes we want to use. 20564b1d0e8SNicholas Kazlauskas * Otherwise, if taking control is not possible, we need to power 20664b1d0e8SNicholas Kazlauskas * everything down. 20764b1d0e8SNicholas Kazlauskas */ 2087aba117aSJarif Aftab if (dcb->funcs->is_accelerated_mode(dcb) || !dc->config.seamless_boot_edp_requested) { 20964b1d0e8SNicholas Kazlauskas hws->funcs.init_pipes(dc, dc->current_state); 21064b1d0e8SNicholas Kazlauskas if (dc->res_pool->hubbub->funcs->allow_self_refresh_control) 21164b1d0e8SNicholas Kazlauskas dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, 21264b1d0e8SNicholas Kazlauskas !dc->res_pool->hubbub->ctx->dc->debug.disable_stutter); 21364b1d0e8SNicholas Kazlauskas } 21464b1d0e8SNicholas Kazlauskas 21564b1d0e8SNicholas Kazlauskas for (i = 0; i < res_pool->audio_count; i++) { 21664b1d0e8SNicholas Kazlauskas struct audio *audio = res_pool->audios[i]; 21764b1d0e8SNicholas Kazlauskas 21864b1d0e8SNicholas Kazlauskas audio->funcs->hw_init(audio); 21964b1d0e8SNicholas Kazlauskas } 22064b1d0e8SNicholas Kazlauskas 22164b1d0e8SNicholas Kazlauskas for (i = 0; i < dc->link_count; i++) { 22264b1d0e8SNicholas Kazlauskas struct dc_link *link = dc->links[i]; 22364b1d0e8SNicholas Kazlauskas 22464b1d0e8SNicholas Kazlauskas if (link->panel_cntl) 22564b1d0e8SNicholas Kazlauskas backlight = link->panel_cntl->funcs->hw_init(link->panel_cntl); 22664b1d0e8SNicholas Kazlauskas } 22764b1d0e8SNicholas Kazlauskas 22864b1d0e8SNicholas Kazlauskas for (i = 0; i < dc->res_pool->pipe_count; i++) { 22964b1d0e8SNicholas Kazlauskas if (abms[i] != NULL) 23064b1d0e8SNicholas Kazlauskas abms[i]->funcs->abm_init(abms[i], backlight); 23164b1d0e8SNicholas Kazlauskas } 23264b1d0e8SNicholas Kazlauskas 23364b1d0e8SNicholas Kazlauskas /* power AFMT HDMI memory TODO: may move to dis/en output save power*/ 23464b1d0e8SNicholas Kazlauskas REG_WRITE(DIO_MEM_PWR_CTRL, 0); 23564b1d0e8SNicholas Kazlauskas 2365ffb5267SMichael Strauss // Set i2c to light sleep until engine is setup 2375ffb5267SMichael Strauss if (dc->debug.enable_mem_low_power.bits.i2c) 2385ffb5267SMichael Strauss REG_UPDATE(DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, 1); 2395ffb5267SMichael Strauss 2400a068b68SJake Wang if (hws->funcs.setup_hpo_hw_control) 2410a068b68SJake Wang hws->funcs.setup_hpo_hw_control(hws, false); 2420a068b68SJake Wang 24364b1d0e8SNicholas Kazlauskas if (!dc->debug.disable_clock_gate) { 24464b1d0e8SNicholas Kazlauskas /* enable all DCN clock gating */ 24564b1d0e8SNicholas Kazlauskas REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); 24664b1d0e8SNicholas Kazlauskas 24764b1d0e8SNicholas Kazlauskas REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); 24864b1d0e8SNicholas Kazlauskas 24964b1d0e8SNicholas Kazlauskas REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); 25064b1d0e8SNicholas Kazlauskas } 25164b1d0e8SNicholas Kazlauskas if (hws->funcs.enable_power_gating_plane) 25264b1d0e8SNicholas Kazlauskas hws->funcs.enable_power_gating_plane(dc->hwseq, true); 25364b1d0e8SNicholas Kazlauskas 25464b1d0e8SNicholas Kazlauskas if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks) 25564b1d0e8SNicholas Kazlauskas dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub); 25664b1d0e8SNicholas Kazlauskas 25764b1d0e8SNicholas Kazlauskas if (dc->clk_mgr->funcs->notify_wm_ranges) 25864b1d0e8SNicholas Kazlauskas dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr); 25964b1d0e8SNicholas Kazlauskas 26064b1d0e8SNicholas Kazlauskas if (dc->clk_mgr->funcs->set_hard_max_memclk) 26164b1d0e8SNicholas Kazlauskas dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr); 26264b1d0e8SNicholas Kazlauskas 26364b1d0e8SNicholas Kazlauskas if (dc->res_pool->hubbub->funcs->force_pstate_change_control) 26464b1d0e8SNicholas Kazlauskas dc->res_pool->hubbub->funcs->force_pstate_change_control( 26564b1d0e8SNicholas Kazlauskas dc->res_pool->hubbub, false, false); 2669fa0fb77SMeenakshikumar Somasundaram #if defined(CONFIG_DRM_AMD_DC_DCN) 26764b1d0e8SNicholas Kazlauskas if (dc->res_pool->hubbub->funcs->init_crb) 26864b1d0e8SNicholas Kazlauskas dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub); 2699fa0fb77SMeenakshikumar Somasundaram #endif 27064b1d0e8SNicholas Kazlauskas } 27164b1d0e8SNicholas Kazlauskas 27264b1d0e8SNicholas Kazlauskas void dcn31_dsc_pg_control( 27364b1d0e8SNicholas Kazlauskas struct dce_hwseq *hws, 27464b1d0e8SNicholas Kazlauskas unsigned int dsc_inst, 27564b1d0e8SNicholas Kazlauskas bool power_on) 27664b1d0e8SNicholas Kazlauskas { 27764b1d0e8SNicholas Kazlauskas uint32_t power_gate = power_on ? 0 : 1; 27864b1d0e8SNicholas Kazlauskas uint32_t pwr_status = power_on ? 0 : 2; 27964b1d0e8SNicholas Kazlauskas uint32_t org_ip_request_cntl = 0; 28064b1d0e8SNicholas Kazlauskas 28164b1d0e8SNicholas Kazlauskas if (hws->ctx->dc->debug.disable_dsc_power_gate) 28264b1d0e8SNicholas Kazlauskas return; 28364b1d0e8SNicholas Kazlauskas 284e22ad7e3SJake Wang if (hws->ctx->dc->debug.root_clock_optimization.bits.dsc && 285e22ad7e3SJake Wang hws->ctx->dc->res_pool->dccg->funcs->enable_dsc && 286e22ad7e3SJake Wang power_on) 287e22ad7e3SJake Wang hws->ctx->dc->res_pool->dccg->funcs->enable_dsc( 288e22ad7e3SJake Wang hws->ctx->dc->res_pool->dccg, dsc_inst); 289e22ad7e3SJake Wang 29064b1d0e8SNicholas Kazlauskas REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); 29164b1d0e8SNicholas Kazlauskas if (org_ip_request_cntl == 0) 29264b1d0e8SNicholas Kazlauskas REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); 29364b1d0e8SNicholas Kazlauskas 29464b1d0e8SNicholas Kazlauskas switch (dsc_inst) { 29564b1d0e8SNicholas Kazlauskas case 0: /* DSC0 */ 29664b1d0e8SNicholas Kazlauskas REG_UPDATE(DOMAIN16_PG_CONFIG, 29764b1d0e8SNicholas Kazlauskas DOMAIN_POWER_GATE, power_gate); 29864b1d0e8SNicholas Kazlauskas 29964b1d0e8SNicholas Kazlauskas REG_WAIT(DOMAIN16_PG_STATUS, 30064b1d0e8SNicholas Kazlauskas DOMAIN_PGFSM_PWR_STATUS, pwr_status, 30164b1d0e8SNicholas Kazlauskas 1, 1000); 30264b1d0e8SNicholas Kazlauskas break; 30364b1d0e8SNicholas Kazlauskas case 1: /* DSC1 */ 30464b1d0e8SNicholas Kazlauskas REG_UPDATE(DOMAIN17_PG_CONFIG, 30564b1d0e8SNicholas Kazlauskas DOMAIN_POWER_GATE, power_gate); 30664b1d0e8SNicholas Kazlauskas 30764b1d0e8SNicholas Kazlauskas REG_WAIT(DOMAIN17_PG_STATUS, 30864b1d0e8SNicholas Kazlauskas DOMAIN_PGFSM_PWR_STATUS, pwr_status, 30964b1d0e8SNicholas Kazlauskas 1, 1000); 31064b1d0e8SNicholas Kazlauskas break; 31164b1d0e8SNicholas Kazlauskas case 2: /* DSC2 */ 31264b1d0e8SNicholas Kazlauskas REG_UPDATE(DOMAIN18_PG_CONFIG, 31364b1d0e8SNicholas Kazlauskas DOMAIN_POWER_GATE, power_gate); 31464b1d0e8SNicholas Kazlauskas 31564b1d0e8SNicholas Kazlauskas REG_WAIT(DOMAIN18_PG_STATUS, 31664b1d0e8SNicholas Kazlauskas DOMAIN_PGFSM_PWR_STATUS, pwr_status, 31764b1d0e8SNicholas Kazlauskas 1, 1000); 31864b1d0e8SNicholas Kazlauskas break; 31964b1d0e8SNicholas Kazlauskas default: 32064b1d0e8SNicholas Kazlauskas BREAK_TO_DEBUGGER(); 32164b1d0e8SNicholas Kazlauskas break; 32264b1d0e8SNicholas Kazlauskas } 32364b1d0e8SNicholas Kazlauskas 32464b1d0e8SNicholas Kazlauskas if (org_ip_request_cntl == 0) 32564b1d0e8SNicholas Kazlauskas REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); 326e22ad7e3SJake Wang 327e22ad7e3SJake Wang if (hws->ctx->dc->debug.root_clock_optimization.bits.dsc) { 328e22ad7e3SJake Wang if (hws->ctx->dc->res_pool->dccg->funcs->disable_dsc && !power_on) 329e22ad7e3SJake Wang hws->ctx->dc->res_pool->dccg->funcs->disable_dsc( 330e22ad7e3SJake Wang hws->ctx->dc->res_pool->dccg, dsc_inst); 331e22ad7e3SJake Wang } 332e22ad7e3SJake Wang 33364b1d0e8SNicholas Kazlauskas } 33464b1d0e8SNicholas Kazlauskas 33564b1d0e8SNicholas Kazlauskas 33664b1d0e8SNicholas Kazlauskas void dcn31_enable_power_gating_plane( 33764b1d0e8SNicholas Kazlauskas struct dce_hwseq *hws, 33864b1d0e8SNicholas Kazlauskas bool enable) 33964b1d0e8SNicholas Kazlauskas { 34064b1d0e8SNicholas Kazlauskas bool force_on = true; /* disable power gating */ 34164b1d0e8SNicholas Kazlauskas 342*8639bd70SCharlene Liu if (enable && !hws->ctx->dc->debug.disable_hubp_power_gate) 34364b1d0e8SNicholas Kazlauskas force_on = false; 34464b1d0e8SNicholas Kazlauskas 34564b1d0e8SNicholas Kazlauskas /* DCHUBP0/1/2/3/4/5 */ 34664b1d0e8SNicholas Kazlauskas REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 347*8639bd70SCharlene Liu REG_WAIT(DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, force_on, 1, 1000); 34864b1d0e8SNicholas Kazlauskas REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 349*8639bd70SCharlene Liu REG_WAIT(DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, force_on, 1, 1000); 35064b1d0e8SNicholas Kazlauskas /* DPP0/1/2/3/4/5 */ 35164b1d0e8SNicholas Kazlauskas REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 352*8639bd70SCharlene Liu REG_WAIT(DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, force_on, 1, 1000); 35364b1d0e8SNicholas Kazlauskas REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 354*8639bd70SCharlene Liu REG_WAIT(DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, force_on, 1, 1000); 355*8639bd70SCharlene Liu 356*8639bd70SCharlene Liu force_on = true; /* disable power gating */ 357*8639bd70SCharlene Liu if (enable && !hws->ctx->dc->debug.disable_dsc_power_gate) 358*8639bd70SCharlene Liu force_on = false; 35964b1d0e8SNicholas Kazlauskas 36064b1d0e8SNicholas Kazlauskas /* DCS0/1/2/3/4/5 */ 36164b1d0e8SNicholas Kazlauskas REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 362*8639bd70SCharlene Liu REG_WAIT(DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, force_on, 1, 1000); 36364b1d0e8SNicholas Kazlauskas REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 364*8639bd70SCharlene Liu REG_WAIT(DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, force_on, 1, 1000); 36564b1d0e8SNicholas Kazlauskas REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 366*8639bd70SCharlene Liu REG_WAIT(DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, force_on, 1, 1000); 36764b1d0e8SNicholas Kazlauskas } 36864b1d0e8SNicholas Kazlauskas 36964b1d0e8SNicholas Kazlauskas void dcn31_update_info_frame(struct pipe_ctx *pipe_ctx) 37064b1d0e8SNicholas Kazlauskas { 37164b1d0e8SNicholas Kazlauskas bool is_hdmi_tmds; 37264b1d0e8SNicholas Kazlauskas bool is_dp; 37364b1d0e8SNicholas Kazlauskas 37464b1d0e8SNicholas Kazlauskas ASSERT(pipe_ctx->stream); 37564b1d0e8SNicholas Kazlauskas 37664b1d0e8SNicholas Kazlauskas if (pipe_ctx->stream_res.stream_enc == NULL) 37764b1d0e8SNicholas Kazlauskas return; /* this is not root pipe */ 37864b1d0e8SNicholas Kazlauskas 37964b1d0e8SNicholas Kazlauskas is_hdmi_tmds = dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal); 38064b1d0e8SNicholas Kazlauskas is_dp = dc_is_dp_signal(pipe_ctx->stream->signal); 38164b1d0e8SNicholas Kazlauskas 382e9cfe00bSNicholas Kazlauskas if (!is_hdmi_tmds && !is_dp) 38364b1d0e8SNicholas Kazlauskas return; 38464b1d0e8SNicholas Kazlauskas 38564b1d0e8SNicholas Kazlauskas if (is_hdmi_tmds) 38664b1d0e8SNicholas Kazlauskas pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets( 38764b1d0e8SNicholas Kazlauskas pipe_ctx->stream_res.stream_enc, 38864b1d0e8SNicholas Kazlauskas &pipe_ctx->stream_res.encoder_info_frame); 38964b1d0e8SNicholas Kazlauskas else { 39064b1d0e8SNicholas Kazlauskas pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets( 39164b1d0e8SNicholas Kazlauskas pipe_ctx->stream_res.stream_enc, 39264b1d0e8SNicholas Kazlauskas &pipe_ctx->stream_res.encoder_info_frame); 39364b1d0e8SNicholas Kazlauskas } 39464b1d0e8SNicholas Kazlauskas } 395f586fea8SJake Wang void dcn31_z10_save_init(struct dc *dc) 396f586fea8SJake Wang { 397f586fea8SJake Wang union dmub_rb_cmd cmd; 398f586fea8SJake Wang 399f586fea8SJake Wang memset(&cmd, 0, sizeof(cmd)); 400f586fea8SJake Wang cmd.dcn_restore.header.type = DMUB_CMD__IDLE_OPT; 401f586fea8SJake Wang cmd.dcn_restore.header.sub_type = DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT; 402f586fea8SJake Wang 403f586fea8SJake Wang dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd); 404f586fea8SJake Wang dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv); 405f586fea8SJake Wang dc_dmub_srv_wait_idle(dc->ctx->dmub_srv); 406f586fea8SJake Wang } 40764b1d0e8SNicholas Kazlauskas 408ac02dc34SEric Yang void dcn31_z10_restore(const struct dc *dc) 40964b1d0e8SNicholas Kazlauskas { 41064b1d0e8SNicholas Kazlauskas union dmub_rb_cmd cmd; 41164b1d0e8SNicholas Kazlauskas 41264b1d0e8SNicholas Kazlauskas /* 41364b1d0e8SNicholas Kazlauskas * DMUB notifies whether restore is required. 41464b1d0e8SNicholas Kazlauskas * Optimization to avoid sending commands when not required. 41564b1d0e8SNicholas Kazlauskas */ 41664b1d0e8SNicholas Kazlauskas if (!dc_dmub_srv_is_restore_required(dc->ctx->dmub_srv)) 41764b1d0e8SNicholas Kazlauskas return; 41864b1d0e8SNicholas Kazlauskas 41964b1d0e8SNicholas Kazlauskas memset(&cmd, 0, sizeof(cmd)); 42064b1d0e8SNicholas Kazlauskas cmd.dcn_restore.header.type = DMUB_CMD__IDLE_OPT; 42164b1d0e8SNicholas Kazlauskas cmd.dcn_restore.header.sub_type = DMUB_CMD__IDLE_OPT_DCN_RESTORE; 42264b1d0e8SNicholas Kazlauskas 42364b1d0e8SNicholas Kazlauskas dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd); 42464b1d0e8SNicholas Kazlauskas dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv); 42564b1d0e8SNicholas Kazlauskas dc_dmub_srv_wait_idle(dc->ctx->dmub_srv); 42664b1d0e8SNicholas Kazlauskas } 42764b1d0e8SNicholas Kazlauskas 42864b1d0e8SNicholas Kazlauskas void dcn31_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on) 42964b1d0e8SNicholas Kazlauskas { 43064b1d0e8SNicholas Kazlauskas uint32_t power_gate = power_on ? 0 : 1; 43164b1d0e8SNicholas Kazlauskas uint32_t pwr_status = power_on ? 0 : 2; 432*8639bd70SCharlene Liu uint32_t org_ip_request_cntl; 43364b1d0e8SNicholas Kazlauskas if (hws->ctx->dc->debug.disable_hubp_power_gate) 43464b1d0e8SNicholas Kazlauskas return; 43564b1d0e8SNicholas Kazlauskas 43664b1d0e8SNicholas Kazlauskas if (REG(DOMAIN0_PG_CONFIG) == 0) 43764b1d0e8SNicholas Kazlauskas return; 438*8639bd70SCharlene Liu REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); 439*8639bd70SCharlene Liu if (org_ip_request_cntl == 0) 440*8639bd70SCharlene Liu REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); 44164b1d0e8SNicholas Kazlauskas 44264b1d0e8SNicholas Kazlauskas switch (hubp_inst) { 44364b1d0e8SNicholas Kazlauskas case 0: 44464b1d0e8SNicholas Kazlauskas REG_SET(DOMAIN0_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 44564b1d0e8SNicholas Kazlauskas REG_WAIT(DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 44664b1d0e8SNicholas Kazlauskas break; 44764b1d0e8SNicholas Kazlauskas case 1: 44864b1d0e8SNicholas Kazlauskas REG_SET(DOMAIN1_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 44964b1d0e8SNicholas Kazlauskas REG_WAIT(DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 45064b1d0e8SNicholas Kazlauskas break; 45164b1d0e8SNicholas Kazlauskas case 2: 45264b1d0e8SNicholas Kazlauskas REG_SET(DOMAIN2_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 45364b1d0e8SNicholas Kazlauskas REG_WAIT(DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 45464b1d0e8SNicholas Kazlauskas break; 45564b1d0e8SNicholas Kazlauskas case 3: 45664b1d0e8SNicholas Kazlauskas REG_SET(DOMAIN3_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 45764b1d0e8SNicholas Kazlauskas REG_WAIT(DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 45864b1d0e8SNicholas Kazlauskas break; 45964b1d0e8SNicholas Kazlauskas default: 46064b1d0e8SNicholas Kazlauskas BREAK_TO_DEBUGGER(); 46164b1d0e8SNicholas Kazlauskas break; 46264b1d0e8SNicholas Kazlauskas } 463*8639bd70SCharlene Liu if (org_ip_request_cntl == 0) 464*8639bd70SCharlene Liu REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); 46564b1d0e8SNicholas Kazlauskas } 46664b1d0e8SNicholas Kazlauskas 46764b1d0e8SNicholas Kazlauskas int dcn31_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config) 46864b1d0e8SNicholas Kazlauskas { 46964b1d0e8SNicholas Kazlauskas struct dcn_hubbub_phys_addr_config config; 47064b1d0e8SNicholas Kazlauskas 47164b1d0e8SNicholas Kazlauskas config.system_aperture.fb_top = pa_config->system_aperture.fb_top; 47264b1d0e8SNicholas Kazlauskas config.system_aperture.fb_offset = pa_config->system_aperture.fb_offset; 47364b1d0e8SNicholas Kazlauskas config.system_aperture.fb_base = pa_config->system_aperture.fb_base; 47464b1d0e8SNicholas Kazlauskas config.system_aperture.agp_top = pa_config->system_aperture.agp_top; 47564b1d0e8SNicholas Kazlauskas config.system_aperture.agp_bot = pa_config->system_aperture.agp_bot; 47664b1d0e8SNicholas Kazlauskas config.system_aperture.agp_base = pa_config->system_aperture.agp_base; 47764b1d0e8SNicholas Kazlauskas config.gart_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr; 47864b1d0e8SNicholas Kazlauskas config.gart_config.page_table_end_addr = pa_config->gart_config.page_table_end_addr; 47964b1d0e8SNicholas Kazlauskas 48064b1d0e8SNicholas Kazlauskas if (pa_config->gart_config.base_addr_is_mc_addr) { 48164b1d0e8SNicholas Kazlauskas /* Convert from MC address to offset into FB */ 48264b1d0e8SNicholas Kazlauskas config.gart_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr - 48364b1d0e8SNicholas Kazlauskas pa_config->system_aperture.fb_base + 48464b1d0e8SNicholas Kazlauskas pa_config->system_aperture.fb_offset; 48564b1d0e8SNicholas Kazlauskas } else 48664b1d0e8SNicholas Kazlauskas config.gart_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr; 48764b1d0e8SNicholas Kazlauskas 48864b1d0e8SNicholas Kazlauskas return dc->res_pool->hubbub->funcs->init_dchub_sys_ctx(dc->res_pool->hubbub, &config); 48964b1d0e8SNicholas Kazlauskas } 49064b1d0e8SNicholas Kazlauskas 49164b1d0e8SNicholas Kazlauskas static void dcn31_reset_back_end_for_pipe( 49264b1d0e8SNicholas Kazlauskas struct dc *dc, 49364b1d0e8SNicholas Kazlauskas struct pipe_ctx *pipe_ctx, 49464b1d0e8SNicholas Kazlauskas struct dc_state *context) 49564b1d0e8SNicholas Kazlauskas { 49664b1d0e8SNicholas Kazlauskas struct dc_link *link; 49764b1d0e8SNicholas Kazlauskas 49864b1d0e8SNicholas Kazlauskas DC_LOGGER_INIT(dc->ctx->logger); 49964b1d0e8SNicholas Kazlauskas if (pipe_ctx->stream_res.stream_enc == NULL) { 50064b1d0e8SNicholas Kazlauskas pipe_ctx->stream = NULL; 50164b1d0e8SNicholas Kazlauskas return; 50264b1d0e8SNicholas Kazlauskas } 50364b1d0e8SNicholas Kazlauskas ASSERT(!pipe_ctx->top_pipe); 50464b1d0e8SNicholas Kazlauskas 50564b1d0e8SNicholas Kazlauskas dc->hwss.set_abm_immediate_disable(pipe_ctx); 50664b1d0e8SNicholas Kazlauskas 50764b1d0e8SNicholas Kazlauskas pipe_ctx->stream_res.tg->funcs->set_dsc_config( 50864b1d0e8SNicholas Kazlauskas pipe_ctx->stream_res.tg, 50964b1d0e8SNicholas Kazlauskas OPTC_DSC_DISABLED, 0, 0); 51064b1d0e8SNicholas Kazlauskas pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg); 51164b1d0e8SNicholas Kazlauskas 51264b1d0e8SNicholas Kazlauskas pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false); 51364b1d0e8SNicholas Kazlauskas if (pipe_ctx->stream_res.tg->funcs->set_odm_bypass) 51464b1d0e8SNicholas Kazlauskas pipe_ctx->stream_res.tg->funcs->set_odm_bypass( 51564b1d0e8SNicholas Kazlauskas pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); 51664b1d0e8SNicholas Kazlauskas 51764b1d0e8SNicholas Kazlauskas if (pipe_ctx->stream_res.tg->funcs->set_drr) 51864b1d0e8SNicholas Kazlauskas pipe_ctx->stream_res.tg->funcs->set_drr( 51964b1d0e8SNicholas Kazlauskas pipe_ctx->stream_res.tg, NULL); 52064b1d0e8SNicholas Kazlauskas 52164b1d0e8SNicholas Kazlauskas if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { 52264b1d0e8SNicholas Kazlauskas link = pipe_ctx->stream->link; 52364b1d0e8SNicholas Kazlauskas /* DPMS may already disable or */ 52464b1d0e8SNicholas Kazlauskas /* dpms_off status is incorrect due to fastboot 52564b1d0e8SNicholas Kazlauskas * feature. When system resume from S4 with second 52664b1d0e8SNicholas Kazlauskas * screen only, the dpms_off would be true but 52764b1d0e8SNicholas Kazlauskas * VBIOS lit up eDP, so check link status too. 52864b1d0e8SNicholas Kazlauskas */ 52964b1d0e8SNicholas Kazlauskas if (!pipe_ctx->stream->dpms_off || link->link_status.link_active) 53064b1d0e8SNicholas Kazlauskas core_link_disable_stream(pipe_ctx); 53164b1d0e8SNicholas Kazlauskas else if (pipe_ctx->stream_res.audio) 53264b1d0e8SNicholas Kazlauskas dc->hwss.disable_audio_stream(pipe_ctx); 53364b1d0e8SNicholas Kazlauskas 53464b1d0e8SNicholas Kazlauskas /* free acquired resources */ 53564b1d0e8SNicholas Kazlauskas if (pipe_ctx->stream_res.audio) { 53664b1d0e8SNicholas Kazlauskas /*disable az_endpoint*/ 53764b1d0e8SNicholas Kazlauskas pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio); 53864b1d0e8SNicholas Kazlauskas 53964b1d0e8SNicholas Kazlauskas /*free audio*/ 54064b1d0e8SNicholas Kazlauskas if (dc->caps.dynamic_audio == true) { 54164b1d0e8SNicholas Kazlauskas /*we have to dynamic arbitrate the audio endpoints*/ 54264b1d0e8SNicholas Kazlauskas /*we free the resource, need reset is_audio_acquired*/ 54364b1d0e8SNicholas Kazlauskas update_audio_usage(&dc->current_state->res_ctx, dc->res_pool, 54464b1d0e8SNicholas Kazlauskas pipe_ctx->stream_res.audio, false); 54564b1d0e8SNicholas Kazlauskas pipe_ctx->stream_res.audio = NULL; 54664b1d0e8SNicholas Kazlauskas } 54764b1d0e8SNicholas Kazlauskas } 54864b1d0e8SNicholas Kazlauskas } else if (pipe_ctx->stream_res.dsc) { 54964b1d0e8SNicholas Kazlauskas dp_set_dsc_enable(pipe_ctx, false); 55064b1d0e8SNicholas Kazlauskas } 55164b1d0e8SNicholas Kazlauskas 55264b1d0e8SNicholas Kazlauskas pipe_ctx->stream = NULL; 55364b1d0e8SNicholas Kazlauskas DC_LOG_DEBUG("Reset back end for pipe %d, tg:%d\n", 55464b1d0e8SNicholas Kazlauskas pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst); 55564b1d0e8SNicholas Kazlauskas } 55664b1d0e8SNicholas Kazlauskas 55764b1d0e8SNicholas Kazlauskas void dcn31_reset_hw_ctx_wrap( 55864b1d0e8SNicholas Kazlauskas struct dc *dc, 55964b1d0e8SNicholas Kazlauskas struct dc_state *context) 56064b1d0e8SNicholas Kazlauskas { 56164b1d0e8SNicholas Kazlauskas int i; 56264b1d0e8SNicholas Kazlauskas struct dce_hwseq *hws = dc->hwseq; 56364b1d0e8SNicholas Kazlauskas 56464b1d0e8SNicholas Kazlauskas /* Reset Back End*/ 56564b1d0e8SNicholas Kazlauskas for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) { 56664b1d0e8SNicholas Kazlauskas struct pipe_ctx *pipe_ctx_old = 56764b1d0e8SNicholas Kazlauskas &dc->current_state->res_ctx.pipe_ctx[i]; 56864b1d0e8SNicholas Kazlauskas struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 56964b1d0e8SNicholas Kazlauskas 57064b1d0e8SNicholas Kazlauskas if (!pipe_ctx_old->stream) 57164b1d0e8SNicholas Kazlauskas continue; 57264b1d0e8SNicholas Kazlauskas 57364b1d0e8SNicholas Kazlauskas if (pipe_ctx_old->top_pipe || pipe_ctx_old->prev_odm_pipe) 57464b1d0e8SNicholas Kazlauskas continue; 57564b1d0e8SNicholas Kazlauskas 57664b1d0e8SNicholas Kazlauskas if (!pipe_ctx->stream || 57764b1d0e8SNicholas Kazlauskas pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) { 57864b1d0e8SNicholas Kazlauskas struct clock_source *old_clk = pipe_ctx_old->clock_source; 57964b1d0e8SNicholas Kazlauskas 58064b1d0e8SNicholas Kazlauskas dcn31_reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state); 58164b1d0e8SNicholas Kazlauskas if (hws->funcs.enable_stream_gating) 582ae6c9601SYi-Ling Chen hws->funcs.enable_stream_gating(dc, pipe_ctx_old); 58364b1d0e8SNicholas Kazlauskas if (old_clk) 58464b1d0e8SNicholas Kazlauskas old_clk->funcs->cs_power_down(old_clk); 58564b1d0e8SNicholas Kazlauskas } 58664b1d0e8SNicholas Kazlauskas } 5870d4b4253SJimmy Kizito 5880d4b4253SJimmy Kizito /* New dc_state in the process of being applied to hardware. */ 5890d4b4253SJimmy Kizito dc->current_state->res_ctx.link_enc_cfg_ctx.mode = LINK_ENC_CFG_TRANSIENT; 59064b1d0e8SNicholas Kazlauskas } 5910a068b68SJake Wang 5920a068b68SJake Wang void dcn31_setup_hpo_hw_control(const struct dce_hwseq *hws, bool enable) 5930a068b68SJake Wang { 5940a068b68SJake Wang if (hws->ctx->dc->debug.hpo_optimization) 5950a068b68SJake Wang REG_UPDATE(HPO_TOP_HW_CONTROL, HPO_IO_EN, !!enable); 5960a068b68SJake Wang } 597