164b1d0e8SNicholas Kazlauskas /* 264b1d0e8SNicholas Kazlauskas * Copyright 2016 Advanced Micro Devices, Inc. 364b1d0e8SNicholas Kazlauskas * 464b1d0e8SNicholas Kazlauskas * Permission is hereby granted, free of charge, to any person obtaining a 564b1d0e8SNicholas Kazlauskas * copy of this software and associated documentation files (the "Software"), 664b1d0e8SNicholas Kazlauskas * to deal in the Software without restriction, including without limitation 764b1d0e8SNicholas Kazlauskas * the rights to use, copy, modify, merge, publish, distribute, sublicense, 864b1d0e8SNicholas Kazlauskas * and/or sell copies of the Software, and to permit persons to whom the 964b1d0e8SNicholas Kazlauskas * Software is furnished to do so, subject to the following conditions: 1064b1d0e8SNicholas Kazlauskas * 1164b1d0e8SNicholas Kazlauskas * The above copyright notice and this permission notice shall be included in 1264b1d0e8SNicholas Kazlauskas * all copies or substantial portions of the Software. 1364b1d0e8SNicholas Kazlauskas * 1464b1d0e8SNicholas Kazlauskas * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1564b1d0e8SNicholas Kazlauskas * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 1664b1d0e8SNicholas Kazlauskas * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 1764b1d0e8SNicholas Kazlauskas * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 1864b1d0e8SNicholas Kazlauskas * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 1964b1d0e8SNicholas Kazlauskas * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 2064b1d0e8SNicholas Kazlauskas * OTHER DEALINGS IN THE SOFTWARE. 2164b1d0e8SNicholas Kazlauskas * 2264b1d0e8SNicholas Kazlauskas * Authors: AMD 2364b1d0e8SNicholas Kazlauskas * 2464b1d0e8SNicholas Kazlauskas */ 2564b1d0e8SNicholas Kazlauskas 2664b1d0e8SNicholas Kazlauskas 2764b1d0e8SNicholas Kazlauskas #include "dm_services.h" 2864b1d0e8SNicholas Kazlauskas #include "dm_helpers.h" 2964b1d0e8SNicholas Kazlauskas #include "core_types.h" 3064b1d0e8SNicholas Kazlauskas #include "resource.h" 3164b1d0e8SNicholas Kazlauskas #include "dccg.h" 3264b1d0e8SNicholas Kazlauskas #include "dce/dce_hwseq.h" 3364b1d0e8SNicholas Kazlauskas #include "clk_mgr.h" 3464b1d0e8SNicholas Kazlauskas #include "reg_helper.h" 3564b1d0e8SNicholas Kazlauskas #include "abm.h" 3664b1d0e8SNicholas Kazlauskas #include "hubp.h" 3764b1d0e8SNicholas Kazlauskas #include "dchubbub.h" 3864b1d0e8SNicholas Kazlauskas #include "timing_generator.h" 3964b1d0e8SNicholas Kazlauskas #include "opp.h" 4064b1d0e8SNicholas Kazlauskas #include "ipp.h" 4164b1d0e8SNicholas Kazlauskas #include "mpc.h" 4264b1d0e8SNicholas Kazlauskas #include "mcif_wb.h" 4364b1d0e8SNicholas Kazlauskas #include "dc_dmub_srv.h" 4464b1d0e8SNicholas Kazlauskas #include "dcn31_hwseq.h" 4564b1d0e8SNicholas Kazlauskas #include "link_hwss.h" 4664b1d0e8SNicholas Kazlauskas #include "dpcd_defs.h" 4764b1d0e8SNicholas Kazlauskas #include "dce/dmub_outbox.h" 4864b1d0e8SNicholas Kazlauskas #include "dc_link_dp.h" 4930adeee5SWesley Chalmers #include "inc/link_dpcd.h" 5032f1d0cfSEric Yang #include "dcn10/dcn10_hw_sequencer.h" 510d4b4253SJimmy Kizito #include "inc/link_enc_cfg.h" 52fd8811e6SMichael Strauss #include "dcn30/dcn30_vpg.h" 535ffb5267SMichael Strauss #include "dce/dce_i2c_hw.h" 5464b1d0e8SNicholas Kazlauskas 5564b1d0e8SNicholas Kazlauskas #define DC_LOGGER_INIT(logger) 5664b1d0e8SNicholas Kazlauskas 5764b1d0e8SNicholas Kazlauskas #define CTX \ 5864b1d0e8SNicholas Kazlauskas hws->ctx 5964b1d0e8SNicholas Kazlauskas #define REG(reg)\ 6064b1d0e8SNicholas Kazlauskas hws->regs->reg 6164b1d0e8SNicholas Kazlauskas #define DC_LOGGER \ 6264b1d0e8SNicholas Kazlauskas dc->ctx->logger 6364b1d0e8SNicholas Kazlauskas 6464b1d0e8SNicholas Kazlauskas 6564b1d0e8SNicholas Kazlauskas #undef FN 6664b1d0e8SNicholas Kazlauskas #define FN(reg_name, field_name) \ 6764b1d0e8SNicholas Kazlauskas hws->shifts->field_name, hws->masks->field_name 6864b1d0e8SNicholas Kazlauskas 6964b1d0e8SNicholas Kazlauskas void dcn31_init_hw(struct dc *dc) 7064b1d0e8SNicholas Kazlauskas { 7164b1d0e8SNicholas Kazlauskas struct abm **abms = dc->res_pool->multiple_abms; 7264b1d0e8SNicholas Kazlauskas struct dce_hwseq *hws = dc->hwseq; 7364b1d0e8SNicholas Kazlauskas struct dc_bios *dcb = dc->ctx->dc_bios; 7464b1d0e8SNicholas Kazlauskas struct resource_pool *res_pool = dc->res_pool; 7564b1d0e8SNicholas Kazlauskas uint32_t backlight = MAX_BACKLIGHT_LEVEL; 76c494e579SAgustin Gutierrez int i, j; 7764b1d0e8SNicholas Kazlauskas 7864b1d0e8SNicholas Kazlauskas if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks) 7964b1d0e8SNicholas Kazlauskas dc->clk_mgr->funcs->init_clocks(dc->clk_mgr); 8064b1d0e8SNicholas Kazlauskas 8164b1d0e8SNicholas Kazlauskas if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { 8264b1d0e8SNicholas Kazlauskas 8364b1d0e8SNicholas Kazlauskas REG_WRITE(REFCLK_CNTL, 0); 8464b1d0e8SNicholas Kazlauskas REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1); 8564b1d0e8SNicholas Kazlauskas REG_WRITE(DIO_MEM_PWR_CTRL, 0); 8664b1d0e8SNicholas Kazlauskas 8764b1d0e8SNicholas Kazlauskas if (!dc->debug.disable_clock_gate) { 8864b1d0e8SNicholas Kazlauskas /* enable all DCN clock gating */ 8964b1d0e8SNicholas Kazlauskas REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); 9064b1d0e8SNicholas Kazlauskas 9164b1d0e8SNicholas Kazlauskas REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); 9264b1d0e8SNicholas Kazlauskas 9364b1d0e8SNicholas Kazlauskas REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); 9464b1d0e8SNicholas Kazlauskas } 9564b1d0e8SNicholas Kazlauskas 9664b1d0e8SNicholas Kazlauskas //Enable ability to power gate / don't force power on permanently 9764b1d0e8SNicholas Kazlauskas if (hws->funcs.enable_power_gating_plane) 9864b1d0e8SNicholas Kazlauskas hws->funcs.enable_power_gating_plane(hws, true); 9964b1d0e8SNicholas Kazlauskas 10064b1d0e8SNicholas Kazlauskas return; 10164b1d0e8SNicholas Kazlauskas } 10264b1d0e8SNicholas Kazlauskas 10364b1d0e8SNicholas Kazlauskas if (!dcb->funcs->is_accelerated_mode(dcb)) { 10464b1d0e8SNicholas Kazlauskas hws->funcs.bios_golden_init(dc); 10564b1d0e8SNicholas Kazlauskas hws->funcs.disable_vga(dc->hwseq); 10664b1d0e8SNicholas Kazlauskas } 107f2949a51SJake Wang // Initialize the dccg 108f2949a51SJake Wang if (res_pool->dccg->funcs->dccg_init) 109f2949a51SJake Wang res_pool->dccg->funcs->dccg_init(res_pool->dccg); 11064b1d0e8SNicholas Kazlauskas 11164b1d0e8SNicholas Kazlauskas if (dc->debug.enable_mem_low_power.bits.dmcu) { 11264b1d0e8SNicholas Kazlauskas // Force ERAM to shutdown if DMCU is not enabled 11364b1d0e8SNicholas Kazlauskas if (dc->debug.disable_dmcu || dc->config.disable_dmcu) { 11464b1d0e8SNicholas Kazlauskas REG_UPDATE(DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, 3); 11564b1d0e8SNicholas Kazlauskas } 11664b1d0e8SNicholas Kazlauskas } 11764b1d0e8SNicholas Kazlauskas 11864b1d0e8SNicholas Kazlauskas // Set default OPTC memory power states 11964b1d0e8SNicholas Kazlauskas if (dc->debug.enable_mem_low_power.bits.optc) { 12064b1d0e8SNicholas Kazlauskas // Shutdown when unassigned and light sleep in VBLANK 12164b1d0e8SNicholas Kazlauskas REG_SET_2(ODM_MEM_PWR_CTRL3, 0, ODM_MEM_UNASSIGNED_PWR_MODE, 3, ODM_MEM_VBLANK_PWR_MODE, 1); 12264b1d0e8SNicholas Kazlauskas } 12364b1d0e8SNicholas Kazlauskas 12464b1d0e8SNicholas Kazlauskas if (dc->debug.enable_mem_low_power.bits.vga) { 12564b1d0e8SNicholas Kazlauskas // Power down VGA memory 12664b1d0e8SNicholas Kazlauskas REG_UPDATE(MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, 1); 12764b1d0e8SNicholas Kazlauskas } 12864b1d0e8SNicholas Kazlauskas 129fd8811e6SMichael Strauss #if defined(CONFIG_DRM_AMD_DC_DCN) 130fd8811e6SMichael Strauss if (dc->debug.enable_mem_low_power.bits.vpg && dc->res_pool->stream_enc[0]->vpg->funcs->vpg_powerdown) { 131fd8811e6SMichael Strauss // Power down VPGs 132fd8811e6SMichael Strauss for (i = 0; i < dc->res_pool->stream_enc_count; i++) 133fd8811e6SMichael Strauss dc->res_pool->stream_enc[i]->vpg->funcs->vpg_powerdown(dc->res_pool->stream_enc[i]->vpg); 134fd8811e6SMichael Strauss #if defined(CONFIG_DRM_AMD_DC_DP2_0) 135fd8811e6SMichael Strauss for (i = 0; i < dc->res_pool->hpo_dp_stream_enc_count; i++) 136fd8811e6SMichael Strauss dc->res_pool->hpo_dp_stream_enc[i]->vpg->funcs->vpg_powerdown(dc->res_pool->hpo_dp_stream_enc[i]->vpg); 137fd8811e6SMichael Strauss #endif 138fd8811e6SMichael Strauss } 139fd8811e6SMichael Strauss #endif 140fd8811e6SMichael Strauss 14164b1d0e8SNicholas Kazlauskas if (dc->ctx->dc_bios->fw_info_valid) { 14264b1d0e8SNicholas Kazlauskas res_pool->ref_clocks.xtalin_clock_inKhz = 14364b1d0e8SNicholas Kazlauskas dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency; 14464b1d0e8SNicholas Kazlauskas 14564b1d0e8SNicholas Kazlauskas if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { 14664b1d0e8SNicholas Kazlauskas if (res_pool->dccg && res_pool->hubbub) { 14764b1d0e8SNicholas Kazlauskas 14864b1d0e8SNicholas Kazlauskas (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg, 14964b1d0e8SNicholas Kazlauskas dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency, 15064b1d0e8SNicholas Kazlauskas &res_pool->ref_clocks.dccg_ref_clock_inKhz); 15164b1d0e8SNicholas Kazlauskas 15264b1d0e8SNicholas Kazlauskas (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub, 15364b1d0e8SNicholas Kazlauskas res_pool->ref_clocks.dccg_ref_clock_inKhz, 15464b1d0e8SNicholas Kazlauskas &res_pool->ref_clocks.dchub_ref_clock_inKhz); 15564b1d0e8SNicholas Kazlauskas } else { 15664b1d0e8SNicholas Kazlauskas // Not all ASICs have DCCG sw component 15764b1d0e8SNicholas Kazlauskas res_pool->ref_clocks.dccg_ref_clock_inKhz = 15864b1d0e8SNicholas Kazlauskas res_pool->ref_clocks.xtalin_clock_inKhz; 15964b1d0e8SNicholas Kazlauskas res_pool->ref_clocks.dchub_ref_clock_inKhz = 16064b1d0e8SNicholas Kazlauskas res_pool->ref_clocks.xtalin_clock_inKhz; 16164b1d0e8SNicholas Kazlauskas } 16264b1d0e8SNicholas Kazlauskas } 16364b1d0e8SNicholas Kazlauskas } else 16464b1d0e8SNicholas Kazlauskas ASSERT_CRITICAL(false); 16564b1d0e8SNicholas Kazlauskas 16664b1d0e8SNicholas Kazlauskas for (i = 0; i < dc->link_count; i++) { 16764b1d0e8SNicholas Kazlauskas /* Power up AND update implementation according to the 16864b1d0e8SNicholas Kazlauskas * required signal (which may be different from the 16964b1d0e8SNicholas Kazlauskas * default signal on connector). 17064b1d0e8SNicholas Kazlauskas */ 17164b1d0e8SNicholas Kazlauskas struct dc_link *link = dc->links[i]; 17264b1d0e8SNicholas Kazlauskas 17364d283cbSJimmy Kizito if (link->ep_type != DISPLAY_ENDPOINT_PHY) 17464d283cbSJimmy Kizito continue; 17564d283cbSJimmy Kizito 17664b1d0e8SNicholas Kazlauskas link->link_enc->funcs->hw_init(link->link_enc); 17764b1d0e8SNicholas Kazlauskas 17864b1d0e8SNicholas Kazlauskas /* Check for enabled DIG to identify enabled display */ 17964b1d0e8SNicholas Kazlauskas if (link->link_enc->funcs->is_dig_enabled && 18064b1d0e8SNicholas Kazlauskas link->link_enc->funcs->is_dig_enabled(link->link_enc)) 18164b1d0e8SNicholas Kazlauskas link->link_status.link_active = true; 18264b1d0e8SNicholas Kazlauskas } 18364b1d0e8SNicholas Kazlauskas 18464b1d0e8SNicholas Kazlauskas /* Power gate DSCs */ 18564b1d0e8SNicholas Kazlauskas for (i = 0; i < res_pool->res_cap->num_dsc; i++) 18664b1d0e8SNicholas Kazlauskas if (hws->funcs.dsc_pg_control != NULL) 18764b1d0e8SNicholas Kazlauskas hws->funcs.dsc_pg_control(hws, res_pool->dscs[i]->inst, false); 18864b1d0e8SNicholas Kazlauskas 1899fa0fb77SMeenakshikumar Somasundaram /* Enables outbox notifications for usb4 dpia */ 1909fa0fb77SMeenakshikumar Somasundaram if (dc->res_pool->usb4_dpia_count) 1919fa0fb77SMeenakshikumar Somasundaram dmub_enable_outbox_notification(dc); 1929fa0fb77SMeenakshikumar Somasundaram 19364b1d0e8SNicholas Kazlauskas /* we want to turn off all dp displays before doing detection */ 194c494e579SAgustin Gutierrez if (dc->config.power_down_display_on_boot) { 195c494e579SAgustin Gutierrez uint8_t dpcd_power_state = '\0'; 196c494e579SAgustin Gutierrez enum dc_status status = DC_ERROR_UNEXPECTED; 19764b1d0e8SNicholas Kazlauskas 198c494e579SAgustin Gutierrez for (i = 0; i < dc->link_count; i++) { 199c494e579SAgustin Gutierrez if (dc->links[i]->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) 200c494e579SAgustin Gutierrez continue; 201c494e579SAgustin Gutierrez 202c494e579SAgustin Gutierrez /* if any of the displays are lit up turn them off */ 203c494e579SAgustin Gutierrez status = core_link_read_dpcd(dc->links[i], DP_SET_POWER, 204c494e579SAgustin Gutierrez &dpcd_power_state, sizeof(dpcd_power_state)); 205c494e579SAgustin Gutierrez if (status == DC_OK && dpcd_power_state == DP_POWER_STATE_D0) { 206c494e579SAgustin Gutierrez /* blank dp stream before power off receiver*/ 207c494e579SAgustin Gutierrez if (dc->links[i]->ep_type == DISPLAY_ENDPOINT_PHY && 208c494e579SAgustin Gutierrez dc->links[i]->link_enc->funcs->get_dig_frontend) { 209c494e579SAgustin Gutierrez unsigned int fe; 210c494e579SAgustin Gutierrez 211c494e579SAgustin Gutierrez fe = dc->links[i]->link_enc->funcs->get_dig_frontend( 212c494e579SAgustin Gutierrez dc->links[i]->link_enc); 213c494e579SAgustin Gutierrez if (fe == ENGINE_ID_UNKNOWN) 214c494e579SAgustin Gutierrez continue; 215c494e579SAgustin Gutierrez 216c494e579SAgustin Gutierrez for (j = 0; j < dc->res_pool->stream_enc_count; j++) { 217c494e579SAgustin Gutierrez if (fe == dc->res_pool->stream_enc[j]->id) { 218c494e579SAgustin Gutierrez dc->res_pool->stream_enc[j]->funcs->dp_blank(dc->links[i], 219c494e579SAgustin Gutierrez dc->res_pool->stream_enc[j]); 220c494e579SAgustin Gutierrez break; 221c494e579SAgustin Gutierrez } 222c494e579SAgustin Gutierrez } 223c494e579SAgustin Gutierrez } 224c494e579SAgustin Gutierrez dp_receiver_power_ctrl(dc->links[i], false); 225c494e579SAgustin Gutierrez } 226c494e579SAgustin Gutierrez } 227c494e579SAgustin Gutierrez } 22864b1d0e8SNicholas Kazlauskas 22964b1d0e8SNicholas Kazlauskas /* If taking control over from VBIOS, we may want to optimize our first 23064b1d0e8SNicholas Kazlauskas * mode set, so we need to skip powering down pipes until we know which 23164b1d0e8SNicholas Kazlauskas * pipes we want to use. 23264b1d0e8SNicholas Kazlauskas * Otherwise, if taking control is not possible, we need to power 23364b1d0e8SNicholas Kazlauskas * everything down. 23464b1d0e8SNicholas Kazlauskas */ 23564b1d0e8SNicholas Kazlauskas if (dcb->funcs->is_accelerated_mode(dcb) || dc->config.power_down_display_on_boot) { 23664b1d0e8SNicholas Kazlauskas hws->funcs.init_pipes(dc, dc->current_state); 23764b1d0e8SNicholas Kazlauskas if (dc->res_pool->hubbub->funcs->allow_self_refresh_control) 23864b1d0e8SNicholas Kazlauskas dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, 23964b1d0e8SNicholas Kazlauskas !dc->res_pool->hubbub->ctx->dc->debug.disable_stutter); 24064b1d0e8SNicholas Kazlauskas } 24164b1d0e8SNicholas Kazlauskas 24264b1d0e8SNicholas Kazlauskas for (i = 0; i < res_pool->audio_count; i++) { 24364b1d0e8SNicholas Kazlauskas struct audio *audio = res_pool->audios[i]; 24464b1d0e8SNicholas Kazlauskas 24564b1d0e8SNicholas Kazlauskas audio->funcs->hw_init(audio); 24664b1d0e8SNicholas Kazlauskas } 24764b1d0e8SNicholas Kazlauskas 24864b1d0e8SNicholas Kazlauskas for (i = 0; i < dc->link_count; i++) { 24964b1d0e8SNicholas Kazlauskas struct dc_link *link = dc->links[i]; 25064b1d0e8SNicholas Kazlauskas 25164b1d0e8SNicholas Kazlauskas if (link->panel_cntl) 25264b1d0e8SNicholas Kazlauskas backlight = link->panel_cntl->funcs->hw_init(link->panel_cntl); 25364b1d0e8SNicholas Kazlauskas } 25464b1d0e8SNicholas Kazlauskas 25564b1d0e8SNicholas Kazlauskas for (i = 0; i < dc->res_pool->pipe_count; i++) { 25664b1d0e8SNicholas Kazlauskas if (abms[i] != NULL) 25764b1d0e8SNicholas Kazlauskas abms[i]->funcs->abm_init(abms[i], backlight); 25864b1d0e8SNicholas Kazlauskas } 25964b1d0e8SNicholas Kazlauskas 26064b1d0e8SNicholas Kazlauskas /* power AFMT HDMI memory TODO: may move to dis/en output save power*/ 26164b1d0e8SNicholas Kazlauskas REG_WRITE(DIO_MEM_PWR_CTRL, 0); 26264b1d0e8SNicholas Kazlauskas 2635ffb5267SMichael Strauss // Set i2c to light sleep until engine is setup 2645ffb5267SMichael Strauss if (dc->debug.enable_mem_low_power.bits.i2c) 2655ffb5267SMichael Strauss REG_UPDATE(DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, 1); 2665ffb5267SMichael Strauss 267*0a068b68SJake Wang if (hws->funcs.setup_hpo_hw_control) 268*0a068b68SJake Wang hws->funcs.setup_hpo_hw_control(hws, false); 269*0a068b68SJake Wang 27064b1d0e8SNicholas Kazlauskas if (!dc->debug.disable_clock_gate) { 27164b1d0e8SNicholas Kazlauskas /* enable all DCN clock gating */ 27264b1d0e8SNicholas Kazlauskas REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); 27364b1d0e8SNicholas Kazlauskas 27464b1d0e8SNicholas Kazlauskas REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); 27564b1d0e8SNicholas Kazlauskas 27664b1d0e8SNicholas Kazlauskas REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); 27764b1d0e8SNicholas Kazlauskas } 27864b1d0e8SNicholas Kazlauskas if (hws->funcs.enable_power_gating_plane) 27964b1d0e8SNicholas Kazlauskas hws->funcs.enable_power_gating_plane(dc->hwseq, true); 28064b1d0e8SNicholas Kazlauskas 28164b1d0e8SNicholas Kazlauskas if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks) 28264b1d0e8SNicholas Kazlauskas dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub); 28364b1d0e8SNicholas Kazlauskas 28464b1d0e8SNicholas Kazlauskas if (dc->clk_mgr->funcs->notify_wm_ranges) 28564b1d0e8SNicholas Kazlauskas dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr); 28664b1d0e8SNicholas Kazlauskas 28764b1d0e8SNicholas Kazlauskas if (dc->clk_mgr->funcs->set_hard_max_memclk) 28864b1d0e8SNicholas Kazlauskas dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr); 28964b1d0e8SNicholas Kazlauskas 29064b1d0e8SNicholas Kazlauskas if (dc->res_pool->hubbub->funcs->force_pstate_change_control) 29164b1d0e8SNicholas Kazlauskas dc->res_pool->hubbub->funcs->force_pstate_change_control( 29264b1d0e8SNicholas Kazlauskas dc->res_pool->hubbub, false, false); 2939fa0fb77SMeenakshikumar Somasundaram #if defined(CONFIG_DRM_AMD_DC_DCN) 29464b1d0e8SNicholas Kazlauskas if (dc->res_pool->hubbub->funcs->init_crb) 29564b1d0e8SNicholas Kazlauskas dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub); 2969fa0fb77SMeenakshikumar Somasundaram #endif 29764b1d0e8SNicholas Kazlauskas } 29864b1d0e8SNicholas Kazlauskas 29964b1d0e8SNicholas Kazlauskas void dcn31_dsc_pg_control( 30064b1d0e8SNicholas Kazlauskas struct dce_hwseq *hws, 30164b1d0e8SNicholas Kazlauskas unsigned int dsc_inst, 30264b1d0e8SNicholas Kazlauskas bool power_on) 30364b1d0e8SNicholas Kazlauskas { 30464b1d0e8SNicholas Kazlauskas uint32_t power_gate = power_on ? 0 : 1; 30564b1d0e8SNicholas Kazlauskas uint32_t pwr_status = power_on ? 0 : 2; 30664b1d0e8SNicholas Kazlauskas uint32_t org_ip_request_cntl = 0; 30764b1d0e8SNicholas Kazlauskas 30864b1d0e8SNicholas Kazlauskas if (hws->ctx->dc->debug.disable_dsc_power_gate) 30964b1d0e8SNicholas Kazlauskas return; 31064b1d0e8SNicholas Kazlauskas 311e22ad7e3SJake Wang if (hws->ctx->dc->debug.root_clock_optimization.bits.dsc && 312e22ad7e3SJake Wang hws->ctx->dc->res_pool->dccg->funcs->enable_dsc && 313e22ad7e3SJake Wang power_on) 314e22ad7e3SJake Wang hws->ctx->dc->res_pool->dccg->funcs->enable_dsc( 315e22ad7e3SJake Wang hws->ctx->dc->res_pool->dccg, dsc_inst); 316e22ad7e3SJake Wang 31764b1d0e8SNicholas Kazlauskas REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); 31864b1d0e8SNicholas Kazlauskas if (org_ip_request_cntl == 0) 31964b1d0e8SNicholas Kazlauskas REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); 32064b1d0e8SNicholas Kazlauskas 32164b1d0e8SNicholas Kazlauskas switch (dsc_inst) { 32264b1d0e8SNicholas Kazlauskas case 0: /* DSC0 */ 32364b1d0e8SNicholas Kazlauskas REG_UPDATE(DOMAIN16_PG_CONFIG, 32464b1d0e8SNicholas Kazlauskas DOMAIN_POWER_GATE, power_gate); 32564b1d0e8SNicholas Kazlauskas 32664b1d0e8SNicholas Kazlauskas REG_WAIT(DOMAIN16_PG_STATUS, 32764b1d0e8SNicholas Kazlauskas DOMAIN_PGFSM_PWR_STATUS, pwr_status, 32864b1d0e8SNicholas Kazlauskas 1, 1000); 32964b1d0e8SNicholas Kazlauskas break; 33064b1d0e8SNicholas Kazlauskas case 1: /* DSC1 */ 33164b1d0e8SNicholas Kazlauskas REG_UPDATE(DOMAIN17_PG_CONFIG, 33264b1d0e8SNicholas Kazlauskas DOMAIN_POWER_GATE, power_gate); 33364b1d0e8SNicholas Kazlauskas 33464b1d0e8SNicholas Kazlauskas REG_WAIT(DOMAIN17_PG_STATUS, 33564b1d0e8SNicholas Kazlauskas DOMAIN_PGFSM_PWR_STATUS, pwr_status, 33664b1d0e8SNicholas Kazlauskas 1, 1000); 33764b1d0e8SNicholas Kazlauskas break; 33864b1d0e8SNicholas Kazlauskas case 2: /* DSC2 */ 33964b1d0e8SNicholas Kazlauskas REG_UPDATE(DOMAIN18_PG_CONFIG, 34064b1d0e8SNicholas Kazlauskas DOMAIN_POWER_GATE, power_gate); 34164b1d0e8SNicholas Kazlauskas 34264b1d0e8SNicholas Kazlauskas REG_WAIT(DOMAIN18_PG_STATUS, 34364b1d0e8SNicholas Kazlauskas DOMAIN_PGFSM_PWR_STATUS, pwr_status, 34464b1d0e8SNicholas Kazlauskas 1, 1000); 34564b1d0e8SNicholas Kazlauskas break; 34664b1d0e8SNicholas Kazlauskas default: 34764b1d0e8SNicholas Kazlauskas BREAK_TO_DEBUGGER(); 34864b1d0e8SNicholas Kazlauskas break; 34964b1d0e8SNicholas Kazlauskas } 35064b1d0e8SNicholas Kazlauskas 35164b1d0e8SNicholas Kazlauskas if (org_ip_request_cntl == 0) 35264b1d0e8SNicholas Kazlauskas REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); 353e22ad7e3SJake Wang 354e22ad7e3SJake Wang if (hws->ctx->dc->debug.root_clock_optimization.bits.dsc) { 355e22ad7e3SJake Wang if (hws->ctx->dc->res_pool->dccg->funcs->disable_dsc && !power_on) 356e22ad7e3SJake Wang hws->ctx->dc->res_pool->dccg->funcs->disable_dsc( 357e22ad7e3SJake Wang hws->ctx->dc->res_pool->dccg, dsc_inst); 358e22ad7e3SJake Wang } 359e22ad7e3SJake Wang 36064b1d0e8SNicholas Kazlauskas } 36164b1d0e8SNicholas Kazlauskas 36264b1d0e8SNicholas Kazlauskas 36364b1d0e8SNicholas Kazlauskas void dcn31_enable_power_gating_plane( 36464b1d0e8SNicholas Kazlauskas struct dce_hwseq *hws, 36564b1d0e8SNicholas Kazlauskas bool enable) 36664b1d0e8SNicholas Kazlauskas { 36764b1d0e8SNicholas Kazlauskas bool force_on = true; /* disable power gating */ 36864b1d0e8SNicholas Kazlauskas 36964b1d0e8SNicholas Kazlauskas if (enable) 37064b1d0e8SNicholas Kazlauskas force_on = false; 37164b1d0e8SNicholas Kazlauskas 37264b1d0e8SNicholas Kazlauskas /* DCHUBP0/1/2/3/4/5 */ 37364b1d0e8SNicholas Kazlauskas REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 37464b1d0e8SNicholas Kazlauskas REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 37564b1d0e8SNicholas Kazlauskas 37664b1d0e8SNicholas Kazlauskas /* DPP0/1/2/3/4/5 */ 37764b1d0e8SNicholas Kazlauskas REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 37864b1d0e8SNicholas Kazlauskas REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 37964b1d0e8SNicholas Kazlauskas 38064b1d0e8SNicholas Kazlauskas /* DCS0/1/2/3/4/5 */ 38164b1d0e8SNicholas Kazlauskas REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 38264b1d0e8SNicholas Kazlauskas REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 38364b1d0e8SNicholas Kazlauskas REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); 38464b1d0e8SNicholas Kazlauskas } 38564b1d0e8SNicholas Kazlauskas 38664b1d0e8SNicholas Kazlauskas void dcn31_update_info_frame(struct pipe_ctx *pipe_ctx) 38764b1d0e8SNicholas Kazlauskas { 38864b1d0e8SNicholas Kazlauskas bool is_hdmi_tmds; 38964b1d0e8SNicholas Kazlauskas bool is_dp; 39064b1d0e8SNicholas Kazlauskas 39164b1d0e8SNicholas Kazlauskas ASSERT(pipe_ctx->stream); 39264b1d0e8SNicholas Kazlauskas 39364b1d0e8SNicholas Kazlauskas if (pipe_ctx->stream_res.stream_enc == NULL) 39464b1d0e8SNicholas Kazlauskas return; /* this is not root pipe */ 39564b1d0e8SNicholas Kazlauskas 39664b1d0e8SNicholas Kazlauskas is_hdmi_tmds = dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal); 39764b1d0e8SNicholas Kazlauskas is_dp = dc_is_dp_signal(pipe_ctx->stream->signal); 39864b1d0e8SNicholas Kazlauskas 399e9cfe00bSNicholas Kazlauskas if (!is_hdmi_tmds && !is_dp) 40064b1d0e8SNicholas Kazlauskas return; 40164b1d0e8SNicholas Kazlauskas 40264b1d0e8SNicholas Kazlauskas if (is_hdmi_tmds) 40364b1d0e8SNicholas Kazlauskas pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets( 40464b1d0e8SNicholas Kazlauskas pipe_ctx->stream_res.stream_enc, 40564b1d0e8SNicholas Kazlauskas &pipe_ctx->stream_res.encoder_info_frame); 40664b1d0e8SNicholas Kazlauskas else { 40764b1d0e8SNicholas Kazlauskas pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets( 40864b1d0e8SNicholas Kazlauskas pipe_ctx->stream_res.stream_enc, 40964b1d0e8SNicholas Kazlauskas &pipe_ctx->stream_res.encoder_info_frame); 41064b1d0e8SNicholas Kazlauskas } 41164b1d0e8SNicholas Kazlauskas } 412f586fea8SJake Wang void dcn31_z10_save_init(struct dc *dc) 413f586fea8SJake Wang { 414f586fea8SJake Wang union dmub_rb_cmd cmd; 415f586fea8SJake Wang 416f586fea8SJake Wang memset(&cmd, 0, sizeof(cmd)); 417f586fea8SJake Wang cmd.dcn_restore.header.type = DMUB_CMD__IDLE_OPT; 418f586fea8SJake Wang cmd.dcn_restore.header.sub_type = DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT; 419f586fea8SJake Wang 420f586fea8SJake Wang dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd); 421f586fea8SJake Wang dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv); 422f586fea8SJake Wang dc_dmub_srv_wait_idle(dc->ctx->dmub_srv); 423f586fea8SJake Wang } 42464b1d0e8SNicholas Kazlauskas 425ac02dc34SEric Yang void dcn31_z10_restore(const struct dc *dc) 42664b1d0e8SNicholas Kazlauskas { 42764b1d0e8SNicholas Kazlauskas union dmub_rb_cmd cmd; 42864b1d0e8SNicholas Kazlauskas 42964b1d0e8SNicholas Kazlauskas /* 43064b1d0e8SNicholas Kazlauskas * DMUB notifies whether restore is required. 43164b1d0e8SNicholas Kazlauskas * Optimization to avoid sending commands when not required. 43264b1d0e8SNicholas Kazlauskas */ 43364b1d0e8SNicholas Kazlauskas if (!dc_dmub_srv_is_restore_required(dc->ctx->dmub_srv)) 43464b1d0e8SNicholas Kazlauskas return; 43564b1d0e8SNicholas Kazlauskas 43664b1d0e8SNicholas Kazlauskas memset(&cmd, 0, sizeof(cmd)); 43764b1d0e8SNicholas Kazlauskas cmd.dcn_restore.header.type = DMUB_CMD__IDLE_OPT; 43864b1d0e8SNicholas Kazlauskas cmd.dcn_restore.header.sub_type = DMUB_CMD__IDLE_OPT_DCN_RESTORE; 43964b1d0e8SNicholas Kazlauskas 44064b1d0e8SNicholas Kazlauskas dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd); 44164b1d0e8SNicholas Kazlauskas dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv); 44264b1d0e8SNicholas Kazlauskas dc_dmub_srv_wait_idle(dc->ctx->dmub_srv); 44364b1d0e8SNicholas Kazlauskas } 44464b1d0e8SNicholas Kazlauskas 44564b1d0e8SNicholas Kazlauskas void dcn31_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on) 44664b1d0e8SNicholas Kazlauskas { 44764b1d0e8SNicholas Kazlauskas uint32_t power_gate = power_on ? 0 : 1; 44864b1d0e8SNicholas Kazlauskas uint32_t pwr_status = power_on ? 0 : 2; 44964b1d0e8SNicholas Kazlauskas 45064b1d0e8SNicholas Kazlauskas if (hws->ctx->dc->debug.disable_hubp_power_gate) 45164b1d0e8SNicholas Kazlauskas return; 45264b1d0e8SNicholas Kazlauskas 45364b1d0e8SNicholas Kazlauskas if (REG(DOMAIN0_PG_CONFIG) == 0) 45464b1d0e8SNicholas Kazlauskas return; 45564b1d0e8SNicholas Kazlauskas 45664b1d0e8SNicholas Kazlauskas switch (hubp_inst) { 45764b1d0e8SNicholas Kazlauskas case 0: 45864b1d0e8SNicholas Kazlauskas REG_SET(DOMAIN0_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 45964b1d0e8SNicholas Kazlauskas REG_WAIT(DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 46064b1d0e8SNicholas Kazlauskas break; 46164b1d0e8SNicholas Kazlauskas case 1: 46264b1d0e8SNicholas Kazlauskas REG_SET(DOMAIN1_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 46364b1d0e8SNicholas Kazlauskas REG_WAIT(DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 46464b1d0e8SNicholas Kazlauskas break; 46564b1d0e8SNicholas Kazlauskas case 2: 46664b1d0e8SNicholas Kazlauskas REG_SET(DOMAIN2_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 46764b1d0e8SNicholas Kazlauskas REG_WAIT(DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 46864b1d0e8SNicholas Kazlauskas break; 46964b1d0e8SNicholas Kazlauskas case 3: 47064b1d0e8SNicholas Kazlauskas REG_SET(DOMAIN3_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); 47164b1d0e8SNicholas Kazlauskas REG_WAIT(DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); 47264b1d0e8SNicholas Kazlauskas break; 47364b1d0e8SNicholas Kazlauskas default: 47464b1d0e8SNicholas Kazlauskas BREAK_TO_DEBUGGER(); 47564b1d0e8SNicholas Kazlauskas break; 47664b1d0e8SNicholas Kazlauskas } 47764b1d0e8SNicholas Kazlauskas } 47864b1d0e8SNicholas Kazlauskas 47964b1d0e8SNicholas Kazlauskas int dcn31_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config) 48064b1d0e8SNicholas Kazlauskas { 48164b1d0e8SNicholas Kazlauskas struct dcn_hubbub_phys_addr_config config; 48264b1d0e8SNicholas Kazlauskas 48364b1d0e8SNicholas Kazlauskas config.system_aperture.fb_top = pa_config->system_aperture.fb_top; 48464b1d0e8SNicholas Kazlauskas config.system_aperture.fb_offset = pa_config->system_aperture.fb_offset; 48564b1d0e8SNicholas Kazlauskas config.system_aperture.fb_base = pa_config->system_aperture.fb_base; 48664b1d0e8SNicholas Kazlauskas config.system_aperture.agp_top = pa_config->system_aperture.agp_top; 48764b1d0e8SNicholas Kazlauskas config.system_aperture.agp_bot = pa_config->system_aperture.agp_bot; 48864b1d0e8SNicholas Kazlauskas config.system_aperture.agp_base = pa_config->system_aperture.agp_base; 48964b1d0e8SNicholas Kazlauskas config.gart_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr; 49064b1d0e8SNicholas Kazlauskas config.gart_config.page_table_end_addr = pa_config->gart_config.page_table_end_addr; 49164b1d0e8SNicholas Kazlauskas 49264b1d0e8SNicholas Kazlauskas if (pa_config->gart_config.base_addr_is_mc_addr) { 49364b1d0e8SNicholas Kazlauskas /* Convert from MC address to offset into FB */ 49464b1d0e8SNicholas Kazlauskas config.gart_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr - 49564b1d0e8SNicholas Kazlauskas pa_config->system_aperture.fb_base + 49664b1d0e8SNicholas Kazlauskas pa_config->system_aperture.fb_offset; 49764b1d0e8SNicholas Kazlauskas } else 49864b1d0e8SNicholas Kazlauskas config.gart_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr; 49964b1d0e8SNicholas Kazlauskas 50064b1d0e8SNicholas Kazlauskas return dc->res_pool->hubbub->funcs->init_dchub_sys_ctx(dc->res_pool->hubbub, &config); 50164b1d0e8SNicholas Kazlauskas } 50264b1d0e8SNicholas Kazlauskas 50364b1d0e8SNicholas Kazlauskas static void dcn31_reset_back_end_for_pipe( 50464b1d0e8SNicholas Kazlauskas struct dc *dc, 50564b1d0e8SNicholas Kazlauskas struct pipe_ctx *pipe_ctx, 50664b1d0e8SNicholas Kazlauskas struct dc_state *context) 50764b1d0e8SNicholas Kazlauskas { 50864b1d0e8SNicholas Kazlauskas struct dc_link *link; 50964b1d0e8SNicholas Kazlauskas 51064b1d0e8SNicholas Kazlauskas DC_LOGGER_INIT(dc->ctx->logger); 51164b1d0e8SNicholas Kazlauskas if (pipe_ctx->stream_res.stream_enc == NULL) { 51264b1d0e8SNicholas Kazlauskas pipe_ctx->stream = NULL; 51364b1d0e8SNicholas Kazlauskas return; 51464b1d0e8SNicholas Kazlauskas } 51564b1d0e8SNicholas Kazlauskas ASSERT(!pipe_ctx->top_pipe); 51664b1d0e8SNicholas Kazlauskas 51764b1d0e8SNicholas Kazlauskas dc->hwss.set_abm_immediate_disable(pipe_ctx); 51864b1d0e8SNicholas Kazlauskas 51964b1d0e8SNicholas Kazlauskas pipe_ctx->stream_res.tg->funcs->set_dsc_config( 52064b1d0e8SNicholas Kazlauskas pipe_ctx->stream_res.tg, 52164b1d0e8SNicholas Kazlauskas OPTC_DSC_DISABLED, 0, 0); 52264b1d0e8SNicholas Kazlauskas pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg); 52364b1d0e8SNicholas Kazlauskas 52464b1d0e8SNicholas Kazlauskas pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false); 52564b1d0e8SNicholas Kazlauskas if (pipe_ctx->stream_res.tg->funcs->set_odm_bypass) 52664b1d0e8SNicholas Kazlauskas pipe_ctx->stream_res.tg->funcs->set_odm_bypass( 52764b1d0e8SNicholas Kazlauskas pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); 52864b1d0e8SNicholas Kazlauskas 52964b1d0e8SNicholas Kazlauskas if (pipe_ctx->stream_res.tg->funcs->set_drr) 53064b1d0e8SNicholas Kazlauskas pipe_ctx->stream_res.tg->funcs->set_drr( 53164b1d0e8SNicholas Kazlauskas pipe_ctx->stream_res.tg, NULL); 53264b1d0e8SNicholas Kazlauskas 53364b1d0e8SNicholas Kazlauskas if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { 53464b1d0e8SNicholas Kazlauskas link = pipe_ctx->stream->link; 53564b1d0e8SNicholas Kazlauskas /* DPMS may already disable or */ 53664b1d0e8SNicholas Kazlauskas /* dpms_off status is incorrect due to fastboot 53764b1d0e8SNicholas Kazlauskas * feature. When system resume from S4 with second 53864b1d0e8SNicholas Kazlauskas * screen only, the dpms_off would be true but 53964b1d0e8SNicholas Kazlauskas * VBIOS lit up eDP, so check link status too. 54064b1d0e8SNicholas Kazlauskas */ 54164b1d0e8SNicholas Kazlauskas if (!pipe_ctx->stream->dpms_off || link->link_status.link_active) 54264b1d0e8SNicholas Kazlauskas core_link_disable_stream(pipe_ctx); 54364b1d0e8SNicholas Kazlauskas else if (pipe_ctx->stream_res.audio) 54464b1d0e8SNicholas Kazlauskas dc->hwss.disable_audio_stream(pipe_ctx); 54564b1d0e8SNicholas Kazlauskas 54664b1d0e8SNicholas Kazlauskas /* free acquired resources */ 54764b1d0e8SNicholas Kazlauskas if (pipe_ctx->stream_res.audio) { 54864b1d0e8SNicholas Kazlauskas /*disable az_endpoint*/ 54964b1d0e8SNicholas Kazlauskas pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio); 55064b1d0e8SNicholas Kazlauskas 55164b1d0e8SNicholas Kazlauskas /*free audio*/ 55264b1d0e8SNicholas Kazlauskas if (dc->caps.dynamic_audio == true) { 55364b1d0e8SNicholas Kazlauskas /*we have to dynamic arbitrate the audio endpoints*/ 55464b1d0e8SNicholas Kazlauskas /*we free the resource, need reset is_audio_acquired*/ 55564b1d0e8SNicholas Kazlauskas update_audio_usage(&dc->current_state->res_ctx, dc->res_pool, 55664b1d0e8SNicholas Kazlauskas pipe_ctx->stream_res.audio, false); 55764b1d0e8SNicholas Kazlauskas pipe_ctx->stream_res.audio = NULL; 55864b1d0e8SNicholas Kazlauskas } 55964b1d0e8SNicholas Kazlauskas } 56064b1d0e8SNicholas Kazlauskas } else if (pipe_ctx->stream_res.dsc) { 56164b1d0e8SNicholas Kazlauskas dp_set_dsc_enable(pipe_ctx, false); 56264b1d0e8SNicholas Kazlauskas } 56364b1d0e8SNicholas Kazlauskas 56464b1d0e8SNicholas Kazlauskas pipe_ctx->stream = NULL; 56564b1d0e8SNicholas Kazlauskas DC_LOG_DEBUG("Reset back end for pipe %d, tg:%d\n", 56664b1d0e8SNicholas Kazlauskas pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst); 56764b1d0e8SNicholas Kazlauskas } 56864b1d0e8SNicholas Kazlauskas 56964b1d0e8SNicholas Kazlauskas void dcn31_reset_hw_ctx_wrap( 57064b1d0e8SNicholas Kazlauskas struct dc *dc, 57164b1d0e8SNicholas Kazlauskas struct dc_state *context) 57264b1d0e8SNicholas Kazlauskas { 57364b1d0e8SNicholas Kazlauskas int i; 57464b1d0e8SNicholas Kazlauskas struct dce_hwseq *hws = dc->hwseq; 57564b1d0e8SNicholas Kazlauskas 57664b1d0e8SNicholas Kazlauskas /* Reset Back End*/ 57764b1d0e8SNicholas Kazlauskas for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) { 57864b1d0e8SNicholas Kazlauskas struct pipe_ctx *pipe_ctx_old = 57964b1d0e8SNicholas Kazlauskas &dc->current_state->res_ctx.pipe_ctx[i]; 58064b1d0e8SNicholas Kazlauskas struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 58164b1d0e8SNicholas Kazlauskas 58264b1d0e8SNicholas Kazlauskas if (!pipe_ctx_old->stream) 58364b1d0e8SNicholas Kazlauskas continue; 58464b1d0e8SNicholas Kazlauskas 58564b1d0e8SNicholas Kazlauskas if (pipe_ctx_old->top_pipe || pipe_ctx_old->prev_odm_pipe) 58664b1d0e8SNicholas Kazlauskas continue; 58764b1d0e8SNicholas Kazlauskas 58864b1d0e8SNicholas Kazlauskas if (!pipe_ctx->stream || 58964b1d0e8SNicholas Kazlauskas pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) { 59064b1d0e8SNicholas Kazlauskas struct clock_source *old_clk = pipe_ctx_old->clock_source; 59164b1d0e8SNicholas Kazlauskas 59264b1d0e8SNicholas Kazlauskas dcn31_reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state); 59364b1d0e8SNicholas Kazlauskas if (hws->funcs.enable_stream_gating) 59464b1d0e8SNicholas Kazlauskas hws->funcs.enable_stream_gating(dc, pipe_ctx); 59564b1d0e8SNicholas Kazlauskas if (old_clk) 59664b1d0e8SNicholas Kazlauskas old_clk->funcs->cs_power_down(old_clk); 59764b1d0e8SNicholas Kazlauskas } 59864b1d0e8SNicholas Kazlauskas } 5990d4b4253SJimmy Kizito 6000d4b4253SJimmy Kizito /* New dc_state in the process of being applied to hardware. */ 6010d4b4253SJimmy Kizito dc->current_state->res_ctx.link_enc_cfg_ctx.mode = LINK_ENC_CFG_TRANSIENT; 60264b1d0e8SNicholas Kazlauskas } 603*0a068b68SJake Wang 604*0a068b68SJake Wang void dcn31_setup_hpo_hw_control(const struct dce_hwseq *hws, bool enable) 605*0a068b68SJake Wang { 606*0a068b68SJake Wang if (hws->ctx->dc->debug.hpo_optimization) 607*0a068b68SJake Wang REG_UPDATE(HPO_TOP_HW_CONTROL, HPO_IO_EN, !!enable); 608*0a068b68SJake Wang } 609