1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 27 #include "reg_helper.h" 28 29 #include "core_types.h" 30 #include "link_encoder.h" 31 #include "dcn31_dio_link_encoder.h" 32 #include "stream_encoder.h" 33 #include "i2caux_interface.h" 34 #include "dc_bios_types.h" 35 36 #include "gpio_service_interface.h" 37 38 #include "link_enc_cfg.h" 39 #include "dc_dmub_srv.h" 40 #include "dal_asic_id.h" 41 42 #define CTX \ 43 enc10->base.ctx 44 #define DC_LOGGER \ 45 enc10->base.ctx->logger 46 47 #define REG(reg)\ 48 (enc10->link_regs->reg) 49 50 #undef FN 51 #define FN(reg_name, field_name) \ 52 enc10->link_shift->field_name, enc10->link_mask->field_name 53 54 #define IND_REG(index) \ 55 (enc10->link_regs->index) 56 57 #define AUX_REG(reg)\ 58 (enc10->aux_regs->reg) 59 60 #define AUX_REG_READ(reg_name) \ 61 dm_read_reg(CTX, AUX_REG(reg_name)) 62 63 #define AUX_REG_WRITE(reg_name, val) \ 64 dm_write_reg(CTX, AUX_REG(reg_name), val) 65 66 #ifndef MIN 67 #define MIN(X, Y) ((X) < (Y) ? (X) : (Y)) 68 #endif 69 70 void dcn31_link_encoder_set_dio_phy_mux( 71 struct link_encoder *enc, 72 enum encoder_type_select sel, 73 uint32_t hpo_inst) 74 { 75 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); 76 77 switch (enc->transmitter) { 78 case TRANSMITTER_UNIPHY_A: 79 if (sel == ENCODER_TYPE_HDMI_FRL) 80 REG_UPDATE(DIO_LINKA_CNTL, 81 HPO_HDMI_ENC_SEL, hpo_inst); 82 else if (sel == ENCODER_TYPE_DP_128B132B) 83 REG_UPDATE(DIO_LINKA_CNTL, 84 HPO_DP_ENC_SEL, hpo_inst); 85 REG_UPDATE(DIO_LINKA_CNTL, 86 ENC_TYPE_SEL, sel); 87 break; 88 case TRANSMITTER_UNIPHY_B: 89 if (sel == ENCODER_TYPE_HDMI_FRL) 90 REG_UPDATE(DIO_LINKB_CNTL, 91 HPO_HDMI_ENC_SEL, hpo_inst); 92 else if (sel == ENCODER_TYPE_DP_128B132B) 93 REG_UPDATE(DIO_LINKB_CNTL, 94 HPO_DP_ENC_SEL, hpo_inst); 95 REG_UPDATE(DIO_LINKB_CNTL, 96 ENC_TYPE_SEL, sel); 97 break; 98 case TRANSMITTER_UNIPHY_C: 99 if (sel == ENCODER_TYPE_HDMI_FRL) 100 REG_UPDATE(DIO_LINKC_CNTL, 101 HPO_HDMI_ENC_SEL, hpo_inst); 102 else if (sel == ENCODER_TYPE_DP_128B132B) 103 REG_UPDATE(DIO_LINKC_CNTL, 104 HPO_DP_ENC_SEL, hpo_inst); 105 REG_UPDATE(DIO_LINKC_CNTL, 106 ENC_TYPE_SEL, sel); 107 break; 108 case TRANSMITTER_UNIPHY_D: 109 if (sel == ENCODER_TYPE_HDMI_FRL) 110 REG_UPDATE(DIO_LINKD_CNTL, 111 HPO_HDMI_ENC_SEL, hpo_inst); 112 else if (sel == ENCODER_TYPE_DP_128B132B) 113 REG_UPDATE(DIO_LINKD_CNTL, 114 HPO_DP_ENC_SEL, hpo_inst); 115 REG_UPDATE(DIO_LINKD_CNTL, 116 ENC_TYPE_SEL, sel); 117 break; 118 case TRANSMITTER_UNIPHY_E: 119 if (sel == ENCODER_TYPE_HDMI_FRL) 120 REG_UPDATE(DIO_LINKE_CNTL, 121 HPO_HDMI_ENC_SEL, hpo_inst); 122 else if (sel == ENCODER_TYPE_DP_128B132B) 123 REG_UPDATE(DIO_LINKE_CNTL, 124 HPO_DP_ENC_SEL, hpo_inst); 125 REG_UPDATE(DIO_LINKE_CNTL, 126 ENC_TYPE_SEL, sel); 127 break; 128 case TRANSMITTER_UNIPHY_F: 129 if (sel == ENCODER_TYPE_HDMI_FRL) 130 REG_UPDATE(DIO_LINKF_CNTL, 131 HPO_HDMI_ENC_SEL, hpo_inst); 132 else if (sel == ENCODER_TYPE_DP_128B132B) 133 REG_UPDATE(DIO_LINKF_CNTL, 134 HPO_DP_ENC_SEL, hpo_inst); 135 REG_UPDATE(DIO_LINKF_CNTL, 136 ENC_TYPE_SEL, sel); 137 break; 138 default: 139 /* Do nothing */ 140 break; 141 } 142 } 143 144 void enc31_hw_init(struct link_encoder *enc) 145 { 146 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); 147 148 /* 149 00 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2 : 1/2 150 01 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4 : 3/4 151 02 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8 : 7/8 152 03 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16 : 15/16 153 04 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32 : 31/32 154 05 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64 : 63/64 155 06 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128 : 127/128 156 07 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256 : 255/256 157 */ 158 159 /* 160 AUX_REG_UPDATE_5(AUX_DPHY_RX_CONTROL0, 161 AUX_RX_START_WINDOW = 1 [6:4] 162 AUX_RX_RECEIVE_WINDOW = 1 default is 2 [10:8] 163 AUX_RX_HALF_SYM_DETECT_LEN = 1 [13:12] default is 1 164 AUX_RX_TRANSITION_FILTER_EN = 1 [16] default is 1 165 AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT [17] is 0 default is 0 166 AUX_RX_ALLOW_BELOW_THRESHOLD_START [18] is 1 default is 1 167 AUX_RX_ALLOW_BELOW_THRESHOLD_STOP [19] is 1 default is 1 168 AUX_RX_PHASE_DETECT_LEN, [21,20] = 0x3 default is 3 169 AUX_RX_DETECTION_THRESHOLD [30:28] = 1 170 */ 171 AUX_REG_WRITE(AUX_DPHY_RX_CONTROL0, 0x103d1110); 172 173 AUX_REG_WRITE(AUX_DPHY_TX_CONTROL, 0x21c7a); 174 175 //AUX_DPHY_TX_REF_CONTROL'AUX_TX_REF_DIV HW default is 0x32; 176 // Set AUX_TX_REF_DIV Divider to generate 2 MHz reference from refclk 177 // 27MHz -> 0xd 178 // 100MHz -> 0x32 179 // 48MHz -> 0x18 180 181 #ifdef CLEANUP_FIXME 182 /*from display_init*/ 183 REG_WRITE(RDPCSTX_DEBUG_CONFIG, 0); 184 #endif 185 186 // Set TMDS_CTL0 to 1. This is a legacy setting. 187 REG_UPDATE(TMDS_CTL_BITS, TMDS_CTL0, 1); 188 189 /*HW default is 5*/ 190 REG_UPDATE(RDPCSTX_CNTL, 191 RDPCS_TX_FIFO_RD_START_DELAY, 4); 192 193 dcn10_aux_initialize(enc10); 194 } 195 196 static const struct link_encoder_funcs dcn31_link_enc_funcs = { 197 .read_state = link_enc2_read_state, 198 .validate_output_with_stream = 199 dcn30_link_encoder_validate_output_with_stream, 200 .hw_init = enc31_hw_init, 201 .setup = dcn10_link_encoder_setup, 202 .enable_tmds_output = dcn10_link_encoder_enable_tmds_output, 203 .enable_dp_output = dcn31_link_encoder_enable_dp_output, 204 .enable_dp_mst_output = dcn31_link_encoder_enable_dp_mst_output, 205 .disable_output = dcn31_link_encoder_disable_output, 206 .dp_set_lane_settings = dcn10_link_encoder_dp_set_lane_settings, 207 .dp_set_phy_pattern = dcn10_link_encoder_dp_set_phy_pattern, 208 .update_mst_stream_allocation_table = 209 dcn10_link_encoder_update_mst_stream_allocation_table, 210 .psr_program_dp_dphy_fast_training = 211 dcn10_psr_program_dp_dphy_fast_training, 212 .psr_program_secondary_packet = dcn10_psr_program_secondary_packet, 213 .connect_dig_be_to_fe = dcn10_link_encoder_connect_dig_be_to_fe, 214 .enable_hpd = dcn10_link_encoder_enable_hpd, 215 .disable_hpd = dcn10_link_encoder_disable_hpd, 216 .is_dig_enabled = dcn10_is_dig_enabled, 217 .destroy = dcn10_link_encoder_destroy, 218 .fec_set_enable = enc2_fec_set_enable, 219 .fec_set_ready = enc2_fec_set_ready, 220 .fec_is_active = enc2_fec_is_active, 221 .get_dig_frontend = dcn10_get_dig_frontend, 222 .get_dig_mode = dcn10_get_dig_mode, 223 .is_in_alt_mode = dcn31_link_encoder_is_in_alt_mode, 224 .get_max_link_cap = dcn31_link_encoder_get_max_link_cap, 225 .set_dio_phy_mux = dcn31_link_encoder_set_dio_phy_mux, 226 }; 227 228 void dcn31_link_encoder_construct( 229 struct dcn20_link_encoder *enc20, 230 const struct encoder_init_data *init_data, 231 const struct encoder_feature_support *enc_features, 232 const struct dcn10_link_enc_registers *link_regs, 233 const struct dcn10_link_enc_aux_registers *aux_regs, 234 const struct dcn10_link_enc_hpd_registers *hpd_regs, 235 const struct dcn10_link_enc_shift *link_shift, 236 const struct dcn10_link_enc_mask *link_mask) 237 { 238 struct bp_encoder_cap_info bp_cap_info = {0}; 239 const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs; 240 enum bp_result result = BP_RESULT_OK; 241 struct dcn10_link_encoder *enc10 = &enc20->enc10; 242 243 enc10->base.funcs = &dcn31_link_enc_funcs; 244 enc10->base.ctx = init_data->ctx; 245 enc10->base.id = init_data->encoder; 246 247 enc10->base.hpd_source = init_data->hpd_source; 248 enc10->base.connector = init_data->connector; 249 250 enc10->base.preferred_engine = ENGINE_ID_UNKNOWN; 251 252 enc10->base.features = *enc_features; 253 254 enc10->base.transmitter = init_data->transmitter; 255 256 /* set the flag to indicate whether driver poll the I2C data pin 257 * while doing the DP sink detect 258 */ 259 260 /* if (dal_adapter_service_is_feature_supported(as, 261 FEATURE_DP_SINK_DETECT_POLL_DATA_PIN)) 262 enc10->base.features.flags.bits. 263 DP_SINK_DETECT_POLL_DATA_PIN = true;*/ 264 265 enc10->base.output_signals = 266 SIGNAL_TYPE_DVI_SINGLE_LINK | 267 SIGNAL_TYPE_DVI_DUAL_LINK | 268 SIGNAL_TYPE_LVDS | 269 SIGNAL_TYPE_DISPLAY_PORT | 270 SIGNAL_TYPE_DISPLAY_PORT_MST | 271 SIGNAL_TYPE_EDP | 272 SIGNAL_TYPE_HDMI_TYPE_A; 273 274 /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE. 275 * SW always assign DIG_FE 1:1 mapped to DIG_FE for non-MST UNIPHY. 276 * SW assign DIG_FE to non-MST UNIPHY first and MST last. So prefer 277 * DIG is per UNIPHY and used by SST DP, eDP, HDMI, DVI and LVDS. 278 * Prefer DIG assignment is decided by board design. 279 * For DCE 8.0, there are only max 6 UNIPHYs, we assume board design 280 * and VBIOS will filter out 7 UNIPHY for DCE 8.0. 281 * By this, adding DIGG should not hurt DCE 8.0. 282 * This will let DCE 8.1 share DCE 8.0 as much as possible 283 */ 284 285 enc10->link_regs = link_regs; 286 enc10->aux_regs = aux_regs; 287 enc10->hpd_regs = hpd_regs; 288 enc10->link_shift = link_shift; 289 enc10->link_mask = link_mask; 290 291 switch (enc10->base.transmitter) { 292 case TRANSMITTER_UNIPHY_A: 293 enc10->base.preferred_engine = ENGINE_ID_DIGA; 294 break; 295 case TRANSMITTER_UNIPHY_B: 296 enc10->base.preferred_engine = ENGINE_ID_DIGB; 297 break; 298 case TRANSMITTER_UNIPHY_C: 299 enc10->base.preferred_engine = ENGINE_ID_DIGC; 300 break; 301 case TRANSMITTER_UNIPHY_D: 302 enc10->base.preferred_engine = ENGINE_ID_DIGD; 303 break; 304 case TRANSMITTER_UNIPHY_E: 305 enc10->base.preferred_engine = ENGINE_ID_DIGE; 306 break; 307 case TRANSMITTER_UNIPHY_F: 308 enc10->base.preferred_engine = ENGINE_ID_DIGF; 309 break; 310 default: 311 ASSERT_CRITICAL(false); 312 enc10->base.preferred_engine = ENGINE_ID_UNKNOWN; 313 } 314 315 /* default to one to mirror Windows behavior */ 316 enc10->base.features.flags.bits.HDMI_6GB_EN = 1; 317 318 result = bp_funcs->get_encoder_cap_info(enc10->base.ctx->dc_bios, 319 enc10->base.id, &bp_cap_info); 320 321 /* Override features with DCE-specific values */ 322 if (result == BP_RESULT_OK) { 323 enc10->base.features.flags.bits.IS_HBR2_CAPABLE = 324 bp_cap_info.DP_HBR2_EN; 325 enc10->base.features.flags.bits.IS_HBR3_CAPABLE = 326 bp_cap_info.DP_HBR3_EN; 327 enc10->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN; 328 enc10->base.features.flags.bits.IS_DP2_CAPABLE = bp_cap_info.IS_DP2_CAPABLE; 329 enc10->base.features.flags.bits.IS_UHBR10_CAPABLE = bp_cap_info.DP_UHBR10_EN; 330 enc10->base.features.flags.bits.IS_UHBR13_5_CAPABLE = bp_cap_info.DP_UHBR13_5_EN; 331 enc10->base.features.flags.bits.IS_UHBR20_CAPABLE = bp_cap_info.DP_UHBR20_EN; 332 enc10->base.features.flags.bits.DP_IS_USB_C = 333 bp_cap_info.DP_IS_USB_C; 334 } else { 335 DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n", 336 __func__, 337 result); 338 } 339 if (enc10->base.ctx->dc->debug.hdmi20_disable) { 340 enc10->base.features.flags.bits.HDMI_6GB_EN = 0; 341 } 342 } 343 344 void dcn31_link_encoder_construct_minimal( 345 struct dcn20_link_encoder *enc20, 346 struct dc_context *ctx, 347 const struct encoder_feature_support *enc_features, 348 const struct dcn10_link_enc_registers *link_regs, 349 enum engine_id eng_id) 350 { 351 struct dcn10_link_encoder *enc10 = &enc20->enc10; 352 353 enc10->base.funcs = &dcn31_link_enc_funcs; 354 enc10->base.ctx = ctx; 355 enc10->base.id.type = OBJECT_TYPE_ENCODER; 356 enc10->base.hpd_source = HPD_SOURCEID_UNKNOWN; 357 enc10->base.connector.type = OBJECT_TYPE_CONNECTOR; 358 enc10->base.preferred_engine = eng_id; 359 enc10->base.features = *enc_features; 360 enc10->base.transmitter = TRANSMITTER_UNKNOWN; 361 enc10->link_regs = link_regs; 362 363 enc10->base.output_signals = 364 SIGNAL_TYPE_DISPLAY_PORT | 365 SIGNAL_TYPE_DISPLAY_PORT_MST | 366 SIGNAL_TYPE_EDP; 367 } 368 369 /* DPIA equivalent of link_transmitter_control. */ 370 static bool link_dpia_control(struct dc_context *dc_ctx, 371 struct dmub_cmd_dig_dpia_control_data *dpia_control) 372 { 373 union dmub_rb_cmd cmd; 374 struct dc_dmub_srv *dmub = dc_ctx->dmub_srv; 375 376 memset(&cmd, 0, sizeof(cmd)); 377 378 cmd.dig1_dpia_control.header.type = DMUB_CMD__DPIA; 379 cmd.dig1_dpia_control.header.sub_type = 380 DMUB_CMD__DPIA_DIG1_DPIA_CONTROL; 381 cmd.dig1_dpia_control.header.payload_bytes = 382 sizeof(cmd.dig1_dpia_control) - 383 sizeof(cmd.dig1_dpia_control.header); 384 385 cmd.dig1_dpia_control.dpia_control = *dpia_control; 386 387 dc_dmub_srv_cmd_queue(dmub, &cmd); 388 dc_dmub_srv_cmd_execute(dmub); 389 dc_dmub_srv_wait_idle(dmub); 390 391 return true; 392 } 393 394 static void link_encoder_disable(struct dcn10_link_encoder *enc10) 395 { 396 /* reset training complete */ 397 REG_UPDATE(DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, 0); 398 } 399 400 void dcn31_link_encoder_enable_dp_output( 401 struct link_encoder *enc, 402 const struct dc_link_settings *link_settings, 403 enum clock_source_id clock_source) 404 { 405 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); 406 407 /* Enable transmitter and encoder. */ 408 if (!link_enc_cfg_is_transmitter_mappable(enc->ctx->dc, enc)) { 409 410 dcn20_link_encoder_enable_dp_output(enc, link_settings, clock_source); 411 412 } else { 413 414 struct dmub_cmd_dig_dpia_control_data dpia_control = { 0 }; 415 struct dc_link *link; 416 417 link = link_enc_cfg_get_link_using_link_enc(enc->ctx->dc, enc->preferred_engine); 418 419 enc1_configure_encoder(enc10, link_settings); 420 421 dpia_control.action = (uint8_t)TRANSMITTER_CONTROL_ENABLE; 422 dpia_control.enc_id = enc->preferred_engine; 423 dpia_control.mode_laneset.digmode = 0; /* 0 for SST; 5 for MST */ 424 dpia_control.lanenum = (uint8_t)link_settings->lane_count; 425 dpia_control.symclk_10khz = link_settings->link_rate * 426 LINK_RATE_REF_FREQ_IN_KHZ / 10; 427 /* DIG_BE_CNTL.DIG_HPD_SELECT set to 5 (hpdsel - 1) to indicate HPD pin 428 * unused by DPIA. 429 */ 430 dpia_control.hpdsel = 6; 431 432 if (link) { 433 dpia_control.dpia_id = link->ddc_hw_inst; 434 dpia_control.fec_rdy = dc_link_should_enable_fec(link); 435 } else { 436 DC_LOG_ERROR("%s: Failed to execute DPIA enable DMUB command.\n", __func__); 437 BREAK_TO_DEBUGGER(); 438 return; 439 } 440 441 link_dpia_control(enc->ctx, &dpia_control); 442 } 443 } 444 445 void dcn31_link_encoder_enable_dp_mst_output( 446 struct link_encoder *enc, 447 const struct dc_link_settings *link_settings, 448 enum clock_source_id clock_source) 449 { 450 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); 451 452 /* Enable transmitter and encoder. */ 453 if (!link_enc_cfg_is_transmitter_mappable(enc->ctx->dc, enc)) { 454 455 dcn10_link_encoder_enable_dp_mst_output(enc, link_settings, clock_source); 456 457 } else { 458 459 struct dmub_cmd_dig_dpia_control_data dpia_control = { 0 }; 460 struct dc_link *link; 461 462 link = link_enc_cfg_get_link_using_link_enc(enc->ctx->dc, enc->preferred_engine); 463 464 enc1_configure_encoder(enc10, link_settings); 465 466 dpia_control.action = (uint8_t)TRANSMITTER_CONTROL_ENABLE; 467 dpia_control.enc_id = enc->preferred_engine; 468 dpia_control.mode_laneset.digmode = 5; /* 0 for SST; 5 for MST */ 469 dpia_control.lanenum = (uint8_t)link_settings->lane_count; 470 dpia_control.symclk_10khz = link_settings->link_rate * 471 LINK_RATE_REF_FREQ_IN_KHZ / 10; 472 /* DIG_BE_CNTL.DIG_HPD_SELECT set to 5 (hpdsel - 1) to indicate HPD pin 473 * unused by DPIA. 474 */ 475 dpia_control.hpdsel = 6; 476 477 if (link) { 478 dpia_control.dpia_id = link->ddc_hw_inst; 479 dpia_control.fec_rdy = dc_link_should_enable_fec(link); 480 } else { 481 DC_LOG_ERROR("%s: Failed to execute DPIA enable DMUB command.\n", __func__); 482 BREAK_TO_DEBUGGER(); 483 return; 484 } 485 486 link_dpia_control(enc->ctx, &dpia_control); 487 } 488 } 489 490 void dcn31_link_encoder_disable_output( 491 struct link_encoder *enc, 492 enum signal_type signal) 493 { 494 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); 495 496 /* Disable transmitter and encoder. */ 497 if (!link_enc_cfg_is_transmitter_mappable(enc->ctx->dc, enc)) { 498 499 dcn10_link_encoder_disable_output(enc, signal); 500 501 } else { 502 503 struct dmub_cmd_dig_dpia_control_data dpia_control = { 0 }; 504 struct dc_link *link; 505 506 if (!dcn10_is_dig_enabled(enc)) 507 return; 508 509 link = link_enc_cfg_get_link_using_link_enc(enc->ctx->dc, enc->preferred_engine); 510 511 dpia_control.action = (uint8_t)TRANSMITTER_CONTROL_DISABLE; 512 dpia_control.enc_id = enc->preferred_engine; 513 if (signal == SIGNAL_TYPE_DISPLAY_PORT) { 514 dpia_control.mode_laneset.digmode = 0; /* 0 for SST; 5 for MST */ 515 } else if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 516 dpia_control.mode_laneset.digmode = 5; /* 0 for SST; 5 for MST */ 517 } else { 518 DC_LOG_ERROR("%s: USB4 DPIA only supports DisplayPort.\n", __func__); 519 BREAK_TO_DEBUGGER(); 520 } 521 522 if (link) { 523 dpia_control.dpia_id = link->ddc_hw_inst; 524 } else { 525 DC_LOG_ERROR("%s: Failed to execute DPIA enable DMUB command.\n", __func__); 526 BREAK_TO_DEBUGGER(); 527 return; 528 } 529 530 link_dpia_control(enc->ctx, &dpia_control); 531 532 link_encoder_disable(enc10); 533 } 534 } 535 536 bool dcn31_link_encoder_is_in_alt_mode(struct link_encoder *enc) 537 { 538 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); 539 uint32_t dp_alt_mode_disable; 540 bool is_usb_c_alt_mode = false; 541 542 if (enc->features.flags.bits.DP_IS_USB_C) { 543 if (enc->ctx->asic_id.hw_internal_rev != YELLOW_CARP_B0) { 544 // [Note] no need to check hw_internal_rev once phy mux selection is ready 545 REG_GET(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE, &dp_alt_mode_disable); 546 } else { 547 /* 548 * B0 phys use a new set of registers to check whether alt mode is disabled. 549 * if value == 1 alt mode is disabled, otherwise it is enabled. 550 */ 551 if ((enc10->base.transmitter == TRANSMITTER_UNIPHY_A) 552 || (enc10->base.transmitter == TRANSMITTER_UNIPHY_B) 553 || (enc10->base.transmitter == TRANSMITTER_UNIPHY_E)) { 554 REG_GET(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE, &dp_alt_mode_disable); 555 } else { 556 // [Note] need to change TRANSMITTER_UNIPHY_C/D to F/G once phy mux selection is ready 557 REG_GET(RDPCSPIPE_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE, &dp_alt_mode_disable); 558 } 559 } 560 561 is_usb_c_alt_mode = (dp_alt_mode_disable == 0); 562 } 563 564 return is_usb_c_alt_mode; 565 } 566 567 void dcn31_link_encoder_get_max_link_cap(struct link_encoder *enc, 568 struct dc_link_settings *link_settings) 569 { 570 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); 571 uint32_t is_in_usb_c_dp4_mode = 0; 572 573 dcn10_link_encoder_get_max_link_cap(enc, link_settings); 574 575 /* in usb c dp2 mode, max lane count is 2 */ 576 if (enc->funcs->is_in_alt_mode && enc->funcs->is_in_alt_mode(enc)) { 577 if (enc->ctx->asic_id.hw_internal_rev != YELLOW_CARP_B0) { 578 // [Note] no need to check hw_internal_rev once phy mux selection is ready 579 REG_GET(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DP4, &is_in_usb_c_dp4_mode); 580 } else { 581 if ((enc10->base.transmitter == TRANSMITTER_UNIPHY_A) 582 || (enc10->base.transmitter == TRANSMITTER_UNIPHY_B) 583 || (enc10->base.transmitter == TRANSMITTER_UNIPHY_E)) { 584 REG_GET(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DP4, &is_in_usb_c_dp4_mode); 585 } else { 586 REG_GET(RDPCSPIPE_PHY_CNTL6, RDPCS_PHY_DPALT_DP4, &is_in_usb_c_dp4_mode); 587 } 588 } 589 if (!is_in_usb_c_dp4_mode) 590 link_settings->lane_count = MIN(LANE_COUNT_TWO, link_settings->lane_count); 591 } 592 } 593