1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "reg_helper.h" 27 #include "core_types.h" 28 #include "dcn31_dccg.h" 29 #include "dal_asic_id.h" 30 31 #define TO_DCN_DCCG(dccg)\ 32 container_of(dccg, struct dcn_dccg, base) 33 34 #define REG(reg) \ 35 (dccg_dcn->regs->reg) 36 37 #undef FN 38 #define FN(reg_name, field_name) \ 39 dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name 40 41 #define CTX \ 42 dccg_dcn->base.ctx 43 #define DC_LOGGER \ 44 dccg->ctx->logger 45 46 void dccg31_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk) 47 { 48 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); 49 50 if (dccg->dpp_clock_gated[dpp_inst]) { 51 /* 52 * Do not update the DPPCLK DTO if the clock is stopped. 53 * It is treated the same as if the pipe itself were in PG. 54 */ 55 return; 56 } 57 58 if (dccg->ref_dppclk && req_dppclk) { 59 int ref_dppclk = dccg->ref_dppclk; 60 int modulo, phase; 61 62 // phase / modulo = dpp pipe clk / dpp global clk 63 modulo = 0xff; // use FF at the end 64 phase = ((modulo * req_dppclk) + ref_dppclk - 1) / ref_dppclk; 65 66 if (phase > 0xff) { 67 ASSERT(false); 68 phase = 0xff; 69 } 70 71 REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0, 72 DPPCLK0_DTO_PHASE, phase, 73 DPPCLK0_DTO_MODULO, modulo); 74 REG_UPDATE(DPPCLK_DTO_CTRL, 75 DPPCLK_DTO_ENABLE[dpp_inst], 1); 76 } else { 77 REG_UPDATE(DPPCLK_DTO_CTRL, 78 DPPCLK_DTO_ENABLE[dpp_inst], 0); 79 } 80 dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk; 81 } 82 83 static enum phyd32clk_clock_source get_phy_mux_symclk( 84 struct dcn_dccg *dccg_dcn, 85 enum phyd32clk_clock_source src) 86 { 87 if (dccg_dcn->base.ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0) { 88 if (src == PHYD32CLKC) 89 src = PHYD32CLKF; 90 if (src == PHYD32CLKD) 91 src = PHYD32CLKG; 92 } 93 return src; 94 } 95 96 static void dccg31_enable_dpstreamclk(struct dccg *dccg, int otg_inst) 97 { 98 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); 99 100 /* enabled to select one of the DTBCLKs for pipe */ 101 switch (otg_inst) { 102 case 0: 103 REG_UPDATE(DPSTREAMCLK_CNTL, 104 DPSTREAMCLK_PIPE0_EN, 1); 105 break; 106 case 1: 107 REG_UPDATE(DPSTREAMCLK_CNTL, 108 DPSTREAMCLK_PIPE1_EN, 1); 109 break; 110 case 2: 111 REG_UPDATE(DPSTREAMCLK_CNTL, 112 DPSTREAMCLK_PIPE2_EN, 1); 113 break; 114 case 3: 115 REG_UPDATE(DPSTREAMCLK_CNTL, 116 DPSTREAMCLK_PIPE3_EN, 1); 117 break; 118 default: 119 BREAK_TO_DEBUGGER(); 120 return; 121 } 122 if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream) 123 REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3, 124 DPSTREAMCLK_GATE_DISABLE, 1, 125 DPSTREAMCLK_ROOT_GATE_DISABLE, 1); 126 } 127 128 static void dccg31_disable_dpstreamclk(struct dccg *dccg, int otg_inst) 129 { 130 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); 131 132 if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream) 133 REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3, 134 DPSTREAMCLK_ROOT_GATE_DISABLE, 0, 135 DPSTREAMCLK_GATE_DISABLE, 0); 136 137 switch (otg_inst) { 138 case 0: 139 REG_UPDATE(DPSTREAMCLK_CNTL, 140 DPSTREAMCLK_PIPE0_EN, 0); 141 break; 142 case 1: 143 REG_UPDATE(DPSTREAMCLK_CNTL, 144 DPSTREAMCLK_PIPE1_EN, 0); 145 break; 146 case 2: 147 REG_UPDATE(DPSTREAMCLK_CNTL, 148 DPSTREAMCLK_PIPE2_EN, 0); 149 break; 150 case 3: 151 REG_UPDATE(DPSTREAMCLK_CNTL, 152 DPSTREAMCLK_PIPE3_EN, 0); 153 break; 154 default: 155 BREAK_TO_DEBUGGER(); 156 return; 157 } 158 } 159 160 void dccg31_set_dpstreamclk( 161 struct dccg *dccg, 162 enum streamclk_source src, 163 int otg_inst, 164 int dp_hpo_inst) 165 { 166 if (src == REFCLK) 167 dccg31_disable_dpstreamclk(dccg, otg_inst); 168 else 169 dccg31_enable_dpstreamclk(dccg, otg_inst); 170 } 171 172 void dccg31_enable_symclk32_se( 173 struct dccg *dccg, 174 int hpo_se_inst, 175 enum phyd32clk_clock_source phyd32clk) 176 { 177 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); 178 179 phyd32clk = get_phy_mux_symclk(dccg_dcn, phyd32clk); 180 181 /* select one of the PHYD32CLKs as the source for symclk32_se */ 182 switch (hpo_se_inst) { 183 case 0: 184 if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se) 185 REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3, 186 SYMCLK32_SE0_GATE_DISABLE, 1, 187 SYMCLK32_ROOT_SE0_GATE_DISABLE, 1); 188 REG_UPDATE_2(SYMCLK32_SE_CNTL, 189 SYMCLK32_SE0_SRC_SEL, phyd32clk, 190 SYMCLK32_SE0_EN, 1); 191 break; 192 case 1: 193 if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se) 194 REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3, 195 SYMCLK32_SE1_GATE_DISABLE, 1, 196 SYMCLK32_ROOT_SE1_GATE_DISABLE, 1); 197 REG_UPDATE_2(SYMCLK32_SE_CNTL, 198 SYMCLK32_SE1_SRC_SEL, phyd32clk, 199 SYMCLK32_SE1_EN, 1); 200 break; 201 case 2: 202 if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se) 203 REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3, 204 SYMCLK32_SE2_GATE_DISABLE, 1, 205 SYMCLK32_ROOT_SE2_GATE_DISABLE, 1); 206 REG_UPDATE_2(SYMCLK32_SE_CNTL, 207 SYMCLK32_SE2_SRC_SEL, phyd32clk, 208 SYMCLK32_SE2_EN, 1); 209 break; 210 case 3: 211 if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se) 212 REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3, 213 SYMCLK32_SE3_GATE_DISABLE, 1, 214 SYMCLK32_ROOT_SE3_GATE_DISABLE, 1); 215 REG_UPDATE_2(SYMCLK32_SE_CNTL, 216 SYMCLK32_SE3_SRC_SEL, phyd32clk, 217 SYMCLK32_SE3_EN, 1); 218 break; 219 default: 220 BREAK_TO_DEBUGGER(); 221 return; 222 } 223 } 224 225 void dccg31_disable_symclk32_se( 226 struct dccg *dccg, 227 int hpo_se_inst) 228 { 229 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); 230 231 /* set refclk as the source for symclk32_se */ 232 switch (hpo_se_inst) { 233 case 0: 234 REG_UPDATE_2(SYMCLK32_SE_CNTL, 235 SYMCLK32_SE0_SRC_SEL, 0, 236 SYMCLK32_SE0_EN, 0); 237 if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se) 238 REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3, 239 SYMCLK32_SE0_GATE_DISABLE, 0, 240 SYMCLK32_ROOT_SE0_GATE_DISABLE, 0); 241 break; 242 case 1: 243 REG_UPDATE_2(SYMCLK32_SE_CNTL, 244 SYMCLK32_SE1_SRC_SEL, 0, 245 SYMCLK32_SE1_EN, 0); 246 if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se) 247 REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3, 248 SYMCLK32_SE1_GATE_DISABLE, 0, 249 SYMCLK32_ROOT_SE1_GATE_DISABLE, 0); 250 break; 251 case 2: 252 REG_UPDATE_2(SYMCLK32_SE_CNTL, 253 SYMCLK32_SE2_SRC_SEL, 0, 254 SYMCLK32_SE2_EN, 0); 255 if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se) 256 REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3, 257 SYMCLK32_SE2_GATE_DISABLE, 0, 258 SYMCLK32_ROOT_SE2_GATE_DISABLE, 0); 259 break; 260 case 3: 261 REG_UPDATE_2(SYMCLK32_SE_CNTL, 262 SYMCLK32_SE3_SRC_SEL, 0, 263 SYMCLK32_SE3_EN, 0); 264 if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se) 265 REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3, 266 SYMCLK32_SE3_GATE_DISABLE, 0, 267 SYMCLK32_ROOT_SE3_GATE_DISABLE, 0); 268 break; 269 default: 270 BREAK_TO_DEBUGGER(); 271 return; 272 } 273 } 274 275 void dccg31_enable_symclk32_le( 276 struct dccg *dccg, 277 int hpo_le_inst, 278 enum phyd32clk_clock_source phyd32clk) 279 { 280 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); 281 282 phyd32clk = get_phy_mux_symclk(dccg_dcn, phyd32clk); 283 284 /* select one of the PHYD32CLKs as the source for symclk32_le */ 285 switch (hpo_le_inst) { 286 case 0: 287 if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le) 288 REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3, 289 SYMCLK32_LE0_GATE_DISABLE, 1, 290 SYMCLK32_ROOT_LE0_GATE_DISABLE, 1); 291 REG_UPDATE_2(SYMCLK32_LE_CNTL, 292 SYMCLK32_LE0_SRC_SEL, phyd32clk, 293 SYMCLK32_LE0_EN, 1); 294 break; 295 case 1: 296 if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le) 297 REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3, 298 SYMCLK32_LE1_GATE_DISABLE, 1, 299 SYMCLK32_ROOT_LE1_GATE_DISABLE, 1); 300 REG_UPDATE_2(SYMCLK32_LE_CNTL, 301 SYMCLK32_LE1_SRC_SEL, phyd32clk, 302 SYMCLK32_LE1_EN, 1); 303 break; 304 default: 305 BREAK_TO_DEBUGGER(); 306 return; 307 } 308 } 309 310 void dccg31_disable_symclk32_le( 311 struct dccg *dccg, 312 int hpo_le_inst) 313 { 314 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); 315 316 /* set refclk as the source for symclk32_le */ 317 switch (hpo_le_inst) { 318 case 0: 319 REG_UPDATE_2(SYMCLK32_LE_CNTL, 320 SYMCLK32_LE0_SRC_SEL, 0, 321 SYMCLK32_LE0_EN, 0); 322 if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le) 323 REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3, 324 SYMCLK32_LE0_GATE_DISABLE, 0, 325 SYMCLK32_ROOT_LE0_GATE_DISABLE, 0); 326 break; 327 case 1: 328 REG_UPDATE_2(SYMCLK32_LE_CNTL, 329 SYMCLK32_LE1_SRC_SEL, 0, 330 SYMCLK32_LE1_EN, 0); 331 if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le) 332 REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3, 333 SYMCLK32_LE1_GATE_DISABLE, 0, 334 SYMCLK32_ROOT_LE1_GATE_DISABLE, 0); 335 break; 336 default: 337 BREAK_TO_DEBUGGER(); 338 return; 339 } 340 } 341 342 void dccg31_disable_dscclk(struct dccg *dccg, int inst) 343 { 344 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); 345 346 if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dsc) 347 return; 348 //DTO must be enabled to generate a 0 Hz clock output 349 switch (inst) { 350 case 0: 351 REG_UPDATE(DSCCLK_DTO_CTRL, 352 DSCCLK0_DTO_ENABLE, 1); 353 REG_UPDATE_2(DSCCLK0_DTO_PARAM, 354 DSCCLK0_DTO_PHASE, 0, 355 DSCCLK0_DTO_MODULO, 1); 356 break; 357 case 1: 358 REG_UPDATE(DSCCLK_DTO_CTRL, 359 DSCCLK1_DTO_ENABLE, 1); 360 REG_UPDATE_2(DSCCLK1_DTO_PARAM, 361 DSCCLK1_DTO_PHASE, 0, 362 DSCCLK1_DTO_MODULO, 1); 363 break; 364 case 2: 365 REG_UPDATE(DSCCLK_DTO_CTRL, 366 DSCCLK2_DTO_ENABLE, 1); 367 REG_UPDATE_2(DSCCLK2_DTO_PARAM, 368 DSCCLK2_DTO_PHASE, 0, 369 DSCCLK2_DTO_MODULO, 1); 370 break; 371 case 3: 372 if (REG(DSCCLK3_DTO_PARAM)) { 373 REG_UPDATE(DSCCLK_DTO_CTRL, 374 DSCCLK3_DTO_ENABLE, 1); 375 REG_UPDATE_2(DSCCLK3_DTO_PARAM, 376 DSCCLK3_DTO_PHASE, 0, 377 DSCCLK3_DTO_MODULO, 1); 378 } 379 break; 380 default: 381 BREAK_TO_DEBUGGER(); 382 return; 383 } 384 } 385 386 void dccg31_enable_dscclk(struct dccg *dccg, int inst) 387 { 388 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); 389 390 if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dsc) 391 return; 392 //Disable DTO 393 switch (inst) { 394 case 0: 395 REG_UPDATE_2(DSCCLK0_DTO_PARAM, 396 DSCCLK0_DTO_PHASE, 0, 397 DSCCLK0_DTO_MODULO, 0); 398 REG_UPDATE(DSCCLK_DTO_CTRL, 399 DSCCLK0_DTO_ENABLE, 0); 400 break; 401 case 1: 402 REG_UPDATE_2(DSCCLK1_DTO_PARAM, 403 DSCCLK1_DTO_PHASE, 0, 404 DSCCLK1_DTO_MODULO, 0); 405 REG_UPDATE(DSCCLK_DTO_CTRL, 406 DSCCLK1_DTO_ENABLE, 0); 407 break; 408 case 2: 409 REG_UPDATE_2(DSCCLK2_DTO_PARAM, 410 DSCCLK2_DTO_PHASE, 0, 411 DSCCLK2_DTO_MODULO, 0); 412 REG_UPDATE(DSCCLK_DTO_CTRL, 413 DSCCLK2_DTO_ENABLE, 0); 414 break; 415 case 3: 416 if (REG(DSCCLK3_DTO_PARAM)) { 417 REG_UPDATE(DSCCLK_DTO_CTRL, 418 DSCCLK3_DTO_ENABLE, 0); 419 REG_UPDATE_2(DSCCLK3_DTO_PARAM, 420 DSCCLK3_DTO_PHASE, 0, 421 DSCCLK3_DTO_MODULO, 0); 422 } 423 break; 424 default: 425 BREAK_TO_DEBUGGER(); 426 return; 427 } 428 } 429 430 void dccg31_set_physymclk( 431 struct dccg *dccg, 432 int phy_inst, 433 enum physymclk_clock_source clk_src, 434 bool force_enable) 435 { 436 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); 437 438 /* Force PHYSYMCLK on and Select phyd32clk as the source of clock which is output to PHY through DCIO */ 439 switch (phy_inst) { 440 case 0: 441 if (force_enable) { 442 REG_UPDATE_2(PHYASYMCLK_CLOCK_CNTL, 443 PHYASYMCLK_FORCE_EN, 1, 444 PHYASYMCLK_FORCE_SRC_SEL, clk_src); 445 if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk) 446 REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, 447 PHYASYMCLK_GATE_DISABLE, 1); 448 } else { 449 REG_UPDATE_2(PHYASYMCLK_CLOCK_CNTL, 450 PHYASYMCLK_FORCE_EN, 0, 451 PHYASYMCLK_FORCE_SRC_SEL, 0); 452 if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk) 453 REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, 454 PHYASYMCLK_GATE_DISABLE, 0); 455 } 456 break; 457 case 1: 458 if (force_enable) { 459 REG_UPDATE_2(PHYBSYMCLK_CLOCK_CNTL, 460 PHYBSYMCLK_FORCE_EN, 1, 461 PHYBSYMCLK_FORCE_SRC_SEL, clk_src); 462 if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk) 463 REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, 464 PHYBSYMCLK_GATE_DISABLE, 1); 465 } else { 466 REG_UPDATE_2(PHYBSYMCLK_CLOCK_CNTL, 467 PHYBSYMCLK_FORCE_EN, 0, 468 PHYBSYMCLK_FORCE_SRC_SEL, 0); 469 if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk) 470 REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, 471 PHYBSYMCLK_GATE_DISABLE, 0); 472 } 473 break; 474 case 2: 475 if (force_enable) { 476 REG_UPDATE_2(PHYCSYMCLK_CLOCK_CNTL, 477 PHYCSYMCLK_FORCE_EN, 1, 478 PHYCSYMCLK_FORCE_SRC_SEL, clk_src); 479 if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk) 480 REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, 481 PHYCSYMCLK_GATE_DISABLE, 1); 482 } else { 483 REG_UPDATE_2(PHYCSYMCLK_CLOCK_CNTL, 484 PHYCSYMCLK_FORCE_EN, 0, 485 PHYCSYMCLK_FORCE_SRC_SEL, 0); 486 if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk) 487 REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, 488 PHYCSYMCLK_GATE_DISABLE, 0); 489 } 490 break; 491 case 3: 492 if (force_enable) { 493 REG_UPDATE_2(PHYDSYMCLK_CLOCK_CNTL, 494 PHYDSYMCLK_FORCE_EN, 1, 495 PHYDSYMCLK_FORCE_SRC_SEL, clk_src); 496 if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk) 497 REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, 498 PHYDSYMCLK_GATE_DISABLE, 1); 499 } else { 500 REG_UPDATE_2(PHYDSYMCLK_CLOCK_CNTL, 501 PHYDSYMCLK_FORCE_EN, 0, 502 PHYDSYMCLK_FORCE_SRC_SEL, 0); 503 if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk) 504 REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, 505 PHYDSYMCLK_GATE_DISABLE, 0); 506 } 507 break; 508 case 4: 509 if (force_enable) { 510 REG_UPDATE_2(PHYESYMCLK_CLOCK_CNTL, 511 PHYESYMCLK_FORCE_EN, 1, 512 PHYESYMCLK_FORCE_SRC_SEL, clk_src); 513 if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk) 514 REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, 515 PHYESYMCLK_GATE_DISABLE, 1); 516 } else { 517 REG_UPDATE_2(PHYESYMCLK_CLOCK_CNTL, 518 PHYESYMCLK_FORCE_EN, 0, 519 PHYESYMCLK_FORCE_SRC_SEL, 0); 520 if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk) 521 REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, 522 PHYESYMCLK_GATE_DISABLE, 0); 523 } 524 break; 525 default: 526 BREAK_TO_DEBUGGER(); 527 return; 528 } 529 } 530 531 /* Controls the generation of pixel valid for OTG in (OTG -> HPO case) */ 532 void dccg31_set_dtbclk_dto( 533 struct dccg *dccg, 534 const struct dtbclk_dto_params *params) 535 { 536 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); 537 int req_dtbclk_khz = params->pixclk_khz; 538 uint32_t dtbdto_div; 539 540 /* Mode DTBDTO Rate DTBCLK_DTO<x>_DIV Register 541 * ODM 4:1 combine pixel rate/4 2 542 * ODM 2:1 combine pixel rate/2 4 543 * non-DSC 4:2:0 mode pixel rate/2 4 544 * DSC native 4:2:0 pixel rate/2 4 545 * DSC native 4:2:2 pixel rate/2 4 546 * Other modes pixel rate 8 547 */ 548 if (params->num_odm_segments == 4) { 549 dtbdto_div = 2; 550 req_dtbclk_khz = params->pixclk_khz / 4; 551 } else if ((params->num_odm_segments == 2) || 552 (params->timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) || 553 (params->timing->flags.DSC && params->timing->pixel_encoding == PIXEL_ENCODING_YCBCR422 554 && !params->timing->dsc_cfg.ycbcr422_simple)) { 555 dtbdto_div = 4; 556 req_dtbclk_khz = params->pixclk_khz / 2; 557 } else 558 dtbdto_div = 8; 559 560 if (params->ref_dtbclk_khz && req_dtbclk_khz) { 561 uint32_t modulo, phase; 562 563 // phase / modulo = dtbclk / dtbclk ref 564 modulo = params->ref_dtbclk_khz * 1000; 565 phase = div_u64((((unsigned long long)modulo * req_dtbclk_khz) + params->ref_dtbclk_khz - 1), 566 params->ref_dtbclk_khz); 567 568 REG_UPDATE(OTG_PIXEL_RATE_CNTL[params->otg_inst], 569 DTBCLK_DTO_DIV[params->otg_inst], dtbdto_div); 570 571 REG_WRITE(DTBCLK_DTO_MODULO[params->otg_inst], modulo); 572 REG_WRITE(DTBCLK_DTO_PHASE[params->otg_inst], phase); 573 574 REG_UPDATE(OTG_PIXEL_RATE_CNTL[params->otg_inst], 575 DTBCLK_DTO_ENABLE[params->otg_inst], 1); 576 577 REG_WAIT(OTG_PIXEL_RATE_CNTL[params->otg_inst], 578 DTBCLKDTO_ENABLE_STATUS[params->otg_inst], 1, 579 1, 100); 580 581 /* The recommended programming sequence to enable DTBCLK DTO to generate 582 * valid pixel HPO DPSTREAM ENCODER, specifies that DTO source select should 583 * be set only after DTO is enabled 584 */ 585 REG_UPDATE(OTG_PIXEL_RATE_CNTL[params->otg_inst], 586 PIPE_DTO_SRC_SEL[params->otg_inst], 1); 587 } else { 588 REG_UPDATE_3(OTG_PIXEL_RATE_CNTL[params->otg_inst], 589 DTBCLK_DTO_ENABLE[params->otg_inst], 0, 590 PIPE_DTO_SRC_SEL[params->otg_inst], 0, 591 DTBCLK_DTO_DIV[params->otg_inst], dtbdto_div); 592 593 REG_WRITE(DTBCLK_DTO_MODULO[params->otg_inst], 0); 594 REG_WRITE(DTBCLK_DTO_PHASE[params->otg_inst], 0); 595 } 596 } 597 598 void dccg31_set_audio_dtbclk_dto( 599 struct dccg *dccg, 600 const struct dtbclk_dto_params *params) 601 { 602 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); 603 604 if (params->ref_dtbclk_khz && params->req_audio_dtbclk_khz) { 605 uint32_t modulo, phase; 606 607 // phase / modulo = dtbclk / dtbclk ref 608 modulo = params->ref_dtbclk_khz * 1000; 609 phase = div_u64((((unsigned long long)modulo * params->req_audio_dtbclk_khz) + params->ref_dtbclk_khz - 1), 610 params->ref_dtbclk_khz); 611 612 613 REG_WRITE(DCCG_AUDIO_DTBCLK_DTO_MODULO, modulo); 614 REG_WRITE(DCCG_AUDIO_DTBCLK_DTO_PHASE, phase); 615 616 //REG_UPDATE(DCCG_AUDIO_DTO_SOURCE, 617 // DCCG_AUDIO_DTBCLK_DTO_USE_512FBR_DTO, 1); 618 619 REG_UPDATE(DCCG_AUDIO_DTO_SOURCE, 620 DCCG_AUDIO_DTO_SEL, 4); // 04 - DCCG_AUDIO_DTO_SEL_AUDIO_DTO_DTBCLK 621 } else { 622 REG_WRITE(DCCG_AUDIO_DTBCLK_DTO_PHASE, 0); 623 REG_WRITE(DCCG_AUDIO_DTBCLK_DTO_MODULO, 0); 624 625 REG_UPDATE(DCCG_AUDIO_DTO_SOURCE, 626 DCCG_AUDIO_DTO_SEL, 3); // 03 - DCCG_AUDIO_DTO_SEL_NO_AUDIO_DTO 627 } 628 } 629 630 void dccg31_get_dccg_ref_freq(struct dccg *dccg, 631 unsigned int xtalin_freq_inKhz, 632 unsigned int *dccg_ref_freq_inKhz) 633 { 634 /* 635 * Assume refclk is sourced from xtalin 636 * expect 24MHz 637 */ 638 *dccg_ref_freq_inKhz = xtalin_freq_inKhz; 639 return; 640 } 641 642 void dccg31_set_dispclk_change_mode( 643 struct dccg *dccg, 644 enum dentist_dispclk_change_mode change_mode) 645 { 646 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); 647 648 REG_UPDATE(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_MODE, 649 change_mode == DISPCLK_CHANGE_MODE_RAMPING ? 2 : 0); 650 } 651 652 void dccg31_init(struct dccg *dccg) 653 { 654 /* Set HPO stream encoder to use refclk to avoid case where PHY is 655 * disabled and SYMCLK32 for HPO SE is sourced from PHYD32CLK which 656 * will cause DCN to hang. 657 */ 658 dccg31_disable_symclk32_se(dccg, 0); 659 dccg31_disable_symclk32_se(dccg, 1); 660 dccg31_disable_symclk32_se(dccg, 2); 661 dccg31_disable_symclk32_se(dccg, 3); 662 663 if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le) { 664 dccg31_disable_symclk32_le(dccg, 0); 665 dccg31_disable_symclk32_le(dccg, 1); 666 } 667 668 if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream) { 669 dccg31_disable_dpstreamclk(dccg, 0); 670 dccg31_disable_dpstreamclk(dccg, 1); 671 dccg31_disable_dpstreamclk(dccg, 2); 672 dccg31_disable_dpstreamclk(dccg, 3); 673 } 674 675 if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk) { 676 dccg31_set_physymclk(dccg, 0, PHYSYMCLK_FORCE_SRC_SYMCLK, false); 677 dccg31_set_physymclk(dccg, 1, PHYSYMCLK_FORCE_SRC_SYMCLK, false); 678 dccg31_set_physymclk(dccg, 2, PHYSYMCLK_FORCE_SRC_SYMCLK, false); 679 dccg31_set_physymclk(dccg, 3, PHYSYMCLK_FORCE_SRC_SYMCLK, false); 680 dccg31_set_physymclk(dccg, 4, PHYSYMCLK_FORCE_SRC_SYMCLK, false); 681 } 682 } 683 684 void dccg31_otg_add_pixel(struct dccg *dccg, 685 uint32_t otg_inst) 686 { 687 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); 688 689 REG_UPDATE(OTG_PIXEL_RATE_CNTL[otg_inst], 690 OTG_ADD_PIXEL[otg_inst], 1); 691 } 692 693 void dccg31_otg_drop_pixel(struct dccg *dccg, 694 uint32_t otg_inst) 695 { 696 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); 697 698 REG_UPDATE(OTG_PIXEL_RATE_CNTL[otg_inst], 699 OTG_DROP_PIXEL[otg_inst], 1); 700 } 701 702 static const struct dccg_funcs dccg31_funcs = { 703 .update_dpp_dto = dccg31_update_dpp_dto, 704 .get_dccg_ref_freq = dccg31_get_dccg_ref_freq, 705 .dccg_init = dccg31_init, 706 .set_dpstreamclk = dccg31_set_dpstreamclk, 707 .enable_symclk32_se = dccg31_enable_symclk32_se, 708 .disable_symclk32_se = dccg31_disable_symclk32_se, 709 .enable_symclk32_le = dccg31_enable_symclk32_le, 710 .disable_symclk32_le = dccg31_disable_symclk32_le, 711 .set_physymclk = dccg31_set_physymclk, 712 .set_dtbclk_dto = dccg31_set_dtbclk_dto, 713 .set_audio_dtbclk_dto = dccg31_set_audio_dtbclk_dto, 714 .set_fifo_errdet_ovr_en = dccg2_set_fifo_errdet_ovr_en, 715 .otg_add_pixel = dccg31_otg_add_pixel, 716 .otg_drop_pixel = dccg31_otg_drop_pixel, 717 .set_dispclk_change_mode = dccg31_set_dispclk_change_mode, 718 .disable_dsc = dccg31_disable_dscclk, 719 .enable_dsc = dccg31_enable_dscclk, 720 }; 721 722 struct dccg *dccg31_create( 723 struct dc_context *ctx, 724 const struct dccg_registers *regs, 725 const struct dccg_shift *dccg_shift, 726 const struct dccg_mask *dccg_mask) 727 { 728 struct dcn_dccg *dccg_dcn = kzalloc(sizeof(*dccg_dcn), GFP_KERNEL); 729 struct dccg *base; 730 731 if (dccg_dcn == NULL) { 732 BREAK_TO_DEBUGGER(); 733 return NULL; 734 } 735 736 base = &dccg_dcn->base; 737 base->ctx = ctx; 738 base->funcs = &dccg31_funcs; 739 740 dccg_dcn->regs = regs; 741 dccg_dcn->dccg_shift = dccg_shift; 742 dccg_dcn->dccg_mask = dccg_mask; 743 744 return &dccg_dcn->base; 745 } 746