1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "reg_helper.h" 27 #include "core_types.h" 28 #include "dcn31_dccg.h" 29 #include "dal_asic_id.h" 30 31 #define TO_DCN_DCCG(dccg)\ 32 container_of(dccg, struct dcn_dccg, base) 33 34 #define REG(reg) \ 35 (dccg_dcn->regs->reg) 36 37 #undef FN 38 #define FN(reg_name, field_name) \ 39 dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name 40 41 #define CTX \ 42 dccg_dcn->base.ctx 43 #define DC_LOGGER \ 44 dccg->ctx->logger 45 46 void dccg31_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk) 47 { 48 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); 49 50 if (dccg->ref_dppclk && req_dppclk) { 51 int ref_dppclk = dccg->ref_dppclk; 52 int modulo, phase; 53 54 // phase / modulo = dpp pipe clk / dpp global clk 55 modulo = 0xff; // use FF at the end 56 phase = ((modulo * req_dppclk) + ref_dppclk - 1) / ref_dppclk; 57 58 if (phase > 0xff) { 59 ASSERT(false); 60 phase = 0xff; 61 } 62 63 REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0, 64 DPPCLK0_DTO_PHASE, phase, 65 DPPCLK0_DTO_MODULO, modulo); 66 REG_UPDATE(DPPCLK_DTO_CTRL, 67 DPPCLK_DTO_ENABLE[dpp_inst], 1); 68 } else { 69 REG_UPDATE(DPPCLK_DTO_CTRL, 70 DPPCLK_DTO_ENABLE[dpp_inst], 0); 71 } 72 dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk; 73 } 74 75 static enum phyd32clk_clock_source get_phy_mux_symclk( 76 struct dcn_dccg *dccg_dcn, 77 enum phyd32clk_clock_source src) 78 { 79 if (dccg_dcn->base.ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0) { 80 if (src == PHYD32CLKC) 81 src = PHYD32CLKF; 82 if (src == PHYD32CLKD) 83 src = PHYD32CLKG; 84 } 85 return src; 86 } 87 88 static void dccg31_enable_dpstreamclk(struct dccg *dccg, int otg_inst) 89 { 90 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); 91 92 /* enabled to select one of the DTBCLKs for pipe */ 93 switch (otg_inst) { 94 case 0: 95 REG_UPDATE(DPSTREAMCLK_CNTL, 96 DPSTREAMCLK_PIPE0_EN, 1); 97 break; 98 case 1: 99 REG_UPDATE(DPSTREAMCLK_CNTL, 100 DPSTREAMCLK_PIPE1_EN, 1); 101 break; 102 case 2: 103 REG_UPDATE(DPSTREAMCLK_CNTL, 104 DPSTREAMCLK_PIPE2_EN, 1); 105 break; 106 case 3: 107 REG_UPDATE(DPSTREAMCLK_CNTL, 108 DPSTREAMCLK_PIPE3_EN, 1); 109 break; 110 default: 111 BREAK_TO_DEBUGGER(); 112 return; 113 } 114 if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream) 115 REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3, 116 DPSTREAMCLK_GATE_DISABLE, 1, 117 DPSTREAMCLK_ROOT_GATE_DISABLE, 1); 118 } 119 120 static void dccg31_disable_dpstreamclk(struct dccg *dccg, int otg_inst) 121 { 122 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); 123 124 if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream) 125 REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3, 126 DPSTREAMCLK_ROOT_GATE_DISABLE, 0, 127 DPSTREAMCLK_GATE_DISABLE, 0); 128 129 switch (otg_inst) { 130 case 0: 131 REG_UPDATE(DPSTREAMCLK_CNTL, 132 DPSTREAMCLK_PIPE0_EN, 0); 133 break; 134 case 1: 135 REG_UPDATE(DPSTREAMCLK_CNTL, 136 DPSTREAMCLK_PIPE1_EN, 0); 137 break; 138 case 2: 139 REG_UPDATE(DPSTREAMCLK_CNTL, 140 DPSTREAMCLK_PIPE2_EN, 0); 141 break; 142 case 3: 143 REG_UPDATE(DPSTREAMCLK_CNTL, 144 DPSTREAMCLK_PIPE3_EN, 0); 145 break; 146 default: 147 BREAK_TO_DEBUGGER(); 148 return; 149 } 150 } 151 152 void dccg31_set_dpstreamclk( 153 struct dccg *dccg, 154 enum streamclk_source src, 155 int otg_inst, 156 int dp_hpo_inst) 157 { 158 if (src == REFCLK) 159 dccg31_disable_dpstreamclk(dccg, otg_inst); 160 else 161 dccg31_enable_dpstreamclk(dccg, otg_inst); 162 } 163 164 void dccg31_enable_symclk32_se( 165 struct dccg *dccg, 166 int hpo_se_inst, 167 enum phyd32clk_clock_source phyd32clk) 168 { 169 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); 170 171 phyd32clk = get_phy_mux_symclk(dccg_dcn, phyd32clk); 172 173 /* select one of the PHYD32CLKs as the source for symclk32_se */ 174 switch (hpo_se_inst) { 175 case 0: 176 if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se) 177 REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3, 178 SYMCLK32_SE0_GATE_DISABLE, 1, 179 SYMCLK32_ROOT_SE0_GATE_DISABLE, 1); 180 REG_UPDATE_2(SYMCLK32_SE_CNTL, 181 SYMCLK32_SE0_SRC_SEL, phyd32clk, 182 SYMCLK32_SE0_EN, 1); 183 break; 184 case 1: 185 if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se) 186 REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3, 187 SYMCLK32_SE1_GATE_DISABLE, 1, 188 SYMCLK32_ROOT_SE1_GATE_DISABLE, 1); 189 REG_UPDATE_2(SYMCLK32_SE_CNTL, 190 SYMCLK32_SE1_SRC_SEL, phyd32clk, 191 SYMCLK32_SE1_EN, 1); 192 break; 193 case 2: 194 if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se) 195 REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3, 196 SYMCLK32_SE2_GATE_DISABLE, 1, 197 SYMCLK32_ROOT_SE2_GATE_DISABLE, 1); 198 REG_UPDATE_2(SYMCLK32_SE_CNTL, 199 SYMCLK32_SE2_SRC_SEL, phyd32clk, 200 SYMCLK32_SE2_EN, 1); 201 break; 202 case 3: 203 if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se) 204 REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3, 205 SYMCLK32_SE3_GATE_DISABLE, 1, 206 SYMCLK32_ROOT_SE3_GATE_DISABLE, 1); 207 REG_UPDATE_2(SYMCLK32_SE_CNTL, 208 SYMCLK32_SE3_SRC_SEL, phyd32clk, 209 SYMCLK32_SE3_EN, 1); 210 break; 211 default: 212 BREAK_TO_DEBUGGER(); 213 return; 214 } 215 } 216 217 void dccg31_disable_symclk32_se( 218 struct dccg *dccg, 219 int hpo_se_inst) 220 { 221 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); 222 223 /* set refclk as the source for symclk32_se */ 224 switch (hpo_se_inst) { 225 case 0: 226 REG_UPDATE_2(SYMCLK32_SE_CNTL, 227 SYMCLK32_SE0_SRC_SEL, 0, 228 SYMCLK32_SE0_EN, 0); 229 if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se) 230 REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3, 231 SYMCLK32_SE0_GATE_DISABLE, 0, 232 SYMCLK32_ROOT_SE0_GATE_DISABLE, 0); 233 break; 234 case 1: 235 REG_UPDATE_2(SYMCLK32_SE_CNTL, 236 SYMCLK32_SE1_SRC_SEL, 0, 237 SYMCLK32_SE1_EN, 0); 238 if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se) 239 REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3, 240 SYMCLK32_SE1_GATE_DISABLE, 0, 241 SYMCLK32_ROOT_SE1_GATE_DISABLE, 0); 242 break; 243 case 2: 244 REG_UPDATE_2(SYMCLK32_SE_CNTL, 245 SYMCLK32_SE2_SRC_SEL, 0, 246 SYMCLK32_SE2_EN, 0); 247 if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se) 248 REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3, 249 SYMCLK32_SE2_GATE_DISABLE, 0, 250 SYMCLK32_ROOT_SE2_GATE_DISABLE, 0); 251 break; 252 case 3: 253 REG_UPDATE_2(SYMCLK32_SE_CNTL, 254 SYMCLK32_SE3_SRC_SEL, 0, 255 SYMCLK32_SE3_EN, 0); 256 if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se) 257 REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3, 258 SYMCLK32_SE3_GATE_DISABLE, 0, 259 SYMCLK32_ROOT_SE3_GATE_DISABLE, 0); 260 break; 261 default: 262 BREAK_TO_DEBUGGER(); 263 return; 264 } 265 } 266 267 void dccg31_enable_symclk32_le( 268 struct dccg *dccg, 269 int hpo_le_inst, 270 enum phyd32clk_clock_source phyd32clk) 271 { 272 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); 273 274 phyd32clk = get_phy_mux_symclk(dccg_dcn, phyd32clk); 275 276 /* select one of the PHYD32CLKs as the source for symclk32_le */ 277 switch (hpo_le_inst) { 278 case 0: 279 if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le) 280 REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3, 281 SYMCLK32_LE0_GATE_DISABLE, 1, 282 SYMCLK32_ROOT_LE0_GATE_DISABLE, 1); 283 REG_UPDATE_2(SYMCLK32_LE_CNTL, 284 SYMCLK32_LE0_SRC_SEL, phyd32clk, 285 SYMCLK32_LE0_EN, 1); 286 break; 287 case 1: 288 if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le) 289 REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3, 290 SYMCLK32_LE1_GATE_DISABLE, 1, 291 SYMCLK32_ROOT_LE1_GATE_DISABLE, 1); 292 REG_UPDATE_2(SYMCLK32_LE_CNTL, 293 SYMCLK32_LE1_SRC_SEL, phyd32clk, 294 SYMCLK32_LE1_EN, 1); 295 break; 296 default: 297 BREAK_TO_DEBUGGER(); 298 return; 299 } 300 } 301 302 void dccg31_disable_symclk32_le( 303 struct dccg *dccg, 304 int hpo_le_inst) 305 { 306 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); 307 308 /* set refclk as the source for symclk32_le */ 309 switch (hpo_le_inst) { 310 case 0: 311 REG_UPDATE_2(SYMCLK32_LE_CNTL, 312 SYMCLK32_LE0_SRC_SEL, 0, 313 SYMCLK32_LE0_EN, 0); 314 if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le) 315 REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3, 316 SYMCLK32_LE0_GATE_DISABLE, 0, 317 SYMCLK32_ROOT_LE0_GATE_DISABLE, 0); 318 break; 319 case 1: 320 REG_UPDATE_2(SYMCLK32_LE_CNTL, 321 SYMCLK32_LE1_SRC_SEL, 0, 322 SYMCLK32_LE1_EN, 0); 323 if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le) 324 REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3, 325 SYMCLK32_LE1_GATE_DISABLE, 0, 326 SYMCLK32_ROOT_LE1_GATE_DISABLE, 0); 327 break; 328 default: 329 BREAK_TO_DEBUGGER(); 330 return; 331 } 332 } 333 334 void dccg31_disable_dscclk(struct dccg *dccg, int inst) 335 { 336 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); 337 338 if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dsc) 339 return; 340 //DTO must be enabled to generate a 0 Hz clock output 341 switch (inst) { 342 case 0: 343 REG_UPDATE(DSCCLK_DTO_CTRL, 344 DSCCLK0_DTO_ENABLE, 1); 345 REG_UPDATE_2(DSCCLK0_DTO_PARAM, 346 DSCCLK0_DTO_PHASE, 0, 347 DSCCLK0_DTO_MODULO, 1); 348 break; 349 case 1: 350 REG_UPDATE(DSCCLK_DTO_CTRL, 351 DSCCLK1_DTO_ENABLE, 1); 352 REG_UPDATE_2(DSCCLK1_DTO_PARAM, 353 DSCCLK1_DTO_PHASE, 0, 354 DSCCLK1_DTO_MODULO, 1); 355 break; 356 case 2: 357 REG_UPDATE(DSCCLK_DTO_CTRL, 358 DSCCLK2_DTO_ENABLE, 1); 359 REG_UPDATE_2(DSCCLK2_DTO_PARAM, 360 DSCCLK2_DTO_PHASE, 0, 361 DSCCLK2_DTO_MODULO, 1); 362 break; 363 default: 364 BREAK_TO_DEBUGGER(); 365 return; 366 } 367 } 368 369 void dccg31_enable_dscclk(struct dccg *dccg, int inst) 370 { 371 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); 372 373 if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dsc) 374 return; 375 //Disable DTO 376 switch (inst) { 377 case 0: 378 REG_UPDATE_2(DSCCLK0_DTO_PARAM, 379 DSCCLK0_DTO_PHASE, 0, 380 DSCCLK0_DTO_MODULO, 0); 381 REG_UPDATE(DSCCLK_DTO_CTRL, 382 DSCCLK0_DTO_ENABLE, 0); 383 break; 384 case 1: 385 REG_UPDATE_2(DSCCLK1_DTO_PARAM, 386 DSCCLK1_DTO_PHASE, 0, 387 DSCCLK1_DTO_MODULO, 0); 388 REG_UPDATE(DSCCLK_DTO_CTRL, 389 DSCCLK1_DTO_ENABLE, 0); 390 break; 391 case 2: 392 REG_UPDATE_2(DSCCLK2_DTO_PARAM, 393 DSCCLK2_DTO_PHASE, 0, 394 DSCCLK2_DTO_MODULO, 0); 395 REG_UPDATE(DSCCLK_DTO_CTRL, 396 DSCCLK2_DTO_ENABLE, 0); 397 break; 398 default: 399 BREAK_TO_DEBUGGER(); 400 return; 401 } 402 } 403 404 void dccg31_set_physymclk( 405 struct dccg *dccg, 406 int phy_inst, 407 enum physymclk_clock_source clk_src, 408 bool force_enable) 409 { 410 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); 411 412 /* Force PHYSYMCLK on and Select phyd32clk as the source of clock which is output to PHY through DCIO */ 413 switch (phy_inst) { 414 case 0: 415 if (force_enable) { 416 REG_UPDATE_2(PHYASYMCLK_CLOCK_CNTL, 417 PHYASYMCLK_FORCE_EN, 1, 418 PHYASYMCLK_FORCE_SRC_SEL, clk_src); 419 if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk) 420 REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, 421 PHYASYMCLK_GATE_DISABLE, 1); 422 } else { 423 REG_UPDATE_2(PHYASYMCLK_CLOCK_CNTL, 424 PHYASYMCLK_FORCE_EN, 0, 425 PHYASYMCLK_FORCE_SRC_SEL, 0); 426 if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk) 427 REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, 428 PHYASYMCLK_GATE_DISABLE, 0); 429 } 430 break; 431 case 1: 432 if (force_enable) { 433 REG_UPDATE_2(PHYBSYMCLK_CLOCK_CNTL, 434 PHYBSYMCLK_FORCE_EN, 1, 435 PHYBSYMCLK_FORCE_SRC_SEL, clk_src); 436 if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk) 437 REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, 438 PHYBSYMCLK_GATE_DISABLE, 1); 439 } else { 440 REG_UPDATE_2(PHYBSYMCLK_CLOCK_CNTL, 441 PHYBSYMCLK_FORCE_EN, 0, 442 PHYBSYMCLK_FORCE_SRC_SEL, 0); 443 if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk) 444 REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, 445 PHYBSYMCLK_GATE_DISABLE, 0); 446 } 447 break; 448 case 2: 449 if (force_enable) { 450 REG_UPDATE_2(PHYCSYMCLK_CLOCK_CNTL, 451 PHYCSYMCLK_FORCE_EN, 1, 452 PHYCSYMCLK_FORCE_SRC_SEL, clk_src); 453 if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk) 454 REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, 455 PHYCSYMCLK_GATE_DISABLE, 1); 456 } else { 457 REG_UPDATE_2(PHYCSYMCLK_CLOCK_CNTL, 458 PHYCSYMCLK_FORCE_EN, 0, 459 PHYCSYMCLK_FORCE_SRC_SEL, 0); 460 if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk) 461 REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, 462 PHYCSYMCLK_GATE_DISABLE, 0); 463 } 464 break; 465 case 3: 466 if (force_enable) { 467 REG_UPDATE_2(PHYDSYMCLK_CLOCK_CNTL, 468 PHYDSYMCLK_FORCE_EN, 1, 469 PHYDSYMCLK_FORCE_SRC_SEL, clk_src); 470 if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk) 471 REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, 472 PHYDSYMCLK_GATE_DISABLE, 1); 473 } else { 474 REG_UPDATE_2(PHYDSYMCLK_CLOCK_CNTL, 475 PHYDSYMCLK_FORCE_EN, 0, 476 PHYDSYMCLK_FORCE_SRC_SEL, 0); 477 if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk) 478 REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, 479 PHYDSYMCLK_GATE_DISABLE, 0); 480 } 481 break; 482 case 4: 483 if (force_enable) { 484 REG_UPDATE_2(PHYESYMCLK_CLOCK_CNTL, 485 PHYESYMCLK_FORCE_EN, 1, 486 PHYESYMCLK_FORCE_SRC_SEL, clk_src); 487 if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk) 488 REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, 489 PHYESYMCLK_GATE_DISABLE, 1); 490 } else { 491 REG_UPDATE_2(PHYESYMCLK_CLOCK_CNTL, 492 PHYESYMCLK_FORCE_EN, 0, 493 PHYESYMCLK_FORCE_SRC_SEL, 0); 494 if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk) 495 REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, 496 PHYESYMCLK_GATE_DISABLE, 0); 497 } 498 break; 499 default: 500 BREAK_TO_DEBUGGER(); 501 return; 502 } 503 } 504 505 /* Controls the generation of pixel valid for OTG in (OTG -> HPO case) */ 506 void dccg31_set_dtbclk_dto( 507 struct dccg *dccg, 508 const struct dtbclk_dto_params *params) 509 { 510 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); 511 int req_dtbclk_khz = params->pixclk_khz; 512 uint32_t dtbdto_div; 513 514 /* Mode DTBDTO Rate DTBCLK_DTO<x>_DIV Register 515 * ODM 4:1 combine pixel rate/4 2 516 * ODM 2:1 combine pixel rate/2 4 517 * non-DSC 4:2:0 mode pixel rate/2 4 518 * DSC native 4:2:0 pixel rate/2 4 519 * DSC native 4:2:2 pixel rate/2 4 520 * Other modes pixel rate 8 521 */ 522 if (params->num_odm_segments == 4) { 523 dtbdto_div = 2; 524 req_dtbclk_khz = params->pixclk_khz / 4; 525 } else if ((params->num_odm_segments == 2) || 526 (params->timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) || 527 (params->timing->flags.DSC && params->timing->pixel_encoding == PIXEL_ENCODING_YCBCR422 528 && !params->timing->dsc_cfg.ycbcr422_simple)) { 529 dtbdto_div = 4; 530 req_dtbclk_khz = params->pixclk_khz / 2; 531 } else 532 dtbdto_div = 8; 533 534 if (params->ref_dtbclk_khz && req_dtbclk_khz) { 535 uint32_t modulo, phase; 536 537 // phase / modulo = dtbclk / dtbclk ref 538 modulo = params->ref_dtbclk_khz * 1000; 539 phase = div_u64((((unsigned long long)modulo * req_dtbclk_khz) + params->ref_dtbclk_khz - 1), 540 params->ref_dtbclk_khz); 541 542 REG_UPDATE(OTG_PIXEL_RATE_CNTL[params->otg_inst], 543 DTBCLK_DTO_DIV[params->otg_inst], dtbdto_div); 544 545 REG_WRITE(DTBCLK_DTO_MODULO[params->otg_inst], modulo); 546 REG_WRITE(DTBCLK_DTO_PHASE[params->otg_inst], phase); 547 548 REG_UPDATE(OTG_PIXEL_RATE_CNTL[params->otg_inst], 549 DTBCLK_DTO_ENABLE[params->otg_inst], 1); 550 551 REG_WAIT(OTG_PIXEL_RATE_CNTL[params->otg_inst], 552 DTBCLKDTO_ENABLE_STATUS[params->otg_inst], 1, 553 1, 100); 554 555 /* The recommended programming sequence to enable DTBCLK DTO to generate 556 * valid pixel HPO DPSTREAM ENCODER, specifies that DTO source select should 557 * be set only after DTO is enabled 558 */ 559 REG_UPDATE(OTG_PIXEL_RATE_CNTL[params->otg_inst], 560 PIPE_DTO_SRC_SEL[params->otg_inst], 1); 561 } else { 562 REG_UPDATE_3(OTG_PIXEL_RATE_CNTL[params->otg_inst], 563 DTBCLK_DTO_ENABLE[params->otg_inst], 0, 564 PIPE_DTO_SRC_SEL[params->otg_inst], 0, 565 DTBCLK_DTO_DIV[params->otg_inst], dtbdto_div); 566 567 REG_WRITE(DTBCLK_DTO_MODULO[params->otg_inst], 0); 568 REG_WRITE(DTBCLK_DTO_PHASE[params->otg_inst], 0); 569 } 570 } 571 572 void dccg31_set_audio_dtbclk_dto( 573 struct dccg *dccg, 574 const struct dtbclk_dto_params *params) 575 { 576 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); 577 578 if (params->ref_dtbclk_khz && params->req_audio_dtbclk_khz) { 579 uint32_t modulo, phase; 580 581 // phase / modulo = dtbclk / dtbclk ref 582 modulo = params->ref_dtbclk_khz * 1000; 583 phase = div_u64((((unsigned long long)modulo * params->req_audio_dtbclk_khz) + params->ref_dtbclk_khz - 1), 584 params->ref_dtbclk_khz); 585 586 587 REG_WRITE(DCCG_AUDIO_DTBCLK_DTO_MODULO, modulo); 588 REG_WRITE(DCCG_AUDIO_DTBCLK_DTO_PHASE, phase); 589 590 //REG_UPDATE(DCCG_AUDIO_DTO_SOURCE, 591 // DCCG_AUDIO_DTBCLK_DTO_USE_512FBR_DTO, 1); 592 593 REG_UPDATE(DCCG_AUDIO_DTO_SOURCE, 594 DCCG_AUDIO_DTO_SEL, 4); // 04 - DCCG_AUDIO_DTO_SEL_AUDIO_DTO_DTBCLK 595 } else { 596 REG_WRITE(DCCG_AUDIO_DTBCLK_DTO_PHASE, 0); 597 REG_WRITE(DCCG_AUDIO_DTBCLK_DTO_MODULO, 0); 598 599 REG_UPDATE(DCCG_AUDIO_DTO_SOURCE, 600 DCCG_AUDIO_DTO_SEL, 3); // 03 - DCCG_AUDIO_DTO_SEL_NO_AUDIO_DTO 601 } 602 } 603 604 void dccg31_get_dccg_ref_freq(struct dccg *dccg, 605 unsigned int xtalin_freq_inKhz, 606 unsigned int *dccg_ref_freq_inKhz) 607 { 608 /* 609 * Assume refclk is sourced from xtalin 610 * expect 24MHz 611 */ 612 *dccg_ref_freq_inKhz = xtalin_freq_inKhz; 613 return; 614 } 615 616 void dccg31_set_dispclk_change_mode( 617 struct dccg *dccg, 618 enum dentist_dispclk_change_mode change_mode) 619 { 620 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); 621 622 REG_UPDATE(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_MODE, 623 change_mode == DISPCLK_CHANGE_MODE_RAMPING ? 2 : 0); 624 } 625 626 void dccg31_init(struct dccg *dccg) 627 { 628 /* Set HPO stream encoder to use refclk to avoid case where PHY is 629 * disabled and SYMCLK32 for HPO SE is sourced from PHYD32CLK which 630 * will cause DCN to hang. 631 */ 632 dccg31_disable_symclk32_se(dccg, 0); 633 dccg31_disable_symclk32_se(dccg, 1); 634 dccg31_disable_symclk32_se(dccg, 2); 635 dccg31_disable_symclk32_se(dccg, 3); 636 637 if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le) { 638 dccg31_disable_symclk32_le(dccg, 0); 639 dccg31_disable_symclk32_le(dccg, 1); 640 } 641 642 if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream) { 643 dccg31_disable_dpstreamclk(dccg, 0); 644 dccg31_disable_dpstreamclk(dccg, 1); 645 dccg31_disable_dpstreamclk(dccg, 2); 646 dccg31_disable_dpstreamclk(dccg, 3); 647 } 648 649 if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk) { 650 dccg31_set_physymclk(dccg, 0, PHYSYMCLK_FORCE_SRC_SYMCLK, false); 651 dccg31_set_physymclk(dccg, 1, PHYSYMCLK_FORCE_SRC_SYMCLK, false); 652 dccg31_set_physymclk(dccg, 2, PHYSYMCLK_FORCE_SRC_SYMCLK, false); 653 dccg31_set_physymclk(dccg, 3, PHYSYMCLK_FORCE_SRC_SYMCLK, false); 654 dccg31_set_physymclk(dccg, 4, PHYSYMCLK_FORCE_SRC_SYMCLK, false); 655 } 656 } 657 658 void dccg31_otg_add_pixel(struct dccg *dccg, 659 uint32_t otg_inst) 660 { 661 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); 662 663 REG_UPDATE(OTG_PIXEL_RATE_CNTL[otg_inst], 664 OTG_ADD_PIXEL[otg_inst], 1); 665 } 666 667 void dccg31_otg_drop_pixel(struct dccg *dccg, 668 uint32_t otg_inst) 669 { 670 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); 671 672 REG_UPDATE(OTG_PIXEL_RATE_CNTL[otg_inst], 673 OTG_DROP_PIXEL[otg_inst], 1); 674 } 675 676 static const struct dccg_funcs dccg31_funcs = { 677 .update_dpp_dto = dccg31_update_dpp_dto, 678 .get_dccg_ref_freq = dccg31_get_dccg_ref_freq, 679 .dccg_init = dccg31_init, 680 .set_dpstreamclk = dccg31_set_dpstreamclk, 681 .enable_symclk32_se = dccg31_enable_symclk32_se, 682 .disable_symclk32_se = dccg31_disable_symclk32_se, 683 .enable_symclk32_le = dccg31_enable_symclk32_le, 684 .disable_symclk32_le = dccg31_disable_symclk32_le, 685 .set_physymclk = dccg31_set_physymclk, 686 .set_dtbclk_dto = dccg31_set_dtbclk_dto, 687 .set_audio_dtbclk_dto = dccg31_set_audio_dtbclk_dto, 688 .set_fifo_errdet_ovr_en = dccg2_set_fifo_errdet_ovr_en, 689 .otg_add_pixel = dccg31_otg_add_pixel, 690 .otg_drop_pixel = dccg31_otg_drop_pixel, 691 .set_dispclk_change_mode = dccg31_set_dispclk_change_mode, 692 .disable_dsc = dccg31_disable_dscclk, 693 .enable_dsc = dccg31_enable_dscclk, 694 }; 695 696 struct dccg *dccg31_create( 697 struct dc_context *ctx, 698 const struct dccg_registers *regs, 699 const struct dccg_shift *dccg_shift, 700 const struct dccg_mask *dccg_mask) 701 { 702 struct dcn_dccg *dccg_dcn = kzalloc(sizeof(*dccg_dcn), GFP_KERNEL); 703 struct dccg *base; 704 705 if (dccg_dcn == NULL) { 706 BREAK_TO_DEBUGGER(); 707 return NULL; 708 } 709 710 base = &dccg_dcn->base; 711 base->ctx = ctx; 712 base->funcs = &dccg31_funcs; 713 714 dccg_dcn->regs = regs; 715 dccg_dcn->dccg_shift = dccg_shift; 716 dccg_dcn->dccg_mask = dccg_mask; 717 718 return &dccg_dcn->base; 719 } 720