1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright (C) 2021 Advanced Micro Devices, Inc. 4 * 5 * Authors: AMD 6 */ 7 8 #include "dcn303_init.h" 9 #include "dcn303_resource.h" 10 #include "dcn303_dccg.h" 11 #include "irq/dcn303/irq_service_dcn303.h" 12 13 #include "dcn30/dcn30_dio_link_encoder.h" 14 #include "dcn30/dcn30_dio_stream_encoder.h" 15 #include "dcn30/dcn30_dpp.h" 16 #include "dcn30/dcn30_dwb.h" 17 #include "dcn30/dcn30_hubbub.h" 18 #include "dcn30/dcn30_hubp.h" 19 #include "dcn30/dcn30_mmhubbub.h" 20 #include "dcn30/dcn30_mpc.h" 21 #include "dcn30/dcn30_opp.h" 22 #include "dcn30/dcn30_optc.h" 23 #include "dcn30/dcn30_resource.h" 24 25 #include "dcn20/dcn20_dsc.h" 26 #include "dcn20/dcn20_resource.h" 27 28 #include "dcn10/dcn10_resource.h" 29 30 #include "dc_link_ddc.h" 31 32 #include "dce/dce_abm.h" 33 #include "dce/dce_audio.h" 34 #include "dce/dce_aux.h" 35 #include "dce/dce_clock_source.h" 36 #include "dce/dce_hwseq.h" 37 #include "dce/dce_i2c_hw.h" 38 #include "dce/dce_panel_cntl.h" 39 #include "dce/dmub_abm.h" 40 #include "dce/dmub_psr.h" 41 #include "clk_mgr.h" 42 43 #include "hw_sequencer_private.h" 44 #include "reg_helper.h" 45 #include "resource.h" 46 #include "vm_helper.h" 47 48 #include "sienna_cichlid_ip_offset.h" 49 #include "dcn/dcn_3_0_3_offset.h" 50 #include "dcn/dcn_3_0_3_sh_mask.h" 51 #include "dcn/dpcs_3_0_3_offset.h" 52 #include "dcn/dpcs_3_0_3_sh_mask.h" 53 #include "nbio/nbio_2_3_offset.h" 54 55 #define DC_LOGGER_INIT(logger) 56 57 struct _vcs_dpi_ip_params_st dcn3_03_ip = { 58 .use_min_dcfclk = 0, 59 .clamp_min_dcfclk = 0, 60 .odm_capable = 1, 61 .gpuvm_enable = 1, 62 .hostvm_enable = 0, 63 .gpuvm_max_page_table_levels = 4, 64 .hostvm_max_page_table_levels = 4, 65 .hostvm_cached_page_table_levels = 0, 66 .pte_group_size_bytes = 2048, 67 .num_dsc = 2, 68 .rob_buffer_size_kbytes = 184, 69 .det_buffer_size_kbytes = 184, 70 .dpte_buffer_size_in_pte_reqs_luma = 64, 71 .dpte_buffer_size_in_pte_reqs_chroma = 34, 72 .pde_proc_buffer_size_64k_reqs = 48, 73 .dpp_output_buffer_pixels = 2560, 74 .opp_output_buffer_lines = 1, 75 .pixel_chunk_size_kbytes = 8, 76 .pte_enable = 1, 77 .max_page_table_levels = 2, 78 .pte_chunk_size_kbytes = 2, // ? 79 .meta_chunk_size_kbytes = 2, 80 .writeback_chunk_size_kbytes = 8, 81 .line_buffer_size_bits = 789504, 82 .is_line_buffer_bpp_fixed = 0, // ? 83 .line_buffer_fixed_bpp = 0, // ? 84 .dcc_supported = true, 85 .writeback_interface_buffer_size_kbytes = 90, 86 .writeback_line_buffer_buffer_size = 0, 87 .max_line_buffer_lines = 12, 88 .writeback_luma_buffer_size_kbytes = 12, // writeback_line_buffer_buffer_size = 656640 89 .writeback_chroma_buffer_size_kbytes = 8, 90 .writeback_chroma_line_buffer_width_pixels = 4, 91 .writeback_max_hscl_ratio = 1, 92 .writeback_max_vscl_ratio = 1, 93 .writeback_min_hscl_ratio = 1, 94 .writeback_min_vscl_ratio = 1, 95 .writeback_max_hscl_taps = 1, 96 .writeback_max_vscl_taps = 1, 97 .writeback_line_buffer_luma_buffer_size = 0, 98 .writeback_line_buffer_chroma_buffer_size = 14643, 99 .cursor_buffer_size = 8, 100 .cursor_chunk_size = 2, 101 .max_num_otg = 2, 102 .max_num_dpp = 2, 103 .max_num_wb = 1, 104 .max_dchub_pscl_bw_pix_per_clk = 4, 105 .max_pscl_lb_bw_pix_per_clk = 2, 106 .max_lb_vscl_bw_pix_per_clk = 4, 107 .max_vscl_hscl_bw_pix_per_clk = 4, 108 .max_hscl_ratio = 6, 109 .max_vscl_ratio = 6, 110 .hscl_mults = 4, 111 .vscl_mults = 4, 112 .max_hscl_taps = 8, 113 .max_vscl_taps = 8, 114 .dispclk_ramp_margin_percent = 1, 115 .underscan_factor = 1.11, 116 .min_vblank_lines = 32, 117 .dppclk_delay_subtotal = 46, 118 .dynamic_metadata_vm_enabled = true, 119 .dppclk_delay_scl_lb_only = 16, 120 .dppclk_delay_scl = 50, 121 .dppclk_delay_cnvc_formatter = 27, 122 .dppclk_delay_cnvc_cursor = 6, 123 .dispclk_delay_subtotal = 119, 124 .dcfclk_cstate_latency = 5.2, // SRExitTime 125 .max_inter_dcn_tile_repeaters = 8, 126 .max_num_hdmi_frl_outputs = 1, 127 .odm_combine_4to1_supported = false, 128 .xfc_supported = false, 129 .xfc_fill_bw_overhead_percent = 10.0, 130 .xfc_fill_constant_bytes = 0, 131 .gfx7_compat_tiling_supported = 0, 132 .number_of_cursors = 1, 133 }; 134 135 struct _vcs_dpi_soc_bounding_box_st dcn3_03_soc = { 136 .clock_limits = { 137 { 138 .state = 0, 139 .dispclk_mhz = 1217.0, 140 .dppclk_mhz = 1217.0, 141 .phyclk_mhz = 810.0, 142 .phyclk_d18_mhz = 667.0, 143 .dscclk_mhz = 405.6, 144 }, 145 }, 146 147 .min_dcfclk = 500.0, /* TODO: set this to actual min DCFCLK */ 148 .num_states = 1, 149 .sr_exit_time_us = 12, 150 .sr_enter_plus_exit_time_us = 20, 151 .urgent_latency_us = 4.0, 152 .urgent_latency_pixel_data_only_us = 4.0, 153 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0, 154 .urgent_latency_vm_data_only_us = 4.0, 155 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096, 156 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096, 157 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096, 158 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 80.0, 159 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0, 160 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0, 161 .max_avg_sdp_bw_use_normal_percent = 60.0, 162 .max_avg_dram_bw_use_normal_percent = 40.0, 163 .writeback_latency_us = 12.0, 164 .max_request_size_bytes = 256, 165 .fabric_datapath_to_dcn_data_return_bytes = 64, 166 .dcn_downspread_percent = 0.5, 167 .downspread_percent = 0.38, 168 .dram_page_open_time_ns = 50.0, 169 .dram_rw_turnaround_time_ns = 17.5, 170 .dram_return_buffer_per_channel_bytes = 8192, 171 .round_trip_ping_latency_dcfclk_cycles = 156, 172 .urgent_out_of_order_return_per_channel_bytes = 4096, 173 .channel_interleave_bytes = 256, 174 .num_banks = 8, 175 .gpuvm_min_page_size_bytes = 4096, 176 .hostvm_min_page_size_bytes = 4096, 177 .dram_clock_change_latency_us = 404, 178 .dummy_pstate_latency_us = 5, 179 .writeback_dram_clock_change_latency_us = 23.0, 180 .return_bus_width_bytes = 64, 181 .dispclk_dppclk_vco_speed_mhz = 3650, 182 .xfc_bus_transport_time_us = 20, // ? 183 .xfc_xbuf_latency_tolerance_us = 4, // ? 184 .use_urgent_burst_bw = 1, // ? 185 .do_urgent_latency_adjustment = true, 186 .urgent_latency_adjustment_fabric_clock_component_us = 1.0, 187 .urgent_latency_adjustment_fabric_clock_reference_mhz = 1000, 188 }; 189 190 static const struct dc_debug_options debug_defaults_drv = { 191 .disable_dmcu = true, 192 .force_abm_enable = false, 193 .timing_trace = false, 194 .clock_trace = true, 195 .disable_pplib_clock_request = true, 196 .pipe_split_policy = MPC_SPLIT_DYNAMIC, 197 .force_single_disp_pipe_split = false, 198 .disable_dcc = DCC_ENABLE, 199 .vsr_support = true, 200 .performance_trace = false, 201 .max_downscale_src_width = 7680,/*upto 8K*/ 202 .disable_pplib_wm_range = false, 203 .scl_reset_length10 = true, 204 .sanity_checks = false, 205 .underflow_assert_delay_us = 0xFFFFFFFF, 206 .dwb_fi_phase = -1, // -1 = disable, 207 .dmub_command_table = true, 208 }; 209 210 static const struct dc_debug_options debug_defaults_diags = { 211 .disable_dmcu = true, 212 .force_abm_enable = false, 213 .timing_trace = true, 214 .clock_trace = true, 215 .disable_dpp_power_gate = true, 216 .disable_hubp_power_gate = true, 217 .disable_clock_gate = true, 218 .disable_pplib_clock_request = true, 219 .disable_pplib_wm_range = true, 220 .disable_stutter = false, 221 .scl_reset_length10 = true, 222 .dwb_fi_phase = -1, // -1 = disable 223 .dmub_command_table = true, 224 .enable_tri_buf = true, 225 .disable_psr = true, 226 }; 227 228 enum dcn303_clk_src_array_id { 229 DCN303_CLK_SRC_PLL0, 230 DCN303_CLK_SRC_PLL1, 231 DCN303_CLK_SRC_TOTAL 232 }; 233 234 static const struct resource_caps res_cap_dcn303 = { 235 .num_timing_generator = 2, 236 .num_opp = 2, 237 .num_video_plane = 2, 238 .num_audio = 2, 239 .num_stream_encoder = 2, 240 .num_dwb = 1, 241 .num_ddc = 2, 242 .num_vmid = 16, 243 .num_mpc_3dlut = 1, 244 .num_dsc = 2, 245 }; 246 247 static const struct dc_plane_cap plane_cap = { 248 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 249 .blends_with_above = true, 250 .blends_with_below = true, 251 .per_pixel_alpha = true, 252 .pixel_format_support = { 253 .argb8888 = true, 254 .nv12 = true, 255 .fp16 = true, 256 .p010 = false, 257 .ayuv = false, 258 }, 259 .max_upscale_factor = { 260 .argb8888 = 16000, 261 .nv12 = 16000, 262 .fp16 = 16000 263 }, 264 .max_downscale_factor = { 265 .argb8888 = 600, 266 .nv12 = 600, 267 .fp16 = 600 268 }, 269 16, 270 16 271 }; 272 273 /* NBIO */ 274 #define NBIO_BASE_INNER(seg) \ 275 NBIO_BASE__INST0_SEG ## seg 276 277 #define NBIO_BASE(seg) \ 278 NBIO_BASE_INNER(seg) 279 280 #define NBIO_SR(reg_name)\ 281 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \ 282 mm ## reg_name 283 284 /* DCN */ 285 #undef BASE_INNER 286 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg 287 288 #define BASE(seg) BASE_INNER(seg) 289 290 #define SR(reg_name)\ 291 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name 292 293 #define SF(reg_name, field_name, post_fix)\ 294 .field_name = reg_name ## __ ## field_name ## post_fix 295 296 #define SRI(reg_name, block, id)\ 297 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + mm ## block ## id ## _ ## reg_name 298 299 #define SRI2(reg_name, block, id)\ 300 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name 301 302 #define SRII(reg_name, block, id)\ 303 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 304 mm ## block ## id ## _ ## reg_name 305 306 #define DCCG_SRII(reg_name, block, id)\ 307 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 308 mm ## block ## id ## _ ## reg_name 309 310 #define VUPDATE_SRII(reg_name, block, id)\ 311 .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \ 312 mm ## reg_name ## _ ## block ## id 313 314 #define SRII_DWB(reg_name, temp_name, block, id)\ 315 .reg_name[id] = BASE(mm ## block ## id ## _ ## temp_name ## _BASE_IDX) + \ 316 mm ## block ## id ## _ ## temp_name 317 318 #define SRII_MPC_RMU(reg_name, block, id)\ 319 .RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 320 mm ## block ## id ## _ ## reg_name 321 322 static const struct dcn_hubbub_registers hubbub_reg = { 323 HUBBUB_REG_LIST_DCN30(0) 324 }; 325 326 static const struct dcn_hubbub_shift hubbub_shift = { 327 HUBBUB_MASK_SH_LIST_DCN30(__SHIFT) 328 }; 329 330 static const struct dcn_hubbub_mask hubbub_mask = { 331 HUBBUB_MASK_SH_LIST_DCN30(_MASK) 332 }; 333 334 #define vmid_regs(id)\ 335 [id] = { DCN20_VMID_REG_LIST(id) } 336 337 static const struct dcn_vmid_registers vmid_regs[] = { 338 vmid_regs(0), 339 vmid_regs(1), 340 vmid_regs(2), 341 vmid_regs(3), 342 vmid_regs(4), 343 vmid_regs(5), 344 vmid_regs(6), 345 vmid_regs(7), 346 vmid_regs(8), 347 vmid_regs(9), 348 vmid_regs(10), 349 vmid_regs(11), 350 vmid_regs(12), 351 vmid_regs(13), 352 vmid_regs(14), 353 vmid_regs(15) 354 }; 355 356 static const struct dcn20_vmid_shift vmid_shifts = { 357 DCN20_VMID_MASK_SH_LIST(__SHIFT) 358 }; 359 360 static const struct dcn20_vmid_mask vmid_masks = { 361 DCN20_VMID_MASK_SH_LIST(_MASK) 362 }; 363 364 static struct hubbub *dcn303_hubbub_create(struct dc_context *ctx) 365 { 366 int i; 367 368 struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub), GFP_KERNEL); 369 370 if (!hubbub3) 371 return NULL; 372 373 hubbub3_construct(hubbub3, ctx, &hubbub_reg, &hubbub_shift, &hubbub_mask); 374 375 for (i = 0; i < res_cap_dcn303.num_vmid; i++) { 376 struct dcn20_vmid *vmid = &hubbub3->vmid[i]; 377 378 vmid->ctx = ctx; 379 380 vmid->regs = &vmid_regs[i]; 381 vmid->shifts = &vmid_shifts; 382 vmid->masks = &vmid_masks; 383 } 384 385 return &hubbub3->base; 386 } 387 388 #define vpg_regs(id)\ 389 [id] = { VPG_DCN3_REG_LIST(id) } 390 391 static const struct dcn30_vpg_registers vpg_regs[] = { 392 vpg_regs(0), 393 vpg_regs(1), 394 vpg_regs(2) 395 }; 396 397 static const struct dcn30_vpg_shift vpg_shift = { 398 DCN3_VPG_MASK_SH_LIST(__SHIFT) 399 }; 400 401 static const struct dcn30_vpg_mask vpg_mask = { 402 DCN3_VPG_MASK_SH_LIST(_MASK) 403 }; 404 405 static struct vpg *dcn303_vpg_create(struct dc_context *ctx, uint32_t inst) 406 { 407 struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL); 408 409 if (!vpg3) 410 return NULL; 411 412 vpg3_construct(vpg3, ctx, inst, &vpg_regs[inst], &vpg_shift, &vpg_mask); 413 414 return &vpg3->base; 415 } 416 417 #define afmt_regs(id)\ 418 [id] = { AFMT_DCN3_REG_LIST(id) } 419 420 static const struct dcn30_afmt_registers afmt_regs[] = { 421 afmt_regs(0), 422 afmt_regs(1), 423 afmt_regs(2) 424 }; 425 426 static const struct dcn30_afmt_shift afmt_shift = { 427 DCN3_AFMT_MASK_SH_LIST(__SHIFT) 428 }; 429 430 static const struct dcn30_afmt_mask afmt_mask = { 431 DCN3_AFMT_MASK_SH_LIST(_MASK) 432 }; 433 434 static struct afmt *dcn303_afmt_create(struct dc_context *ctx, uint32_t inst) 435 { 436 struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL); 437 438 if (!afmt3) 439 return NULL; 440 441 afmt3_construct(afmt3, ctx, inst, &afmt_regs[inst], &afmt_shift, &afmt_mask); 442 443 return &afmt3->base; 444 } 445 446 #define audio_regs(id)\ 447 [id] = { AUD_COMMON_REG_LIST(id) } 448 449 static const struct dce_audio_registers audio_regs[] = { 450 audio_regs(0), 451 audio_regs(1), 452 audio_regs(2), 453 audio_regs(3), 454 audio_regs(4), 455 audio_regs(5), 456 audio_regs(6) 457 }; 458 459 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 460 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 461 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 462 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 463 464 static const struct dce_audio_shift audio_shift = { 465 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 466 }; 467 468 static const struct dce_audio_mask audio_mask = { 469 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 470 }; 471 472 static struct audio *dcn303_create_audio(struct dc_context *ctx, unsigned int inst) 473 { 474 return dce_audio_create(ctx, inst, &audio_regs[inst], &audio_shift, &audio_mask); 475 } 476 477 #define stream_enc_regs(id)\ 478 [id] = { SE_DCN3_REG_LIST(id) } 479 480 static const struct dcn10_stream_enc_registers stream_enc_regs[] = { 481 stream_enc_regs(0), 482 stream_enc_regs(1) 483 }; 484 485 static const struct dcn10_stream_encoder_shift se_shift = { 486 SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 487 }; 488 489 static const struct dcn10_stream_encoder_mask se_mask = { 490 SE_COMMON_MASK_SH_LIST_DCN30(_MASK) 491 }; 492 493 static struct stream_encoder *dcn303_stream_encoder_create(enum engine_id eng_id, struct dc_context *ctx) 494 { 495 struct dcn10_stream_encoder *enc1; 496 struct vpg *vpg; 497 struct afmt *afmt; 498 int vpg_inst; 499 int afmt_inst; 500 501 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */ 502 if (eng_id <= ENGINE_ID_DIGE) { 503 vpg_inst = eng_id; 504 afmt_inst = eng_id; 505 } else 506 return NULL; 507 508 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 509 vpg = dcn303_vpg_create(ctx, vpg_inst); 510 afmt = dcn303_afmt_create(ctx, afmt_inst); 511 512 if (!enc1 || !vpg || !afmt) 513 return NULL; 514 515 dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id, vpg, afmt, &stream_enc_regs[eng_id], 516 &se_shift, &se_mask); 517 518 return &enc1->base; 519 } 520 521 #define clk_src_regs(index, pllid)\ 522 [index] = { CS_COMMON_REG_LIST_DCN3_03(index, pllid) } 523 524 static const struct dce110_clk_src_regs clk_src_regs[] = { 525 clk_src_regs(0, A), 526 clk_src_regs(1, B) 527 }; 528 529 static const struct dce110_clk_src_shift cs_shift = { 530 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 531 }; 532 533 static const struct dce110_clk_src_mask cs_mask = { 534 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 535 }; 536 537 static struct clock_source *dcn303_clock_source_create(struct dc_context *ctx, struct dc_bios *bios, 538 enum clock_source_id id, const struct dce110_clk_src_regs *regs, bool dp_clk_src) 539 { 540 struct dce110_clk_src *clk_src = kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 541 542 if (!clk_src) 543 return NULL; 544 545 if (dcn3_clk_src_construct(clk_src, ctx, bios, id, regs, &cs_shift, &cs_mask)) { 546 clk_src->base.dp_clk_src = dp_clk_src; 547 return &clk_src->base; 548 } 549 550 BREAK_TO_DEBUGGER(); 551 return NULL; 552 } 553 554 static const struct dce_hwseq_registers hwseq_reg = { 555 HWSEQ_DCN303_REG_LIST() 556 }; 557 558 static const struct dce_hwseq_shift hwseq_shift = { 559 HWSEQ_DCN303_MASK_SH_LIST(__SHIFT) 560 }; 561 562 static const struct dce_hwseq_mask hwseq_mask = { 563 HWSEQ_DCN303_MASK_SH_LIST(_MASK) 564 }; 565 566 static struct dce_hwseq *dcn303_hwseq_create(struct dc_context *ctx) 567 { 568 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 569 570 if (hws) { 571 hws->ctx = ctx; 572 hws->regs = &hwseq_reg; 573 hws->shifts = &hwseq_shift; 574 hws->masks = &hwseq_mask; 575 } 576 return hws; 577 } 578 579 #define hubp_regs(id)\ 580 [id] = { HUBP_REG_LIST_DCN30(id) } 581 582 static const struct dcn_hubp2_registers hubp_regs[] = { 583 hubp_regs(0), 584 hubp_regs(1) 585 }; 586 587 static const struct dcn_hubp2_shift hubp_shift = { 588 HUBP_MASK_SH_LIST_DCN30(__SHIFT) 589 }; 590 591 static const struct dcn_hubp2_mask hubp_mask = { 592 HUBP_MASK_SH_LIST_DCN30(_MASK) 593 }; 594 595 static struct hubp *dcn303_hubp_create(struct dc_context *ctx, uint32_t inst) 596 { 597 struct dcn20_hubp *hubp2 = kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL); 598 599 if (!hubp2) 600 return NULL; 601 602 if (hubp3_construct(hubp2, ctx, inst, &hubp_regs[inst], &hubp_shift, &hubp_mask)) 603 return &hubp2->base; 604 605 BREAK_TO_DEBUGGER(); 606 kfree(hubp2); 607 return NULL; 608 } 609 610 #define dpp_regs(id)\ 611 [id] = { DPP_REG_LIST_DCN30(id) } 612 613 static const struct dcn3_dpp_registers dpp_regs[] = { 614 dpp_regs(0), 615 dpp_regs(1) 616 }; 617 618 static const struct dcn3_dpp_shift tf_shift = { 619 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT) 620 }; 621 622 static const struct dcn3_dpp_mask tf_mask = { 623 DPP_REG_LIST_SH_MASK_DCN30(_MASK) 624 }; 625 626 static struct dpp *dcn303_dpp_create(struct dc_context *ctx, uint32_t inst) 627 { 628 struct dcn3_dpp *dpp = kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL); 629 630 if (!dpp) 631 return NULL; 632 633 if (dpp3_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, &tf_mask)) 634 return &dpp->base; 635 636 BREAK_TO_DEBUGGER(); 637 kfree(dpp); 638 return NULL; 639 } 640 641 #define opp_regs(id)\ 642 [id] = { OPP_REG_LIST_DCN30(id) } 643 644 static const struct dcn20_opp_registers opp_regs[] = { 645 opp_regs(0), 646 opp_regs(1) 647 }; 648 649 static const struct dcn20_opp_shift opp_shift = { 650 OPP_MASK_SH_LIST_DCN20(__SHIFT) 651 }; 652 653 static const struct dcn20_opp_mask opp_mask = { 654 OPP_MASK_SH_LIST_DCN20(_MASK) 655 }; 656 657 static struct output_pixel_processor *dcn303_opp_create(struct dc_context *ctx, uint32_t inst) 658 { 659 struct dcn20_opp *opp = kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); 660 661 if (!opp) { 662 BREAK_TO_DEBUGGER(); 663 return NULL; 664 } 665 666 dcn20_opp_construct(opp, ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask); 667 return &opp->base; 668 } 669 670 #define optc_regs(id)\ 671 [id] = { OPTC_COMMON_REG_LIST_DCN3_0(id) } 672 673 static const struct dcn_optc_registers optc_regs[] = { 674 optc_regs(0), 675 optc_regs(1) 676 }; 677 678 static const struct dcn_optc_shift optc_shift = { 679 OPTC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 680 }; 681 682 static const struct dcn_optc_mask optc_mask = { 683 OPTC_COMMON_MASK_SH_LIST_DCN30(_MASK) 684 }; 685 686 static struct timing_generator *dcn303_timing_generator_create(struct dc_context *ctx, uint32_t instance) 687 { 688 struct optc *tgn10 = kzalloc(sizeof(struct optc), GFP_KERNEL); 689 690 if (!tgn10) 691 return NULL; 692 693 tgn10->base.inst = instance; 694 tgn10->base.ctx = ctx; 695 696 tgn10->tg_regs = &optc_regs[instance]; 697 tgn10->tg_shift = &optc_shift; 698 tgn10->tg_mask = &optc_mask; 699 700 dcn30_timing_generator_init(tgn10); 701 702 return &tgn10->base; 703 } 704 705 static const struct dcn30_mpc_registers mpc_regs = { 706 MPC_REG_LIST_DCN3_0(0), 707 MPC_REG_LIST_DCN3_0(1), 708 MPC_OUT_MUX_REG_LIST_DCN3_0(0), 709 MPC_OUT_MUX_REG_LIST_DCN3_0(1), 710 MPC_RMU_GLOBAL_REG_LIST_DCN3AG, 711 MPC_RMU_REG_LIST_DCN3AG(0), 712 MPC_DWB_MUX_REG_LIST_DCN3_0(0), 713 }; 714 715 static const struct dcn30_mpc_shift mpc_shift = { 716 MPC_COMMON_MASK_SH_LIST_DCN303(__SHIFT) 717 }; 718 719 static const struct dcn30_mpc_mask mpc_mask = { 720 MPC_COMMON_MASK_SH_LIST_DCN303(_MASK) 721 }; 722 723 static struct mpc *dcn303_mpc_create(struct dc_context *ctx, int num_mpcc, int num_rmu) 724 { 725 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), GFP_KERNEL); 726 727 if (!mpc30) 728 return NULL; 729 730 dcn30_mpc_construct(mpc30, ctx, &mpc_regs, &mpc_shift, &mpc_mask, num_mpcc, num_rmu); 731 732 return &mpc30->base; 733 } 734 735 #define dsc_regsDCN20(id)\ 736 [id] = { DSC_REG_LIST_DCN20(id) } 737 738 static const struct dcn20_dsc_registers dsc_regs[] = { 739 dsc_regsDCN20(0), 740 dsc_regsDCN20(1) 741 }; 742 743 static const struct dcn20_dsc_shift dsc_shift = { 744 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) 745 }; 746 747 static const struct dcn20_dsc_mask dsc_mask = { 748 DSC_REG_LIST_SH_MASK_DCN20(_MASK) 749 }; 750 751 static struct display_stream_compressor *dcn303_dsc_create(struct dc_context *ctx, uint32_t inst) 752 { 753 struct dcn20_dsc *dsc = kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); 754 755 if (!dsc) { 756 BREAK_TO_DEBUGGER(); 757 return NULL; 758 } 759 760 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 761 return &dsc->base; 762 } 763 764 #define dwbc_regs_dcn3(id)\ 765 [id] = { DWBC_COMMON_REG_LIST_DCN30(id) } 766 767 static const struct dcn30_dwbc_registers dwbc30_regs[] = { 768 dwbc_regs_dcn3(0) 769 }; 770 771 static const struct dcn30_dwbc_shift dwbc30_shift = { 772 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 773 }; 774 775 static const struct dcn30_dwbc_mask dwbc30_mask = { 776 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK) 777 }; 778 779 static bool dcn303_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) 780 { 781 int i; 782 uint32_t pipe_count = pool->res_cap->num_dwb; 783 784 for (i = 0; i < pipe_count; i++) { 785 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), GFP_KERNEL); 786 787 if (!dwbc30) { 788 dm_error("DC: failed to create dwbc30!\n"); 789 return false; 790 } 791 792 dcn30_dwbc_construct(dwbc30, ctx, &dwbc30_regs[i], &dwbc30_shift, &dwbc30_mask, i); 793 794 pool->dwbc[i] = &dwbc30->base; 795 } 796 return true; 797 } 798 799 #define mcif_wb_regs_dcn3(id)\ 800 [id] = { MCIF_WB_COMMON_REG_LIST_DCN30(id) } 801 802 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = { 803 mcif_wb_regs_dcn3(0) 804 }; 805 806 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = { 807 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 808 }; 809 810 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { 811 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK) 812 }; 813 814 static bool dcn303_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) 815 { 816 int i; 817 uint32_t pipe_count = pool->res_cap->num_dwb; 818 819 for (i = 0; i < pipe_count; i++) { 820 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), GFP_KERNEL); 821 822 if (!mcif_wb30) { 823 dm_error("DC: failed to create mcif_wb30!\n"); 824 return false; 825 } 826 827 dcn30_mmhubbub_construct(mcif_wb30, ctx, &mcif_wb30_regs[i], &mcif_wb30_shift, &mcif_wb30_mask, i); 828 829 pool->mcif_wb[i] = &mcif_wb30->base; 830 } 831 return true; 832 } 833 834 #define aux_engine_regs(id)\ 835 [id] = {\ 836 AUX_COMMON_REG_LIST0(id), \ 837 .AUXN_IMPCAL = 0, \ 838 .AUXP_IMPCAL = 0, \ 839 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \ 840 } 841 842 static const struct dce110_aux_registers aux_engine_regs[] = { 843 aux_engine_regs(0), 844 aux_engine_regs(1) 845 }; 846 847 static const struct dce110_aux_registers_shift aux_shift = { 848 DCN_AUX_MASK_SH_LIST(__SHIFT) 849 }; 850 851 static const struct dce110_aux_registers_mask aux_mask = { 852 DCN_AUX_MASK_SH_LIST(_MASK) 853 }; 854 855 static struct dce_aux *dcn303_aux_engine_create(struct dc_context *ctx, uint32_t inst) 856 { 857 struct aux_engine_dce110 *aux_engine = kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 858 859 if (!aux_engine) 860 return NULL; 861 862 dce110_aux_engine_construct(aux_engine, ctx, inst, SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 863 &aux_engine_regs[inst], &aux_mask, &aux_shift, ctx->dc->caps.extended_aux_timeout_support); 864 865 return &aux_engine->base; 866 } 867 868 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 869 870 static const struct dce_i2c_registers i2c_hw_regs[] = { 871 i2c_inst_regs(1), 872 i2c_inst_regs(2) 873 }; 874 875 static const struct dce_i2c_shift i2c_shifts = { 876 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT) 877 }; 878 879 static const struct dce_i2c_mask i2c_masks = { 880 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK) 881 }; 882 883 static struct dce_i2c_hw *dcn303_i2c_hw_create(struct dc_context *ctx, uint32_t inst) 884 { 885 struct dce_i2c_hw *dce_i2c_hw = kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 886 887 if (!dce_i2c_hw) 888 return NULL; 889 890 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 891 892 return dce_i2c_hw; 893 } 894 895 static const struct encoder_feature_support link_enc_feature = { 896 .max_hdmi_deep_color = COLOR_DEPTH_121212, 897 .max_hdmi_pixel_clock = 600000, 898 .hdmi_ycbcr420_supported = true, 899 .dp_ycbcr420_supported = true, 900 .fec_supported = true, 901 .flags.bits.IS_HBR2_CAPABLE = true, 902 .flags.bits.IS_HBR3_CAPABLE = true, 903 .flags.bits.IS_TPS3_CAPABLE = true, 904 .flags.bits.IS_TPS4_CAPABLE = true 905 }; 906 907 #define link_regs(id, phyid)\ 908 [id] = {\ 909 LE_DCN3_REG_LIST(id), \ 910 UNIPHY_DCN2_REG_LIST(phyid), \ 911 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \ 912 } 913 914 static const struct dcn10_link_enc_registers link_enc_regs[] = { 915 link_regs(0, A), 916 link_regs(1, B) 917 }; 918 919 static const struct dcn10_link_enc_shift le_shift = { 920 LINK_ENCODER_MASK_SH_LIST_DCN30(__SHIFT), 921 DPCS_DCN2_MASK_SH_LIST(__SHIFT) 922 }; 923 924 static const struct dcn10_link_enc_mask le_mask = { 925 LINK_ENCODER_MASK_SH_LIST_DCN30(_MASK), 926 DPCS_DCN2_MASK_SH_LIST(_MASK) 927 }; 928 929 #define aux_regs(id)\ 930 [id] = { DCN2_AUX_REG_LIST(id) } 931 932 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { 933 aux_regs(0), 934 aux_regs(1) 935 }; 936 937 #define hpd_regs(id)\ 938 [id] = { HPD_REG_LIST(id) } 939 940 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { 941 hpd_regs(0), 942 hpd_regs(1) 943 }; 944 945 static struct link_encoder *dcn303_link_encoder_create(const struct encoder_init_data *enc_init_data) 946 { 947 struct dcn20_link_encoder *enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 948 949 if (!enc20) 950 return NULL; 951 952 dcn30_link_encoder_construct(enc20, enc_init_data, &link_enc_feature, 953 &link_enc_regs[enc_init_data->transmitter], &link_enc_aux_regs[enc_init_data->channel - 1], 954 &link_enc_hpd_regs[enc_init_data->hpd_source], &le_shift, &le_mask); 955 956 return &enc20->enc10.base; 957 } 958 959 static const struct dce_panel_cntl_registers panel_cntl_regs[] = { 960 { DCN_PANEL_CNTL_REG_LIST() } 961 }; 962 963 static const struct dce_panel_cntl_shift panel_cntl_shift = { 964 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT) 965 }; 966 967 static const struct dce_panel_cntl_mask panel_cntl_mask = { 968 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK) 969 }; 970 971 static struct panel_cntl *dcn303_panel_cntl_create(const struct panel_cntl_init_data *init_data) 972 { 973 struct dce_panel_cntl *panel_cntl = kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL); 974 975 if (!panel_cntl) 976 return NULL; 977 978 dce_panel_cntl_construct(panel_cntl, init_data, &panel_cntl_regs[init_data->inst], 979 &panel_cntl_shift, &panel_cntl_mask); 980 981 return &panel_cntl->base; 982 } 983 984 static void read_dce_straps(struct dc_context *ctx, struct resource_straps *straps) 985 { 986 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX), 987 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 988 } 989 990 static const struct resource_create_funcs res_create_funcs = { 991 .read_dce_straps = read_dce_straps, 992 .create_audio = dcn303_create_audio, 993 .create_stream_encoder = dcn303_stream_encoder_create, 994 .create_hwseq = dcn303_hwseq_create, 995 }; 996 997 static const struct resource_create_funcs res_create_maximus_funcs = { 998 .read_dce_straps = NULL, 999 .create_audio = NULL, 1000 .create_stream_encoder = NULL, 1001 .create_hwseq = dcn303_hwseq_create, 1002 }; 1003 1004 static bool is_soc_bounding_box_valid(struct dc *dc) 1005 { 1006 uint32_t hw_internal_rev = dc->ctx->asic_id.hw_internal_rev; 1007 1008 if (ASICREV_IS_BEIGE_GOBY_P(hw_internal_rev)) 1009 return true; 1010 1011 return false; 1012 } 1013 1014 static bool init_soc_bounding_box(struct dc *dc, struct resource_pool *pool) 1015 { 1016 struct _vcs_dpi_soc_bounding_box_st *loaded_bb = &dcn3_03_soc; 1017 struct _vcs_dpi_ip_params_st *loaded_ip = &dcn3_03_ip; 1018 1019 DC_LOGGER_INIT(dc->ctx->logger); 1020 1021 if (!is_soc_bounding_box_valid(dc)) { 1022 DC_LOG_ERROR("%s: not valid soc bounding box/n", __func__); 1023 return false; 1024 } 1025 1026 loaded_ip->max_num_otg = pool->pipe_count; 1027 loaded_ip->max_num_dpp = pool->pipe_count; 1028 loaded_ip->clamp_min_dcfclk = dc->config.clamp_min_dcfclk; 1029 dcn20_patch_bounding_box(dc, loaded_bb); 1030 return true; 1031 } 1032 1033 static void dcn303_resource_destruct(struct resource_pool *pool) 1034 { 1035 unsigned int i; 1036 1037 for (i = 0; i < pool->stream_enc_count; i++) { 1038 if (pool->stream_enc[i] != NULL) { 1039 if (pool->stream_enc[i]->vpg != NULL) { 1040 kfree(DCN30_VPG_FROM_VPG(pool->stream_enc[i]->vpg)); 1041 pool->stream_enc[i]->vpg = NULL; 1042 } 1043 if (pool->stream_enc[i]->afmt != NULL) { 1044 kfree(DCN30_AFMT_FROM_AFMT(pool->stream_enc[i]->afmt)); 1045 pool->stream_enc[i]->afmt = NULL; 1046 } 1047 kfree(DCN10STRENC_FROM_STRENC(pool->stream_enc[i])); 1048 pool->stream_enc[i] = NULL; 1049 } 1050 } 1051 1052 for (i = 0; i < pool->res_cap->num_dsc; i++) { 1053 if (pool->dscs[i] != NULL) 1054 dcn20_dsc_destroy(&pool->dscs[i]); 1055 } 1056 1057 if (pool->mpc != NULL) { 1058 kfree(TO_DCN20_MPC(pool->mpc)); 1059 pool->mpc = NULL; 1060 } 1061 1062 if (pool->hubbub != NULL) { 1063 kfree(pool->hubbub); 1064 pool->hubbub = NULL; 1065 } 1066 1067 for (i = 0; i < pool->pipe_count; i++) { 1068 if (pool->dpps[i] != NULL) { 1069 kfree(TO_DCN20_DPP(pool->dpps[i])); 1070 pool->dpps[i] = NULL; 1071 } 1072 1073 if (pool->hubps[i] != NULL) { 1074 kfree(TO_DCN20_HUBP(pool->hubps[i])); 1075 pool->hubps[i] = NULL; 1076 } 1077 1078 if (pool->irqs != NULL) 1079 dal_irq_service_destroy(&pool->irqs); 1080 } 1081 1082 for (i = 0; i < pool->res_cap->num_ddc; i++) { 1083 if (pool->engines[i] != NULL) 1084 dce110_engine_destroy(&pool->engines[i]); 1085 if (pool->hw_i2cs[i] != NULL) { 1086 kfree(pool->hw_i2cs[i]); 1087 pool->hw_i2cs[i] = NULL; 1088 } 1089 if (pool->sw_i2cs[i] != NULL) { 1090 kfree(pool->sw_i2cs[i]); 1091 pool->sw_i2cs[i] = NULL; 1092 } 1093 } 1094 1095 for (i = 0; i < pool->res_cap->num_opp; i++) { 1096 if (pool->opps[i] != NULL) 1097 pool->opps[i]->funcs->opp_destroy(&pool->opps[i]); 1098 } 1099 1100 for (i = 0; i < pool->res_cap->num_timing_generator; i++) { 1101 if (pool->timing_generators[i] != NULL) { 1102 kfree(DCN10TG_FROM_TG(pool->timing_generators[i])); 1103 pool->timing_generators[i] = NULL; 1104 } 1105 } 1106 1107 for (i = 0; i < pool->res_cap->num_dwb; i++) { 1108 if (pool->dwbc[i] != NULL) { 1109 kfree(TO_DCN30_DWBC(pool->dwbc[i])); 1110 pool->dwbc[i] = NULL; 1111 } 1112 if (pool->mcif_wb[i] != NULL) { 1113 kfree(TO_DCN30_MMHUBBUB(pool->mcif_wb[i])); 1114 pool->mcif_wb[i] = NULL; 1115 } 1116 } 1117 1118 for (i = 0; i < pool->audio_count; i++) { 1119 if (pool->audios[i]) 1120 dce_aud_destroy(&pool->audios[i]); 1121 } 1122 1123 for (i = 0; i < pool->clk_src_count; i++) { 1124 if (pool->clock_sources[i] != NULL) 1125 dcn20_clock_source_destroy(&pool->clock_sources[i]); 1126 } 1127 1128 if (pool->dp_clock_source != NULL) 1129 dcn20_clock_source_destroy(&pool->dp_clock_source); 1130 1131 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { 1132 if (pool->mpc_lut[i] != NULL) { 1133 dc_3dlut_func_release(pool->mpc_lut[i]); 1134 pool->mpc_lut[i] = NULL; 1135 } 1136 if (pool->mpc_shaper[i] != NULL) { 1137 dc_transfer_func_release(pool->mpc_shaper[i]); 1138 pool->mpc_shaper[i] = NULL; 1139 } 1140 } 1141 1142 for (i = 0; i < pool->pipe_count; i++) { 1143 if (pool->multiple_abms[i] != NULL) 1144 dce_abm_destroy(&pool->multiple_abms[i]); 1145 } 1146 1147 if (pool->psr != NULL) 1148 dmub_psr_destroy(&pool->psr); 1149 1150 if (pool->dccg != NULL) 1151 dcn_dccg_destroy(&pool->dccg); 1152 1153 if (pool->oem_device != NULL) 1154 dal_ddc_service_destroy(&pool->oem_device); 1155 } 1156 1157 static void dcn303_destroy_resource_pool(struct resource_pool **pool) 1158 { 1159 dcn303_resource_destruct(*pool); 1160 kfree(*pool); 1161 *pool = NULL; 1162 } 1163 1164 static void dcn303_get_optimal_dcfclk_fclk_for_uclk(unsigned int uclk_mts, 1165 unsigned int *optimal_dcfclk, 1166 unsigned int *optimal_fclk) 1167 { 1168 double bw_from_dram, bw_from_dram1, bw_from_dram2; 1169 1170 bw_from_dram1 = uclk_mts * dcn3_03_soc.num_chans * 1171 dcn3_03_soc.dram_channel_width_bytes * (dcn3_03_soc.max_avg_dram_bw_use_normal_percent / 100); 1172 bw_from_dram2 = uclk_mts * dcn3_03_soc.num_chans * 1173 dcn3_03_soc.dram_channel_width_bytes * (dcn3_03_soc.max_avg_sdp_bw_use_normal_percent / 100); 1174 1175 bw_from_dram = (bw_from_dram1 < bw_from_dram2) ? bw_from_dram1 : bw_from_dram2; 1176 1177 if (optimal_fclk) 1178 *optimal_fclk = bw_from_dram / 1179 (dcn3_03_soc.fabric_datapath_to_dcn_data_return_bytes * 1180 (dcn3_03_soc.max_avg_sdp_bw_use_normal_percent / 100)); 1181 1182 if (optimal_dcfclk) 1183 *optimal_dcfclk = bw_from_dram / 1184 (dcn3_03_soc.return_bus_width_bytes * (dcn3_03_soc.max_avg_sdp_bw_use_normal_percent / 100)); 1185 } 1186 1187 void dcn303_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) 1188 { 1189 unsigned int i, j; 1190 unsigned int num_states = 0; 1191 1192 unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0}; 1193 unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0}; 1194 unsigned int optimal_uclk_for_dcfclk_sta_targets[DC__VOLTAGE_STATES] = {0}; 1195 unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0}; 1196 1197 unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {694, 875, 1000, 1200}; 1198 unsigned int num_dcfclk_sta_targets = 4; 1199 unsigned int num_uclk_states; 1200 1201 1202 if (dc->ctx->dc_bios->vram_info.num_chans) 1203 dcn3_03_soc.num_chans = dc->ctx->dc_bios->vram_info.num_chans; 1204 1205 if (dc->ctx->dc_bios->vram_info.dram_channel_width_bytes) 1206 dcn3_03_soc.dram_channel_width_bytes = dc->ctx->dc_bios->vram_info.dram_channel_width_bytes; 1207 1208 dcn3_03_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0; 1209 dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0; 1210 1211 if (bw_params->clk_table.entries[0].memclk_mhz) { 1212 int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0, max_phyclk_mhz = 0; 1213 1214 for (i = 0; i < MAX_NUM_DPM_LVL; i++) { 1215 if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz) 1216 max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; 1217 if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz) 1218 max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz; 1219 if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz) 1220 max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz; 1221 if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz) 1222 max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz; 1223 } 1224 if (!max_dcfclk_mhz) 1225 max_dcfclk_mhz = dcn3_03_soc.clock_limits[0].dcfclk_mhz; 1226 if (!max_dispclk_mhz) 1227 max_dispclk_mhz = dcn3_03_soc.clock_limits[0].dispclk_mhz; 1228 if (!max_dppclk_mhz) 1229 max_dppclk_mhz = dcn3_03_soc.clock_limits[0].dppclk_mhz; 1230 if (!max_phyclk_mhz) 1231 max_phyclk_mhz = dcn3_03_soc.clock_limits[0].phyclk_mhz; 1232 1233 if (max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { 1234 dcfclk_sta_targets[num_dcfclk_sta_targets] = max_dcfclk_mhz; 1235 num_dcfclk_sta_targets++; 1236 } else if (max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { 1237 for (i = 0; i < num_dcfclk_sta_targets; i++) { 1238 if (dcfclk_sta_targets[i] > max_dcfclk_mhz) { 1239 dcfclk_sta_targets[i] = max_dcfclk_mhz; 1240 break; 1241 } 1242 } 1243 /* Update size of array since we "removed" duplicates */ 1244 num_dcfclk_sta_targets = i + 1; 1245 } 1246 1247 num_uclk_states = bw_params->clk_table.num_entries; 1248 1249 /* Calculate optimal dcfclk for each uclk */ 1250 for (i = 0; i < num_uclk_states; i++) { 1251 dcn303_get_optimal_dcfclk_fclk_for_uclk(bw_params->clk_table.entries[i].memclk_mhz * 16, 1252 &optimal_dcfclk_for_uclk[i], NULL); 1253 if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz) 1254 optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz; 1255 } 1256 1257 /* Calculate optimal uclk for each dcfclk sta target */ 1258 for (i = 0; i < num_dcfclk_sta_targets; i++) { 1259 for (j = 0; j < num_uclk_states; j++) { 1260 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) { 1261 optimal_uclk_for_dcfclk_sta_targets[i] = 1262 bw_params->clk_table.entries[j].memclk_mhz * 16; 1263 break; 1264 } 1265 } 1266 } 1267 1268 i = 0; 1269 j = 0; 1270 /* create the final dcfclk and uclk table */ 1271 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { 1272 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) { 1273 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; 1274 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; 1275 } else { 1276 if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) { 1277 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; 1278 dram_speed_mts[num_states++] = 1279 bw_params->clk_table.entries[j++].memclk_mhz * 16; 1280 } else { 1281 j = num_uclk_states; 1282 } 1283 } 1284 } 1285 1286 while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) { 1287 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; 1288 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; 1289 } 1290 1291 while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES && 1292 optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) { 1293 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; 1294 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16; 1295 } 1296 1297 dcn3_03_soc.num_states = num_states; 1298 for (i = 0; i < dcn3_03_soc.num_states; i++) { 1299 dcn3_03_soc.clock_limits[i].state = i; 1300 dcn3_03_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i]; 1301 dcn3_03_soc.clock_limits[i].fabricclk_mhz = dcfclk_mhz[i]; 1302 dcn3_03_soc.clock_limits[i].dram_speed_mts = dram_speed_mts[i]; 1303 1304 /* Fill all states with max values of all other clocks */ 1305 dcn3_03_soc.clock_limits[i].dispclk_mhz = max_dispclk_mhz; 1306 dcn3_03_soc.clock_limits[i].dppclk_mhz = max_dppclk_mhz; 1307 dcn3_03_soc.clock_limits[i].phyclk_mhz = max_phyclk_mhz; 1308 dcn3_03_soc.clock_limits[i].dtbclk_mhz = dcn3_03_soc.clock_limits[0].dtbclk_mhz; 1309 /* These clocks cannot come from bw_params, always fill from dcn3_03_soc[1] */ 1310 /* FCLK, PHYCLK_D18, SOCCLK, DSCCLK */ 1311 dcn3_03_soc.clock_limits[i].phyclk_d18_mhz = dcn3_03_soc.clock_limits[0].phyclk_d18_mhz; 1312 dcn3_03_soc.clock_limits[i].socclk_mhz = dcn3_03_soc.clock_limits[0].socclk_mhz; 1313 dcn3_03_soc.clock_limits[i].dscclk_mhz = dcn3_03_soc.clock_limits[0].dscclk_mhz; 1314 } 1315 /* re-init DML with updated bb */ 1316 dml_init_instance(&dc->dml, &dcn3_03_soc, &dcn3_03_ip, DML_PROJECT_DCN30); 1317 if (dc->current_state) 1318 dml_init_instance(&dc->current_state->bw_ctx.dml, &dcn3_03_soc, &dcn3_03_ip, DML_PROJECT_DCN30); 1319 } 1320 } 1321 1322 static struct resource_funcs dcn303_res_pool_funcs = { 1323 .destroy = dcn303_destroy_resource_pool, 1324 .link_enc_create = dcn303_link_encoder_create, 1325 .panel_cntl_create = dcn303_panel_cntl_create, 1326 .validate_bandwidth = dcn30_validate_bandwidth, 1327 .calculate_wm_and_dlg = dcn30_calculate_wm_and_dlg, 1328 .update_soc_for_wm_a = dcn30_update_soc_for_wm_a, 1329 .populate_dml_pipes = dcn30_populate_dml_pipes_from_context, 1330 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer, 1331 .add_stream_to_ctx = dcn30_add_stream_to_ctx, 1332 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, 1333 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 1334 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, 1335 .set_mcif_arb_params = dcn30_set_mcif_arb_params, 1336 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, 1337 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut, 1338 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut, 1339 .update_bw_bounding_box = dcn303_update_bw_bounding_box, 1340 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, 1341 }; 1342 1343 static struct dc_cap_funcs cap_funcs = { 1344 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap 1345 }; 1346 1347 static const struct bios_registers bios_regs = { 1348 NBIO_SR(BIOS_SCRATCH_3), 1349 NBIO_SR(BIOS_SCRATCH_6) 1350 }; 1351 1352 static const struct dccg_registers dccg_regs = { 1353 DCCG_REG_LIST_DCN3_03() 1354 }; 1355 1356 static const struct dccg_shift dccg_shift = { 1357 DCCG_MASK_SH_LIST_DCN3_03(__SHIFT) 1358 }; 1359 1360 static const struct dccg_mask dccg_mask = { 1361 DCCG_MASK_SH_LIST_DCN3_03(_MASK) 1362 }; 1363 1364 #define abm_regs(id)\ 1365 [id] = { ABM_DCN301_REG_LIST(id) } 1366 1367 static const struct dce_abm_registers abm_regs[] = { 1368 abm_regs(0), 1369 abm_regs(1) 1370 }; 1371 1372 static const struct dce_abm_shift abm_shift = { 1373 ABM_MASK_SH_LIST_DCN30(__SHIFT) 1374 }; 1375 1376 static const struct dce_abm_mask abm_mask = { 1377 ABM_MASK_SH_LIST_DCN30(_MASK) 1378 }; 1379 1380 static bool dcn303_resource_construct( 1381 uint8_t num_virtual_links, 1382 struct dc *dc, 1383 struct resource_pool *pool) 1384 { 1385 int i; 1386 struct dc_context *ctx = dc->ctx; 1387 struct irq_service_init_data init_data; 1388 struct ddc_service_init_data ddc_init_data; 1389 1390 ctx->dc_bios->regs = &bios_regs; 1391 1392 pool->res_cap = &res_cap_dcn303; 1393 1394 pool->funcs = &dcn303_res_pool_funcs; 1395 1396 /************************************************* 1397 * Resource + asic cap harcoding * 1398 *************************************************/ 1399 pool->underlay_pipe_index = NO_UNDERLAY_PIPE; 1400 pool->pipe_count = pool->res_cap->num_timing_generator; 1401 pool->mpcc_count = pool->res_cap->num_timing_generator; 1402 dc->caps.max_downscale_ratio = 600; 1403 dc->caps.i2c_speed_in_khz = 100; 1404 dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by derfault*/ 1405 dc->caps.max_cursor_size = 256; 1406 dc->caps.min_horizontal_blanking_period = 80; 1407 dc->caps.dmdata_alloc_size = 2048; 1408 #if defined(CONFIG_DRM_AMD_DC_DCN) 1409 dc->caps.mall_size_per_mem_channel = 4; 1410 /* total size = mall per channel * num channels * 1024 * 1024 */ 1411 dc->caps.mall_size_total = dc->caps.mall_size_per_mem_channel * 1412 dc->ctx->dc_bios->vram_info.num_chans * 1413 1024 * 1024; 1414 dc->caps.cursor_cache_size = 1415 dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8; 1416 #endif 1417 dc->caps.max_slave_planes = 1; 1418 dc->caps.post_blend_color_processing = true; 1419 dc->caps.force_dp_tps4_for_cp2520 = true; 1420 dc->caps.extended_aux_timeout_support = true; 1421 dc->caps.dmcub_support = true; 1422 1423 /* Color pipeline capabilities */ 1424 dc->caps.color.dpp.dcn_arch = 1; 1425 dc->caps.color.dpp.input_lut_shared = 0; 1426 dc->caps.color.dpp.icsc = 1; 1427 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr 1428 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; 1429 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; 1430 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1; 1431 dc->caps.color.dpp.dgam_rom_caps.pq = 1; 1432 dc->caps.color.dpp.dgam_rom_caps.hlg = 1; 1433 dc->caps.color.dpp.post_csc = 1; 1434 dc->caps.color.dpp.gamma_corr = 1; 1435 dc->caps.color.dpp.dgam_rom_for_yuv = 0; 1436 1437 dc->caps.color.dpp.hw_3d_lut = 1; 1438 dc->caps.color.dpp.ogam_ram = 1; 1439 // no OGAM ROM on DCN3 1440 dc->caps.color.dpp.ogam_rom_caps.srgb = 0; 1441 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; 1442 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; 1443 dc->caps.color.dpp.ogam_rom_caps.pq = 0; 1444 dc->caps.color.dpp.ogam_rom_caps.hlg = 0; 1445 dc->caps.color.dpp.ocsc = 0; 1446 1447 dc->caps.color.mpc.gamut_remap = 1; 1448 dc->caps.color.mpc.num_3dluts = pool->res_cap->num_mpc_3dlut; //3 1449 dc->caps.color.mpc.ogam_ram = 1; 1450 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; 1451 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; 1452 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; 1453 dc->caps.color.mpc.ogam_rom_caps.pq = 0; 1454 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 1455 dc->caps.color.mpc.ocsc = 1; 1456 1457 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 1458 dc->debug = debug_defaults_drv; 1459 else 1460 dc->debug = debug_defaults_diags; 1461 1462 // Init the vm_helper 1463 if (dc->vm_helper) 1464 vm_helper_init(dc->vm_helper, 16); 1465 1466 /************************************************* 1467 * Create resources * 1468 *************************************************/ 1469 1470 /* Clock Sources for Pixel Clock*/ 1471 pool->clock_sources[DCN303_CLK_SRC_PLL0] = 1472 dcn303_clock_source_create(ctx, ctx->dc_bios, 1473 CLOCK_SOURCE_COMBO_PHY_PLL0, 1474 &clk_src_regs[0], false); 1475 pool->clock_sources[DCN303_CLK_SRC_PLL1] = 1476 dcn303_clock_source_create(ctx, ctx->dc_bios, 1477 CLOCK_SOURCE_COMBO_PHY_PLL1, 1478 &clk_src_regs[1], false); 1479 1480 pool->clk_src_count = DCN303_CLK_SRC_TOTAL; 1481 1482 /* todo: not reuse phy_pll registers */ 1483 pool->dp_clock_source = 1484 dcn303_clock_source_create(ctx, ctx->dc_bios, 1485 CLOCK_SOURCE_ID_DP_DTO, 1486 &clk_src_regs[0], true); 1487 1488 for (i = 0; i < pool->clk_src_count; i++) { 1489 if (pool->clock_sources[i] == NULL) { 1490 dm_error("DC: failed to create clock sources!\n"); 1491 BREAK_TO_DEBUGGER(); 1492 goto create_fail; 1493 } 1494 } 1495 1496 /* DCCG */ 1497 pool->dccg = dccg30_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 1498 if (pool->dccg == NULL) { 1499 dm_error("DC: failed to create dccg!\n"); 1500 BREAK_TO_DEBUGGER(); 1501 goto create_fail; 1502 } 1503 1504 /* PP Lib and SMU interfaces */ 1505 init_soc_bounding_box(dc, pool); 1506 1507 /* DML */ 1508 dml_init_instance(&dc->dml, &dcn3_03_soc, &dcn3_03_ip, DML_PROJECT_DCN30); 1509 1510 /* IRQ */ 1511 init_data.ctx = dc->ctx; 1512 pool->irqs = dal_irq_service_dcn303_create(&init_data); 1513 if (!pool->irqs) 1514 goto create_fail; 1515 1516 /* HUBBUB */ 1517 pool->hubbub = dcn303_hubbub_create(ctx); 1518 if (pool->hubbub == NULL) { 1519 BREAK_TO_DEBUGGER(); 1520 dm_error("DC: failed to create hubbub!\n"); 1521 goto create_fail; 1522 } 1523 1524 /* HUBPs, DPPs, OPPs and TGs */ 1525 for (i = 0; i < pool->pipe_count; i++) { 1526 pool->hubps[i] = dcn303_hubp_create(ctx, i); 1527 if (pool->hubps[i] == NULL) { 1528 BREAK_TO_DEBUGGER(); 1529 dm_error("DC: failed to create hubps!\n"); 1530 goto create_fail; 1531 } 1532 1533 pool->dpps[i] = dcn303_dpp_create(ctx, i); 1534 if (pool->dpps[i] == NULL) { 1535 BREAK_TO_DEBUGGER(); 1536 dm_error("DC: failed to create dpps!\n"); 1537 goto create_fail; 1538 } 1539 } 1540 1541 for (i = 0; i < pool->res_cap->num_opp; i++) { 1542 pool->opps[i] = dcn303_opp_create(ctx, i); 1543 if (pool->opps[i] == NULL) { 1544 BREAK_TO_DEBUGGER(); 1545 dm_error("DC: failed to create output pixel processor!\n"); 1546 goto create_fail; 1547 } 1548 } 1549 1550 for (i = 0; i < pool->res_cap->num_timing_generator; i++) { 1551 pool->timing_generators[i] = dcn303_timing_generator_create(ctx, i); 1552 if (pool->timing_generators[i] == NULL) { 1553 BREAK_TO_DEBUGGER(); 1554 dm_error("DC: failed to create tg!\n"); 1555 goto create_fail; 1556 } 1557 } 1558 pool->timing_generator_count = i; 1559 1560 /* PSR */ 1561 pool->psr = dmub_psr_create(ctx); 1562 if (pool->psr == NULL) { 1563 dm_error("DC: failed to create psr!\n"); 1564 BREAK_TO_DEBUGGER(); 1565 goto create_fail; 1566 } 1567 1568 /* ABM */ 1569 for (i = 0; i < pool->res_cap->num_timing_generator; i++) { 1570 pool->multiple_abms[i] = dmub_abm_create(ctx, &abm_regs[i], &abm_shift, &abm_mask); 1571 if (pool->multiple_abms[i] == NULL) { 1572 dm_error("DC: failed to create abm for pipe %d!\n", i); 1573 BREAK_TO_DEBUGGER(); 1574 goto create_fail; 1575 } 1576 } 1577 1578 /* MPC and DSC */ 1579 pool->mpc = dcn303_mpc_create(ctx, pool->mpcc_count, pool->res_cap->num_mpc_3dlut); 1580 if (pool->mpc == NULL) { 1581 BREAK_TO_DEBUGGER(); 1582 dm_error("DC: failed to create mpc!\n"); 1583 goto create_fail; 1584 } 1585 1586 for (i = 0; i < pool->res_cap->num_dsc; i++) { 1587 pool->dscs[i] = dcn303_dsc_create(ctx, i); 1588 if (pool->dscs[i] == NULL) { 1589 BREAK_TO_DEBUGGER(); 1590 dm_error("DC: failed to create display stream compressor %d!\n", i); 1591 goto create_fail; 1592 } 1593 } 1594 1595 /* DWB and MMHUBBUB */ 1596 if (!dcn303_dwbc_create(ctx, pool)) { 1597 BREAK_TO_DEBUGGER(); 1598 dm_error("DC: failed to create dwbc!\n"); 1599 goto create_fail; 1600 } 1601 1602 if (!dcn303_mmhubbub_create(ctx, pool)) { 1603 BREAK_TO_DEBUGGER(); 1604 dm_error("DC: failed to create mcif_wb!\n"); 1605 goto create_fail; 1606 } 1607 1608 /* AUX and I2C */ 1609 for (i = 0; i < pool->res_cap->num_ddc; i++) { 1610 pool->engines[i] = dcn303_aux_engine_create(ctx, i); 1611 if (pool->engines[i] == NULL) { 1612 BREAK_TO_DEBUGGER(); 1613 dm_error("DC:failed to create aux engine!!\n"); 1614 goto create_fail; 1615 } 1616 pool->hw_i2cs[i] = dcn303_i2c_hw_create(ctx, i); 1617 if (pool->hw_i2cs[i] == NULL) { 1618 BREAK_TO_DEBUGGER(); 1619 dm_error("DC:failed to create hw i2c!!\n"); 1620 goto create_fail; 1621 } 1622 pool->sw_i2cs[i] = NULL; 1623 } 1624 1625 /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */ 1626 if (!resource_construct(num_virtual_links, dc, pool, 1627 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? 1628 &res_create_funcs : &res_create_maximus_funcs))) 1629 goto create_fail; 1630 1631 /* HW Sequencer and Plane caps */ 1632 dcn303_hw_sequencer_construct(dc); 1633 1634 dc->caps.max_planes = pool->pipe_count; 1635 1636 for (i = 0; i < dc->caps.max_planes; ++i) 1637 dc->caps.planes[i] = plane_cap; 1638 1639 dc->cap_funcs = cap_funcs; 1640 1641 if (dc->ctx->dc_bios->fw_info.oem_i2c_present) { 1642 ddc_init_data.ctx = dc->ctx; 1643 ddc_init_data.link = NULL; 1644 ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id; 1645 ddc_init_data.id.enum_id = 0; 1646 ddc_init_data.id.type = OBJECT_TYPE_GENERIC; 1647 pool->oem_device = dal_ddc_service_create(&ddc_init_data); 1648 } else { 1649 pool->oem_device = NULL; 1650 } 1651 1652 return true; 1653 1654 create_fail: 1655 1656 dcn303_resource_destruct(pool); 1657 1658 return false; 1659 } 1660 1661 struct resource_pool *dcn303_create_resource_pool(const struct dc_init_data *init_data, struct dc *dc) 1662 { 1663 struct resource_pool *pool = kzalloc(sizeof(struct resource_pool), GFP_KERNEL); 1664 1665 if (!pool) 1666 return NULL; 1667 1668 if (dcn303_resource_construct(init_data->num_virtual_links, dc, pool)) 1669 return pool; 1670 1671 BREAK_TO_DEBUGGER(); 1672 kfree(pool); 1673 return NULL; 1674 } 1675