1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright (C) 2021 Advanced Micro Devices, Inc. 4 * 5 * Authors: AMD 6 */ 7 8 #include "dcn303_init.h" 9 #include "dcn303_resource.h" 10 #include "dcn303_dccg.h" 11 #include "irq/dcn303/irq_service_dcn303.h" 12 13 #include "dcn30/dcn30_dio_link_encoder.h" 14 #include "dcn30/dcn30_dio_stream_encoder.h" 15 #include "dcn30/dcn30_dpp.h" 16 #include "dcn30/dcn30_dwb.h" 17 #include "dcn30/dcn30_hubbub.h" 18 #include "dcn30/dcn30_hubp.h" 19 #include "dcn30/dcn30_mmhubbub.h" 20 #include "dcn30/dcn30_mpc.h" 21 #include "dcn30/dcn30_opp.h" 22 #include "dcn30/dcn30_optc.h" 23 #include "dcn30/dcn30_resource.h" 24 25 #include "dcn20/dcn20_dsc.h" 26 #include "dcn20/dcn20_resource.h" 27 28 #include "dml/dcn30/dcn30_fpu.h" 29 30 #include "dcn10/dcn10_resource.h" 31 32 #include "link.h" 33 34 #include "dce/dce_abm.h" 35 #include "dce/dce_audio.h" 36 #include "dce/dce_aux.h" 37 #include "dce/dce_clock_source.h" 38 #include "dce/dce_hwseq.h" 39 #include "dce/dce_i2c_hw.h" 40 #include "dce/dce_panel_cntl.h" 41 #include "dce/dmub_abm.h" 42 #include "dce/dmub_psr.h" 43 #include "clk_mgr.h" 44 45 #include "hw_sequencer_private.h" 46 #include "reg_helper.h" 47 #include "resource.h" 48 #include "vm_helper.h" 49 50 #include "sienna_cichlid_ip_offset.h" 51 #include "dcn/dcn_3_0_3_offset.h" 52 #include "dcn/dcn_3_0_3_sh_mask.h" 53 #include "dpcs/dpcs_3_0_3_offset.h" 54 #include "dpcs/dpcs_3_0_3_sh_mask.h" 55 #include "nbio/nbio_2_3_offset.h" 56 57 #include "dml/dcn303/dcn303_fpu.h" 58 59 #define DC_LOGGER_INIT(logger) 60 61 62 static const struct dc_debug_options debug_defaults_drv = { 63 .disable_dmcu = true, 64 .force_abm_enable = false, 65 .timing_trace = false, 66 .clock_trace = true, 67 .disable_pplib_clock_request = true, 68 .pipe_split_policy = MPC_SPLIT_AVOID, 69 .force_single_disp_pipe_split = false, 70 .disable_dcc = DCC_ENABLE, 71 .vsr_support = true, 72 .performance_trace = false, 73 .max_downscale_src_width = 7680,/*upto 8K*/ 74 .disable_pplib_wm_range = false, 75 .scl_reset_length10 = true, 76 .sanity_checks = false, 77 .underflow_assert_delay_us = 0xFFFFFFFF, 78 .dwb_fi_phase = -1, // -1 = disable, 79 .dmub_command_table = true, 80 .exit_idle_opt_for_cursor_updates = true, 81 .disable_idle_power_optimizations = false, 82 }; 83 84 static const struct dc_panel_config panel_config_defaults = { 85 .psr = { 86 .disable_psr = false, 87 .disallow_psrsu = false, 88 .disallow_replay = false, 89 }, 90 }; 91 92 enum dcn303_clk_src_array_id { 93 DCN303_CLK_SRC_PLL0, 94 DCN303_CLK_SRC_PLL1, 95 DCN303_CLK_SRC_TOTAL 96 }; 97 98 static const struct resource_caps res_cap_dcn303 = { 99 .num_timing_generator = 2, 100 .num_opp = 2, 101 .num_video_plane = 2, 102 .num_audio = 2, 103 .num_stream_encoder = 2, 104 .num_dwb = 1, 105 .num_ddc = 2, 106 .num_vmid = 16, 107 .num_mpc_3dlut = 1, 108 .num_dsc = 2, 109 }; 110 111 static const struct dc_plane_cap plane_cap = { 112 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 113 .per_pixel_alpha = true, 114 .pixel_format_support = { 115 .argb8888 = true, 116 .nv12 = true, 117 .fp16 = true, 118 .p010 = true, 119 .ayuv = false, 120 }, 121 .max_upscale_factor = { 122 .argb8888 = 16000, 123 .nv12 = 16000, 124 .fp16 = 16000 125 }, 126 .max_downscale_factor = { 127 .argb8888 = 600, 128 .nv12 = 600, 129 .fp16 = 600 130 }, 131 16, 132 16 133 }; 134 135 /* NBIO */ 136 #define NBIO_BASE_INNER(seg) \ 137 NBIO_BASE__INST0_SEG ## seg 138 139 #define NBIO_BASE(seg) \ 140 NBIO_BASE_INNER(seg) 141 142 #define NBIO_SR(reg_name)\ 143 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \ 144 mm ## reg_name 145 146 /* DCN */ 147 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg 148 149 #define BASE(seg) BASE_INNER(seg) 150 151 #define SR(reg_name)\ 152 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name 153 154 #define SF(reg_name, field_name, post_fix)\ 155 .field_name = reg_name ## __ ## field_name ## post_fix 156 157 #define SRI(reg_name, block, id)\ 158 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + mm ## block ## id ## _ ## reg_name 159 160 #define SRI2(reg_name, block, id)\ 161 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name 162 163 #define SRII(reg_name, block, id)\ 164 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 165 mm ## block ## id ## _ ## reg_name 166 167 #define DCCG_SRII(reg_name, block, id)\ 168 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 169 mm ## block ## id ## _ ## reg_name 170 171 #define VUPDATE_SRII(reg_name, block, id)\ 172 .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \ 173 mm ## reg_name ## _ ## block ## id 174 175 #define SRII_DWB(reg_name, temp_name, block, id)\ 176 .reg_name[id] = BASE(mm ## block ## id ## _ ## temp_name ## _BASE_IDX) + \ 177 mm ## block ## id ## _ ## temp_name 178 179 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \ 180 .field_name = reg_name ## __ ## field_name ## post_fix 181 182 #define SRII_MPC_RMU(reg_name, block, id)\ 183 .RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 184 mm ## block ## id ## _ ## reg_name 185 186 static const struct dcn_hubbub_registers hubbub_reg = { 187 HUBBUB_REG_LIST_DCN30(0) 188 }; 189 190 static const struct dcn_hubbub_shift hubbub_shift = { 191 HUBBUB_MASK_SH_LIST_DCN30(__SHIFT) 192 }; 193 194 static const struct dcn_hubbub_mask hubbub_mask = { 195 HUBBUB_MASK_SH_LIST_DCN30(_MASK) 196 }; 197 198 #define vmid_regs(id)\ 199 [id] = { DCN20_VMID_REG_LIST(id) } 200 201 static const struct dcn_vmid_registers vmid_regs[] = { 202 vmid_regs(0), 203 vmid_regs(1), 204 vmid_regs(2), 205 vmid_regs(3), 206 vmid_regs(4), 207 vmid_regs(5), 208 vmid_regs(6), 209 vmid_regs(7), 210 vmid_regs(8), 211 vmid_regs(9), 212 vmid_regs(10), 213 vmid_regs(11), 214 vmid_regs(12), 215 vmid_regs(13), 216 vmid_regs(14), 217 vmid_regs(15) 218 }; 219 220 static const struct dcn20_vmid_shift vmid_shifts = { 221 DCN20_VMID_MASK_SH_LIST(__SHIFT) 222 }; 223 224 static const struct dcn20_vmid_mask vmid_masks = { 225 DCN20_VMID_MASK_SH_LIST(_MASK) 226 }; 227 228 static struct hubbub *dcn303_hubbub_create(struct dc_context *ctx) 229 { 230 int i; 231 232 struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub), GFP_KERNEL); 233 234 if (!hubbub3) 235 return NULL; 236 237 hubbub3_construct(hubbub3, ctx, &hubbub_reg, &hubbub_shift, &hubbub_mask); 238 239 for (i = 0; i < res_cap_dcn303.num_vmid; i++) { 240 struct dcn20_vmid *vmid = &hubbub3->vmid[i]; 241 242 vmid->ctx = ctx; 243 244 vmid->regs = &vmid_regs[i]; 245 vmid->shifts = &vmid_shifts; 246 vmid->masks = &vmid_masks; 247 } 248 249 return &hubbub3->base; 250 } 251 252 #define vpg_regs(id)\ 253 [id] = { VPG_DCN3_REG_LIST(id) } 254 255 static const struct dcn30_vpg_registers vpg_regs[] = { 256 vpg_regs(0), 257 vpg_regs(1), 258 vpg_regs(2) 259 }; 260 261 static const struct dcn30_vpg_shift vpg_shift = { 262 DCN3_VPG_MASK_SH_LIST(__SHIFT) 263 }; 264 265 static const struct dcn30_vpg_mask vpg_mask = { 266 DCN3_VPG_MASK_SH_LIST(_MASK) 267 }; 268 269 static struct vpg *dcn303_vpg_create(struct dc_context *ctx, uint32_t inst) 270 { 271 struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL); 272 273 if (!vpg3) 274 return NULL; 275 276 vpg3_construct(vpg3, ctx, inst, &vpg_regs[inst], &vpg_shift, &vpg_mask); 277 278 return &vpg3->base; 279 } 280 281 #define afmt_regs(id)\ 282 [id] = { AFMT_DCN3_REG_LIST(id) } 283 284 static const struct dcn30_afmt_registers afmt_regs[] = { 285 afmt_regs(0), 286 afmt_regs(1), 287 afmt_regs(2) 288 }; 289 290 static const struct dcn30_afmt_shift afmt_shift = { 291 DCN3_AFMT_MASK_SH_LIST(__SHIFT) 292 }; 293 294 static const struct dcn30_afmt_mask afmt_mask = { 295 DCN3_AFMT_MASK_SH_LIST(_MASK) 296 }; 297 298 static struct afmt *dcn303_afmt_create(struct dc_context *ctx, uint32_t inst) 299 { 300 struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL); 301 302 if (!afmt3) 303 return NULL; 304 305 afmt3_construct(afmt3, ctx, inst, &afmt_regs[inst], &afmt_shift, &afmt_mask); 306 307 return &afmt3->base; 308 } 309 310 #define audio_regs(id)\ 311 [id] = { AUD_COMMON_REG_LIST(id) } 312 313 static const struct dce_audio_registers audio_regs[] = { 314 audio_regs(0), 315 audio_regs(1), 316 audio_regs(2), 317 audio_regs(3), 318 audio_regs(4), 319 audio_regs(5), 320 audio_regs(6) 321 }; 322 323 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 324 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 325 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 326 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 327 328 static const struct dce_audio_shift audio_shift = { 329 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 330 }; 331 332 static const struct dce_audio_mask audio_mask = { 333 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 334 }; 335 336 static struct audio *dcn303_create_audio(struct dc_context *ctx, unsigned int inst) 337 { 338 return dce_audio_create(ctx, inst, &audio_regs[inst], &audio_shift, &audio_mask); 339 } 340 341 #define stream_enc_regs(id)\ 342 [id] = { SE_DCN3_REG_LIST(id) } 343 344 static const struct dcn10_stream_enc_registers stream_enc_regs[] = { 345 stream_enc_regs(0), 346 stream_enc_regs(1) 347 }; 348 349 static const struct dcn10_stream_encoder_shift se_shift = { 350 SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 351 }; 352 353 static const struct dcn10_stream_encoder_mask se_mask = { 354 SE_COMMON_MASK_SH_LIST_DCN30(_MASK) 355 }; 356 357 static struct stream_encoder *dcn303_stream_encoder_create(enum engine_id eng_id, struct dc_context *ctx) 358 { 359 struct dcn10_stream_encoder *enc1; 360 struct vpg *vpg; 361 struct afmt *afmt; 362 int vpg_inst; 363 int afmt_inst; 364 365 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */ 366 if (eng_id <= ENGINE_ID_DIGB) { 367 vpg_inst = eng_id; 368 afmt_inst = eng_id; 369 } else 370 return NULL; 371 372 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 373 vpg = dcn303_vpg_create(ctx, vpg_inst); 374 afmt = dcn303_afmt_create(ctx, afmt_inst); 375 376 if (!enc1 || !vpg || !afmt) { 377 kfree(enc1); 378 kfree(vpg); 379 kfree(afmt); 380 return NULL; 381 } 382 383 dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id, vpg, afmt, &stream_enc_regs[eng_id], 384 &se_shift, &se_mask); 385 386 return &enc1->base; 387 } 388 389 #define clk_src_regs(index, pllid)\ 390 [index] = { CS_COMMON_REG_LIST_DCN3_03(index, pllid) } 391 392 static const struct dce110_clk_src_regs clk_src_regs[] = { 393 clk_src_regs(0, A), 394 clk_src_regs(1, B) 395 }; 396 397 static const struct dce110_clk_src_shift cs_shift = { 398 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 399 }; 400 401 static const struct dce110_clk_src_mask cs_mask = { 402 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 403 }; 404 405 static struct clock_source *dcn303_clock_source_create(struct dc_context *ctx, struct dc_bios *bios, 406 enum clock_source_id id, const struct dce110_clk_src_regs *regs, bool dp_clk_src) 407 { 408 struct dce110_clk_src *clk_src = kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 409 410 if (!clk_src) 411 return NULL; 412 413 if (dcn3_clk_src_construct(clk_src, ctx, bios, id, regs, &cs_shift, &cs_mask)) { 414 clk_src->base.dp_clk_src = dp_clk_src; 415 return &clk_src->base; 416 } 417 418 kfree(clk_src); 419 BREAK_TO_DEBUGGER(); 420 return NULL; 421 } 422 423 static const struct dce_hwseq_registers hwseq_reg = { 424 HWSEQ_DCN303_REG_LIST() 425 }; 426 427 static const struct dce_hwseq_shift hwseq_shift = { 428 HWSEQ_DCN303_MASK_SH_LIST(__SHIFT) 429 }; 430 431 static const struct dce_hwseq_mask hwseq_mask = { 432 HWSEQ_DCN303_MASK_SH_LIST(_MASK) 433 }; 434 435 static struct dce_hwseq *dcn303_hwseq_create(struct dc_context *ctx) 436 { 437 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 438 439 if (hws) { 440 hws->ctx = ctx; 441 hws->regs = &hwseq_reg; 442 hws->shifts = &hwseq_shift; 443 hws->masks = &hwseq_mask; 444 } 445 return hws; 446 } 447 448 #define hubp_regs(id)\ 449 [id] = { HUBP_REG_LIST_DCN30(id) } 450 451 static const struct dcn_hubp2_registers hubp_regs[] = { 452 hubp_regs(0), 453 hubp_regs(1) 454 }; 455 456 static const struct dcn_hubp2_shift hubp_shift = { 457 HUBP_MASK_SH_LIST_DCN30(__SHIFT) 458 }; 459 460 static const struct dcn_hubp2_mask hubp_mask = { 461 HUBP_MASK_SH_LIST_DCN30(_MASK) 462 }; 463 464 static struct hubp *dcn303_hubp_create(struct dc_context *ctx, uint32_t inst) 465 { 466 struct dcn20_hubp *hubp2 = kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL); 467 468 if (!hubp2) 469 return NULL; 470 471 if (hubp3_construct(hubp2, ctx, inst, &hubp_regs[inst], &hubp_shift, &hubp_mask)) 472 return &hubp2->base; 473 474 BREAK_TO_DEBUGGER(); 475 kfree(hubp2); 476 return NULL; 477 } 478 479 #define dpp_regs(id)\ 480 [id] = { DPP_REG_LIST_DCN30(id) } 481 482 static const struct dcn3_dpp_registers dpp_regs[] = { 483 dpp_regs(0), 484 dpp_regs(1) 485 }; 486 487 static const struct dcn3_dpp_shift tf_shift = { 488 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT) 489 }; 490 491 static const struct dcn3_dpp_mask tf_mask = { 492 DPP_REG_LIST_SH_MASK_DCN30(_MASK) 493 }; 494 495 static struct dpp *dcn303_dpp_create(struct dc_context *ctx, uint32_t inst) 496 { 497 struct dcn3_dpp *dpp = kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL); 498 499 if (!dpp) 500 return NULL; 501 502 if (dpp3_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, &tf_mask)) 503 return &dpp->base; 504 505 BREAK_TO_DEBUGGER(); 506 kfree(dpp); 507 return NULL; 508 } 509 510 #define opp_regs(id)\ 511 [id] = { OPP_REG_LIST_DCN30(id) } 512 513 static const struct dcn20_opp_registers opp_regs[] = { 514 opp_regs(0), 515 opp_regs(1) 516 }; 517 518 static const struct dcn20_opp_shift opp_shift = { 519 OPP_MASK_SH_LIST_DCN20(__SHIFT) 520 }; 521 522 static const struct dcn20_opp_mask opp_mask = { 523 OPP_MASK_SH_LIST_DCN20(_MASK) 524 }; 525 526 static struct output_pixel_processor *dcn303_opp_create(struct dc_context *ctx, uint32_t inst) 527 { 528 struct dcn20_opp *opp = kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); 529 530 if (!opp) { 531 BREAK_TO_DEBUGGER(); 532 return NULL; 533 } 534 535 dcn20_opp_construct(opp, ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask); 536 return &opp->base; 537 } 538 539 #define optc_regs(id)\ 540 [id] = { OPTC_COMMON_REG_LIST_DCN3_0(id) } 541 542 static const struct dcn_optc_registers optc_regs[] = { 543 optc_regs(0), 544 optc_regs(1) 545 }; 546 547 static const struct dcn_optc_shift optc_shift = { 548 OPTC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 549 }; 550 551 static const struct dcn_optc_mask optc_mask = { 552 OPTC_COMMON_MASK_SH_LIST_DCN30(_MASK) 553 }; 554 555 static struct timing_generator *dcn303_timing_generator_create(struct dc_context *ctx, uint32_t instance) 556 { 557 struct optc *tgn10 = kzalloc(sizeof(struct optc), GFP_KERNEL); 558 559 if (!tgn10) 560 return NULL; 561 562 tgn10->base.inst = instance; 563 tgn10->base.ctx = ctx; 564 565 tgn10->tg_regs = &optc_regs[instance]; 566 tgn10->tg_shift = &optc_shift; 567 tgn10->tg_mask = &optc_mask; 568 569 dcn30_timing_generator_init(tgn10); 570 571 return &tgn10->base; 572 } 573 574 static const struct dcn30_mpc_registers mpc_regs = { 575 MPC_REG_LIST_DCN3_0(0), 576 MPC_REG_LIST_DCN3_0(1), 577 MPC_OUT_MUX_REG_LIST_DCN3_0(0), 578 MPC_OUT_MUX_REG_LIST_DCN3_0(1), 579 MPC_RMU_GLOBAL_REG_LIST_DCN3AG, 580 MPC_RMU_REG_LIST_DCN3AG(0), 581 MPC_DWB_MUX_REG_LIST_DCN3_0(0), 582 }; 583 584 static const struct dcn30_mpc_shift mpc_shift = { 585 MPC_COMMON_MASK_SH_LIST_DCN303(__SHIFT) 586 }; 587 588 static const struct dcn30_mpc_mask mpc_mask = { 589 MPC_COMMON_MASK_SH_LIST_DCN303(_MASK) 590 }; 591 592 static struct mpc *dcn303_mpc_create(struct dc_context *ctx, int num_mpcc, int num_rmu) 593 { 594 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), GFP_KERNEL); 595 596 if (!mpc30) 597 return NULL; 598 599 dcn30_mpc_construct(mpc30, ctx, &mpc_regs, &mpc_shift, &mpc_mask, num_mpcc, num_rmu); 600 601 return &mpc30->base; 602 } 603 604 #define dsc_regsDCN20(id)\ 605 [id] = { DSC_REG_LIST_DCN20(id) } 606 607 static const struct dcn20_dsc_registers dsc_regs[] = { 608 dsc_regsDCN20(0), 609 dsc_regsDCN20(1) 610 }; 611 612 static const struct dcn20_dsc_shift dsc_shift = { 613 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) 614 }; 615 616 static const struct dcn20_dsc_mask dsc_mask = { 617 DSC_REG_LIST_SH_MASK_DCN20(_MASK) 618 }; 619 620 static struct display_stream_compressor *dcn303_dsc_create(struct dc_context *ctx, uint32_t inst) 621 { 622 struct dcn20_dsc *dsc = kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); 623 624 if (!dsc) { 625 BREAK_TO_DEBUGGER(); 626 return NULL; 627 } 628 629 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 630 return &dsc->base; 631 } 632 633 #define dwbc_regs_dcn3(id)\ 634 [id] = { DWBC_COMMON_REG_LIST_DCN30(id) } 635 636 static const struct dcn30_dwbc_registers dwbc30_regs[] = { 637 dwbc_regs_dcn3(0) 638 }; 639 640 static const struct dcn30_dwbc_shift dwbc30_shift = { 641 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 642 }; 643 644 static const struct dcn30_dwbc_mask dwbc30_mask = { 645 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK) 646 }; 647 648 static bool dcn303_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) 649 { 650 int i; 651 uint32_t pipe_count = pool->res_cap->num_dwb; 652 653 for (i = 0; i < pipe_count; i++) { 654 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), GFP_KERNEL); 655 656 if (!dwbc30) { 657 dm_error("DC: failed to create dwbc30!\n"); 658 return false; 659 } 660 661 dcn30_dwbc_construct(dwbc30, ctx, &dwbc30_regs[i], &dwbc30_shift, &dwbc30_mask, i); 662 663 pool->dwbc[i] = &dwbc30->base; 664 } 665 return true; 666 } 667 668 #define mcif_wb_regs_dcn3(id)\ 669 [id] = { MCIF_WB_COMMON_REG_LIST_DCN30(id) } 670 671 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = { 672 mcif_wb_regs_dcn3(0) 673 }; 674 675 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = { 676 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 677 }; 678 679 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { 680 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK) 681 }; 682 683 static bool dcn303_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) 684 { 685 int i; 686 uint32_t pipe_count = pool->res_cap->num_dwb; 687 688 for (i = 0; i < pipe_count; i++) { 689 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), GFP_KERNEL); 690 691 if (!mcif_wb30) { 692 dm_error("DC: failed to create mcif_wb30!\n"); 693 return false; 694 } 695 696 dcn30_mmhubbub_construct(mcif_wb30, ctx, &mcif_wb30_regs[i], &mcif_wb30_shift, &mcif_wb30_mask, i); 697 698 pool->mcif_wb[i] = &mcif_wb30->base; 699 } 700 return true; 701 } 702 703 #define aux_engine_regs(id)\ 704 [id] = {\ 705 AUX_COMMON_REG_LIST0(id), \ 706 .AUXN_IMPCAL = 0, \ 707 .AUXP_IMPCAL = 0, \ 708 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \ 709 } 710 711 static const struct dce110_aux_registers aux_engine_regs[] = { 712 aux_engine_regs(0), 713 aux_engine_regs(1) 714 }; 715 716 static const struct dce110_aux_registers_shift aux_shift = { 717 DCN_AUX_MASK_SH_LIST(__SHIFT) 718 }; 719 720 static const struct dce110_aux_registers_mask aux_mask = { 721 DCN_AUX_MASK_SH_LIST(_MASK) 722 }; 723 724 static struct dce_aux *dcn303_aux_engine_create(struct dc_context *ctx, uint32_t inst) 725 { 726 struct aux_engine_dce110 *aux_engine = kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 727 728 if (!aux_engine) 729 return NULL; 730 731 dce110_aux_engine_construct(aux_engine, ctx, inst, SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 732 &aux_engine_regs[inst], &aux_mask, &aux_shift, ctx->dc->caps.extended_aux_timeout_support); 733 734 return &aux_engine->base; 735 } 736 737 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 738 739 static const struct dce_i2c_registers i2c_hw_regs[] = { 740 i2c_inst_regs(1), 741 i2c_inst_regs(2) 742 }; 743 744 static const struct dce_i2c_shift i2c_shifts = { 745 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT) 746 }; 747 748 static const struct dce_i2c_mask i2c_masks = { 749 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK) 750 }; 751 752 static struct dce_i2c_hw *dcn303_i2c_hw_create(struct dc_context *ctx, uint32_t inst) 753 { 754 struct dce_i2c_hw *dce_i2c_hw = kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 755 756 if (!dce_i2c_hw) 757 return NULL; 758 759 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 760 761 return dce_i2c_hw; 762 } 763 764 static const struct encoder_feature_support link_enc_feature = { 765 .max_hdmi_deep_color = COLOR_DEPTH_121212, 766 .max_hdmi_pixel_clock = 600000, 767 .hdmi_ycbcr420_supported = true, 768 .dp_ycbcr420_supported = true, 769 .fec_supported = true, 770 .flags.bits.IS_HBR2_CAPABLE = true, 771 .flags.bits.IS_HBR3_CAPABLE = true, 772 .flags.bits.IS_TPS3_CAPABLE = true, 773 .flags.bits.IS_TPS4_CAPABLE = true 774 }; 775 776 #define link_regs(id, phyid)\ 777 [id] = {\ 778 LE_DCN3_REG_LIST(id), \ 779 UNIPHY_DCN2_REG_LIST(phyid), \ 780 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \ 781 } 782 783 static const struct dcn10_link_enc_registers link_enc_regs[] = { 784 link_regs(0, A), 785 link_regs(1, B) 786 }; 787 788 static const struct dcn10_link_enc_shift le_shift = { 789 LINK_ENCODER_MASK_SH_LIST_DCN30(__SHIFT), 790 DPCS_DCN2_MASK_SH_LIST(__SHIFT) 791 }; 792 793 static const struct dcn10_link_enc_mask le_mask = { 794 LINK_ENCODER_MASK_SH_LIST_DCN30(_MASK), 795 DPCS_DCN2_MASK_SH_LIST(_MASK) 796 }; 797 798 #define aux_regs(id)\ 799 [id] = { DCN2_AUX_REG_LIST(id) } 800 801 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { 802 aux_regs(0), 803 aux_regs(1) 804 }; 805 806 #define hpd_regs(id)\ 807 [id] = { HPD_REG_LIST(id) } 808 809 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { 810 hpd_regs(0), 811 hpd_regs(1) 812 }; 813 814 static struct link_encoder *dcn303_link_encoder_create( 815 struct dc_context *ctx, 816 const struct encoder_init_data *enc_init_data) 817 { 818 struct dcn20_link_encoder *enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 819 820 if (!enc20) 821 return NULL; 822 823 dcn30_link_encoder_construct(enc20, enc_init_data, &link_enc_feature, 824 &link_enc_regs[enc_init_data->transmitter], &link_enc_aux_regs[enc_init_data->channel - 1], 825 &link_enc_hpd_regs[enc_init_data->hpd_source], &le_shift, &le_mask); 826 827 return &enc20->enc10.base; 828 } 829 830 static const struct dce_panel_cntl_registers panel_cntl_regs[] = { 831 { DCN_PANEL_CNTL_REG_LIST() } 832 }; 833 834 static const struct dce_panel_cntl_shift panel_cntl_shift = { 835 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT) 836 }; 837 838 static const struct dce_panel_cntl_mask panel_cntl_mask = { 839 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK) 840 }; 841 842 static struct panel_cntl *dcn303_panel_cntl_create(const struct panel_cntl_init_data *init_data) 843 { 844 struct dce_panel_cntl *panel_cntl = kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL); 845 846 if (!panel_cntl) 847 return NULL; 848 849 dce_panel_cntl_construct(panel_cntl, init_data, &panel_cntl_regs[init_data->inst], 850 &panel_cntl_shift, &panel_cntl_mask); 851 852 return &panel_cntl->base; 853 } 854 855 static void read_dce_straps(struct dc_context *ctx, struct resource_straps *straps) 856 { 857 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX), 858 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 859 } 860 861 static const struct resource_create_funcs res_create_funcs = { 862 .read_dce_straps = read_dce_straps, 863 .create_audio = dcn303_create_audio, 864 .create_stream_encoder = dcn303_stream_encoder_create, 865 .create_hwseq = dcn303_hwseq_create, 866 }; 867 868 static bool is_soc_bounding_box_valid(struct dc *dc) 869 { 870 uint32_t hw_internal_rev = dc->ctx->asic_id.hw_internal_rev; 871 872 if (ASICREV_IS_BEIGE_GOBY_P(hw_internal_rev)) 873 return true; 874 875 return false; 876 } 877 878 static bool init_soc_bounding_box(struct dc *dc, struct resource_pool *pool) 879 { 880 struct _vcs_dpi_soc_bounding_box_st *loaded_bb = &dcn3_03_soc; 881 struct _vcs_dpi_ip_params_st *loaded_ip = &dcn3_03_ip; 882 883 DC_LOGGER_INIT(dc->ctx->logger); 884 885 if (!is_soc_bounding_box_valid(dc)) { 886 DC_LOG_ERROR("%s: not valid soc bounding box/n", __func__); 887 return false; 888 } 889 890 loaded_ip->max_num_otg = pool->pipe_count; 891 loaded_ip->max_num_dpp = pool->pipe_count; 892 loaded_ip->clamp_min_dcfclk = dc->config.clamp_min_dcfclk; 893 DC_FP_START(); 894 dcn20_patch_bounding_box(dc, loaded_bb); 895 DC_FP_END(); 896 897 if (dc->ctx->dc_bios->funcs->get_soc_bb_info) { 898 struct bp_soc_bb_info bb_info = { 0 }; 899 900 if (dc->ctx->dc_bios->funcs->get_soc_bb_info( 901 dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) { 902 DC_FP_START(); 903 dcn303_fpu_init_soc_bounding_box(bb_info); 904 DC_FP_END(); 905 } 906 } 907 908 return true; 909 } 910 911 static void dcn303_resource_destruct(struct resource_pool *pool) 912 { 913 unsigned int i; 914 915 for (i = 0; i < pool->stream_enc_count; i++) { 916 if (pool->stream_enc[i] != NULL) { 917 if (pool->stream_enc[i]->vpg != NULL) { 918 kfree(DCN30_VPG_FROM_VPG(pool->stream_enc[i]->vpg)); 919 pool->stream_enc[i]->vpg = NULL; 920 } 921 if (pool->stream_enc[i]->afmt != NULL) { 922 kfree(DCN30_AFMT_FROM_AFMT(pool->stream_enc[i]->afmt)); 923 pool->stream_enc[i]->afmt = NULL; 924 } 925 kfree(DCN10STRENC_FROM_STRENC(pool->stream_enc[i])); 926 pool->stream_enc[i] = NULL; 927 } 928 } 929 930 for (i = 0; i < pool->res_cap->num_dsc; i++) { 931 if (pool->dscs[i] != NULL) 932 dcn20_dsc_destroy(&pool->dscs[i]); 933 } 934 935 if (pool->mpc != NULL) { 936 kfree(TO_DCN20_MPC(pool->mpc)); 937 pool->mpc = NULL; 938 } 939 940 if (pool->hubbub != NULL) { 941 kfree(pool->hubbub); 942 pool->hubbub = NULL; 943 } 944 945 for (i = 0; i < pool->pipe_count; i++) { 946 if (pool->dpps[i] != NULL) { 947 kfree(TO_DCN20_DPP(pool->dpps[i])); 948 pool->dpps[i] = NULL; 949 } 950 951 if (pool->hubps[i] != NULL) { 952 kfree(TO_DCN20_HUBP(pool->hubps[i])); 953 pool->hubps[i] = NULL; 954 } 955 956 if (pool->irqs != NULL) 957 dal_irq_service_destroy(&pool->irqs); 958 } 959 960 for (i = 0; i < pool->res_cap->num_ddc; i++) { 961 if (pool->engines[i] != NULL) 962 dce110_engine_destroy(&pool->engines[i]); 963 if (pool->hw_i2cs[i] != NULL) { 964 kfree(pool->hw_i2cs[i]); 965 pool->hw_i2cs[i] = NULL; 966 } 967 if (pool->sw_i2cs[i] != NULL) { 968 kfree(pool->sw_i2cs[i]); 969 pool->sw_i2cs[i] = NULL; 970 } 971 } 972 973 for (i = 0; i < pool->res_cap->num_opp; i++) { 974 if (pool->opps[i] != NULL) 975 pool->opps[i]->funcs->opp_destroy(&pool->opps[i]); 976 } 977 978 for (i = 0; i < pool->res_cap->num_timing_generator; i++) { 979 if (pool->timing_generators[i] != NULL) { 980 kfree(DCN10TG_FROM_TG(pool->timing_generators[i])); 981 pool->timing_generators[i] = NULL; 982 } 983 } 984 985 for (i = 0; i < pool->res_cap->num_dwb; i++) { 986 if (pool->dwbc[i] != NULL) { 987 kfree(TO_DCN30_DWBC(pool->dwbc[i])); 988 pool->dwbc[i] = NULL; 989 } 990 if (pool->mcif_wb[i] != NULL) { 991 kfree(TO_DCN30_MMHUBBUB(pool->mcif_wb[i])); 992 pool->mcif_wb[i] = NULL; 993 } 994 } 995 996 for (i = 0; i < pool->audio_count; i++) { 997 if (pool->audios[i]) 998 dce_aud_destroy(&pool->audios[i]); 999 } 1000 1001 for (i = 0; i < pool->clk_src_count; i++) { 1002 if (pool->clock_sources[i] != NULL) 1003 dcn20_clock_source_destroy(&pool->clock_sources[i]); 1004 } 1005 1006 if (pool->dp_clock_source != NULL) 1007 dcn20_clock_source_destroy(&pool->dp_clock_source); 1008 1009 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { 1010 if (pool->mpc_lut[i] != NULL) { 1011 dc_3dlut_func_release(pool->mpc_lut[i]); 1012 pool->mpc_lut[i] = NULL; 1013 } 1014 if (pool->mpc_shaper[i] != NULL) { 1015 dc_transfer_func_release(pool->mpc_shaper[i]); 1016 pool->mpc_shaper[i] = NULL; 1017 } 1018 } 1019 1020 for (i = 0; i < pool->pipe_count; i++) { 1021 if (pool->multiple_abms[i] != NULL) 1022 dce_abm_destroy(&pool->multiple_abms[i]); 1023 } 1024 1025 if (pool->psr != NULL) 1026 dmub_psr_destroy(&pool->psr); 1027 1028 if (pool->dccg != NULL) 1029 dcn_dccg_destroy(&pool->dccg); 1030 1031 if (pool->oem_device != NULL) { 1032 struct dc *dc = pool->oem_device->ctx->dc; 1033 1034 dc->link_srv->destroy_ddc_service(&pool->oem_device); 1035 } 1036 } 1037 1038 static void dcn303_destroy_resource_pool(struct resource_pool **pool) 1039 { 1040 dcn303_resource_destruct(*pool); 1041 kfree(*pool); 1042 *pool = NULL; 1043 } 1044 1045 static void dcn303_get_panel_config_defaults(struct dc_panel_config *panel_config) 1046 { 1047 *panel_config = panel_config_defaults; 1048 } 1049 1050 void dcn303_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) 1051 { 1052 DC_FP_START(); 1053 dcn303_fpu_update_bw_bounding_box(dc, bw_params); 1054 DC_FP_END(); 1055 } 1056 1057 static struct resource_funcs dcn303_res_pool_funcs = { 1058 .destroy = dcn303_destroy_resource_pool, 1059 .link_enc_create = dcn303_link_encoder_create, 1060 .panel_cntl_create = dcn303_panel_cntl_create, 1061 .validate_bandwidth = dcn30_validate_bandwidth, 1062 .calculate_wm_and_dlg = dcn30_calculate_wm_and_dlg, 1063 .update_soc_for_wm_a = dcn30_update_soc_for_wm_a, 1064 .populate_dml_pipes = dcn30_populate_dml_pipes_from_context, 1065 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer, 1066 .add_stream_to_ctx = dcn30_add_stream_to_ctx, 1067 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, 1068 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 1069 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, 1070 .set_mcif_arb_params = dcn30_set_mcif_arb_params, 1071 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, 1072 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut, 1073 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut, 1074 .update_bw_bounding_box = dcn303_update_bw_bounding_box, 1075 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, 1076 .get_panel_config_defaults = dcn303_get_panel_config_defaults, 1077 }; 1078 1079 static struct dc_cap_funcs cap_funcs = { 1080 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap 1081 }; 1082 1083 static const struct bios_registers bios_regs = { 1084 NBIO_SR(BIOS_SCRATCH_3), 1085 NBIO_SR(BIOS_SCRATCH_6) 1086 }; 1087 1088 static const struct dccg_registers dccg_regs = { 1089 DCCG_REG_LIST_DCN3_03() 1090 }; 1091 1092 static const struct dccg_shift dccg_shift = { 1093 DCCG_MASK_SH_LIST_DCN3_03(__SHIFT) 1094 }; 1095 1096 static const struct dccg_mask dccg_mask = { 1097 DCCG_MASK_SH_LIST_DCN3_03(_MASK) 1098 }; 1099 1100 #define abm_regs(id)\ 1101 [id] = { ABM_DCN302_REG_LIST(id) } 1102 1103 static const struct dce_abm_registers abm_regs[] = { 1104 abm_regs(0), 1105 abm_regs(1) 1106 }; 1107 1108 static const struct dce_abm_shift abm_shift = { 1109 ABM_MASK_SH_LIST_DCN30(__SHIFT) 1110 }; 1111 1112 static const struct dce_abm_mask abm_mask = { 1113 ABM_MASK_SH_LIST_DCN30(_MASK) 1114 }; 1115 1116 static bool dcn303_resource_construct( 1117 uint8_t num_virtual_links, 1118 struct dc *dc, 1119 struct resource_pool *pool) 1120 { 1121 int i; 1122 struct dc_context *ctx = dc->ctx; 1123 struct irq_service_init_data init_data; 1124 struct ddc_service_init_data ddc_init_data; 1125 1126 ctx->dc_bios->regs = &bios_regs; 1127 1128 pool->res_cap = &res_cap_dcn303; 1129 1130 pool->funcs = &dcn303_res_pool_funcs; 1131 1132 /************************************************* 1133 * Resource + asic cap harcoding * 1134 *************************************************/ 1135 pool->underlay_pipe_index = NO_UNDERLAY_PIPE; 1136 pool->pipe_count = pool->res_cap->num_timing_generator; 1137 pool->mpcc_count = pool->res_cap->num_timing_generator; 1138 dc->caps.max_downscale_ratio = 600; 1139 dc->caps.i2c_speed_in_khz = 100; 1140 dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by derfault*/ 1141 dc->caps.max_cursor_size = 256; 1142 dc->caps.min_horizontal_blanking_period = 80; 1143 dc->caps.dmdata_alloc_size = 2048; 1144 dc->caps.mall_size_per_mem_channel = 4; 1145 /* total size = mall per channel * num channels * 1024 * 1024 */ 1146 dc->caps.mall_size_total = dc->caps.mall_size_per_mem_channel * 1147 dc->ctx->dc_bios->vram_info.num_chans * 1148 1024 * 1024; 1149 dc->caps.cursor_cache_size = 1150 dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8; 1151 dc->caps.max_slave_planes = 1; 1152 dc->caps.post_blend_color_processing = true; 1153 dc->caps.force_dp_tps4_for_cp2520 = true; 1154 dc->caps.extended_aux_timeout_support = true; 1155 dc->caps.dmcub_support = true; 1156 dc->caps.max_v_total = (1 << 15) - 1; 1157 1158 /* Color pipeline capabilities */ 1159 dc->caps.color.dpp.dcn_arch = 1; 1160 dc->caps.color.dpp.input_lut_shared = 0; 1161 dc->caps.color.dpp.icsc = 1; 1162 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr 1163 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; 1164 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; 1165 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1; 1166 dc->caps.color.dpp.dgam_rom_caps.pq = 1; 1167 dc->caps.color.dpp.dgam_rom_caps.hlg = 1; 1168 dc->caps.color.dpp.post_csc = 1; 1169 dc->caps.color.dpp.gamma_corr = 1; 1170 dc->caps.color.dpp.dgam_rom_for_yuv = 0; 1171 1172 dc->caps.color.dpp.hw_3d_lut = 1; 1173 dc->caps.color.dpp.ogam_ram = 1; 1174 // no OGAM ROM on DCN3 1175 dc->caps.color.dpp.ogam_rom_caps.srgb = 0; 1176 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; 1177 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; 1178 dc->caps.color.dpp.ogam_rom_caps.pq = 0; 1179 dc->caps.color.dpp.ogam_rom_caps.hlg = 0; 1180 dc->caps.color.dpp.ocsc = 0; 1181 1182 dc->caps.color.mpc.gamut_remap = 1; 1183 dc->caps.color.mpc.num_3dluts = pool->res_cap->num_mpc_3dlut; //3 1184 dc->caps.color.mpc.ogam_ram = 1; 1185 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; 1186 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; 1187 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; 1188 dc->caps.color.mpc.ogam_rom_caps.pq = 0; 1189 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 1190 dc->caps.color.mpc.ocsc = 1; 1191 1192 dc->caps.dp_hdmi21_pcon_support = true; 1193 1194 dc->config.dc_mode_clk_limit_support = true; 1195 /* read VBIOS LTTPR caps */ 1196 if (ctx->dc_bios->funcs->get_lttpr_caps) { 1197 enum bp_result bp_query_result; 1198 uint8_t is_vbios_lttpr_enable = 0; 1199 1200 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable); 1201 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable; 1202 } 1203 1204 if (ctx->dc_bios->funcs->get_lttpr_interop) { 1205 enum bp_result bp_query_result; 1206 uint8_t is_vbios_interop_enabled = 0; 1207 1208 bp_query_result = ctx->dc_bios->funcs->get_lttpr_interop(ctx->dc_bios, &is_vbios_interop_enabled); 1209 dc->caps.vbios_lttpr_aware = (bp_query_result == BP_RESULT_OK) && !!is_vbios_interop_enabled; 1210 } 1211 1212 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 1213 dc->debug = debug_defaults_drv; 1214 1215 // Init the vm_helper 1216 if (dc->vm_helper) 1217 vm_helper_init(dc->vm_helper, 16); 1218 1219 /************************************************* 1220 * Create resources * 1221 *************************************************/ 1222 1223 /* Clock Sources for Pixel Clock*/ 1224 pool->clock_sources[DCN303_CLK_SRC_PLL0] = 1225 dcn303_clock_source_create(ctx, ctx->dc_bios, 1226 CLOCK_SOURCE_COMBO_PHY_PLL0, 1227 &clk_src_regs[0], false); 1228 pool->clock_sources[DCN303_CLK_SRC_PLL1] = 1229 dcn303_clock_source_create(ctx, ctx->dc_bios, 1230 CLOCK_SOURCE_COMBO_PHY_PLL1, 1231 &clk_src_regs[1], false); 1232 1233 pool->clk_src_count = DCN303_CLK_SRC_TOTAL; 1234 1235 /* todo: not reuse phy_pll registers */ 1236 pool->dp_clock_source = 1237 dcn303_clock_source_create(ctx, ctx->dc_bios, 1238 CLOCK_SOURCE_ID_DP_DTO, 1239 &clk_src_regs[0], true); 1240 1241 for (i = 0; i < pool->clk_src_count; i++) { 1242 if (pool->clock_sources[i] == NULL) { 1243 dm_error("DC: failed to create clock sources!\n"); 1244 BREAK_TO_DEBUGGER(); 1245 goto create_fail; 1246 } 1247 } 1248 1249 /* DCCG */ 1250 pool->dccg = dccg30_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 1251 if (pool->dccg == NULL) { 1252 dm_error("DC: failed to create dccg!\n"); 1253 BREAK_TO_DEBUGGER(); 1254 goto create_fail; 1255 } 1256 1257 /* PP Lib and SMU interfaces */ 1258 init_soc_bounding_box(dc, pool); 1259 1260 /* DML */ 1261 dml_init_instance(&dc->dml, &dcn3_03_soc, &dcn3_03_ip, DML_PROJECT_DCN30); 1262 1263 /* IRQ */ 1264 init_data.ctx = dc->ctx; 1265 pool->irqs = dal_irq_service_dcn303_create(&init_data); 1266 if (!pool->irqs) 1267 goto create_fail; 1268 1269 /* HUBBUB */ 1270 pool->hubbub = dcn303_hubbub_create(ctx); 1271 if (pool->hubbub == NULL) { 1272 BREAK_TO_DEBUGGER(); 1273 dm_error("DC: failed to create hubbub!\n"); 1274 goto create_fail; 1275 } 1276 1277 /* HUBPs, DPPs, OPPs and TGs */ 1278 for (i = 0; i < pool->pipe_count; i++) { 1279 pool->hubps[i] = dcn303_hubp_create(ctx, i); 1280 if (pool->hubps[i] == NULL) { 1281 BREAK_TO_DEBUGGER(); 1282 dm_error("DC: failed to create hubps!\n"); 1283 goto create_fail; 1284 } 1285 1286 pool->dpps[i] = dcn303_dpp_create(ctx, i); 1287 if (pool->dpps[i] == NULL) { 1288 BREAK_TO_DEBUGGER(); 1289 dm_error("DC: failed to create dpps!\n"); 1290 goto create_fail; 1291 } 1292 } 1293 1294 for (i = 0; i < pool->res_cap->num_opp; i++) { 1295 pool->opps[i] = dcn303_opp_create(ctx, i); 1296 if (pool->opps[i] == NULL) { 1297 BREAK_TO_DEBUGGER(); 1298 dm_error("DC: failed to create output pixel processor!\n"); 1299 goto create_fail; 1300 } 1301 } 1302 1303 for (i = 0; i < pool->res_cap->num_timing_generator; i++) { 1304 pool->timing_generators[i] = dcn303_timing_generator_create(ctx, i); 1305 if (pool->timing_generators[i] == NULL) { 1306 BREAK_TO_DEBUGGER(); 1307 dm_error("DC: failed to create tg!\n"); 1308 goto create_fail; 1309 } 1310 } 1311 pool->timing_generator_count = i; 1312 1313 /* PSR */ 1314 pool->psr = dmub_psr_create(ctx); 1315 if (pool->psr == NULL) { 1316 dm_error("DC: failed to create psr!\n"); 1317 BREAK_TO_DEBUGGER(); 1318 goto create_fail; 1319 } 1320 1321 /* ABM */ 1322 for (i = 0; i < pool->res_cap->num_timing_generator; i++) { 1323 pool->multiple_abms[i] = dmub_abm_create(ctx, &abm_regs[i], &abm_shift, &abm_mask); 1324 if (pool->multiple_abms[i] == NULL) { 1325 dm_error("DC: failed to create abm for pipe %d!\n", i); 1326 BREAK_TO_DEBUGGER(); 1327 goto create_fail; 1328 } 1329 } 1330 1331 /* MPC and DSC */ 1332 pool->mpc = dcn303_mpc_create(ctx, pool->mpcc_count, pool->res_cap->num_mpc_3dlut); 1333 if (pool->mpc == NULL) { 1334 BREAK_TO_DEBUGGER(); 1335 dm_error("DC: failed to create mpc!\n"); 1336 goto create_fail; 1337 } 1338 1339 for (i = 0; i < pool->res_cap->num_dsc; i++) { 1340 pool->dscs[i] = dcn303_dsc_create(ctx, i); 1341 if (pool->dscs[i] == NULL) { 1342 BREAK_TO_DEBUGGER(); 1343 dm_error("DC: failed to create display stream compressor %d!\n", i); 1344 goto create_fail; 1345 } 1346 } 1347 1348 /* DWB and MMHUBBUB */ 1349 if (!dcn303_dwbc_create(ctx, pool)) { 1350 BREAK_TO_DEBUGGER(); 1351 dm_error("DC: failed to create dwbc!\n"); 1352 goto create_fail; 1353 } 1354 1355 if (!dcn303_mmhubbub_create(ctx, pool)) { 1356 BREAK_TO_DEBUGGER(); 1357 dm_error("DC: failed to create mcif_wb!\n"); 1358 goto create_fail; 1359 } 1360 1361 /* AUX and I2C */ 1362 for (i = 0; i < pool->res_cap->num_ddc; i++) { 1363 pool->engines[i] = dcn303_aux_engine_create(ctx, i); 1364 if (pool->engines[i] == NULL) { 1365 BREAK_TO_DEBUGGER(); 1366 dm_error("DC:failed to create aux engine!!\n"); 1367 goto create_fail; 1368 } 1369 pool->hw_i2cs[i] = dcn303_i2c_hw_create(ctx, i); 1370 if (pool->hw_i2cs[i] == NULL) { 1371 BREAK_TO_DEBUGGER(); 1372 dm_error("DC:failed to create hw i2c!!\n"); 1373 goto create_fail; 1374 } 1375 pool->sw_i2cs[i] = NULL; 1376 } 1377 1378 /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */ 1379 if (!resource_construct(num_virtual_links, dc, pool, 1380 &res_create_funcs)) 1381 goto create_fail; 1382 1383 /* HW Sequencer and Plane caps */ 1384 dcn303_hw_sequencer_construct(dc); 1385 1386 dc->caps.max_planes = pool->pipe_count; 1387 1388 for (i = 0; i < dc->caps.max_planes; ++i) 1389 dc->caps.planes[i] = plane_cap; 1390 1391 dc->cap_funcs = cap_funcs; 1392 1393 if (dc->ctx->dc_bios->fw_info.oem_i2c_present) { 1394 ddc_init_data.ctx = dc->ctx; 1395 ddc_init_data.link = NULL; 1396 ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id; 1397 ddc_init_data.id.enum_id = 0; 1398 ddc_init_data.id.type = OBJECT_TYPE_GENERIC; 1399 pool->oem_device = dc->link_srv->create_ddc_service(&ddc_init_data); 1400 } else { 1401 pool->oem_device = NULL; 1402 } 1403 1404 return true; 1405 1406 create_fail: 1407 1408 dcn303_resource_destruct(pool); 1409 1410 return false; 1411 } 1412 1413 struct resource_pool *dcn303_create_resource_pool(const struct dc_init_data *init_data, struct dc *dc) 1414 { 1415 struct resource_pool *pool = kzalloc(sizeof(struct resource_pool), GFP_KERNEL); 1416 1417 if (!pool) 1418 return NULL; 1419 1420 if (dcn303_resource_construct(init_data->num_virtual_links, dc, pool)) 1421 return pool; 1422 1423 BREAK_TO_DEBUGGER(); 1424 kfree(pool); 1425 return NULL; 1426 } 1427