1 // SPDX-License-Identifier: MIT
2 /*
3  * Copyright (C) 2021 Advanced Micro Devices, Inc.
4  *
5  * Authors: AMD
6  */
7 
8 #include "dcn303_init.h"
9 #include "dcn303_resource.h"
10 #include "dcn303_dccg.h"
11 #include "irq/dcn303/irq_service_dcn303.h"
12 
13 #include "dcn30/dcn30_dio_link_encoder.h"
14 #include "dcn30/dcn30_dio_stream_encoder.h"
15 #include "dcn30/dcn30_dpp.h"
16 #include "dcn30/dcn30_dwb.h"
17 #include "dcn30/dcn30_hubbub.h"
18 #include "dcn30/dcn30_hubp.h"
19 #include "dcn30/dcn30_mmhubbub.h"
20 #include "dcn30/dcn30_mpc.h"
21 #include "dcn30/dcn30_opp.h"
22 #include "dcn30/dcn30_optc.h"
23 #include "dcn30/dcn30_resource.h"
24 
25 #include "dcn20/dcn20_dsc.h"
26 #include "dcn20/dcn20_resource.h"
27 
28 #include "dml/dcn30/dcn30_fpu.h"
29 
30 #include "dcn10/dcn10_resource.h"
31 
32 #include "dc_link_ddc.h"
33 
34 #include "dce/dce_abm.h"
35 #include "dce/dce_audio.h"
36 #include "dce/dce_aux.h"
37 #include "dce/dce_clock_source.h"
38 #include "dce/dce_hwseq.h"
39 #include "dce/dce_i2c_hw.h"
40 #include "dce/dce_panel_cntl.h"
41 #include "dce/dmub_abm.h"
42 #include "dce/dmub_psr.h"
43 #include "clk_mgr.h"
44 
45 #include "hw_sequencer_private.h"
46 #include "reg_helper.h"
47 #include "resource.h"
48 #include "vm_helper.h"
49 
50 #include "sienna_cichlid_ip_offset.h"
51 #include "dcn/dcn_3_0_3_offset.h"
52 #include "dcn/dcn_3_0_3_sh_mask.h"
53 #include "dpcs/dpcs_3_0_3_offset.h"
54 #include "dpcs/dpcs_3_0_3_sh_mask.h"
55 #include "nbio/nbio_2_3_offset.h"
56 
57 #include "dml/dcn303/dcn303_fpu.h"
58 
59 #define DC_LOGGER_INIT(logger)
60 
61 
62 static const struct dc_debug_options debug_defaults_drv = {
63 		.disable_dmcu = true,
64 		.force_abm_enable = false,
65 		.timing_trace = false,
66 		.clock_trace = true,
67 		.disable_pplib_clock_request = true,
68 		.pipe_split_policy = MPC_SPLIT_DYNAMIC,
69 		.force_single_disp_pipe_split = false,
70 		.disable_dcc = DCC_ENABLE,
71 		.vsr_support = true,
72 		.performance_trace = false,
73 		.max_downscale_src_width = 7680,/*upto 8K*/
74 		.disable_pplib_wm_range = false,
75 		.scl_reset_length10 = true,
76 		.sanity_checks = false,
77 		.underflow_assert_delay_us = 0xFFFFFFFF,
78 		.dwb_fi_phase = -1, // -1 = disable,
79 		.dmub_command_table = true,
80 		.exit_idle_opt_for_cursor_updates = true,
81 		.disable_idle_power_optimizations = false,
82 };
83 
84 static const struct dc_debug_options debug_defaults_diags = {
85 		.disable_dmcu = true,
86 		.force_abm_enable = false,
87 		.timing_trace = true,
88 		.clock_trace = true,
89 		.disable_dpp_power_gate = true,
90 		.disable_hubp_power_gate = true,
91 		.disable_clock_gate = true,
92 		.disable_pplib_clock_request = true,
93 		.disable_pplib_wm_range = true,
94 		.disable_stutter = false,
95 		.scl_reset_length10 = true,
96 		.dwb_fi_phase = -1, // -1 = disable
97 		.dmub_command_table = true,
98 		.enable_tri_buf = true,
99 };
100 
101 static const struct dc_panel_config panel_config_defaults = {
102 		.psr = {
103 			.disable_psr = false,
104 			.disallow_psrsu = false,
105 		},
106 };
107 
108 enum dcn303_clk_src_array_id {
109 	DCN303_CLK_SRC_PLL0,
110 	DCN303_CLK_SRC_PLL1,
111 	DCN303_CLK_SRC_TOTAL
112 };
113 
114 static const struct resource_caps res_cap_dcn303 = {
115 		.num_timing_generator = 2,
116 		.num_opp = 2,
117 		.num_video_plane = 2,
118 		.num_audio = 2,
119 		.num_stream_encoder = 2,
120 		.num_dwb = 1,
121 		.num_ddc = 2,
122 		.num_vmid = 16,
123 		.num_mpc_3dlut = 1,
124 		.num_dsc = 2,
125 };
126 
127 static const struct dc_plane_cap plane_cap = {
128 		.type = DC_PLANE_TYPE_DCN_UNIVERSAL,
129 		.blends_with_above = true,
130 		.blends_with_below = true,
131 		.per_pixel_alpha = true,
132 		.pixel_format_support = {
133 				.argb8888 = true,
134 				.nv12 = true,
135 				.fp16 = true,
136 				.p010 = true,
137 				.ayuv = false,
138 		},
139 		.max_upscale_factor = {
140 				.argb8888 = 16000,
141 				.nv12 = 16000,
142 				.fp16 = 16000
143 		},
144 		.max_downscale_factor = {
145 				.argb8888 = 600,
146 				.nv12 = 600,
147 				.fp16 = 600
148 		},
149 		16,
150 		16
151 };
152 
153 /* NBIO */
154 #define NBIO_BASE_INNER(seg) \
155 		NBIO_BASE__INST0_SEG ## seg
156 
157 #define NBIO_BASE(seg) \
158 		NBIO_BASE_INNER(seg)
159 
160 #define NBIO_SR(reg_name)\
161 		.reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
162 		mm ## reg_name
163 
164 /* DCN */
165 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
166 
167 #define BASE(seg) BASE_INNER(seg)
168 
169 #define SR(reg_name)\
170 		.reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
171 
172 #define SF(reg_name, field_name, post_fix)\
173 		.field_name = reg_name ## __ ## field_name ## post_fix
174 
175 #define SRI(reg_name, block, id)\
176 		.reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + mm ## block ## id ## _ ## reg_name
177 
178 #define SRI2(reg_name, block, id)\
179 		.reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
180 
181 #define SRII(reg_name, block, id)\
182 		.reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
183 		mm ## block ## id ## _ ## reg_name
184 
185 #define DCCG_SRII(reg_name, block, id)\
186 		.block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
187 		mm ## block ## id ## _ ## reg_name
188 
189 #define VUPDATE_SRII(reg_name, block, id)\
190 		.reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
191 		mm ## reg_name ## _ ## block ## id
192 
193 #define SRII_DWB(reg_name, temp_name, block, id)\
194 		.reg_name[id] = BASE(mm ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
195 		mm ## block ## id ## _ ## temp_name
196 
197 #define SF_DWB2(reg_name, block, id, field_name, post_fix)	\
198 	.field_name = reg_name ## __ ## field_name ## post_fix
199 
200 #define SRII_MPC_RMU(reg_name, block, id)\
201 		.RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
202 		mm ## block ## id ## _ ## reg_name
203 
204 static const struct dcn_hubbub_registers hubbub_reg = {
205 		HUBBUB_REG_LIST_DCN30(0)
206 };
207 
208 static const struct dcn_hubbub_shift hubbub_shift = {
209 		HUBBUB_MASK_SH_LIST_DCN30(__SHIFT)
210 };
211 
212 static const struct dcn_hubbub_mask hubbub_mask = {
213 		HUBBUB_MASK_SH_LIST_DCN30(_MASK)
214 };
215 
216 #define vmid_regs(id)\
217 		[id] = { DCN20_VMID_REG_LIST(id) }
218 
219 static const struct dcn_vmid_registers vmid_regs[] = {
220 		vmid_regs(0),
221 		vmid_regs(1),
222 		vmid_regs(2),
223 		vmid_regs(3),
224 		vmid_regs(4),
225 		vmid_regs(5),
226 		vmid_regs(6),
227 		vmid_regs(7),
228 		vmid_regs(8),
229 		vmid_regs(9),
230 		vmid_regs(10),
231 		vmid_regs(11),
232 		vmid_regs(12),
233 		vmid_regs(13),
234 		vmid_regs(14),
235 		vmid_regs(15)
236 };
237 
238 static const struct dcn20_vmid_shift vmid_shifts = {
239 		DCN20_VMID_MASK_SH_LIST(__SHIFT)
240 };
241 
242 static const struct dcn20_vmid_mask vmid_masks = {
243 		DCN20_VMID_MASK_SH_LIST(_MASK)
244 };
245 
246 static struct hubbub *dcn303_hubbub_create(struct dc_context *ctx)
247 {
248 	int i;
249 
250 	struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub), GFP_KERNEL);
251 
252 	if (!hubbub3)
253 		return NULL;
254 
255 	hubbub3_construct(hubbub3, ctx, &hubbub_reg, &hubbub_shift, &hubbub_mask);
256 
257 	for (i = 0; i < res_cap_dcn303.num_vmid; i++) {
258 		struct dcn20_vmid *vmid = &hubbub3->vmid[i];
259 
260 		vmid->ctx = ctx;
261 
262 		vmid->regs = &vmid_regs[i];
263 		vmid->shifts = &vmid_shifts;
264 		vmid->masks = &vmid_masks;
265 	}
266 
267 	return &hubbub3->base;
268 }
269 
270 #define vpg_regs(id)\
271 		[id] = { VPG_DCN3_REG_LIST(id) }
272 
273 static const struct dcn30_vpg_registers vpg_regs[] = {
274 		vpg_regs(0),
275 		vpg_regs(1),
276 		vpg_regs(2)
277 };
278 
279 static const struct dcn30_vpg_shift vpg_shift = {
280 		DCN3_VPG_MASK_SH_LIST(__SHIFT)
281 };
282 
283 static const struct dcn30_vpg_mask vpg_mask = {
284 		DCN3_VPG_MASK_SH_LIST(_MASK)
285 };
286 
287 static struct vpg *dcn303_vpg_create(struct dc_context *ctx, uint32_t inst)
288 {
289 	struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL);
290 
291 	if (!vpg3)
292 		return NULL;
293 
294 	vpg3_construct(vpg3, ctx, inst, &vpg_regs[inst], &vpg_shift, &vpg_mask);
295 
296 	return &vpg3->base;
297 }
298 
299 #define afmt_regs(id)\
300 		[id] = { AFMT_DCN3_REG_LIST(id) }
301 
302 static const struct dcn30_afmt_registers afmt_regs[] = {
303 		afmt_regs(0),
304 		afmt_regs(1),
305 		afmt_regs(2)
306 };
307 
308 static const struct dcn30_afmt_shift afmt_shift = {
309 		DCN3_AFMT_MASK_SH_LIST(__SHIFT)
310 };
311 
312 static const struct dcn30_afmt_mask afmt_mask = {
313 		DCN3_AFMT_MASK_SH_LIST(_MASK)
314 };
315 
316 static struct afmt *dcn303_afmt_create(struct dc_context *ctx, uint32_t inst)
317 {
318 	struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL);
319 
320 	if (!afmt3)
321 		return NULL;
322 
323 	afmt3_construct(afmt3, ctx, inst, &afmt_regs[inst], &afmt_shift, &afmt_mask);
324 
325 	return &afmt3->base;
326 }
327 
328 #define audio_regs(id)\
329 		[id] = { AUD_COMMON_REG_LIST(id) }
330 
331 static const struct dce_audio_registers audio_regs[] = {
332 		audio_regs(0),
333 		audio_regs(1),
334 		audio_regs(2),
335 		audio_regs(3),
336 		audio_regs(4),
337 		audio_regs(5),
338 		audio_regs(6)
339 };
340 
341 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
342 		SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
343 		SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
344 		AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
345 
346 static const struct dce_audio_shift audio_shift = {
347 		DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
348 };
349 
350 static const struct dce_audio_mask audio_mask = {
351 		DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
352 };
353 
354 static struct audio *dcn303_create_audio(struct dc_context *ctx, unsigned int inst)
355 {
356 	return dce_audio_create(ctx, inst, &audio_regs[inst], &audio_shift, &audio_mask);
357 }
358 
359 #define stream_enc_regs(id)\
360 		[id] = { SE_DCN3_REG_LIST(id) }
361 
362 static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
363 		stream_enc_regs(0),
364 		stream_enc_regs(1)
365 };
366 
367 static const struct dcn10_stream_encoder_shift se_shift = {
368 		SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
369 };
370 
371 static const struct dcn10_stream_encoder_mask se_mask = {
372 		SE_COMMON_MASK_SH_LIST_DCN30(_MASK)
373 };
374 
375 static struct stream_encoder *dcn303_stream_encoder_create(enum engine_id eng_id, struct dc_context *ctx)
376 {
377 	struct dcn10_stream_encoder *enc1;
378 	struct vpg *vpg;
379 	struct afmt *afmt;
380 	int vpg_inst;
381 	int afmt_inst;
382 
383 	/* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
384 	if (eng_id <= ENGINE_ID_DIGB) {
385 		vpg_inst = eng_id;
386 		afmt_inst = eng_id;
387 	} else
388 		return NULL;
389 
390 	enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
391 	vpg = dcn303_vpg_create(ctx, vpg_inst);
392 	afmt = dcn303_afmt_create(ctx, afmt_inst);
393 
394 	if (!enc1 || !vpg || !afmt) {
395 		kfree(enc1);
396 		kfree(vpg);
397 		kfree(afmt);
398 		return NULL;
399 	}
400 
401 	dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id, vpg, afmt, &stream_enc_regs[eng_id],
402 			&se_shift, &se_mask);
403 
404 	return &enc1->base;
405 }
406 
407 #define clk_src_regs(index, pllid)\
408 		[index] = { CS_COMMON_REG_LIST_DCN3_03(index, pllid) }
409 
410 static const struct dce110_clk_src_regs clk_src_regs[] = {
411 		clk_src_regs(0, A),
412 		clk_src_regs(1, B)
413 };
414 
415 static const struct dce110_clk_src_shift cs_shift = {
416 		CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
417 };
418 
419 static const struct dce110_clk_src_mask cs_mask = {
420 		CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
421 };
422 
423 static struct clock_source *dcn303_clock_source_create(struct dc_context *ctx, struct dc_bios *bios,
424 		enum clock_source_id id, const struct dce110_clk_src_regs *regs, bool dp_clk_src)
425 {
426 	struct dce110_clk_src *clk_src = kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
427 
428 	if (!clk_src)
429 		return NULL;
430 
431 	if (dcn3_clk_src_construct(clk_src, ctx, bios, id, regs, &cs_shift, &cs_mask)) {
432 		clk_src->base.dp_clk_src = dp_clk_src;
433 		return &clk_src->base;
434 	}
435 
436 	kfree(clk_src);
437 	BREAK_TO_DEBUGGER();
438 	return NULL;
439 }
440 
441 static const struct dce_hwseq_registers hwseq_reg = {
442 		HWSEQ_DCN303_REG_LIST()
443 };
444 
445 static const struct dce_hwseq_shift hwseq_shift = {
446 		HWSEQ_DCN303_MASK_SH_LIST(__SHIFT)
447 };
448 
449 static const struct dce_hwseq_mask hwseq_mask = {
450 		HWSEQ_DCN303_MASK_SH_LIST(_MASK)
451 };
452 
453 static struct dce_hwseq *dcn303_hwseq_create(struct dc_context *ctx)
454 {
455 	struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
456 
457 	if (hws) {
458 		hws->ctx = ctx;
459 		hws->regs = &hwseq_reg;
460 		hws->shifts = &hwseq_shift;
461 		hws->masks = &hwseq_mask;
462 	}
463 	return hws;
464 }
465 
466 #define hubp_regs(id)\
467 		[id] = { HUBP_REG_LIST_DCN30(id) }
468 
469 static const struct dcn_hubp2_registers hubp_regs[] = {
470 		hubp_regs(0),
471 		hubp_regs(1)
472 };
473 
474 static const struct dcn_hubp2_shift hubp_shift = {
475 		HUBP_MASK_SH_LIST_DCN30(__SHIFT)
476 };
477 
478 static const struct dcn_hubp2_mask hubp_mask = {
479 		HUBP_MASK_SH_LIST_DCN30(_MASK)
480 };
481 
482 static struct hubp *dcn303_hubp_create(struct dc_context *ctx, uint32_t inst)
483 {
484 	struct dcn20_hubp *hubp2 = kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
485 
486 	if (!hubp2)
487 		return NULL;
488 
489 	if (hubp3_construct(hubp2, ctx, inst, &hubp_regs[inst], &hubp_shift, &hubp_mask))
490 		return &hubp2->base;
491 
492 	BREAK_TO_DEBUGGER();
493 	kfree(hubp2);
494 	return NULL;
495 }
496 
497 #define dpp_regs(id)\
498 		[id] = { DPP_REG_LIST_DCN30(id) }
499 
500 static const struct dcn3_dpp_registers dpp_regs[] = {
501 		dpp_regs(0),
502 		dpp_regs(1)
503 };
504 
505 static const struct dcn3_dpp_shift tf_shift = {
506 		DPP_REG_LIST_SH_MASK_DCN30(__SHIFT)
507 };
508 
509 static const struct dcn3_dpp_mask tf_mask = {
510 		DPP_REG_LIST_SH_MASK_DCN30(_MASK)
511 };
512 
513 static struct dpp *dcn303_dpp_create(struct dc_context *ctx, uint32_t inst)
514 {
515 	struct dcn3_dpp *dpp = kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);
516 
517 	if (!dpp)
518 		return NULL;
519 
520 	if (dpp3_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, &tf_mask))
521 		return &dpp->base;
522 
523 	BREAK_TO_DEBUGGER();
524 	kfree(dpp);
525 	return NULL;
526 }
527 
528 #define opp_regs(id)\
529 		[id] = { OPP_REG_LIST_DCN30(id) }
530 
531 static const struct dcn20_opp_registers opp_regs[] = {
532 		opp_regs(0),
533 		opp_regs(1)
534 };
535 
536 static const struct dcn20_opp_shift opp_shift = {
537 		OPP_MASK_SH_LIST_DCN20(__SHIFT)
538 };
539 
540 static const struct dcn20_opp_mask opp_mask = {
541 		OPP_MASK_SH_LIST_DCN20(_MASK)
542 };
543 
544 static struct output_pixel_processor *dcn303_opp_create(struct dc_context *ctx, uint32_t inst)
545 {
546 	struct dcn20_opp *opp = kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
547 
548 	if (!opp) {
549 		BREAK_TO_DEBUGGER();
550 		return NULL;
551 	}
552 
553 	dcn20_opp_construct(opp, ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);
554 	return &opp->base;
555 }
556 
557 #define optc_regs(id)\
558 		[id] = { OPTC_COMMON_REG_LIST_DCN3_0(id) }
559 
560 static const struct dcn_optc_registers optc_regs[] = {
561 		optc_regs(0),
562 		optc_regs(1)
563 };
564 
565 static const struct dcn_optc_shift optc_shift = {
566 		OPTC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
567 };
568 
569 static const struct dcn_optc_mask optc_mask = {
570 		OPTC_COMMON_MASK_SH_LIST_DCN30(_MASK)
571 };
572 
573 static struct timing_generator *dcn303_timing_generator_create(struct dc_context *ctx, uint32_t instance)
574 {
575 	struct optc *tgn10 = kzalloc(sizeof(struct optc), GFP_KERNEL);
576 
577 	if (!tgn10)
578 		return NULL;
579 
580 	tgn10->base.inst = instance;
581 	tgn10->base.ctx = ctx;
582 
583 	tgn10->tg_regs = &optc_regs[instance];
584 	tgn10->tg_shift = &optc_shift;
585 	tgn10->tg_mask = &optc_mask;
586 
587 	dcn30_timing_generator_init(tgn10);
588 
589 	return &tgn10->base;
590 }
591 
592 static const struct dcn30_mpc_registers mpc_regs = {
593 		MPC_REG_LIST_DCN3_0(0),
594 		MPC_REG_LIST_DCN3_0(1),
595 		MPC_OUT_MUX_REG_LIST_DCN3_0(0),
596 		MPC_OUT_MUX_REG_LIST_DCN3_0(1),
597 		MPC_RMU_GLOBAL_REG_LIST_DCN3AG,
598 		MPC_RMU_REG_LIST_DCN3AG(0),
599 		MPC_DWB_MUX_REG_LIST_DCN3_0(0),
600 };
601 
602 static const struct dcn30_mpc_shift mpc_shift = {
603 		MPC_COMMON_MASK_SH_LIST_DCN303(__SHIFT)
604 };
605 
606 static const struct dcn30_mpc_mask mpc_mask = {
607 		MPC_COMMON_MASK_SH_LIST_DCN303(_MASK)
608 };
609 
610 static struct mpc *dcn303_mpc_create(struct dc_context *ctx, int num_mpcc, int num_rmu)
611 {
612 	struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), GFP_KERNEL);
613 
614 	if (!mpc30)
615 		return NULL;
616 
617 	dcn30_mpc_construct(mpc30, ctx, &mpc_regs, &mpc_shift, &mpc_mask, num_mpcc, num_rmu);
618 
619 	return &mpc30->base;
620 }
621 
622 #define dsc_regsDCN20(id)\
623 [id] = { DSC_REG_LIST_DCN20(id) }
624 
625 static const struct dcn20_dsc_registers dsc_regs[] = {
626 		dsc_regsDCN20(0),
627 		dsc_regsDCN20(1)
628 };
629 
630 static const struct dcn20_dsc_shift dsc_shift = {
631 		DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
632 };
633 
634 static const struct dcn20_dsc_mask dsc_mask = {
635 		DSC_REG_LIST_SH_MASK_DCN20(_MASK)
636 };
637 
638 static struct display_stream_compressor *dcn303_dsc_create(struct dc_context *ctx, uint32_t inst)
639 {
640 	struct dcn20_dsc *dsc = kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
641 
642 	if (!dsc) {
643 		BREAK_TO_DEBUGGER();
644 		return NULL;
645 	}
646 
647 	dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
648 	return &dsc->base;
649 }
650 
651 #define dwbc_regs_dcn3(id)\
652 [id] = { DWBC_COMMON_REG_LIST_DCN30(id) }
653 
654 static const struct dcn30_dwbc_registers dwbc30_regs[] = {
655 		dwbc_regs_dcn3(0)
656 };
657 
658 static const struct dcn30_dwbc_shift dwbc30_shift = {
659 		DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
660 };
661 
662 static const struct dcn30_dwbc_mask dwbc30_mask = {
663 		DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
664 };
665 
666 static bool dcn303_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
667 {
668 	int i;
669 	uint32_t pipe_count = pool->res_cap->num_dwb;
670 
671 	for (i = 0; i < pipe_count; i++) {
672 		struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), GFP_KERNEL);
673 
674 		if (!dwbc30) {
675 			dm_error("DC: failed to create dwbc30!\n");
676 			return false;
677 		}
678 
679 		dcn30_dwbc_construct(dwbc30, ctx, &dwbc30_regs[i], &dwbc30_shift, &dwbc30_mask, i);
680 
681 		pool->dwbc[i] = &dwbc30->base;
682 	}
683 	return true;
684 }
685 
686 #define mcif_wb_regs_dcn3(id)\
687 [id] = { MCIF_WB_COMMON_REG_LIST_DCN30(id) }
688 
689 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = {
690 		mcif_wb_regs_dcn3(0)
691 };
692 
693 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
694 		MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
695 };
696 
697 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
698 		MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK)
699 };
700 
701 static bool dcn303_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
702 {
703 	int i;
704 	uint32_t pipe_count = pool->res_cap->num_dwb;
705 
706 	for (i = 0; i < pipe_count; i++) {
707 		struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), GFP_KERNEL);
708 
709 		if (!mcif_wb30) {
710 			dm_error("DC: failed to create mcif_wb30!\n");
711 			return false;
712 		}
713 
714 		dcn30_mmhubbub_construct(mcif_wb30, ctx, &mcif_wb30_regs[i], &mcif_wb30_shift, &mcif_wb30_mask, i);
715 
716 		pool->mcif_wb[i] = &mcif_wb30->base;
717 	}
718 	return true;
719 }
720 
721 #define aux_engine_regs(id)\
722 [id] = {\
723 		AUX_COMMON_REG_LIST0(id), \
724 		.AUXN_IMPCAL = 0, \
725 		.AUXP_IMPCAL = 0, \
726 		.AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
727 }
728 
729 static const struct dce110_aux_registers aux_engine_regs[] = {
730 		aux_engine_regs(0),
731 		aux_engine_regs(1)
732 };
733 
734 static const struct dce110_aux_registers_shift aux_shift = {
735 		DCN_AUX_MASK_SH_LIST(__SHIFT)
736 };
737 
738 static const struct dce110_aux_registers_mask aux_mask = {
739 		DCN_AUX_MASK_SH_LIST(_MASK)
740 };
741 
742 static struct dce_aux *dcn303_aux_engine_create(struct dc_context *ctx, uint32_t inst)
743 {
744 	struct aux_engine_dce110 *aux_engine = kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
745 
746 	if (!aux_engine)
747 		return NULL;
748 
749 	dce110_aux_engine_construct(aux_engine, ctx, inst, SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
750 			&aux_engine_regs[inst], &aux_mask, &aux_shift, ctx->dc->caps.extended_aux_timeout_support);
751 
752 	return &aux_engine->base;
753 }
754 
755 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
756 
757 static const struct dce_i2c_registers i2c_hw_regs[] = {
758 		i2c_inst_regs(1),
759 		i2c_inst_regs(2)
760 };
761 
762 static const struct dce_i2c_shift i2c_shifts = {
763 		I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT)
764 };
765 
766 static const struct dce_i2c_mask i2c_masks = {
767 		I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)
768 };
769 
770 static struct dce_i2c_hw *dcn303_i2c_hw_create(struct dc_context *ctx, uint32_t inst)
771 {
772 	struct dce_i2c_hw *dce_i2c_hw = kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
773 
774 	if (!dce_i2c_hw)
775 		return NULL;
776 
777 	dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
778 
779 	return dce_i2c_hw;
780 }
781 
782 static const struct encoder_feature_support link_enc_feature = {
783 		.max_hdmi_deep_color = COLOR_DEPTH_121212,
784 		.max_hdmi_pixel_clock = 600000,
785 		.hdmi_ycbcr420_supported = true,
786 		.dp_ycbcr420_supported = true,
787 		.fec_supported = true,
788 		.flags.bits.IS_HBR2_CAPABLE = true,
789 		.flags.bits.IS_HBR3_CAPABLE = true,
790 		.flags.bits.IS_TPS3_CAPABLE = true,
791 		.flags.bits.IS_TPS4_CAPABLE = true
792 };
793 
794 #define link_regs(id, phyid)\
795 		[id] = {\
796 				LE_DCN3_REG_LIST(id), \
797 				UNIPHY_DCN2_REG_LIST(phyid), \
798 				SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
799 		}
800 
801 static const struct dcn10_link_enc_registers link_enc_regs[] = {
802 		link_regs(0, A),
803 		link_regs(1, B)
804 };
805 
806 static const struct dcn10_link_enc_shift le_shift = {
807 		LINK_ENCODER_MASK_SH_LIST_DCN30(__SHIFT),
808 		DPCS_DCN2_MASK_SH_LIST(__SHIFT)
809 };
810 
811 static const struct dcn10_link_enc_mask le_mask = {
812 		LINK_ENCODER_MASK_SH_LIST_DCN30(_MASK),
813 		DPCS_DCN2_MASK_SH_LIST(_MASK)
814 };
815 
816 #define aux_regs(id)\
817 		[id] = { DCN2_AUX_REG_LIST(id) }
818 
819 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
820 		aux_regs(0),
821 		aux_regs(1)
822 };
823 
824 #define hpd_regs(id)\
825 		[id] = { HPD_REG_LIST(id) }
826 
827 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
828 		hpd_regs(0),
829 		hpd_regs(1)
830 };
831 
832 static struct link_encoder *dcn303_link_encoder_create(
833 	struct dc_context *ctx,
834 	const struct encoder_init_data *enc_init_data)
835 {
836 	struct dcn20_link_encoder *enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
837 
838 	if (!enc20)
839 		return NULL;
840 
841 	dcn30_link_encoder_construct(enc20, enc_init_data, &link_enc_feature,
842 			&link_enc_regs[enc_init_data->transmitter], &link_enc_aux_regs[enc_init_data->channel - 1],
843 			&link_enc_hpd_regs[enc_init_data->hpd_source], &le_shift, &le_mask);
844 
845 	return &enc20->enc10.base;
846 }
847 
848 static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
849 		{ DCN_PANEL_CNTL_REG_LIST() }
850 };
851 
852 static const struct dce_panel_cntl_shift panel_cntl_shift = {
853 		DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
854 };
855 
856 static const struct dce_panel_cntl_mask panel_cntl_mask = {
857 		DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
858 };
859 
860 static struct panel_cntl *dcn303_panel_cntl_create(const struct panel_cntl_init_data *init_data)
861 {
862 	struct dce_panel_cntl *panel_cntl = kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
863 
864 	if (!panel_cntl)
865 		return NULL;
866 
867 	dce_panel_cntl_construct(panel_cntl, init_data, &panel_cntl_regs[init_data->inst],
868 			&panel_cntl_shift, &panel_cntl_mask);
869 
870 	return &panel_cntl->base;
871 }
872 
873 static void read_dce_straps(struct dc_context *ctx, struct resource_straps *straps)
874 {
875 	generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
876 			FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
877 }
878 
879 static const struct resource_create_funcs res_create_funcs = {
880 		.read_dce_straps = read_dce_straps,
881 		.create_audio = dcn303_create_audio,
882 		.create_stream_encoder = dcn303_stream_encoder_create,
883 		.create_hwseq = dcn303_hwseq_create,
884 };
885 
886 static const struct resource_create_funcs res_create_maximus_funcs = {
887 		.read_dce_straps = NULL,
888 		.create_audio = NULL,
889 		.create_stream_encoder = NULL,
890 		.create_hwseq = dcn303_hwseq_create,
891 };
892 
893 static bool is_soc_bounding_box_valid(struct dc *dc)
894 {
895 	uint32_t hw_internal_rev = dc->ctx->asic_id.hw_internal_rev;
896 
897 	if (ASICREV_IS_BEIGE_GOBY_P(hw_internal_rev))
898 		return true;
899 
900 	return false;
901 }
902 
903 static bool init_soc_bounding_box(struct dc *dc,  struct resource_pool *pool)
904 {
905 	struct _vcs_dpi_soc_bounding_box_st *loaded_bb = &dcn3_03_soc;
906 	struct _vcs_dpi_ip_params_st *loaded_ip = &dcn3_03_ip;
907 
908 	DC_LOGGER_INIT(dc->ctx->logger);
909 
910 	if (!is_soc_bounding_box_valid(dc)) {
911 		DC_LOG_ERROR("%s: not valid soc bounding box/n", __func__);
912 		return false;
913 	}
914 
915 	loaded_ip->max_num_otg = pool->pipe_count;
916 	loaded_ip->max_num_dpp = pool->pipe_count;
917 	loaded_ip->clamp_min_dcfclk = dc->config.clamp_min_dcfclk;
918 	DC_FP_START();
919 	dcn20_patch_bounding_box(dc, loaded_bb);
920 	DC_FP_END();
921 
922 	if (dc->ctx->dc_bios->funcs->get_soc_bb_info) {
923 		struct bp_soc_bb_info bb_info = { 0 };
924 
925 		if (dc->ctx->dc_bios->funcs->get_soc_bb_info(
926 			    dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) {
927 					DC_FP_START();
928 					dcn303_fpu_init_soc_bounding_box(bb_info);
929 					DC_FP_END();
930 		}
931 	}
932 
933 	return true;
934 }
935 
936 static void dcn303_resource_destruct(struct resource_pool *pool)
937 {
938 	unsigned int i;
939 
940 	for (i = 0; i < pool->stream_enc_count; i++) {
941 		if (pool->stream_enc[i] != NULL) {
942 			if (pool->stream_enc[i]->vpg != NULL) {
943 				kfree(DCN30_VPG_FROM_VPG(pool->stream_enc[i]->vpg));
944 				pool->stream_enc[i]->vpg = NULL;
945 			}
946 			if (pool->stream_enc[i]->afmt != NULL) {
947 				kfree(DCN30_AFMT_FROM_AFMT(pool->stream_enc[i]->afmt));
948 				pool->stream_enc[i]->afmt = NULL;
949 			}
950 			kfree(DCN10STRENC_FROM_STRENC(pool->stream_enc[i]));
951 			pool->stream_enc[i] = NULL;
952 		}
953 	}
954 
955 	for (i = 0; i < pool->res_cap->num_dsc; i++) {
956 		if (pool->dscs[i] != NULL)
957 			dcn20_dsc_destroy(&pool->dscs[i]);
958 	}
959 
960 	if (pool->mpc != NULL) {
961 		kfree(TO_DCN20_MPC(pool->mpc));
962 		pool->mpc = NULL;
963 	}
964 
965 	if (pool->hubbub != NULL) {
966 		kfree(pool->hubbub);
967 		pool->hubbub = NULL;
968 	}
969 
970 	for (i = 0; i < pool->pipe_count; i++) {
971 		if (pool->dpps[i] != NULL) {
972 			kfree(TO_DCN20_DPP(pool->dpps[i]));
973 			pool->dpps[i] = NULL;
974 		}
975 
976 		if (pool->hubps[i] != NULL) {
977 			kfree(TO_DCN20_HUBP(pool->hubps[i]));
978 			pool->hubps[i] = NULL;
979 		}
980 
981 		if (pool->irqs != NULL)
982 			dal_irq_service_destroy(&pool->irqs);
983 	}
984 
985 	for (i = 0; i < pool->res_cap->num_ddc; i++) {
986 		if (pool->engines[i] != NULL)
987 			dce110_engine_destroy(&pool->engines[i]);
988 		if (pool->hw_i2cs[i] != NULL) {
989 			kfree(pool->hw_i2cs[i]);
990 			pool->hw_i2cs[i] = NULL;
991 		}
992 		if (pool->sw_i2cs[i] != NULL) {
993 			kfree(pool->sw_i2cs[i]);
994 			pool->sw_i2cs[i] = NULL;
995 		}
996 	}
997 
998 	for (i = 0; i < pool->res_cap->num_opp; i++) {
999 		if (pool->opps[i] != NULL)
1000 			pool->opps[i]->funcs->opp_destroy(&pool->opps[i]);
1001 	}
1002 
1003 	for (i = 0; i < pool->res_cap->num_timing_generator; i++) {
1004 		if (pool->timing_generators[i] != NULL)	{
1005 			kfree(DCN10TG_FROM_TG(pool->timing_generators[i]));
1006 			pool->timing_generators[i] = NULL;
1007 		}
1008 	}
1009 
1010 	for (i = 0; i < pool->res_cap->num_dwb; i++) {
1011 		if (pool->dwbc[i] != NULL) {
1012 			kfree(TO_DCN30_DWBC(pool->dwbc[i]));
1013 			pool->dwbc[i] = NULL;
1014 		}
1015 		if (pool->mcif_wb[i] != NULL) {
1016 			kfree(TO_DCN30_MMHUBBUB(pool->mcif_wb[i]));
1017 			pool->mcif_wb[i] = NULL;
1018 		}
1019 	}
1020 
1021 	for (i = 0; i < pool->audio_count; i++) {
1022 		if (pool->audios[i])
1023 			dce_aud_destroy(&pool->audios[i]);
1024 	}
1025 
1026 	for (i = 0; i < pool->clk_src_count; i++) {
1027 		if (pool->clock_sources[i] != NULL)
1028 			dcn20_clock_source_destroy(&pool->clock_sources[i]);
1029 	}
1030 
1031 	if (pool->dp_clock_source != NULL)
1032 		dcn20_clock_source_destroy(&pool->dp_clock_source);
1033 
1034 	for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) {
1035 		if (pool->mpc_lut[i] != NULL) {
1036 			dc_3dlut_func_release(pool->mpc_lut[i]);
1037 			pool->mpc_lut[i] = NULL;
1038 		}
1039 		if (pool->mpc_shaper[i] != NULL) {
1040 			dc_transfer_func_release(pool->mpc_shaper[i]);
1041 			pool->mpc_shaper[i] = NULL;
1042 		}
1043 	}
1044 
1045 	for (i = 0; i < pool->pipe_count; i++) {
1046 		if (pool->multiple_abms[i] != NULL)
1047 			dce_abm_destroy(&pool->multiple_abms[i]);
1048 	}
1049 
1050 	if (pool->psr != NULL)
1051 		dmub_psr_destroy(&pool->psr);
1052 
1053 	if (pool->dccg != NULL)
1054 		dcn_dccg_destroy(&pool->dccg);
1055 
1056 	if (pool->oem_device != NULL)
1057 		dal_ddc_service_destroy(&pool->oem_device);
1058 }
1059 
1060 static void dcn303_destroy_resource_pool(struct resource_pool **pool)
1061 {
1062 	dcn303_resource_destruct(*pool);
1063 	kfree(*pool);
1064 	*pool = NULL;
1065 }
1066 
1067 static void dcn303_get_panel_config_defaults(struct dc_panel_config *panel_config)
1068 {
1069 	*panel_config = panel_config_defaults;
1070 }
1071 
1072 void dcn303_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
1073 {
1074 	DC_FP_START();
1075 	dcn303_fpu_update_bw_bounding_box(dc, bw_params);
1076 	DC_FP_END();
1077 }
1078 
1079 static struct resource_funcs dcn303_res_pool_funcs = {
1080 		.destroy = dcn303_destroy_resource_pool,
1081 		.link_enc_create = dcn303_link_encoder_create,
1082 		.panel_cntl_create = dcn303_panel_cntl_create,
1083 		.validate_bandwidth = dcn30_validate_bandwidth,
1084 		.calculate_wm_and_dlg = dcn30_calculate_wm_and_dlg,
1085 		.update_soc_for_wm_a = dcn30_update_soc_for_wm_a,
1086 		.populate_dml_pipes = dcn30_populate_dml_pipes_from_context,
1087 		.acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
1088 		.add_stream_to_ctx = dcn30_add_stream_to_ctx,
1089 		.add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
1090 		.remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1091 		.populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
1092 		.set_mcif_arb_params = dcn30_set_mcif_arb_params,
1093 		.find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1094 		.acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
1095 		.release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
1096 		.update_bw_bounding_box = dcn303_update_bw_bounding_box,
1097 		.patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
1098 		.get_panel_config_defaults = dcn303_get_panel_config_defaults,
1099 };
1100 
1101 static struct dc_cap_funcs cap_funcs = {
1102 		.get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1103 };
1104 
1105 static const struct bios_registers bios_regs = {
1106 		NBIO_SR(BIOS_SCRATCH_3),
1107 		NBIO_SR(BIOS_SCRATCH_6)
1108 };
1109 
1110 static const struct dccg_registers dccg_regs = {
1111 		DCCG_REG_LIST_DCN3_03()
1112 };
1113 
1114 static const struct dccg_shift dccg_shift = {
1115 		DCCG_MASK_SH_LIST_DCN3_03(__SHIFT)
1116 };
1117 
1118 static const struct dccg_mask dccg_mask = {
1119 		DCCG_MASK_SH_LIST_DCN3_03(_MASK)
1120 };
1121 
1122 #define abm_regs(id)\
1123 		[id] = { ABM_DCN302_REG_LIST(id) }
1124 
1125 static const struct dce_abm_registers abm_regs[] = {
1126 		abm_regs(0),
1127 		abm_regs(1)
1128 };
1129 
1130 static const struct dce_abm_shift abm_shift = {
1131 		ABM_MASK_SH_LIST_DCN30(__SHIFT)
1132 };
1133 
1134 static const struct dce_abm_mask abm_mask = {
1135 		ABM_MASK_SH_LIST_DCN30(_MASK)
1136 };
1137 
1138 static bool dcn303_resource_construct(
1139 		uint8_t num_virtual_links,
1140 		struct dc *dc,
1141 		struct resource_pool *pool)
1142 {
1143 	int i;
1144 	struct dc_context *ctx = dc->ctx;
1145 	struct irq_service_init_data init_data;
1146 	struct ddc_service_init_data ddc_init_data;
1147 
1148 	ctx->dc_bios->regs = &bios_regs;
1149 
1150 	pool->res_cap = &res_cap_dcn303;
1151 
1152 	pool->funcs = &dcn303_res_pool_funcs;
1153 
1154 	/*************************************************
1155 	 *  Resource + asic cap harcoding                *
1156 	 *************************************************/
1157 	pool->underlay_pipe_index = NO_UNDERLAY_PIPE;
1158 	pool->pipe_count = pool->res_cap->num_timing_generator;
1159 	pool->mpcc_count = pool->res_cap->num_timing_generator;
1160 	dc->caps.max_downscale_ratio = 600;
1161 	dc->caps.i2c_speed_in_khz = 100;
1162 	dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by derfault*/
1163 	dc->caps.max_cursor_size = 256;
1164 	dc->caps.min_horizontal_blanking_period = 80;
1165 	dc->caps.dmdata_alloc_size = 2048;
1166 #if defined(CONFIG_DRM_AMD_DC_DCN)
1167 	dc->caps.mall_size_per_mem_channel = 4;
1168 	/* total size = mall per channel * num channels * 1024 * 1024 */
1169 	dc->caps.mall_size_total = dc->caps.mall_size_per_mem_channel *
1170 				   dc->ctx->dc_bios->vram_info.num_chans *
1171 				   1024 * 1024;
1172 	dc->caps.cursor_cache_size =
1173 		dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8;
1174 #endif
1175 	dc->caps.max_slave_planes = 1;
1176 	dc->caps.post_blend_color_processing = true;
1177 	dc->caps.force_dp_tps4_for_cp2520 = true;
1178 	dc->caps.extended_aux_timeout_support = true;
1179 	dc->caps.dmcub_support = true;
1180 
1181 	/* Color pipeline capabilities */
1182 	dc->caps.color.dpp.dcn_arch = 1;
1183 	dc->caps.color.dpp.input_lut_shared = 0;
1184 	dc->caps.color.dpp.icsc = 1;
1185 	dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
1186 	dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1187 	dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1188 	dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
1189 	dc->caps.color.dpp.dgam_rom_caps.pq = 1;
1190 	dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
1191 	dc->caps.color.dpp.post_csc = 1;
1192 	dc->caps.color.dpp.gamma_corr = 1;
1193 	dc->caps.color.dpp.dgam_rom_for_yuv = 0;
1194 
1195 	dc->caps.color.dpp.hw_3d_lut = 1;
1196 	dc->caps.color.dpp.ogam_ram = 1;
1197 	// no OGAM ROM on DCN3
1198 	dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
1199 	dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
1200 	dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
1201 	dc->caps.color.dpp.ogam_rom_caps.pq = 0;
1202 	dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
1203 	dc->caps.color.dpp.ocsc = 0;
1204 
1205 	dc->caps.color.mpc.gamut_remap = 1;
1206 	dc->caps.color.mpc.num_3dluts = pool->res_cap->num_mpc_3dlut; //3
1207 	dc->caps.color.mpc.ogam_ram = 1;
1208 	dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
1209 	dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
1210 	dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
1211 	dc->caps.color.mpc.ogam_rom_caps.pq = 0;
1212 	dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1213 	dc->caps.color.mpc.ocsc = 1;
1214 
1215 	dc->caps.dp_hdmi21_pcon_support = true;
1216 
1217 	/* read VBIOS LTTPR caps */
1218 	if (ctx->dc_bios->funcs->get_lttpr_caps) {
1219 		enum bp_result bp_query_result;
1220 		uint8_t is_vbios_lttpr_enable = 0;
1221 
1222 		bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
1223 		dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
1224 	}
1225 
1226 	if (ctx->dc_bios->funcs->get_lttpr_interop) {
1227 		enum bp_result bp_query_result;
1228 		uint8_t is_vbios_interop_enabled = 0;
1229 
1230 		bp_query_result = ctx->dc_bios->funcs->get_lttpr_interop(ctx->dc_bios, &is_vbios_interop_enabled);
1231 		dc->caps.vbios_lttpr_aware = (bp_query_result == BP_RESULT_OK) && !!is_vbios_interop_enabled;
1232 	}
1233 
1234 	if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1235 		dc->debug = debug_defaults_drv;
1236 	else
1237 		dc->debug = debug_defaults_diags;
1238 
1239 	// Init the vm_helper
1240 	if (dc->vm_helper)
1241 		vm_helper_init(dc->vm_helper, 16);
1242 
1243 	/*************************************************
1244 	 *  Create resources                             *
1245 	 *************************************************/
1246 
1247 	/* Clock Sources for Pixel Clock*/
1248 	pool->clock_sources[DCN303_CLK_SRC_PLL0] =
1249 			dcn303_clock_source_create(ctx, ctx->dc_bios,
1250 					CLOCK_SOURCE_COMBO_PHY_PLL0,
1251 					&clk_src_regs[0], false);
1252 	pool->clock_sources[DCN303_CLK_SRC_PLL1] =
1253 			dcn303_clock_source_create(ctx, ctx->dc_bios,
1254 					CLOCK_SOURCE_COMBO_PHY_PLL1,
1255 					&clk_src_regs[1], false);
1256 
1257 	pool->clk_src_count = DCN303_CLK_SRC_TOTAL;
1258 
1259 	/* todo: not reuse phy_pll registers */
1260 	pool->dp_clock_source =
1261 			dcn303_clock_source_create(ctx, ctx->dc_bios,
1262 					CLOCK_SOURCE_ID_DP_DTO,
1263 					&clk_src_regs[0], true);
1264 
1265 	for (i = 0; i < pool->clk_src_count; i++) {
1266 		if (pool->clock_sources[i] == NULL) {
1267 			dm_error("DC: failed to create clock sources!\n");
1268 			BREAK_TO_DEBUGGER();
1269 			goto create_fail;
1270 		}
1271 	}
1272 
1273 	/* DCCG */
1274 	pool->dccg = dccg30_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
1275 	if (pool->dccg == NULL) {
1276 		dm_error("DC: failed to create dccg!\n");
1277 		BREAK_TO_DEBUGGER();
1278 		goto create_fail;
1279 	}
1280 
1281 	/* PP Lib and SMU interfaces */
1282 	init_soc_bounding_box(dc, pool);
1283 
1284 	/* DML */
1285 	dml_init_instance(&dc->dml, &dcn3_03_soc, &dcn3_03_ip, DML_PROJECT_DCN30);
1286 
1287 	/* IRQ */
1288 	init_data.ctx = dc->ctx;
1289 	pool->irqs = dal_irq_service_dcn303_create(&init_data);
1290 	if (!pool->irqs)
1291 		goto create_fail;
1292 
1293 	/* HUBBUB */
1294 	pool->hubbub = dcn303_hubbub_create(ctx);
1295 	if (pool->hubbub == NULL) {
1296 		BREAK_TO_DEBUGGER();
1297 		dm_error("DC: failed to create hubbub!\n");
1298 		goto create_fail;
1299 	}
1300 
1301 	/* HUBPs, DPPs, OPPs and TGs */
1302 	for (i = 0; i < pool->pipe_count; i++) {
1303 		pool->hubps[i] = dcn303_hubp_create(ctx, i);
1304 		if (pool->hubps[i] == NULL) {
1305 			BREAK_TO_DEBUGGER();
1306 			dm_error("DC: failed to create hubps!\n");
1307 			goto create_fail;
1308 		}
1309 
1310 		pool->dpps[i] = dcn303_dpp_create(ctx, i);
1311 		if (pool->dpps[i] == NULL) {
1312 			BREAK_TO_DEBUGGER();
1313 			dm_error("DC: failed to create dpps!\n");
1314 			goto create_fail;
1315 		}
1316 	}
1317 
1318 	for (i = 0; i < pool->res_cap->num_opp; i++) {
1319 		pool->opps[i] = dcn303_opp_create(ctx, i);
1320 		if (pool->opps[i] == NULL) {
1321 			BREAK_TO_DEBUGGER();
1322 			dm_error("DC: failed to create output pixel processor!\n");
1323 			goto create_fail;
1324 		}
1325 	}
1326 
1327 	for (i = 0; i < pool->res_cap->num_timing_generator; i++) {
1328 		pool->timing_generators[i] = dcn303_timing_generator_create(ctx, i);
1329 		if (pool->timing_generators[i] == NULL) {
1330 			BREAK_TO_DEBUGGER();
1331 			dm_error("DC: failed to create tg!\n");
1332 			goto create_fail;
1333 		}
1334 	}
1335 	pool->timing_generator_count = i;
1336 
1337 	/* PSR */
1338 	pool->psr = dmub_psr_create(ctx);
1339 	if (pool->psr == NULL) {
1340 		dm_error("DC: failed to create psr!\n");
1341 		BREAK_TO_DEBUGGER();
1342 		goto create_fail;
1343 	}
1344 
1345 	/* ABM */
1346 	for (i = 0; i < pool->res_cap->num_timing_generator; i++) {
1347 		pool->multiple_abms[i] = dmub_abm_create(ctx, &abm_regs[i], &abm_shift, &abm_mask);
1348 		if (pool->multiple_abms[i] == NULL) {
1349 			dm_error("DC: failed to create abm for pipe %d!\n", i);
1350 			BREAK_TO_DEBUGGER();
1351 			goto create_fail;
1352 		}
1353 	}
1354 
1355 	/* MPC and DSC */
1356 	pool->mpc = dcn303_mpc_create(ctx, pool->mpcc_count, pool->res_cap->num_mpc_3dlut);
1357 	if (pool->mpc == NULL) {
1358 		BREAK_TO_DEBUGGER();
1359 		dm_error("DC: failed to create mpc!\n");
1360 		goto create_fail;
1361 	}
1362 
1363 	for (i = 0; i < pool->res_cap->num_dsc; i++) {
1364 		pool->dscs[i] = dcn303_dsc_create(ctx, i);
1365 		if (pool->dscs[i] == NULL) {
1366 			BREAK_TO_DEBUGGER();
1367 			dm_error("DC: failed to create display stream compressor %d!\n", i);
1368 			goto create_fail;
1369 		}
1370 	}
1371 
1372 	/* DWB and MMHUBBUB */
1373 	if (!dcn303_dwbc_create(ctx, pool)) {
1374 		BREAK_TO_DEBUGGER();
1375 		dm_error("DC: failed to create dwbc!\n");
1376 		goto create_fail;
1377 	}
1378 
1379 	if (!dcn303_mmhubbub_create(ctx, pool)) {
1380 		BREAK_TO_DEBUGGER();
1381 		dm_error("DC: failed to create mcif_wb!\n");
1382 		goto create_fail;
1383 	}
1384 
1385 	/* AUX and I2C */
1386 	for (i = 0; i < pool->res_cap->num_ddc; i++) {
1387 		pool->engines[i] = dcn303_aux_engine_create(ctx, i);
1388 		if (pool->engines[i] == NULL) {
1389 			BREAK_TO_DEBUGGER();
1390 			dm_error("DC:failed to create aux engine!!\n");
1391 			goto create_fail;
1392 		}
1393 		pool->hw_i2cs[i] = dcn303_i2c_hw_create(ctx, i);
1394 		if (pool->hw_i2cs[i] == NULL) {
1395 			BREAK_TO_DEBUGGER();
1396 			dm_error("DC:failed to create hw i2c!!\n");
1397 			goto create_fail;
1398 		}
1399 		pool->sw_i2cs[i] = NULL;
1400 	}
1401 
1402 	/* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */
1403 	if (!resource_construct(num_virtual_links, dc, pool,
1404 			(!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
1405 					&res_create_funcs : &res_create_maximus_funcs)))
1406 		goto create_fail;
1407 
1408 	/* HW Sequencer and Plane caps */
1409 	dcn303_hw_sequencer_construct(dc);
1410 
1411 	dc->caps.max_planes =  pool->pipe_count;
1412 
1413 	for (i = 0; i < dc->caps.max_planes; ++i)
1414 		dc->caps.planes[i] = plane_cap;
1415 
1416 	dc->cap_funcs = cap_funcs;
1417 
1418 	if (dc->ctx->dc_bios->fw_info.oem_i2c_present) {
1419 		ddc_init_data.ctx = dc->ctx;
1420 		ddc_init_data.link = NULL;
1421 		ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id;
1422 		ddc_init_data.id.enum_id = 0;
1423 		ddc_init_data.id.type = OBJECT_TYPE_GENERIC;
1424 		pool->oem_device = dal_ddc_service_create(&ddc_init_data);
1425 	} else {
1426 		pool->oem_device = NULL;
1427 	}
1428 
1429 	return true;
1430 
1431 create_fail:
1432 
1433 	dcn303_resource_destruct(pool);
1434 
1435 	return false;
1436 }
1437 
1438 struct resource_pool *dcn303_create_resource_pool(const struct dc_init_data *init_data, struct dc *dc)
1439 {
1440 	struct resource_pool *pool = kzalloc(sizeof(struct resource_pool), GFP_KERNEL);
1441 
1442 	if (!pool)
1443 		return NULL;
1444 
1445 	if (dcn303_resource_construct(init_data->num_virtual_links, dc, pool))
1446 		return pool;
1447 
1448 	BREAK_TO_DEBUGGER();
1449 	kfree(pool);
1450 	return NULL;
1451 }
1452