1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dcn303_init.h" 27 #include "dcn303_resource.h" 28 #include "dcn303_dccg.h" 29 #include "irq/dcn303/irq_service_dcn303.h" 30 31 #include "dcn30/dcn30_dio_link_encoder.h" 32 #include "dcn30/dcn30_dio_stream_encoder.h" 33 #include "dcn30/dcn30_dpp.h" 34 #include "dcn30/dcn30_dwb.h" 35 #include "dcn30/dcn30_hubbub.h" 36 #include "dcn30/dcn30_hubp.h" 37 #include "dcn30/dcn30_mmhubbub.h" 38 #include "dcn30/dcn30_mpc.h" 39 #include "dcn30/dcn30_opp.h" 40 #include "dcn30/dcn30_optc.h" 41 #include "dcn30/dcn30_resource.h" 42 43 #include "dcn20/dcn20_dsc.h" 44 #include "dcn20/dcn20_resource.h" 45 46 #include "dcn10/dcn10_resource.h" 47 48 #include "dc_link_ddc.h" 49 50 #include "dce/dce_abm.h" 51 #include "dce/dce_audio.h" 52 #include "dce/dce_aux.h" 53 #include "dce/dce_clock_source.h" 54 #include "dce/dce_hwseq.h" 55 #include "dce/dce_i2c_hw.h" 56 #include "dce/dce_panel_cntl.h" 57 #include "dce/dmub_abm.h" 58 #include "dce/dmub_psr.h" 59 #include "clk_mgr.h" 60 61 #include "hw_sequencer_private.h" 62 #include "reg_helper.h" 63 #include "resource.h" 64 #include "vm_helper.h" 65 66 #include "sienna_cichlid_ip_offset.h" 67 #include "dcn/dcn_3_0_3_offset.h" 68 #include "dcn/dcn_3_0_3_sh_mask.h" 69 #include "dcn/dpcs_3_0_3_offset.h" 70 #include "dcn/dpcs_3_0_3_sh_mask.h" 71 #include "nbio/nbio_2_3_offset.h" 72 73 #define DC_LOGGER_INIT(logger) 74 75 struct _vcs_dpi_ip_params_st dcn3_03_ip = { 76 .use_min_dcfclk = 0, 77 .clamp_min_dcfclk = 0, 78 .odm_capable = 1, 79 .gpuvm_enable = 1, 80 .hostvm_enable = 0, 81 .gpuvm_max_page_table_levels = 4, 82 .hostvm_max_page_table_levels = 4, 83 .hostvm_cached_page_table_levels = 0, 84 .pte_group_size_bytes = 2048, 85 .num_dsc = 2, 86 .rob_buffer_size_kbytes = 184, 87 .det_buffer_size_kbytes = 184, 88 .dpte_buffer_size_in_pte_reqs_luma = 64, 89 .dpte_buffer_size_in_pte_reqs_chroma = 34, 90 .pde_proc_buffer_size_64k_reqs = 48, 91 .dpp_output_buffer_pixels = 2560, 92 .opp_output_buffer_lines = 1, 93 .pixel_chunk_size_kbytes = 8, 94 .pte_enable = 1, 95 .max_page_table_levels = 2, 96 .pte_chunk_size_kbytes = 2, // ? 97 .meta_chunk_size_kbytes = 2, 98 .writeback_chunk_size_kbytes = 8, 99 .line_buffer_size_bits = 789504, 100 .is_line_buffer_bpp_fixed = 0, // ? 101 .line_buffer_fixed_bpp = 0, // ? 102 .dcc_supported = true, 103 .writeback_interface_buffer_size_kbytes = 90, 104 .writeback_line_buffer_buffer_size = 0, 105 .max_line_buffer_lines = 12, 106 .writeback_luma_buffer_size_kbytes = 12, // writeback_line_buffer_buffer_size = 656640 107 .writeback_chroma_buffer_size_kbytes = 8, 108 .writeback_chroma_line_buffer_width_pixels = 4, 109 .writeback_max_hscl_ratio = 1, 110 .writeback_max_vscl_ratio = 1, 111 .writeback_min_hscl_ratio = 1, 112 .writeback_min_vscl_ratio = 1, 113 .writeback_max_hscl_taps = 1, 114 .writeback_max_vscl_taps = 1, 115 .writeback_line_buffer_luma_buffer_size = 0, 116 .writeback_line_buffer_chroma_buffer_size = 14643, 117 .cursor_buffer_size = 8, 118 .cursor_chunk_size = 2, 119 .max_num_otg = 2, 120 .max_num_dpp = 2, 121 .max_num_wb = 1, 122 .max_dchub_pscl_bw_pix_per_clk = 4, 123 .max_pscl_lb_bw_pix_per_clk = 2, 124 .max_lb_vscl_bw_pix_per_clk = 4, 125 .max_vscl_hscl_bw_pix_per_clk = 4, 126 .max_hscl_ratio = 6, 127 .max_vscl_ratio = 6, 128 .hscl_mults = 4, 129 .vscl_mults = 4, 130 .max_hscl_taps = 8, 131 .max_vscl_taps = 8, 132 .dispclk_ramp_margin_percent = 1, 133 .underscan_factor = 1.11, 134 .min_vblank_lines = 32, 135 .dppclk_delay_subtotal = 46, 136 .dynamic_metadata_vm_enabled = true, 137 .dppclk_delay_scl_lb_only = 16, 138 .dppclk_delay_scl = 50, 139 .dppclk_delay_cnvc_formatter = 27, 140 .dppclk_delay_cnvc_cursor = 6, 141 .dispclk_delay_subtotal = 119, 142 .dcfclk_cstate_latency = 5.2, // SRExitTime 143 .max_inter_dcn_tile_repeaters = 8, 144 .max_num_hdmi_frl_outputs = 1, 145 .odm_combine_4to1_supported = false, 146 .xfc_supported = false, 147 .xfc_fill_bw_overhead_percent = 10.0, 148 .xfc_fill_constant_bytes = 0, 149 .gfx7_compat_tiling_supported = 0, 150 .number_of_cursors = 1, 151 }; 152 153 struct _vcs_dpi_soc_bounding_box_st dcn3_03_soc = { 154 .clock_limits = { 155 { 156 .state = 0, 157 .dispclk_mhz = 1217.0, 158 .dppclk_mhz = 1217.0, 159 .phyclk_mhz = 810.0, 160 .phyclk_d18_mhz = 667.0, 161 .dscclk_mhz = 405.6, 162 }, 163 }, 164 165 .min_dcfclk = 500.0, /* TODO: set this to actual min DCFCLK */ 166 .num_states = 1, 167 .sr_exit_time_us = 12, 168 .sr_enter_plus_exit_time_us = 20, 169 .urgent_latency_us = 4.0, 170 .urgent_latency_pixel_data_only_us = 4.0, 171 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0, 172 .urgent_latency_vm_data_only_us = 4.0, 173 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096, 174 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096, 175 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096, 176 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 80.0, 177 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0, 178 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0, 179 .max_avg_sdp_bw_use_normal_percent = 60.0, 180 .max_avg_dram_bw_use_normal_percent = 40.0, 181 .writeback_latency_us = 12.0, 182 .max_request_size_bytes = 256, 183 .fabric_datapath_to_dcn_data_return_bytes = 64, 184 .dcn_downspread_percent = 0.5, 185 .downspread_percent = 0.38, 186 .dram_page_open_time_ns = 50.0, 187 .dram_rw_turnaround_time_ns = 17.5, 188 .dram_return_buffer_per_channel_bytes = 8192, 189 .round_trip_ping_latency_dcfclk_cycles = 156, 190 .urgent_out_of_order_return_per_channel_bytes = 4096, 191 .channel_interleave_bytes = 256, 192 .num_banks = 8, 193 .gpuvm_min_page_size_bytes = 4096, 194 .hostvm_min_page_size_bytes = 4096, 195 .dram_clock_change_latency_us = 404, 196 .dummy_pstate_latency_us = 5, 197 .writeback_dram_clock_change_latency_us = 23.0, 198 .return_bus_width_bytes = 64, 199 .dispclk_dppclk_vco_speed_mhz = 3650, 200 .xfc_bus_transport_time_us = 20, // ? 201 .xfc_xbuf_latency_tolerance_us = 4, // ? 202 .use_urgent_burst_bw = 1, // ? 203 .do_urgent_latency_adjustment = true, 204 .urgent_latency_adjustment_fabric_clock_component_us = 1.0, 205 .urgent_latency_adjustment_fabric_clock_reference_mhz = 1000, 206 }; 207 208 static const struct dc_debug_options debug_defaults_drv = { 209 .disable_dmcu = true, 210 .force_abm_enable = false, 211 .timing_trace = false, 212 .clock_trace = true, 213 .disable_pplib_clock_request = true, 214 .pipe_split_policy = MPC_SPLIT_DYNAMIC, 215 .force_single_disp_pipe_split = false, 216 .disable_dcc = DCC_ENABLE, 217 .vsr_support = true, 218 .performance_trace = false, 219 .max_downscale_src_width = 7680,/*upto 8K*/ 220 .disable_pplib_wm_range = false, 221 .scl_reset_length10 = true, 222 .sanity_checks = false, 223 .underflow_assert_delay_us = 0xFFFFFFFF, 224 .dwb_fi_phase = -1, // -1 = disable, 225 .dmub_command_table = true, 226 }; 227 228 static const struct dc_debug_options debug_defaults_diags = { 229 .disable_dmcu = true, 230 .force_abm_enable = false, 231 .timing_trace = true, 232 .clock_trace = true, 233 .disable_dpp_power_gate = true, 234 .disable_hubp_power_gate = true, 235 .disable_clock_gate = true, 236 .disable_pplib_clock_request = true, 237 .disable_pplib_wm_range = true, 238 .disable_stutter = false, 239 .scl_reset_length10 = true, 240 .dwb_fi_phase = -1, // -1 = disable 241 .dmub_command_table = true, 242 .enable_tri_buf = true, 243 .disable_psr = true, 244 }; 245 246 enum dcn303_clk_src_array_id { 247 DCN303_CLK_SRC_PLL0, 248 DCN303_CLK_SRC_PLL1, 249 DCN303_CLK_SRC_TOTAL 250 }; 251 252 static const struct resource_caps res_cap_dcn303 = { 253 .num_timing_generator = 2, 254 .num_opp = 2, 255 .num_video_plane = 2, 256 .num_audio = 2, 257 .num_stream_encoder = 2, 258 .num_dwb = 1, 259 .num_ddc = 2, 260 .num_vmid = 16, 261 .num_mpc_3dlut = 1, 262 .num_dsc = 2, 263 }; 264 265 static const struct dc_plane_cap plane_cap = { 266 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 267 .blends_with_above = true, 268 .blends_with_below = true, 269 .per_pixel_alpha = true, 270 .pixel_format_support = { 271 .argb8888 = true, 272 .nv12 = true, 273 .fp16 = true, 274 .p010 = false, 275 .ayuv = false, 276 }, 277 .max_upscale_factor = { 278 .argb8888 = 16000, 279 .nv12 = 16000, 280 .fp16 = 16000 281 }, 282 .max_downscale_factor = { 283 .argb8888 = 600, 284 .nv12 = 600, 285 .fp16 = 600 286 }, 287 16, 288 16 289 }; 290 291 /* NBIO */ 292 #define NBIO_BASE_INNER(seg) \ 293 NBIO_BASE__INST0_SEG ## seg 294 295 #define NBIO_BASE(seg) \ 296 NBIO_BASE_INNER(seg) 297 298 #define NBIO_SR(reg_name)\ 299 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \ 300 mm ## reg_name 301 302 /* DCN */ 303 #undef BASE_INNER 304 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg 305 306 #define BASE(seg) BASE_INNER(seg) 307 308 #define SR(reg_name)\ 309 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name 310 311 #define SF(reg_name, field_name, post_fix)\ 312 .field_name = reg_name ## __ ## field_name ## post_fix 313 314 #define SRI(reg_name, block, id)\ 315 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + mm ## block ## id ## _ ## reg_name 316 317 #define SRI2(reg_name, block, id)\ 318 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name 319 320 #define SRII(reg_name, block, id)\ 321 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 322 mm ## block ## id ## _ ## reg_name 323 324 #define DCCG_SRII(reg_name, block, id)\ 325 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 326 mm ## block ## id ## _ ## reg_name 327 328 #define VUPDATE_SRII(reg_name, block, id)\ 329 .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \ 330 mm ## reg_name ## _ ## block ## id 331 332 #define SRII_DWB(reg_name, temp_name, block, id)\ 333 .reg_name[id] = BASE(mm ## block ## id ## _ ## temp_name ## _BASE_IDX) + \ 334 mm ## block ## id ## _ ## temp_name 335 336 #define SRII_MPC_RMU(reg_name, block, id)\ 337 .RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 338 mm ## block ## id ## _ ## reg_name 339 340 static const struct dcn_hubbub_registers hubbub_reg = { 341 HUBBUB_REG_LIST_DCN30(0) 342 }; 343 344 static const struct dcn_hubbub_shift hubbub_shift = { 345 HUBBUB_MASK_SH_LIST_DCN30(__SHIFT) 346 }; 347 348 static const struct dcn_hubbub_mask hubbub_mask = { 349 HUBBUB_MASK_SH_LIST_DCN30(_MASK) 350 }; 351 352 #define vmid_regs(id)\ 353 [id] = { DCN20_VMID_REG_LIST(id) } 354 355 static const struct dcn_vmid_registers vmid_regs[] = { 356 vmid_regs(0), 357 vmid_regs(1), 358 vmid_regs(2), 359 vmid_regs(3), 360 vmid_regs(4), 361 vmid_regs(5), 362 vmid_regs(6), 363 vmid_regs(7), 364 vmid_regs(8), 365 vmid_regs(9), 366 vmid_regs(10), 367 vmid_regs(11), 368 vmid_regs(12), 369 vmid_regs(13), 370 vmid_regs(14), 371 vmid_regs(15) 372 }; 373 374 static const struct dcn20_vmid_shift vmid_shifts = { 375 DCN20_VMID_MASK_SH_LIST(__SHIFT) 376 }; 377 378 static const struct dcn20_vmid_mask vmid_masks = { 379 DCN20_VMID_MASK_SH_LIST(_MASK) 380 }; 381 382 static struct hubbub *dcn303_hubbub_create(struct dc_context *ctx) 383 { 384 int i; 385 386 struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub), GFP_KERNEL); 387 388 if (!hubbub3) 389 return NULL; 390 391 hubbub3_construct(hubbub3, ctx, &hubbub_reg, &hubbub_shift, &hubbub_mask); 392 393 for (i = 0; i < res_cap_dcn303.num_vmid; i++) { 394 struct dcn20_vmid *vmid = &hubbub3->vmid[i]; 395 396 vmid->ctx = ctx; 397 398 vmid->regs = &vmid_regs[i]; 399 vmid->shifts = &vmid_shifts; 400 vmid->masks = &vmid_masks; 401 } 402 403 return &hubbub3->base; 404 } 405 406 #define vpg_regs(id)\ 407 [id] = { VPG_DCN3_REG_LIST(id) } 408 409 static const struct dcn30_vpg_registers vpg_regs[] = { 410 vpg_regs(0), 411 vpg_regs(1), 412 vpg_regs(2) 413 }; 414 415 static const struct dcn30_vpg_shift vpg_shift = { 416 DCN3_VPG_MASK_SH_LIST(__SHIFT) 417 }; 418 419 static const struct dcn30_vpg_mask vpg_mask = { 420 DCN3_VPG_MASK_SH_LIST(_MASK) 421 }; 422 423 static struct vpg *dcn303_vpg_create(struct dc_context *ctx, uint32_t inst) 424 { 425 struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL); 426 427 if (!vpg3) 428 return NULL; 429 430 vpg3_construct(vpg3, ctx, inst, &vpg_regs[inst], &vpg_shift, &vpg_mask); 431 432 return &vpg3->base; 433 } 434 435 #define afmt_regs(id)\ 436 [id] = { AFMT_DCN3_REG_LIST(id) } 437 438 static const struct dcn30_afmt_registers afmt_regs[] = { 439 afmt_regs(0), 440 afmt_regs(1), 441 afmt_regs(2) 442 }; 443 444 static const struct dcn30_afmt_shift afmt_shift = { 445 DCN3_AFMT_MASK_SH_LIST(__SHIFT) 446 }; 447 448 static const struct dcn30_afmt_mask afmt_mask = { 449 DCN3_AFMT_MASK_SH_LIST(_MASK) 450 }; 451 452 static struct afmt *dcn303_afmt_create(struct dc_context *ctx, uint32_t inst) 453 { 454 struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL); 455 456 if (!afmt3) 457 return NULL; 458 459 afmt3_construct(afmt3, ctx, inst, &afmt_regs[inst], &afmt_shift, &afmt_mask); 460 461 return &afmt3->base; 462 } 463 464 #define audio_regs(id)\ 465 [id] = { AUD_COMMON_REG_LIST(id) } 466 467 static const struct dce_audio_registers audio_regs[] = { 468 audio_regs(0), 469 audio_regs(1), 470 audio_regs(2), 471 audio_regs(3), 472 audio_regs(4), 473 audio_regs(5), 474 audio_regs(6) 475 }; 476 477 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 478 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 479 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 480 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 481 482 static const struct dce_audio_shift audio_shift = { 483 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 484 }; 485 486 static const struct dce_audio_mask audio_mask = { 487 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 488 }; 489 490 static struct audio *dcn303_create_audio(struct dc_context *ctx, unsigned int inst) 491 { 492 return dce_audio_create(ctx, inst, &audio_regs[inst], &audio_shift, &audio_mask); 493 } 494 495 #define stream_enc_regs(id)\ 496 [id] = { SE_DCN3_REG_LIST(id) } 497 498 static const struct dcn10_stream_enc_registers stream_enc_regs[] = { 499 stream_enc_regs(0), 500 stream_enc_regs(1) 501 }; 502 503 static const struct dcn10_stream_encoder_shift se_shift = { 504 SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 505 }; 506 507 static const struct dcn10_stream_encoder_mask se_mask = { 508 SE_COMMON_MASK_SH_LIST_DCN30(_MASK) 509 }; 510 511 static struct stream_encoder *dcn303_stream_encoder_create(enum engine_id eng_id, struct dc_context *ctx) 512 { 513 struct dcn10_stream_encoder *enc1; 514 struct vpg *vpg; 515 struct afmt *afmt; 516 int vpg_inst; 517 int afmt_inst; 518 519 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */ 520 if (eng_id <= ENGINE_ID_DIGE) { 521 vpg_inst = eng_id; 522 afmt_inst = eng_id; 523 } else 524 return NULL; 525 526 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 527 vpg = dcn303_vpg_create(ctx, vpg_inst); 528 afmt = dcn303_afmt_create(ctx, afmt_inst); 529 530 if (!enc1 || !vpg || !afmt) 531 return NULL; 532 533 dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id, vpg, afmt, &stream_enc_regs[eng_id], 534 &se_shift, &se_mask); 535 536 return &enc1->base; 537 } 538 539 #define clk_src_regs(index, pllid)\ 540 [index] = { CS_COMMON_REG_LIST_DCN3_03(index, pllid) } 541 542 static const struct dce110_clk_src_regs clk_src_regs[] = { 543 clk_src_regs(0, A), 544 clk_src_regs(1, B) 545 }; 546 547 static const struct dce110_clk_src_shift cs_shift = { 548 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 549 }; 550 551 static const struct dce110_clk_src_mask cs_mask = { 552 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 553 }; 554 555 static struct clock_source *dcn303_clock_source_create(struct dc_context *ctx, struct dc_bios *bios, 556 enum clock_source_id id, const struct dce110_clk_src_regs *regs, bool dp_clk_src) 557 { 558 struct dce110_clk_src *clk_src = kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 559 560 if (!clk_src) 561 return NULL; 562 563 if (dcn3_clk_src_construct(clk_src, ctx, bios, id, regs, &cs_shift, &cs_mask)) { 564 clk_src->base.dp_clk_src = dp_clk_src; 565 return &clk_src->base; 566 } 567 568 BREAK_TO_DEBUGGER(); 569 return NULL; 570 } 571 572 static const struct dce_hwseq_registers hwseq_reg = { 573 HWSEQ_DCN303_REG_LIST() 574 }; 575 576 static const struct dce_hwseq_shift hwseq_shift = { 577 HWSEQ_DCN303_MASK_SH_LIST(__SHIFT) 578 }; 579 580 static const struct dce_hwseq_mask hwseq_mask = { 581 HWSEQ_DCN303_MASK_SH_LIST(_MASK) 582 }; 583 584 static struct dce_hwseq *dcn303_hwseq_create(struct dc_context *ctx) 585 { 586 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 587 588 if (hws) { 589 hws->ctx = ctx; 590 hws->regs = &hwseq_reg; 591 hws->shifts = &hwseq_shift; 592 hws->masks = &hwseq_mask; 593 } 594 return hws; 595 } 596 597 #define hubp_regs(id)\ 598 [id] = { HUBP_REG_LIST_DCN30(id) } 599 600 static const struct dcn_hubp2_registers hubp_regs[] = { 601 hubp_regs(0), 602 hubp_regs(1) 603 }; 604 605 static const struct dcn_hubp2_shift hubp_shift = { 606 HUBP_MASK_SH_LIST_DCN30(__SHIFT) 607 }; 608 609 static const struct dcn_hubp2_mask hubp_mask = { 610 HUBP_MASK_SH_LIST_DCN30(_MASK) 611 }; 612 613 static struct hubp *dcn303_hubp_create(struct dc_context *ctx, uint32_t inst) 614 { 615 struct dcn20_hubp *hubp2 = kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL); 616 617 if (!hubp2) 618 return NULL; 619 620 if (hubp3_construct(hubp2, ctx, inst, &hubp_regs[inst], &hubp_shift, &hubp_mask)) 621 return &hubp2->base; 622 623 BREAK_TO_DEBUGGER(); 624 kfree(hubp2); 625 return NULL; 626 } 627 628 #define dpp_regs(id)\ 629 [id] = { DPP_REG_LIST_DCN30(id) } 630 631 static const struct dcn3_dpp_registers dpp_regs[] = { 632 dpp_regs(0), 633 dpp_regs(1) 634 }; 635 636 static const struct dcn3_dpp_shift tf_shift = { 637 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT) 638 }; 639 640 static const struct dcn3_dpp_mask tf_mask = { 641 DPP_REG_LIST_SH_MASK_DCN30(_MASK) 642 }; 643 644 static struct dpp *dcn303_dpp_create(struct dc_context *ctx, uint32_t inst) 645 { 646 struct dcn3_dpp *dpp = kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL); 647 648 if (!dpp) 649 return NULL; 650 651 if (dpp3_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, &tf_mask)) 652 return &dpp->base; 653 654 BREAK_TO_DEBUGGER(); 655 kfree(dpp); 656 return NULL; 657 } 658 659 #define opp_regs(id)\ 660 [id] = { OPP_REG_LIST_DCN30(id) } 661 662 static const struct dcn20_opp_registers opp_regs[] = { 663 opp_regs(0), 664 opp_regs(1) 665 }; 666 667 static const struct dcn20_opp_shift opp_shift = { 668 OPP_MASK_SH_LIST_DCN20(__SHIFT) 669 }; 670 671 static const struct dcn20_opp_mask opp_mask = { 672 OPP_MASK_SH_LIST_DCN20(_MASK) 673 }; 674 675 static struct output_pixel_processor *dcn303_opp_create(struct dc_context *ctx, uint32_t inst) 676 { 677 struct dcn20_opp *opp = kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); 678 679 if (!opp) { 680 BREAK_TO_DEBUGGER(); 681 return NULL; 682 } 683 684 dcn20_opp_construct(opp, ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask); 685 return &opp->base; 686 } 687 688 #define optc_regs(id)\ 689 [id] = { OPTC_COMMON_REG_LIST_DCN3_0(id) } 690 691 static const struct dcn_optc_registers optc_regs[] = { 692 optc_regs(0), 693 optc_regs(1) 694 }; 695 696 static const struct dcn_optc_shift optc_shift = { 697 OPTC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 698 }; 699 700 static const struct dcn_optc_mask optc_mask = { 701 OPTC_COMMON_MASK_SH_LIST_DCN30(_MASK) 702 }; 703 704 static struct timing_generator *dcn303_timing_generator_create(struct dc_context *ctx, uint32_t instance) 705 { 706 struct optc *tgn10 = kzalloc(sizeof(struct optc), GFP_KERNEL); 707 708 if (!tgn10) 709 return NULL; 710 711 tgn10->base.inst = instance; 712 tgn10->base.ctx = ctx; 713 714 tgn10->tg_regs = &optc_regs[instance]; 715 tgn10->tg_shift = &optc_shift; 716 tgn10->tg_mask = &optc_mask; 717 718 dcn30_timing_generator_init(tgn10); 719 720 return &tgn10->base; 721 } 722 723 static const struct dcn30_mpc_registers mpc_regs = { 724 MPC_REG_LIST_DCN3_0(0), 725 MPC_REG_LIST_DCN3_0(1), 726 MPC_OUT_MUX_REG_LIST_DCN3_0(0), 727 MPC_OUT_MUX_REG_LIST_DCN3_0(1), 728 MPC_RMU_GLOBAL_REG_LIST_DCN3AG, 729 MPC_RMU_REG_LIST_DCN3AG(0), 730 MPC_DWB_MUX_REG_LIST_DCN3_0(0), 731 }; 732 733 static const struct dcn30_mpc_shift mpc_shift = { 734 MPC_COMMON_MASK_SH_LIST_DCN303(__SHIFT) 735 }; 736 737 static const struct dcn30_mpc_mask mpc_mask = { 738 MPC_COMMON_MASK_SH_LIST_DCN303(_MASK) 739 }; 740 741 static struct mpc *dcn303_mpc_create(struct dc_context *ctx, int num_mpcc, int num_rmu) 742 { 743 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), GFP_KERNEL); 744 745 if (!mpc30) 746 return NULL; 747 748 dcn30_mpc_construct(mpc30, ctx, &mpc_regs, &mpc_shift, &mpc_mask, num_mpcc, num_rmu); 749 750 return &mpc30->base; 751 } 752 753 #define dsc_regsDCN20(id)\ 754 [id] = { DSC_REG_LIST_DCN20(id) } 755 756 static const struct dcn20_dsc_registers dsc_regs[] = { 757 dsc_regsDCN20(0), 758 dsc_regsDCN20(1) 759 }; 760 761 static const struct dcn20_dsc_shift dsc_shift = { 762 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) 763 }; 764 765 static const struct dcn20_dsc_mask dsc_mask = { 766 DSC_REG_LIST_SH_MASK_DCN20(_MASK) 767 }; 768 769 static struct display_stream_compressor *dcn303_dsc_create(struct dc_context *ctx, uint32_t inst) 770 { 771 struct dcn20_dsc *dsc = kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); 772 773 if (!dsc) { 774 BREAK_TO_DEBUGGER(); 775 return NULL; 776 } 777 778 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 779 return &dsc->base; 780 } 781 782 #define dwbc_regs_dcn3(id)\ 783 [id] = { DWBC_COMMON_REG_LIST_DCN30(id) } 784 785 static const struct dcn30_dwbc_registers dwbc30_regs[] = { 786 dwbc_regs_dcn3(0) 787 }; 788 789 static const struct dcn30_dwbc_shift dwbc30_shift = { 790 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 791 }; 792 793 static const struct dcn30_dwbc_mask dwbc30_mask = { 794 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK) 795 }; 796 797 static bool dcn303_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) 798 { 799 int i; 800 uint32_t pipe_count = pool->res_cap->num_dwb; 801 802 for (i = 0; i < pipe_count; i++) { 803 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), GFP_KERNEL); 804 805 if (!dwbc30) { 806 dm_error("DC: failed to create dwbc30!\n"); 807 return false; 808 } 809 810 dcn30_dwbc_construct(dwbc30, ctx, &dwbc30_regs[i], &dwbc30_shift, &dwbc30_mask, i); 811 812 pool->dwbc[i] = &dwbc30->base; 813 } 814 return true; 815 } 816 817 #define mcif_wb_regs_dcn3(id)\ 818 [id] = { MCIF_WB_COMMON_REG_LIST_DCN30(id) } 819 820 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = { 821 mcif_wb_regs_dcn3(0) 822 }; 823 824 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = { 825 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 826 }; 827 828 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { 829 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK) 830 }; 831 832 static bool dcn303_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) 833 { 834 int i; 835 uint32_t pipe_count = pool->res_cap->num_dwb; 836 837 for (i = 0; i < pipe_count; i++) { 838 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), GFP_KERNEL); 839 840 if (!mcif_wb30) { 841 dm_error("DC: failed to create mcif_wb30!\n"); 842 return false; 843 } 844 845 dcn30_mmhubbub_construct(mcif_wb30, ctx, &mcif_wb30_regs[i], &mcif_wb30_shift, &mcif_wb30_mask, i); 846 847 pool->mcif_wb[i] = &mcif_wb30->base; 848 } 849 return true; 850 } 851 852 #define aux_engine_regs(id)\ 853 [id] = {\ 854 AUX_COMMON_REG_LIST0(id), \ 855 .AUXN_IMPCAL = 0, \ 856 .AUXP_IMPCAL = 0, \ 857 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \ 858 } 859 860 static const struct dce110_aux_registers aux_engine_regs[] = { 861 aux_engine_regs(0), 862 aux_engine_regs(1) 863 }; 864 865 static const struct dce110_aux_registers_shift aux_shift = { 866 DCN_AUX_MASK_SH_LIST(__SHIFT) 867 }; 868 869 static const struct dce110_aux_registers_mask aux_mask = { 870 DCN_AUX_MASK_SH_LIST(_MASK) 871 }; 872 873 static struct dce_aux *dcn303_aux_engine_create(struct dc_context *ctx, uint32_t inst) 874 { 875 struct aux_engine_dce110 *aux_engine = kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 876 877 if (!aux_engine) 878 return NULL; 879 880 dce110_aux_engine_construct(aux_engine, ctx, inst, SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 881 &aux_engine_regs[inst], &aux_mask, &aux_shift, ctx->dc->caps.extended_aux_timeout_support); 882 883 return &aux_engine->base; 884 } 885 886 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 887 888 static const struct dce_i2c_registers i2c_hw_regs[] = { 889 i2c_inst_regs(1), 890 i2c_inst_regs(2) 891 }; 892 893 static const struct dce_i2c_shift i2c_shifts = { 894 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT) 895 }; 896 897 static const struct dce_i2c_mask i2c_masks = { 898 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK) 899 }; 900 901 static struct dce_i2c_hw *dcn303_i2c_hw_create(struct dc_context *ctx, uint32_t inst) 902 { 903 struct dce_i2c_hw *dce_i2c_hw = kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 904 905 if (!dce_i2c_hw) 906 return NULL; 907 908 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 909 910 return dce_i2c_hw; 911 } 912 913 static const struct encoder_feature_support link_enc_feature = { 914 .max_hdmi_deep_color = COLOR_DEPTH_121212, 915 .max_hdmi_pixel_clock = 600000, 916 .hdmi_ycbcr420_supported = true, 917 .dp_ycbcr420_supported = true, 918 .fec_supported = true, 919 .flags.bits.IS_HBR2_CAPABLE = true, 920 .flags.bits.IS_HBR3_CAPABLE = true, 921 .flags.bits.IS_TPS3_CAPABLE = true, 922 .flags.bits.IS_TPS4_CAPABLE = true 923 }; 924 925 #define link_regs(id, phyid)\ 926 [id] = {\ 927 LE_DCN3_REG_LIST(id), \ 928 UNIPHY_DCN2_REG_LIST(phyid), \ 929 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \ 930 } 931 932 static const struct dcn10_link_enc_registers link_enc_regs[] = { 933 link_regs(0, A), 934 link_regs(1, B) 935 }; 936 937 static const struct dcn10_link_enc_shift le_shift = { 938 LINK_ENCODER_MASK_SH_LIST_DCN30(__SHIFT), 939 DPCS_DCN2_MASK_SH_LIST(__SHIFT) 940 }; 941 942 static const struct dcn10_link_enc_mask le_mask = { 943 LINK_ENCODER_MASK_SH_LIST_DCN30(_MASK), 944 DPCS_DCN2_MASK_SH_LIST(_MASK) 945 }; 946 947 #define aux_regs(id)\ 948 [id] = { DCN2_AUX_REG_LIST(id) } 949 950 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { 951 aux_regs(0), 952 aux_regs(1) 953 }; 954 955 #define hpd_regs(id)\ 956 [id] = { HPD_REG_LIST(id) } 957 958 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { 959 hpd_regs(0), 960 hpd_regs(1) 961 }; 962 963 static struct link_encoder *dcn303_link_encoder_create(const struct encoder_init_data *enc_init_data) 964 { 965 struct dcn20_link_encoder *enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 966 967 if (!enc20) 968 return NULL; 969 970 dcn30_link_encoder_construct(enc20, enc_init_data, &link_enc_feature, 971 &link_enc_regs[enc_init_data->transmitter], &link_enc_aux_regs[enc_init_data->channel - 1], 972 &link_enc_hpd_regs[enc_init_data->hpd_source], &le_shift, &le_mask); 973 974 return &enc20->enc10.base; 975 } 976 977 static const struct dce_panel_cntl_registers panel_cntl_regs[] = { 978 { DCN_PANEL_CNTL_REG_LIST() } 979 }; 980 981 static const struct dce_panel_cntl_shift panel_cntl_shift = { 982 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT) 983 }; 984 985 static const struct dce_panel_cntl_mask panel_cntl_mask = { 986 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK) 987 }; 988 989 static struct panel_cntl *dcn303_panel_cntl_create(const struct panel_cntl_init_data *init_data) 990 { 991 struct dce_panel_cntl *panel_cntl = kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL); 992 993 if (!panel_cntl) 994 return NULL; 995 996 dce_panel_cntl_construct(panel_cntl, init_data, &panel_cntl_regs[init_data->inst], 997 &panel_cntl_shift, &panel_cntl_mask); 998 999 return &panel_cntl->base; 1000 } 1001 1002 static void read_dce_straps(struct dc_context *ctx, struct resource_straps *straps) 1003 { 1004 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX), 1005 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 1006 } 1007 1008 static const struct resource_create_funcs res_create_funcs = { 1009 .read_dce_straps = read_dce_straps, 1010 .create_audio = dcn303_create_audio, 1011 .create_stream_encoder = dcn303_stream_encoder_create, 1012 .create_hwseq = dcn303_hwseq_create, 1013 }; 1014 1015 static const struct resource_create_funcs res_create_maximus_funcs = { 1016 .read_dce_straps = NULL, 1017 .create_audio = NULL, 1018 .create_stream_encoder = NULL, 1019 .create_hwseq = dcn303_hwseq_create, 1020 }; 1021 1022 static bool is_soc_bounding_box_valid(struct dc *dc) 1023 { 1024 uint32_t hw_internal_rev = dc->ctx->asic_id.hw_internal_rev; 1025 1026 if (ASICREV_IS_BEIGE_GOBY_P(hw_internal_rev)) 1027 return true; 1028 1029 return false; 1030 } 1031 1032 static bool init_soc_bounding_box(struct dc *dc, struct resource_pool *pool) 1033 { 1034 struct _vcs_dpi_soc_bounding_box_st *loaded_bb = &dcn3_03_soc; 1035 struct _vcs_dpi_ip_params_st *loaded_ip = &dcn3_03_ip; 1036 1037 DC_LOGGER_INIT(dc->ctx->logger); 1038 1039 if (!is_soc_bounding_box_valid(dc)) { 1040 DC_LOG_ERROR("%s: not valid soc bounding box/n", __func__); 1041 return false; 1042 } 1043 1044 loaded_ip->max_num_otg = pool->pipe_count; 1045 loaded_ip->max_num_dpp = pool->pipe_count; 1046 loaded_ip->clamp_min_dcfclk = dc->config.clamp_min_dcfclk; 1047 dcn20_patch_bounding_box(dc, loaded_bb); 1048 return true; 1049 } 1050 1051 static void dcn303_resource_destruct(struct resource_pool *pool) 1052 { 1053 unsigned int i; 1054 1055 for (i = 0; i < pool->stream_enc_count; i++) { 1056 if (pool->stream_enc[i] != NULL) { 1057 if (pool->stream_enc[i]->vpg != NULL) { 1058 kfree(DCN30_VPG_FROM_VPG(pool->stream_enc[i]->vpg)); 1059 pool->stream_enc[i]->vpg = NULL; 1060 } 1061 if (pool->stream_enc[i]->afmt != NULL) { 1062 kfree(DCN30_AFMT_FROM_AFMT(pool->stream_enc[i]->afmt)); 1063 pool->stream_enc[i]->afmt = NULL; 1064 } 1065 kfree(DCN10STRENC_FROM_STRENC(pool->stream_enc[i])); 1066 pool->stream_enc[i] = NULL; 1067 } 1068 } 1069 1070 for (i = 0; i < pool->res_cap->num_dsc; i++) { 1071 if (pool->dscs[i] != NULL) 1072 dcn20_dsc_destroy(&pool->dscs[i]); 1073 } 1074 1075 if (pool->mpc != NULL) { 1076 kfree(TO_DCN20_MPC(pool->mpc)); 1077 pool->mpc = NULL; 1078 } 1079 1080 if (pool->hubbub != NULL) { 1081 kfree(pool->hubbub); 1082 pool->hubbub = NULL; 1083 } 1084 1085 for (i = 0; i < pool->pipe_count; i++) { 1086 if (pool->dpps[i] != NULL) { 1087 kfree(TO_DCN20_DPP(pool->dpps[i])); 1088 pool->dpps[i] = NULL; 1089 } 1090 1091 if (pool->hubps[i] != NULL) { 1092 kfree(TO_DCN20_HUBP(pool->hubps[i])); 1093 pool->hubps[i] = NULL; 1094 } 1095 1096 if (pool->irqs != NULL) 1097 dal_irq_service_destroy(&pool->irqs); 1098 } 1099 1100 for (i = 0; i < pool->res_cap->num_ddc; i++) { 1101 if (pool->engines[i] != NULL) 1102 dce110_engine_destroy(&pool->engines[i]); 1103 if (pool->hw_i2cs[i] != NULL) { 1104 kfree(pool->hw_i2cs[i]); 1105 pool->hw_i2cs[i] = NULL; 1106 } 1107 if (pool->sw_i2cs[i] != NULL) { 1108 kfree(pool->sw_i2cs[i]); 1109 pool->sw_i2cs[i] = NULL; 1110 } 1111 } 1112 1113 for (i = 0; i < pool->res_cap->num_opp; i++) { 1114 if (pool->opps[i] != NULL) 1115 pool->opps[i]->funcs->opp_destroy(&pool->opps[i]); 1116 } 1117 1118 for (i = 0; i < pool->res_cap->num_timing_generator; i++) { 1119 if (pool->timing_generators[i] != NULL) { 1120 kfree(DCN10TG_FROM_TG(pool->timing_generators[i])); 1121 pool->timing_generators[i] = NULL; 1122 } 1123 } 1124 1125 for (i = 0; i < pool->res_cap->num_dwb; i++) { 1126 if (pool->dwbc[i] != NULL) { 1127 kfree(TO_DCN30_DWBC(pool->dwbc[i])); 1128 pool->dwbc[i] = NULL; 1129 } 1130 if (pool->mcif_wb[i] != NULL) { 1131 kfree(TO_DCN30_MMHUBBUB(pool->mcif_wb[i])); 1132 pool->mcif_wb[i] = NULL; 1133 } 1134 } 1135 1136 for (i = 0; i < pool->audio_count; i++) { 1137 if (pool->audios[i]) 1138 dce_aud_destroy(&pool->audios[i]); 1139 } 1140 1141 for (i = 0; i < pool->clk_src_count; i++) { 1142 if (pool->clock_sources[i] != NULL) 1143 dcn20_clock_source_destroy(&pool->clock_sources[i]); 1144 } 1145 1146 if (pool->dp_clock_source != NULL) 1147 dcn20_clock_source_destroy(&pool->dp_clock_source); 1148 1149 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { 1150 if (pool->mpc_lut[i] != NULL) { 1151 dc_3dlut_func_release(pool->mpc_lut[i]); 1152 pool->mpc_lut[i] = NULL; 1153 } 1154 if (pool->mpc_shaper[i] != NULL) { 1155 dc_transfer_func_release(pool->mpc_shaper[i]); 1156 pool->mpc_shaper[i] = NULL; 1157 } 1158 } 1159 1160 for (i = 0; i < pool->pipe_count; i++) { 1161 if (pool->multiple_abms[i] != NULL) 1162 dce_abm_destroy(&pool->multiple_abms[i]); 1163 } 1164 1165 if (pool->psr != NULL) 1166 dmub_psr_destroy(&pool->psr); 1167 1168 if (pool->dccg != NULL) 1169 dcn_dccg_destroy(&pool->dccg); 1170 1171 if (pool->oem_device != NULL) 1172 dal_ddc_service_destroy(&pool->oem_device); 1173 } 1174 1175 static void dcn303_destroy_resource_pool(struct resource_pool **pool) 1176 { 1177 dcn303_resource_destruct(*pool); 1178 kfree(*pool); 1179 *pool = NULL; 1180 } 1181 1182 static void dcn303_get_optimal_dcfclk_fclk_for_uclk(unsigned int uclk_mts, 1183 unsigned int *optimal_dcfclk, 1184 unsigned int *optimal_fclk) 1185 { 1186 double bw_from_dram, bw_from_dram1, bw_from_dram2; 1187 1188 bw_from_dram1 = uclk_mts * dcn3_03_soc.num_chans * 1189 dcn3_03_soc.dram_channel_width_bytes * (dcn3_03_soc.max_avg_dram_bw_use_normal_percent / 100); 1190 bw_from_dram2 = uclk_mts * dcn3_03_soc.num_chans * 1191 dcn3_03_soc.dram_channel_width_bytes * (dcn3_03_soc.max_avg_sdp_bw_use_normal_percent / 100); 1192 1193 bw_from_dram = (bw_from_dram1 < bw_from_dram2) ? bw_from_dram1 : bw_from_dram2; 1194 1195 if (optimal_fclk) 1196 *optimal_fclk = bw_from_dram / 1197 (dcn3_03_soc.fabric_datapath_to_dcn_data_return_bytes * 1198 (dcn3_03_soc.max_avg_sdp_bw_use_normal_percent / 100)); 1199 1200 if (optimal_dcfclk) 1201 *optimal_dcfclk = bw_from_dram / 1202 (dcn3_03_soc.return_bus_width_bytes * (dcn3_03_soc.max_avg_sdp_bw_use_normal_percent / 100)); 1203 } 1204 1205 void dcn303_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) 1206 { 1207 unsigned int i, j; 1208 unsigned int num_states = 0; 1209 1210 unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0}; 1211 unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0}; 1212 unsigned int optimal_uclk_for_dcfclk_sta_targets[DC__VOLTAGE_STATES] = {0}; 1213 unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0}; 1214 1215 unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {694, 875, 1000, 1200}; 1216 unsigned int num_dcfclk_sta_targets = 4; 1217 unsigned int num_uclk_states; 1218 1219 1220 if (dc->ctx->dc_bios->vram_info.num_chans) 1221 dcn3_03_soc.num_chans = dc->ctx->dc_bios->vram_info.num_chans; 1222 1223 if (dc->ctx->dc_bios->vram_info.dram_channel_width_bytes) 1224 dcn3_03_soc.dram_channel_width_bytes = dc->ctx->dc_bios->vram_info.dram_channel_width_bytes; 1225 1226 dcn3_03_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0; 1227 dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0; 1228 1229 if (bw_params->clk_table.entries[0].memclk_mhz) { 1230 int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0, max_phyclk_mhz = 0; 1231 1232 for (i = 0; i < MAX_NUM_DPM_LVL; i++) { 1233 if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz) 1234 max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; 1235 if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz) 1236 max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz; 1237 if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz) 1238 max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz; 1239 if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz) 1240 max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz; 1241 } 1242 if (!max_dcfclk_mhz) 1243 max_dcfclk_mhz = dcn3_03_soc.clock_limits[0].dcfclk_mhz; 1244 if (!max_dispclk_mhz) 1245 max_dispclk_mhz = dcn3_03_soc.clock_limits[0].dispclk_mhz; 1246 if (!max_dppclk_mhz) 1247 max_dppclk_mhz = dcn3_03_soc.clock_limits[0].dppclk_mhz; 1248 if (!max_phyclk_mhz) 1249 max_phyclk_mhz = dcn3_03_soc.clock_limits[0].phyclk_mhz; 1250 1251 if (max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { 1252 dcfclk_sta_targets[num_dcfclk_sta_targets] = max_dcfclk_mhz; 1253 num_dcfclk_sta_targets++; 1254 } else if (max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { 1255 for (i = 0; i < num_dcfclk_sta_targets; i++) { 1256 if (dcfclk_sta_targets[i] > max_dcfclk_mhz) { 1257 dcfclk_sta_targets[i] = max_dcfclk_mhz; 1258 break; 1259 } 1260 } 1261 /* Update size of array since we "removed" duplicates */ 1262 num_dcfclk_sta_targets = i + 1; 1263 } 1264 1265 num_uclk_states = bw_params->clk_table.num_entries; 1266 1267 /* Calculate optimal dcfclk for each uclk */ 1268 for (i = 0; i < num_uclk_states; i++) { 1269 dcn303_get_optimal_dcfclk_fclk_for_uclk(bw_params->clk_table.entries[i].memclk_mhz * 16, 1270 &optimal_dcfclk_for_uclk[i], NULL); 1271 if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz) 1272 optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz; 1273 } 1274 1275 /* Calculate optimal uclk for each dcfclk sta target */ 1276 for (i = 0; i < num_dcfclk_sta_targets; i++) { 1277 for (j = 0; j < num_uclk_states; j++) { 1278 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) { 1279 optimal_uclk_for_dcfclk_sta_targets[i] = 1280 bw_params->clk_table.entries[j].memclk_mhz * 16; 1281 break; 1282 } 1283 } 1284 } 1285 1286 i = 0; 1287 j = 0; 1288 /* create the final dcfclk and uclk table */ 1289 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { 1290 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) { 1291 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; 1292 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; 1293 } else { 1294 if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) { 1295 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; 1296 dram_speed_mts[num_states++] = 1297 bw_params->clk_table.entries[j++].memclk_mhz * 16; 1298 } else { 1299 j = num_uclk_states; 1300 } 1301 } 1302 } 1303 1304 while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) { 1305 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; 1306 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; 1307 } 1308 1309 while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES && 1310 optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) { 1311 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; 1312 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16; 1313 } 1314 1315 dcn3_03_soc.num_states = num_states; 1316 for (i = 0; i < dcn3_03_soc.num_states; i++) { 1317 dcn3_03_soc.clock_limits[i].state = i; 1318 dcn3_03_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i]; 1319 dcn3_03_soc.clock_limits[i].fabricclk_mhz = dcfclk_mhz[i]; 1320 dcn3_03_soc.clock_limits[i].dram_speed_mts = dram_speed_mts[i]; 1321 1322 /* Fill all states with max values of all other clocks */ 1323 dcn3_03_soc.clock_limits[i].dispclk_mhz = max_dispclk_mhz; 1324 dcn3_03_soc.clock_limits[i].dppclk_mhz = max_dppclk_mhz; 1325 dcn3_03_soc.clock_limits[i].phyclk_mhz = max_phyclk_mhz; 1326 dcn3_03_soc.clock_limits[i].dtbclk_mhz = dcn3_03_soc.clock_limits[0].dtbclk_mhz; 1327 /* These clocks cannot come from bw_params, always fill from dcn3_03_soc[1] */ 1328 /* FCLK, PHYCLK_D18, SOCCLK, DSCCLK */ 1329 dcn3_03_soc.clock_limits[i].phyclk_d18_mhz = dcn3_03_soc.clock_limits[0].phyclk_d18_mhz; 1330 dcn3_03_soc.clock_limits[i].socclk_mhz = dcn3_03_soc.clock_limits[0].socclk_mhz; 1331 dcn3_03_soc.clock_limits[i].dscclk_mhz = dcn3_03_soc.clock_limits[0].dscclk_mhz; 1332 } 1333 /* re-init DML with updated bb */ 1334 dml_init_instance(&dc->dml, &dcn3_03_soc, &dcn3_03_ip, DML_PROJECT_DCN30); 1335 if (dc->current_state) 1336 dml_init_instance(&dc->current_state->bw_ctx.dml, &dcn3_03_soc, &dcn3_03_ip, DML_PROJECT_DCN30); 1337 } 1338 } 1339 1340 static struct resource_funcs dcn303_res_pool_funcs = { 1341 .destroy = dcn303_destroy_resource_pool, 1342 .link_enc_create = dcn303_link_encoder_create, 1343 .panel_cntl_create = dcn303_panel_cntl_create, 1344 .validate_bandwidth = dcn30_validate_bandwidth, 1345 .calculate_wm_and_dlg = dcn30_calculate_wm_and_dlg, 1346 .populate_dml_pipes = dcn30_populate_dml_pipes_from_context, 1347 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer, 1348 .add_stream_to_ctx = dcn30_add_stream_to_ctx, 1349 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, 1350 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 1351 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, 1352 .set_mcif_arb_params = dcn30_set_mcif_arb_params, 1353 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, 1354 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut, 1355 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut, 1356 .update_bw_bounding_box = dcn303_update_bw_bounding_box, 1357 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, 1358 }; 1359 1360 static struct dc_cap_funcs cap_funcs = { 1361 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap 1362 }; 1363 1364 static const struct bios_registers bios_regs = { 1365 NBIO_SR(BIOS_SCRATCH_3), 1366 NBIO_SR(BIOS_SCRATCH_6) 1367 }; 1368 1369 static const struct dccg_registers dccg_regs = { 1370 DCCG_REG_LIST_DCN3_03() 1371 }; 1372 1373 static const struct dccg_shift dccg_shift = { 1374 DCCG_MASK_SH_LIST_DCN3_03(__SHIFT) 1375 }; 1376 1377 static const struct dccg_mask dccg_mask = { 1378 DCCG_MASK_SH_LIST_DCN3_03(_MASK) 1379 }; 1380 1381 #define abm_regs(id)\ 1382 [id] = { ABM_DCN301_REG_LIST(id) } 1383 1384 static const struct dce_abm_registers abm_regs[] = { 1385 abm_regs(0), 1386 abm_regs(1) 1387 }; 1388 1389 static const struct dce_abm_shift abm_shift = { 1390 ABM_MASK_SH_LIST_DCN30(__SHIFT) 1391 }; 1392 1393 static const struct dce_abm_mask abm_mask = { 1394 ABM_MASK_SH_LIST_DCN30(_MASK) 1395 }; 1396 1397 static bool dcn303_resource_construct( 1398 uint8_t num_virtual_links, 1399 struct dc *dc, 1400 struct resource_pool *pool) 1401 { 1402 int i; 1403 struct dc_context *ctx = dc->ctx; 1404 struct irq_service_init_data init_data; 1405 struct ddc_service_init_data ddc_init_data; 1406 1407 ctx->dc_bios->regs = &bios_regs; 1408 1409 pool->res_cap = &res_cap_dcn303; 1410 1411 pool->funcs = &dcn303_res_pool_funcs; 1412 1413 /************************************************* 1414 * Resource + asic cap harcoding * 1415 *************************************************/ 1416 pool->underlay_pipe_index = NO_UNDERLAY_PIPE; 1417 pool->pipe_count = pool->res_cap->num_timing_generator; 1418 pool->mpcc_count = pool->res_cap->num_timing_generator; 1419 dc->caps.max_downscale_ratio = 600; 1420 dc->caps.i2c_speed_in_khz = 100; 1421 dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by derfault*/ 1422 dc->caps.max_cursor_size = 256; 1423 dc->caps.min_horizontal_blanking_period = 80; 1424 dc->caps.dmdata_alloc_size = 2048; 1425 #if defined(CONFIG_DRM_AMD_DC_DCN) 1426 dc->caps.mall_size_per_mem_channel = 4; 1427 /* total size = mall per channel * num channels * 1024 * 1024 */ 1428 dc->caps.mall_size_total = dc->caps.mall_size_per_mem_channel * 1429 dc->ctx->dc_bios->vram_info.num_chans * 1430 1024 * 1024; 1431 dc->caps.cursor_cache_size = 1432 dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8; 1433 #endif 1434 dc->caps.max_slave_planes = 1; 1435 dc->caps.post_blend_color_processing = true; 1436 dc->caps.force_dp_tps4_for_cp2520 = true; 1437 dc->caps.extended_aux_timeout_support = true; 1438 dc->caps.dmcub_support = true; 1439 1440 /* Color pipeline capabilities */ 1441 dc->caps.color.dpp.dcn_arch = 1; 1442 dc->caps.color.dpp.input_lut_shared = 0; 1443 dc->caps.color.dpp.icsc = 1; 1444 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr 1445 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; 1446 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; 1447 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1; 1448 dc->caps.color.dpp.dgam_rom_caps.pq = 1; 1449 dc->caps.color.dpp.dgam_rom_caps.hlg = 1; 1450 dc->caps.color.dpp.post_csc = 1; 1451 dc->caps.color.dpp.gamma_corr = 1; 1452 dc->caps.color.dpp.dgam_rom_for_yuv = 0; 1453 1454 dc->caps.color.dpp.hw_3d_lut = 1; 1455 dc->caps.color.dpp.ogam_ram = 1; 1456 // no OGAM ROM on DCN3 1457 dc->caps.color.dpp.ogam_rom_caps.srgb = 0; 1458 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; 1459 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; 1460 dc->caps.color.dpp.ogam_rom_caps.pq = 0; 1461 dc->caps.color.dpp.ogam_rom_caps.hlg = 0; 1462 dc->caps.color.dpp.ocsc = 0; 1463 1464 dc->caps.color.mpc.gamut_remap = 1; 1465 dc->caps.color.mpc.num_3dluts = pool->res_cap->num_mpc_3dlut; //3 1466 dc->caps.color.mpc.ogam_ram = 1; 1467 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; 1468 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; 1469 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; 1470 dc->caps.color.mpc.ogam_rom_caps.pq = 0; 1471 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 1472 dc->caps.color.mpc.ocsc = 1; 1473 1474 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 1475 dc->debug = debug_defaults_drv; 1476 else 1477 dc->debug = debug_defaults_diags; 1478 1479 // Init the vm_helper 1480 if (dc->vm_helper) 1481 vm_helper_init(dc->vm_helper, 16); 1482 1483 /************************************************* 1484 * Create resources * 1485 *************************************************/ 1486 1487 /* Clock Sources for Pixel Clock*/ 1488 pool->clock_sources[DCN303_CLK_SRC_PLL0] = 1489 dcn303_clock_source_create(ctx, ctx->dc_bios, 1490 CLOCK_SOURCE_COMBO_PHY_PLL0, 1491 &clk_src_regs[0], false); 1492 pool->clock_sources[DCN303_CLK_SRC_PLL1] = 1493 dcn303_clock_source_create(ctx, ctx->dc_bios, 1494 CLOCK_SOURCE_COMBO_PHY_PLL1, 1495 &clk_src_regs[1], false); 1496 1497 pool->clk_src_count = DCN303_CLK_SRC_TOTAL; 1498 1499 /* todo: not reuse phy_pll registers */ 1500 pool->dp_clock_source = 1501 dcn303_clock_source_create(ctx, ctx->dc_bios, 1502 CLOCK_SOURCE_ID_DP_DTO, 1503 &clk_src_regs[0], true); 1504 1505 for (i = 0; i < pool->clk_src_count; i++) { 1506 if (pool->clock_sources[i] == NULL) { 1507 dm_error("DC: failed to create clock sources!\n"); 1508 BREAK_TO_DEBUGGER(); 1509 goto create_fail; 1510 } 1511 } 1512 1513 /* DCCG */ 1514 pool->dccg = dccg30_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 1515 if (pool->dccg == NULL) { 1516 dm_error("DC: failed to create dccg!\n"); 1517 BREAK_TO_DEBUGGER(); 1518 goto create_fail; 1519 } 1520 1521 /* PP Lib and SMU interfaces */ 1522 init_soc_bounding_box(dc, pool); 1523 1524 /* DML */ 1525 dml_init_instance(&dc->dml, &dcn3_03_soc, &dcn3_03_ip, DML_PROJECT_DCN30); 1526 1527 /* IRQ */ 1528 init_data.ctx = dc->ctx; 1529 pool->irqs = dal_irq_service_dcn303_create(&init_data); 1530 if (!pool->irqs) 1531 goto create_fail; 1532 1533 /* HUBBUB */ 1534 pool->hubbub = dcn303_hubbub_create(ctx); 1535 if (pool->hubbub == NULL) { 1536 BREAK_TO_DEBUGGER(); 1537 dm_error("DC: failed to create hubbub!\n"); 1538 goto create_fail; 1539 } 1540 1541 /* HUBPs, DPPs, OPPs and TGs */ 1542 for (i = 0; i < pool->pipe_count; i++) { 1543 pool->hubps[i] = dcn303_hubp_create(ctx, i); 1544 if (pool->hubps[i] == NULL) { 1545 BREAK_TO_DEBUGGER(); 1546 dm_error("DC: failed to create hubps!\n"); 1547 goto create_fail; 1548 } 1549 1550 pool->dpps[i] = dcn303_dpp_create(ctx, i); 1551 if (pool->dpps[i] == NULL) { 1552 BREAK_TO_DEBUGGER(); 1553 dm_error("DC: failed to create dpps!\n"); 1554 goto create_fail; 1555 } 1556 } 1557 1558 for (i = 0; i < pool->res_cap->num_opp; i++) { 1559 pool->opps[i] = dcn303_opp_create(ctx, i); 1560 if (pool->opps[i] == NULL) { 1561 BREAK_TO_DEBUGGER(); 1562 dm_error("DC: failed to create output pixel processor!\n"); 1563 goto create_fail; 1564 } 1565 } 1566 1567 for (i = 0; i < pool->res_cap->num_timing_generator; i++) { 1568 pool->timing_generators[i] = dcn303_timing_generator_create(ctx, i); 1569 if (pool->timing_generators[i] == NULL) { 1570 BREAK_TO_DEBUGGER(); 1571 dm_error("DC: failed to create tg!\n"); 1572 goto create_fail; 1573 } 1574 } 1575 pool->timing_generator_count = i; 1576 1577 /* PSR */ 1578 pool->psr = dmub_psr_create(ctx); 1579 if (pool->psr == NULL) { 1580 dm_error("DC: failed to create psr!\n"); 1581 BREAK_TO_DEBUGGER(); 1582 goto create_fail; 1583 } 1584 1585 /* ABM */ 1586 for (i = 0; i < pool->res_cap->num_timing_generator; i++) { 1587 pool->multiple_abms[i] = dmub_abm_create(ctx, &abm_regs[i], &abm_shift, &abm_mask); 1588 if (pool->multiple_abms[i] == NULL) { 1589 dm_error("DC: failed to create abm for pipe %d!\n", i); 1590 BREAK_TO_DEBUGGER(); 1591 goto create_fail; 1592 } 1593 } 1594 1595 /* MPC and DSC */ 1596 pool->mpc = dcn303_mpc_create(ctx, pool->mpcc_count, pool->res_cap->num_mpc_3dlut); 1597 if (pool->mpc == NULL) { 1598 BREAK_TO_DEBUGGER(); 1599 dm_error("DC: failed to create mpc!\n"); 1600 goto create_fail; 1601 } 1602 1603 for (i = 0; i < pool->res_cap->num_dsc; i++) { 1604 pool->dscs[i] = dcn303_dsc_create(ctx, i); 1605 if (pool->dscs[i] == NULL) { 1606 BREAK_TO_DEBUGGER(); 1607 dm_error("DC: failed to create display stream compressor %d!\n", i); 1608 goto create_fail; 1609 } 1610 } 1611 1612 /* DWB and MMHUBBUB */ 1613 if (!dcn303_dwbc_create(ctx, pool)) { 1614 BREAK_TO_DEBUGGER(); 1615 dm_error("DC: failed to create dwbc!\n"); 1616 goto create_fail; 1617 } 1618 1619 if (!dcn303_mmhubbub_create(ctx, pool)) { 1620 BREAK_TO_DEBUGGER(); 1621 dm_error("DC: failed to create mcif_wb!\n"); 1622 goto create_fail; 1623 } 1624 1625 /* AUX and I2C */ 1626 for (i = 0; i < pool->res_cap->num_ddc; i++) { 1627 pool->engines[i] = dcn303_aux_engine_create(ctx, i); 1628 if (pool->engines[i] == NULL) { 1629 BREAK_TO_DEBUGGER(); 1630 dm_error("DC:failed to create aux engine!!\n"); 1631 goto create_fail; 1632 } 1633 pool->hw_i2cs[i] = dcn303_i2c_hw_create(ctx, i); 1634 if (pool->hw_i2cs[i] == NULL) { 1635 BREAK_TO_DEBUGGER(); 1636 dm_error("DC:failed to create hw i2c!!\n"); 1637 goto create_fail; 1638 } 1639 pool->sw_i2cs[i] = NULL; 1640 } 1641 1642 /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */ 1643 if (!resource_construct(num_virtual_links, dc, pool, 1644 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? 1645 &res_create_funcs : &res_create_maximus_funcs))) 1646 goto create_fail; 1647 1648 /* HW Sequencer and Plane caps */ 1649 dcn303_hw_sequencer_construct(dc); 1650 1651 dc->caps.max_planes = pool->pipe_count; 1652 1653 for (i = 0; i < dc->caps.max_planes; ++i) 1654 dc->caps.planes[i] = plane_cap; 1655 1656 dc->cap_funcs = cap_funcs; 1657 1658 if (dc->ctx->dc_bios->fw_info.oem_i2c_present) { 1659 ddc_init_data.ctx = dc->ctx; 1660 ddc_init_data.link = NULL; 1661 ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id; 1662 ddc_init_data.id.enum_id = 0; 1663 ddc_init_data.id.type = OBJECT_TYPE_GENERIC; 1664 pool->oem_device = dal_ddc_service_create(&ddc_init_data); 1665 } else { 1666 pool->oem_device = NULL; 1667 } 1668 1669 return true; 1670 1671 create_fail: 1672 1673 dcn303_resource_destruct(pool); 1674 1675 return false; 1676 } 1677 1678 struct resource_pool *dcn303_create_resource_pool(const struct dc_init_data *init_data, struct dc *dc) 1679 { 1680 struct resource_pool *pool = kzalloc(sizeof(struct resource_pool), GFP_KERNEL); 1681 1682 if (!pool) 1683 return NULL; 1684 1685 if (dcn303_resource_construct(init_data->num_virtual_links, dc, pool)) 1686 return pool; 1687 1688 BREAK_TO_DEBUGGER(); 1689 kfree(pool); 1690 return NULL; 1691 } 1692