1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright (C) 2021 Advanced Micro Devices, Inc. 4 * 5 * Authors: AMD 6 */ 7 8 #include "dcn303_init.h" 9 #include "dcn303_resource.h" 10 #include "dcn303_dccg.h" 11 #include "irq/dcn303/irq_service_dcn303.h" 12 13 #include "dcn30/dcn30_dio_link_encoder.h" 14 #include "dcn30/dcn30_dio_stream_encoder.h" 15 #include "dcn30/dcn30_dpp.h" 16 #include "dcn30/dcn30_dwb.h" 17 #include "dcn30/dcn30_hubbub.h" 18 #include "dcn30/dcn30_hubp.h" 19 #include "dcn30/dcn30_mmhubbub.h" 20 #include "dcn30/dcn30_mpc.h" 21 #include "dcn30/dcn30_opp.h" 22 #include "dcn30/dcn30_optc.h" 23 #include "dcn30/dcn30_resource.h" 24 25 #include "dcn20/dcn20_dsc.h" 26 #include "dcn20/dcn20_resource.h" 27 28 #include "dml/dcn30/dcn30_fpu.h" 29 30 #include "dcn10/dcn10_resource.h" 31 32 #include "link.h" 33 34 #include "dce/dce_abm.h" 35 #include "dce/dce_audio.h" 36 #include "dce/dce_aux.h" 37 #include "dce/dce_clock_source.h" 38 #include "dce/dce_hwseq.h" 39 #include "dce/dce_i2c_hw.h" 40 #include "dce/dce_panel_cntl.h" 41 #include "dce/dmub_abm.h" 42 #include "dce/dmub_psr.h" 43 #include "clk_mgr.h" 44 45 #include "hw_sequencer_private.h" 46 #include "reg_helper.h" 47 #include "resource.h" 48 #include "vm_helper.h" 49 50 #include "sienna_cichlid_ip_offset.h" 51 #include "dcn/dcn_3_0_3_offset.h" 52 #include "dcn/dcn_3_0_3_sh_mask.h" 53 #include "dpcs/dpcs_3_0_3_offset.h" 54 #include "dpcs/dpcs_3_0_3_sh_mask.h" 55 #include "nbio/nbio_2_3_offset.h" 56 57 #include "dml/dcn303/dcn303_fpu.h" 58 59 #define DC_LOGGER_INIT(logger) 60 61 62 static const struct dc_debug_options debug_defaults_drv = { 63 .disable_dmcu = true, 64 .force_abm_enable = false, 65 .timing_trace = false, 66 .clock_trace = true, 67 .disable_pplib_clock_request = true, 68 .pipe_split_policy = MPC_SPLIT_AVOID, 69 .force_single_disp_pipe_split = false, 70 .disable_dcc = DCC_ENABLE, 71 .vsr_support = true, 72 .performance_trace = false, 73 .max_downscale_src_width = 7680,/*upto 8K*/ 74 .disable_pplib_wm_range = false, 75 .scl_reset_length10 = true, 76 .sanity_checks = false, 77 .underflow_assert_delay_us = 0xFFFFFFFF, 78 .dwb_fi_phase = -1, // -1 = disable, 79 .dmub_command_table = true, 80 .exit_idle_opt_for_cursor_updates = true, 81 .disable_idle_power_optimizations = false, 82 }; 83 84 static const struct dc_panel_config panel_config_defaults = { 85 .psr = { 86 .disable_psr = false, 87 .disallow_psrsu = false, 88 }, 89 }; 90 91 enum dcn303_clk_src_array_id { 92 DCN303_CLK_SRC_PLL0, 93 DCN303_CLK_SRC_PLL1, 94 DCN303_CLK_SRC_TOTAL 95 }; 96 97 static const struct resource_caps res_cap_dcn303 = { 98 .num_timing_generator = 2, 99 .num_opp = 2, 100 .num_video_plane = 2, 101 .num_audio = 2, 102 .num_stream_encoder = 2, 103 .num_dwb = 1, 104 .num_ddc = 2, 105 .num_vmid = 16, 106 .num_mpc_3dlut = 1, 107 .num_dsc = 2, 108 }; 109 110 static const struct dc_plane_cap plane_cap = { 111 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 112 .per_pixel_alpha = true, 113 .pixel_format_support = { 114 .argb8888 = true, 115 .nv12 = true, 116 .fp16 = true, 117 .p010 = true, 118 .ayuv = false, 119 }, 120 .max_upscale_factor = { 121 .argb8888 = 16000, 122 .nv12 = 16000, 123 .fp16 = 16000 124 }, 125 .max_downscale_factor = { 126 .argb8888 = 600, 127 .nv12 = 600, 128 .fp16 = 600 129 }, 130 16, 131 16 132 }; 133 134 /* NBIO */ 135 #define NBIO_BASE_INNER(seg) \ 136 NBIO_BASE__INST0_SEG ## seg 137 138 #define NBIO_BASE(seg) \ 139 NBIO_BASE_INNER(seg) 140 141 #define NBIO_SR(reg_name)\ 142 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \ 143 mm ## reg_name 144 145 /* DCN */ 146 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg 147 148 #define BASE(seg) BASE_INNER(seg) 149 150 #define SR(reg_name)\ 151 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name 152 153 #define SF(reg_name, field_name, post_fix)\ 154 .field_name = reg_name ## __ ## field_name ## post_fix 155 156 #define SRI(reg_name, block, id)\ 157 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + mm ## block ## id ## _ ## reg_name 158 159 #define SRI2(reg_name, block, id)\ 160 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name 161 162 #define SRII(reg_name, block, id)\ 163 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 164 mm ## block ## id ## _ ## reg_name 165 166 #define DCCG_SRII(reg_name, block, id)\ 167 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 168 mm ## block ## id ## _ ## reg_name 169 170 #define VUPDATE_SRII(reg_name, block, id)\ 171 .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \ 172 mm ## reg_name ## _ ## block ## id 173 174 #define SRII_DWB(reg_name, temp_name, block, id)\ 175 .reg_name[id] = BASE(mm ## block ## id ## _ ## temp_name ## _BASE_IDX) + \ 176 mm ## block ## id ## _ ## temp_name 177 178 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \ 179 .field_name = reg_name ## __ ## field_name ## post_fix 180 181 #define SRII_MPC_RMU(reg_name, block, id)\ 182 .RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 183 mm ## block ## id ## _ ## reg_name 184 185 static const struct dcn_hubbub_registers hubbub_reg = { 186 HUBBUB_REG_LIST_DCN30(0) 187 }; 188 189 static const struct dcn_hubbub_shift hubbub_shift = { 190 HUBBUB_MASK_SH_LIST_DCN30(__SHIFT) 191 }; 192 193 static const struct dcn_hubbub_mask hubbub_mask = { 194 HUBBUB_MASK_SH_LIST_DCN30(_MASK) 195 }; 196 197 #define vmid_regs(id)\ 198 [id] = { DCN20_VMID_REG_LIST(id) } 199 200 static const struct dcn_vmid_registers vmid_regs[] = { 201 vmid_regs(0), 202 vmid_regs(1), 203 vmid_regs(2), 204 vmid_regs(3), 205 vmid_regs(4), 206 vmid_regs(5), 207 vmid_regs(6), 208 vmid_regs(7), 209 vmid_regs(8), 210 vmid_regs(9), 211 vmid_regs(10), 212 vmid_regs(11), 213 vmid_regs(12), 214 vmid_regs(13), 215 vmid_regs(14), 216 vmid_regs(15) 217 }; 218 219 static const struct dcn20_vmid_shift vmid_shifts = { 220 DCN20_VMID_MASK_SH_LIST(__SHIFT) 221 }; 222 223 static const struct dcn20_vmid_mask vmid_masks = { 224 DCN20_VMID_MASK_SH_LIST(_MASK) 225 }; 226 227 static struct hubbub *dcn303_hubbub_create(struct dc_context *ctx) 228 { 229 int i; 230 231 struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub), GFP_KERNEL); 232 233 if (!hubbub3) 234 return NULL; 235 236 hubbub3_construct(hubbub3, ctx, &hubbub_reg, &hubbub_shift, &hubbub_mask); 237 238 for (i = 0; i < res_cap_dcn303.num_vmid; i++) { 239 struct dcn20_vmid *vmid = &hubbub3->vmid[i]; 240 241 vmid->ctx = ctx; 242 243 vmid->regs = &vmid_regs[i]; 244 vmid->shifts = &vmid_shifts; 245 vmid->masks = &vmid_masks; 246 } 247 248 return &hubbub3->base; 249 } 250 251 #define vpg_regs(id)\ 252 [id] = { VPG_DCN3_REG_LIST(id) } 253 254 static const struct dcn30_vpg_registers vpg_regs[] = { 255 vpg_regs(0), 256 vpg_regs(1), 257 vpg_regs(2) 258 }; 259 260 static const struct dcn30_vpg_shift vpg_shift = { 261 DCN3_VPG_MASK_SH_LIST(__SHIFT) 262 }; 263 264 static const struct dcn30_vpg_mask vpg_mask = { 265 DCN3_VPG_MASK_SH_LIST(_MASK) 266 }; 267 268 static struct vpg *dcn303_vpg_create(struct dc_context *ctx, uint32_t inst) 269 { 270 struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL); 271 272 if (!vpg3) 273 return NULL; 274 275 vpg3_construct(vpg3, ctx, inst, &vpg_regs[inst], &vpg_shift, &vpg_mask); 276 277 return &vpg3->base; 278 } 279 280 #define afmt_regs(id)\ 281 [id] = { AFMT_DCN3_REG_LIST(id) } 282 283 static const struct dcn30_afmt_registers afmt_regs[] = { 284 afmt_regs(0), 285 afmt_regs(1), 286 afmt_regs(2) 287 }; 288 289 static const struct dcn30_afmt_shift afmt_shift = { 290 DCN3_AFMT_MASK_SH_LIST(__SHIFT) 291 }; 292 293 static const struct dcn30_afmt_mask afmt_mask = { 294 DCN3_AFMT_MASK_SH_LIST(_MASK) 295 }; 296 297 static struct afmt *dcn303_afmt_create(struct dc_context *ctx, uint32_t inst) 298 { 299 struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL); 300 301 if (!afmt3) 302 return NULL; 303 304 afmt3_construct(afmt3, ctx, inst, &afmt_regs[inst], &afmt_shift, &afmt_mask); 305 306 return &afmt3->base; 307 } 308 309 #define audio_regs(id)\ 310 [id] = { AUD_COMMON_REG_LIST(id) } 311 312 static const struct dce_audio_registers audio_regs[] = { 313 audio_regs(0), 314 audio_regs(1), 315 audio_regs(2), 316 audio_regs(3), 317 audio_regs(4), 318 audio_regs(5), 319 audio_regs(6) 320 }; 321 322 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 323 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 324 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 325 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 326 327 static const struct dce_audio_shift audio_shift = { 328 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 329 }; 330 331 static const struct dce_audio_mask audio_mask = { 332 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 333 }; 334 335 static struct audio *dcn303_create_audio(struct dc_context *ctx, unsigned int inst) 336 { 337 return dce_audio_create(ctx, inst, &audio_regs[inst], &audio_shift, &audio_mask); 338 } 339 340 #define stream_enc_regs(id)\ 341 [id] = { SE_DCN3_REG_LIST(id) } 342 343 static const struct dcn10_stream_enc_registers stream_enc_regs[] = { 344 stream_enc_regs(0), 345 stream_enc_regs(1) 346 }; 347 348 static const struct dcn10_stream_encoder_shift se_shift = { 349 SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 350 }; 351 352 static const struct dcn10_stream_encoder_mask se_mask = { 353 SE_COMMON_MASK_SH_LIST_DCN30(_MASK) 354 }; 355 356 static struct stream_encoder *dcn303_stream_encoder_create(enum engine_id eng_id, struct dc_context *ctx) 357 { 358 struct dcn10_stream_encoder *enc1; 359 struct vpg *vpg; 360 struct afmt *afmt; 361 int vpg_inst; 362 int afmt_inst; 363 364 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */ 365 if (eng_id <= ENGINE_ID_DIGB) { 366 vpg_inst = eng_id; 367 afmt_inst = eng_id; 368 } else 369 return NULL; 370 371 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 372 vpg = dcn303_vpg_create(ctx, vpg_inst); 373 afmt = dcn303_afmt_create(ctx, afmt_inst); 374 375 if (!enc1 || !vpg || !afmt) { 376 kfree(enc1); 377 kfree(vpg); 378 kfree(afmt); 379 return NULL; 380 } 381 382 dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id, vpg, afmt, &stream_enc_regs[eng_id], 383 &se_shift, &se_mask); 384 385 return &enc1->base; 386 } 387 388 #define clk_src_regs(index, pllid)\ 389 [index] = { CS_COMMON_REG_LIST_DCN3_03(index, pllid) } 390 391 static const struct dce110_clk_src_regs clk_src_regs[] = { 392 clk_src_regs(0, A), 393 clk_src_regs(1, B) 394 }; 395 396 static const struct dce110_clk_src_shift cs_shift = { 397 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 398 }; 399 400 static const struct dce110_clk_src_mask cs_mask = { 401 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 402 }; 403 404 static struct clock_source *dcn303_clock_source_create(struct dc_context *ctx, struct dc_bios *bios, 405 enum clock_source_id id, const struct dce110_clk_src_regs *regs, bool dp_clk_src) 406 { 407 struct dce110_clk_src *clk_src = kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 408 409 if (!clk_src) 410 return NULL; 411 412 if (dcn3_clk_src_construct(clk_src, ctx, bios, id, regs, &cs_shift, &cs_mask)) { 413 clk_src->base.dp_clk_src = dp_clk_src; 414 return &clk_src->base; 415 } 416 417 kfree(clk_src); 418 BREAK_TO_DEBUGGER(); 419 return NULL; 420 } 421 422 static const struct dce_hwseq_registers hwseq_reg = { 423 HWSEQ_DCN303_REG_LIST() 424 }; 425 426 static const struct dce_hwseq_shift hwseq_shift = { 427 HWSEQ_DCN303_MASK_SH_LIST(__SHIFT) 428 }; 429 430 static const struct dce_hwseq_mask hwseq_mask = { 431 HWSEQ_DCN303_MASK_SH_LIST(_MASK) 432 }; 433 434 static struct dce_hwseq *dcn303_hwseq_create(struct dc_context *ctx) 435 { 436 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 437 438 if (hws) { 439 hws->ctx = ctx; 440 hws->regs = &hwseq_reg; 441 hws->shifts = &hwseq_shift; 442 hws->masks = &hwseq_mask; 443 } 444 return hws; 445 } 446 447 #define hubp_regs(id)\ 448 [id] = { HUBP_REG_LIST_DCN30(id) } 449 450 static const struct dcn_hubp2_registers hubp_regs[] = { 451 hubp_regs(0), 452 hubp_regs(1) 453 }; 454 455 static const struct dcn_hubp2_shift hubp_shift = { 456 HUBP_MASK_SH_LIST_DCN30(__SHIFT) 457 }; 458 459 static const struct dcn_hubp2_mask hubp_mask = { 460 HUBP_MASK_SH_LIST_DCN30(_MASK) 461 }; 462 463 static struct hubp *dcn303_hubp_create(struct dc_context *ctx, uint32_t inst) 464 { 465 struct dcn20_hubp *hubp2 = kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL); 466 467 if (!hubp2) 468 return NULL; 469 470 if (hubp3_construct(hubp2, ctx, inst, &hubp_regs[inst], &hubp_shift, &hubp_mask)) 471 return &hubp2->base; 472 473 BREAK_TO_DEBUGGER(); 474 kfree(hubp2); 475 return NULL; 476 } 477 478 #define dpp_regs(id)\ 479 [id] = { DPP_REG_LIST_DCN30(id) } 480 481 static const struct dcn3_dpp_registers dpp_regs[] = { 482 dpp_regs(0), 483 dpp_regs(1) 484 }; 485 486 static const struct dcn3_dpp_shift tf_shift = { 487 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT) 488 }; 489 490 static const struct dcn3_dpp_mask tf_mask = { 491 DPP_REG_LIST_SH_MASK_DCN30(_MASK) 492 }; 493 494 static struct dpp *dcn303_dpp_create(struct dc_context *ctx, uint32_t inst) 495 { 496 struct dcn3_dpp *dpp = kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL); 497 498 if (!dpp) 499 return NULL; 500 501 if (dpp3_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, &tf_mask)) 502 return &dpp->base; 503 504 BREAK_TO_DEBUGGER(); 505 kfree(dpp); 506 return NULL; 507 } 508 509 #define opp_regs(id)\ 510 [id] = { OPP_REG_LIST_DCN30(id) } 511 512 static const struct dcn20_opp_registers opp_regs[] = { 513 opp_regs(0), 514 opp_regs(1) 515 }; 516 517 static const struct dcn20_opp_shift opp_shift = { 518 OPP_MASK_SH_LIST_DCN20(__SHIFT) 519 }; 520 521 static const struct dcn20_opp_mask opp_mask = { 522 OPP_MASK_SH_LIST_DCN20(_MASK) 523 }; 524 525 static struct output_pixel_processor *dcn303_opp_create(struct dc_context *ctx, uint32_t inst) 526 { 527 struct dcn20_opp *opp = kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); 528 529 if (!opp) { 530 BREAK_TO_DEBUGGER(); 531 return NULL; 532 } 533 534 dcn20_opp_construct(opp, ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask); 535 return &opp->base; 536 } 537 538 #define optc_regs(id)\ 539 [id] = { OPTC_COMMON_REG_LIST_DCN3_0(id) } 540 541 static const struct dcn_optc_registers optc_regs[] = { 542 optc_regs(0), 543 optc_regs(1) 544 }; 545 546 static const struct dcn_optc_shift optc_shift = { 547 OPTC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 548 }; 549 550 static const struct dcn_optc_mask optc_mask = { 551 OPTC_COMMON_MASK_SH_LIST_DCN30(_MASK) 552 }; 553 554 static struct timing_generator *dcn303_timing_generator_create(struct dc_context *ctx, uint32_t instance) 555 { 556 struct optc *tgn10 = kzalloc(sizeof(struct optc), GFP_KERNEL); 557 558 if (!tgn10) 559 return NULL; 560 561 tgn10->base.inst = instance; 562 tgn10->base.ctx = ctx; 563 564 tgn10->tg_regs = &optc_regs[instance]; 565 tgn10->tg_shift = &optc_shift; 566 tgn10->tg_mask = &optc_mask; 567 568 dcn30_timing_generator_init(tgn10); 569 570 return &tgn10->base; 571 } 572 573 static const struct dcn30_mpc_registers mpc_regs = { 574 MPC_REG_LIST_DCN3_0(0), 575 MPC_REG_LIST_DCN3_0(1), 576 MPC_OUT_MUX_REG_LIST_DCN3_0(0), 577 MPC_OUT_MUX_REG_LIST_DCN3_0(1), 578 MPC_RMU_GLOBAL_REG_LIST_DCN3AG, 579 MPC_RMU_REG_LIST_DCN3AG(0), 580 MPC_DWB_MUX_REG_LIST_DCN3_0(0), 581 }; 582 583 static const struct dcn30_mpc_shift mpc_shift = { 584 MPC_COMMON_MASK_SH_LIST_DCN303(__SHIFT) 585 }; 586 587 static const struct dcn30_mpc_mask mpc_mask = { 588 MPC_COMMON_MASK_SH_LIST_DCN303(_MASK) 589 }; 590 591 static struct mpc *dcn303_mpc_create(struct dc_context *ctx, int num_mpcc, int num_rmu) 592 { 593 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), GFP_KERNEL); 594 595 if (!mpc30) 596 return NULL; 597 598 dcn30_mpc_construct(mpc30, ctx, &mpc_regs, &mpc_shift, &mpc_mask, num_mpcc, num_rmu); 599 600 return &mpc30->base; 601 } 602 603 #define dsc_regsDCN20(id)\ 604 [id] = { DSC_REG_LIST_DCN20(id) } 605 606 static const struct dcn20_dsc_registers dsc_regs[] = { 607 dsc_regsDCN20(0), 608 dsc_regsDCN20(1) 609 }; 610 611 static const struct dcn20_dsc_shift dsc_shift = { 612 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) 613 }; 614 615 static const struct dcn20_dsc_mask dsc_mask = { 616 DSC_REG_LIST_SH_MASK_DCN20(_MASK) 617 }; 618 619 static struct display_stream_compressor *dcn303_dsc_create(struct dc_context *ctx, uint32_t inst) 620 { 621 struct dcn20_dsc *dsc = kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); 622 623 if (!dsc) { 624 BREAK_TO_DEBUGGER(); 625 return NULL; 626 } 627 628 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 629 return &dsc->base; 630 } 631 632 #define dwbc_regs_dcn3(id)\ 633 [id] = { DWBC_COMMON_REG_LIST_DCN30(id) } 634 635 static const struct dcn30_dwbc_registers dwbc30_regs[] = { 636 dwbc_regs_dcn3(0) 637 }; 638 639 static const struct dcn30_dwbc_shift dwbc30_shift = { 640 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 641 }; 642 643 static const struct dcn30_dwbc_mask dwbc30_mask = { 644 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK) 645 }; 646 647 static bool dcn303_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) 648 { 649 int i; 650 uint32_t pipe_count = pool->res_cap->num_dwb; 651 652 for (i = 0; i < pipe_count; i++) { 653 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), GFP_KERNEL); 654 655 if (!dwbc30) { 656 dm_error("DC: failed to create dwbc30!\n"); 657 return false; 658 } 659 660 dcn30_dwbc_construct(dwbc30, ctx, &dwbc30_regs[i], &dwbc30_shift, &dwbc30_mask, i); 661 662 pool->dwbc[i] = &dwbc30->base; 663 } 664 return true; 665 } 666 667 #define mcif_wb_regs_dcn3(id)\ 668 [id] = { MCIF_WB_COMMON_REG_LIST_DCN30(id) } 669 670 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = { 671 mcif_wb_regs_dcn3(0) 672 }; 673 674 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = { 675 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 676 }; 677 678 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { 679 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK) 680 }; 681 682 static bool dcn303_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) 683 { 684 int i; 685 uint32_t pipe_count = pool->res_cap->num_dwb; 686 687 for (i = 0; i < pipe_count; i++) { 688 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), GFP_KERNEL); 689 690 if (!mcif_wb30) { 691 dm_error("DC: failed to create mcif_wb30!\n"); 692 return false; 693 } 694 695 dcn30_mmhubbub_construct(mcif_wb30, ctx, &mcif_wb30_regs[i], &mcif_wb30_shift, &mcif_wb30_mask, i); 696 697 pool->mcif_wb[i] = &mcif_wb30->base; 698 } 699 return true; 700 } 701 702 #define aux_engine_regs(id)\ 703 [id] = {\ 704 AUX_COMMON_REG_LIST0(id), \ 705 .AUXN_IMPCAL = 0, \ 706 .AUXP_IMPCAL = 0, \ 707 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \ 708 } 709 710 static const struct dce110_aux_registers aux_engine_regs[] = { 711 aux_engine_regs(0), 712 aux_engine_regs(1) 713 }; 714 715 static const struct dce110_aux_registers_shift aux_shift = { 716 DCN_AUX_MASK_SH_LIST(__SHIFT) 717 }; 718 719 static const struct dce110_aux_registers_mask aux_mask = { 720 DCN_AUX_MASK_SH_LIST(_MASK) 721 }; 722 723 static struct dce_aux *dcn303_aux_engine_create(struct dc_context *ctx, uint32_t inst) 724 { 725 struct aux_engine_dce110 *aux_engine = kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 726 727 if (!aux_engine) 728 return NULL; 729 730 dce110_aux_engine_construct(aux_engine, ctx, inst, SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 731 &aux_engine_regs[inst], &aux_mask, &aux_shift, ctx->dc->caps.extended_aux_timeout_support); 732 733 return &aux_engine->base; 734 } 735 736 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 737 738 static const struct dce_i2c_registers i2c_hw_regs[] = { 739 i2c_inst_regs(1), 740 i2c_inst_regs(2) 741 }; 742 743 static const struct dce_i2c_shift i2c_shifts = { 744 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT) 745 }; 746 747 static const struct dce_i2c_mask i2c_masks = { 748 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK) 749 }; 750 751 static struct dce_i2c_hw *dcn303_i2c_hw_create(struct dc_context *ctx, uint32_t inst) 752 { 753 struct dce_i2c_hw *dce_i2c_hw = kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 754 755 if (!dce_i2c_hw) 756 return NULL; 757 758 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 759 760 return dce_i2c_hw; 761 } 762 763 static const struct encoder_feature_support link_enc_feature = { 764 .max_hdmi_deep_color = COLOR_DEPTH_121212, 765 .max_hdmi_pixel_clock = 600000, 766 .hdmi_ycbcr420_supported = true, 767 .dp_ycbcr420_supported = true, 768 .fec_supported = true, 769 .flags.bits.IS_HBR2_CAPABLE = true, 770 .flags.bits.IS_HBR3_CAPABLE = true, 771 .flags.bits.IS_TPS3_CAPABLE = true, 772 .flags.bits.IS_TPS4_CAPABLE = true 773 }; 774 775 #define link_regs(id, phyid)\ 776 [id] = {\ 777 LE_DCN3_REG_LIST(id), \ 778 UNIPHY_DCN2_REG_LIST(phyid), \ 779 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \ 780 } 781 782 static const struct dcn10_link_enc_registers link_enc_regs[] = { 783 link_regs(0, A), 784 link_regs(1, B) 785 }; 786 787 static const struct dcn10_link_enc_shift le_shift = { 788 LINK_ENCODER_MASK_SH_LIST_DCN30(__SHIFT), 789 DPCS_DCN2_MASK_SH_LIST(__SHIFT) 790 }; 791 792 static const struct dcn10_link_enc_mask le_mask = { 793 LINK_ENCODER_MASK_SH_LIST_DCN30(_MASK), 794 DPCS_DCN2_MASK_SH_LIST(_MASK) 795 }; 796 797 #define aux_regs(id)\ 798 [id] = { DCN2_AUX_REG_LIST(id) } 799 800 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { 801 aux_regs(0), 802 aux_regs(1) 803 }; 804 805 #define hpd_regs(id)\ 806 [id] = { HPD_REG_LIST(id) } 807 808 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { 809 hpd_regs(0), 810 hpd_regs(1) 811 }; 812 813 static struct link_encoder *dcn303_link_encoder_create( 814 struct dc_context *ctx, 815 const struct encoder_init_data *enc_init_data) 816 { 817 struct dcn20_link_encoder *enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 818 819 if (!enc20) 820 return NULL; 821 822 dcn30_link_encoder_construct(enc20, enc_init_data, &link_enc_feature, 823 &link_enc_regs[enc_init_data->transmitter], &link_enc_aux_regs[enc_init_data->channel - 1], 824 &link_enc_hpd_regs[enc_init_data->hpd_source], &le_shift, &le_mask); 825 826 return &enc20->enc10.base; 827 } 828 829 static const struct dce_panel_cntl_registers panel_cntl_regs[] = { 830 { DCN_PANEL_CNTL_REG_LIST() } 831 }; 832 833 static const struct dce_panel_cntl_shift panel_cntl_shift = { 834 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT) 835 }; 836 837 static const struct dce_panel_cntl_mask panel_cntl_mask = { 838 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK) 839 }; 840 841 static struct panel_cntl *dcn303_panel_cntl_create(const struct panel_cntl_init_data *init_data) 842 { 843 struct dce_panel_cntl *panel_cntl = kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL); 844 845 if (!panel_cntl) 846 return NULL; 847 848 dce_panel_cntl_construct(panel_cntl, init_data, &panel_cntl_regs[init_data->inst], 849 &panel_cntl_shift, &panel_cntl_mask); 850 851 return &panel_cntl->base; 852 } 853 854 static void read_dce_straps(struct dc_context *ctx, struct resource_straps *straps) 855 { 856 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX), 857 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 858 } 859 860 static const struct resource_create_funcs res_create_funcs = { 861 .read_dce_straps = read_dce_straps, 862 .create_audio = dcn303_create_audio, 863 .create_stream_encoder = dcn303_stream_encoder_create, 864 .create_hwseq = dcn303_hwseq_create, 865 }; 866 867 static bool is_soc_bounding_box_valid(struct dc *dc) 868 { 869 uint32_t hw_internal_rev = dc->ctx->asic_id.hw_internal_rev; 870 871 if (ASICREV_IS_BEIGE_GOBY_P(hw_internal_rev)) 872 return true; 873 874 return false; 875 } 876 877 static bool init_soc_bounding_box(struct dc *dc, struct resource_pool *pool) 878 { 879 struct _vcs_dpi_soc_bounding_box_st *loaded_bb = &dcn3_03_soc; 880 struct _vcs_dpi_ip_params_st *loaded_ip = &dcn3_03_ip; 881 882 DC_LOGGER_INIT(dc->ctx->logger); 883 884 if (!is_soc_bounding_box_valid(dc)) { 885 DC_LOG_ERROR("%s: not valid soc bounding box/n", __func__); 886 return false; 887 } 888 889 loaded_ip->max_num_otg = pool->pipe_count; 890 loaded_ip->max_num_dpp = pool->pipe_count; 891 loaded_ip->clamp_min_dcfclk = dc->config.clamp_min_dcfclk; 892 DC_FP_START(); 893 dcn20_patch_bounding_box(dc, loaded_bb); 894 DC_FP_END(); 895 896 if (dc->ctx->dc_bios->funcs->get_soc_bb_info) { 897 struct bp_soc_bb_info bb_info = { 0 }; 898 899 if (dc->ctx->dc_bios->funcs->get_soc_bb_info( 900 dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) { 901 DC_FP_START(); 902 dcn303_fpu_init_soc_bounding_box(bb_info); 903 DC_FP_END(); 904 } 905 } 906 907 return true; 908 } 909 910 static void dcn303_resource_destruct(struct resource_pool *pool) 911 { 912 unsigned int i; 913 914 for (i = 0; i < pool->stream_enc_count; i++) { 915 if (pool->stream_enc[i] != NULL) { 916 if (pool->stream_enc[i]->vpg != NULL) { 917 kfree(DCN30_VPG_FROM_VPG(pool->stream_enc[i]->vpg)); 918 pool->stream_enc[i]->vpg = NULL; 919 } 920 if (pool->stream_enc[i]->afmt != NULL) { 921 kfree(DCN30_AFMT_FROM_AFMT(pool->stream_enc[i]->afmt)); 922 pool->stream_enc[i]->afmt = NULL; 923 } 924 kfree(DCN10STRENC_FROM_STRENC(pool->stream_enc[i])); 925 pool->stream_enc[i] = NULL; 926 } 927 } 928 929 for (i = 0; i < pool->res_cap->num_dsc; i++) { 930 if (pool->dscs[i] != NULL) 931 dcn20_dsc_destroy(&pool->dscs[i]); 932 } 933 934 if (pool->mpc != NULL) { 935 kfree(TO_DCN20_MPC(pool->mpc)); 936 pool->mpc = NULL; 937 } 938 939 if (pool->hubbub != NULL) { 940 kfree(pool->hubbub); 941 pool->hubbub = NULL; 942 } 943 944 for (i = 0; i < pool->pipe_count; i++) { 945 if (pool->dpps[i] != NULL) { 946 kfree(TO_DCN20_DPP(pool->dpps[i])); 947 pool->dpps[i] = NULL; 948 } 949 950 if (pool->hubps[i] != NULL) { 951 kfree(TO_DCN20_HUBP(pool->hubps[i])); 952 pool->hubps[i] = NULL; 953 } 954 955 if (pool->irqs != NULL) 956 dal_irq_service_destroy(&pool->irqs); 957 } 958 959 for (i = 0; i < pool->res_cap->num_ddc; i++) { 960 if (pool->engines[i] != NULL) 961 dce110_engine_destroy(&pool->engines[i]); 962 if (pool->hw_i2cs[i] != NULL) { 963 kfree(pool->hw_i2cs[i]); 964 pool->hw_i2cs[i] = NULL; 965 } 966 if (pool->sw_i2cs[i] != NULL) { 967 kfree(pool->sw_i2cs[i]); 968 pool->sw_i2cs[i] = NULL; 969 } 970 } 971 972 for (i = 0; i < pool->res_cap->num_opp; i++) { 973 if (pool->opps[i] != NULL) 974 pool->opps[i]->funcs->opp_destroy(&pool->opps[i]); 975 } 976 977 for (i = 0; i < pool->res_cap->num_timing_generator; i++) { 978 if (pool->timing_generators[i] != NULL) { 979 kfree(DCN10TG_FROM_TG(pool->timing_generators[i])); 980 pool->timing_generators[i] = NULL; 981 } 982 } 983 984 for (i = 0; i < pool->res_cap->num_dwb; i++) { 985 if (pool->dwbc[i] != NULL) { 986 kfree(TO_DCN30_DWBC(pool->dwbc[i])); 987 pool->dwbc[i] = NULL; 988 } 989 if (pool->mcif_wb[i] != NULL) { 990 kfree(TO_DCN30_MMHUBBUB(pool->mcif_wb[i])); 991 pool->mcif_wb[i] = NULL; 992 } 993 } 994 995 for (i = 0; i < pool->audio_count; i++) { 996 if (pool->audios[i]) 997 dce_aud_destroy(&pool->audios[i]); 998 } 999 1000 for (i = 0; i < pool->clk_src_count; i++) { 1001 if (pool->clock_sources[i] != NULL) 1002 dcn20_clock_source_destroy(&pool->clock_sources[i]); 1003 } 1004 1005 if (pool->dp_clock_source != NULL) 1006 dcn20_clock_source_destroy(&pool->dp_clock_source); 1007 1008 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { 1009 if (pool->mpc_lut[i] != NULL) { 1010 dc_3dlut_func_release(pool->mpc_lut[i]); 1011 pool->mpc_lut[i] = NULL; 1012 } 1013 if (pool->mpc_shaper[i] != NULL) { 1014 dc_transfer_func_release(pool->mpc_shaper[i]); 1015 pool->mpc_shaper[i] = NULL; 1016 } 1017 } 1018 1019 for (i = 0; i < pool->pipe_count; i++) { 1020 if (pool->multiple_abms[i] != NULL) 1021 dce_abm_destroy(&pool->multiple_abms[i]); 1022 } 1023 1024 if (pool->psr != NULL) 1025 dmub_psr_destroy(&pool->psr); 1026 1027 if (pool->dccg != NULL) 1028 dcn_dccg_destroy(&pool->dccg); 1029 1030 if (pool->oem_device != NULL) { 1031 struct dc *dc = pool->oem_device->ctx->dc; 1032 1033 dc->link_srv->destroy_ddc_service(&pool->oem_device); 1034 } 1035 } 1036 1037 static void dcn303_destroy_resource_pool(struct resource_pool **pool) 1038 { 1039 dcn303_resource_destruct(*pool); 1040 kfree(*pool); 1041 *pool = NULL; 1042 } 1043 1044 static void dcn303_get_panel_config_defaults(struct dc_panel_config *panel_config) 1045 { 1046 *panel_config = panel_config_defaults; 1047 } 1048 1049 void dcn303_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) 1050 { 1051 DC_FP_START(); 1052 dcn303_fpu_update_bw_bounding_box(dc, bw_params); 1053 DC_FP_END(); 1054 } 1055 1056 static struct resource_funcs dcn303_res_pool_funcs = { 1057 .destroy = dcn303_destroy_resource_pool, 1058 .link_enc_create = dcn303_link_encoder_create, 1059 .panel_cntl_create = dcn303_panel_cntl_create, 1060 .validate_bandwidth = dcn30_validate_bandwidth, 1061 .calculate_wm_and_dlg = dcn30_calculate_wm_and_dlg, 1062 .update_soc_for_wm_a = dcn30_update_soc_for_wm_a, 1063 .populate_dml_pipes = dcn30_populate_dml_pipes_from_context, 1064 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer, 1065 .add_stream_to_ctx = dcn30_add_stream_to_ctx, 1066 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, 1067 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 1068 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, 1069 .set_mcif_arb_params = dcn30_set_mcif_arb_params, 1070 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, 1071 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut, 1072 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut, 1073 .update_bw_bounding_box = dcn303_update_bw_bounding_box, 1074 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, 1075 .get_panel_config_defaults = dcn303_get_panel_config_defaults, 1076 }; 1077 1078 static struct dc_cap_funcs cap_funcs = { 1079 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap 1080 }; 1081 1082 static const struct bios_registers bios_regs = { 1083 NBIO_SR(BIOS_SCRATCH_3), 1084 NBIO_SR(BIOS_SCRATCH_6) 1085 }; 1086 1087 static const struct dccg_registers dccg_regs = { 1088 DCCG_REG_LIST_DCN3_03() 1089 }; 1090 1091 static const struct dccg_shift dccg_shift = { 1092 DCCG_MASK_SH_LIST_DCN3_03(__SHIFT) 1093 }; 1094 1095 static const struct dccg_mask dccg_mask = { 1096 DCCG_MASK_SH_LIST_DCN3_03(_MASK) 1097 }; 1098 1099 #define abm_regs(id)\ 1100 [id] = { ABM_DCN302_REG_LIST(id) } 1101 1102 static const struct dce_abm_registers abm_regs[] = { 1103 abm_regs(0), 1104 abm_regs(1) 1105 }; 1106 1107 static const struct dce_abm_shift abm_shift = { 1108 ABM_MASK_SH_LIST_DCN30(__SHIFT) 1109 }; 1110 1111 static const struct dce_abm_mask abm_mask = { 1112 ABM_MASK_SH_LIST_DCN30(_MASK) 1113 }; 1114 1115 static bool dcn303_resource_construct( 1116 uint8_t num_virtual_links, 1117 struct dc *dc, 1118 struct resource_pool *pool) 1119 { 1120 int i; 1121 struct dc_context *ctx = dc->ctx; 1122 struct irq_service_init_data init_data; 1123 struct ddc_service_init_data ddc_init_data; 1124 1125 ctx->dc_bios->regs = &bios_regs; 1126 1127 pool->res_cap = &res_cap_dcn303; 1128 1129 pool->funcs = &dcn303_res_pool_funcs; 1130 1131 /************************************************* 1132 * Resource + asic cap harcoding * 1133 *************************************************/ 1134 pool->underlay_pipe_index = NO_UNDERLAY_PIPE; 1135 pool->pipe_count = pool->res_cap->num_timing_generator; 1136 pool->mpcc_count = pool->res_cap->num_timing_generator; 1137 dc->caps.max_downscale_ratio = 600; 1138 dc->caps.i2c_speed_in_khz = 100; 1139 dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by derfault*/ 1140 dc->caps.max_cursor_size = 256; 1141 dc->caps.min_horizontal_blanking_period = 80; 1142 dc->caps.dmdata_alloc_size = 2048; 1143 dc->caps.mall_size_per_mem_channel = 4; 1144 /* total size = mall per channel * num channels * 1024 * 1024 */ 1145 dc->caps.mall_size_total = dc->caps.mall_size_per_mem_channel * 1146 dc->ctx->dc_bios->vram_info.num_chans * 1147 1024 * 1024; 1148 dc->caps.cursor_cache_size = 1149 dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8; 1150 dc->caps.max_slave_planes = 1; 1151 dc->caps.post_blend_color_processing = true; 1152 dc->caps.force_dp_tps4_for_cp2520 = true; 1153 dc->caps.extended_aux_timeout_support = true; 1154 dc->caps.dmcub_support = true; 1155 dc->caps.max_v_total = (1 << 15) - 1; 1156 1157 /* Color pipeline capabilities */ 1158 dc->caps.color.dpp.dcn_arch = 1; 1159 dc->caps.color.dpp.input_lut_shared = 0; 1160 dc->caps.color.dpp.icsc = 1; 1161 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr 1162 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; 1163 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; 1164 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1; 1165 dc->caps.color.dpp.dgam_rom_caps.pq = 1; 1166 dc->caps.color.dpp.dgam_rom_caps.hlg = 1; 1167 dc->caps.color.dpp.post_csc = 1; 1168 dc->caps.color.dpp.gamma_corr = 1; 1169 dc->caps.color.dpp.dgam_rom_for_yuv = 0; 1170 1171 dc->caps.color.dpp.hw_3d_lut = 1; 1172 dc->caps.color.dpp.ogam_ram = 1; 1173 // no OGAM ROM on DCN3 1174 dc->caps.color.dpp.ogam_rom_caps.srgb = 0; 1175 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; 1176 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; 1177 dc->caps.color.dpp.ogam_rom_caps.pq = 0; 1178 dc->caps.color.dpp.ogam_rom_caps.hlg = 0; 1179 dc->caps.color.dpp.ocsc = 0; 1180 1181 dc->caps.color.mpc.gamut_remap = 1; 1182 dc->caps.color.mpc.num_3dluts = pool->res_cap->num_mpc_3dlut; //3 1183 dc->caps.color.mpc.ogam_ram = 1; 1184 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; 1185 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; 1186 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; 1187 dc->caps.color.mpc.ogam_rom_caps.pq = 0; 1188 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 1189 dc->caps.color.mpc.ocsc = 1; 1190 1191 dc->caps.dp_hdmi21_pcon_support = true; 1192 1193 dc->config.dc_mode_clk_limit_support = true; 1194 /* read VBIOS LTTPR caps */ 1195 if (ctx->dc_bios->funcs->get_lttpr_caps) { 1196 enum bp_result bp_query_result; 1197 uint8_t is_vbios_lttpr_enable = 0; 1198 1199 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable); 1200 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable; 1201 } 1202 1203 if (ctx->dc_bios->funcs->get_lttpr_interop) { 1204 enum bp_result bp_query_result; 1205 uint8_t is_vbios_interop_enabled = 0; 1206 1207 bp_query_result = ctx->dc_bios->funcs->get_lttpr_interop(ctx->dc_bios, &is_vbios_interop_enabled); 1208 dc->caps.vbios_lttpr_aware = (bp_query_result == BP_RESULT_OK) && !!is_vbios_interop_enabled; 1209 } 1210 1211 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 1212 dc->debug = debug_defaults_drv; 1213 1214 // Init the vm_helper 1215 if (dc->vm_helper) 1216 vm_helper_init(dc->vm_helper, 16); 1217 1218 /************************************************* 1219 * Create resources * 1220 *************************************************/ 1221 1222 /* Clock Sources for Pixel Clock*/ 1223 pool->clock_sources[DCN303_CLK_SRC_PLL0] = 1224 dcn303_clock_source_create(ctx, ctx->dc_bios, 1225 CLOCK_SOURCE_COMBO_PHY_PLL0, 1226 &clk_src_regs[0], false); 1227 pool->clock_sources[DCN303_CLK_SRC_PLL1] = 1228 dcn303_clock_source_create(ctx, ctx->dc_bios, 1229 CLOCK_SOURCE_COMBO_PHY_PLL1, 1230 &clk_src_regs[1], false); 1231 1232 pool->clk_src_count = DCN303_CLK_SRC_TOTAL; 1233 1234 /* todo: not reuse phy_pll registers */ 1235 pool->dp_clock_source = 1236 dcn303_clock_source_create(ctx, ctx->dc_bios, 1237 CLOCK_SOURCE_ID_DP_DTO, 1238 &clk_src_regs[0], true); 1239 1240 for (i = 0; i < pool->clk_src_count; i++) { 1241 if (pool->clock_sources[i] == NULL) { 1242 dm_error("DC: failed to create clock sources!\n"); 1243 BREAK_TO_DEBUGGER(); 1244 goto create_fail; 1245 } 1246 } 1247 1248 /* DCCG */ 1249 pool->dccg = dccg30_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 1250 if (pool->dccg == NULL) { 1251 dm_error("DC: failed to create dccg!\n"); 1252 BREAK_TO_DEBUGGER(); 1253 goto create_fail; 1254 } 1255 1256 /* PP Lib and SMU interfaces */ 1257 init_soc_bounding_box(dc, pool); 1258 1259 /* DML */ 1260 dml_init_instance(&dc->dml, &dcn3_03_soc, &dcn3_03_ip, DML_PROJECT_DCN30); 1261 1262 /* IRQ */ 1263 init_data.ctx = dc->ctx; 1264 pool->irqs = dal_irq_service_dcn303_create(&init_data); 1265 if (!pool->irqs) 1266 goto create_fail; 1267 1268 /* HUBBUB */ 1269 pool->hubbub = dcn303_hubbub_create(ctx); 1270 if (pool->hubbub == NULL) { 1271 BREAK_TO_DEBUGGER(); 1272 dm_error("DC: failed to create hubbub!\n"); 1273 goto create_fail; 1274 } 1275 1276 /* HUBPs, DPPs, OPPs and TGs */ 1277 for (i = 0; i < pool->pipe_count; i++) { 1278 pool->hubps[i] = dcn303_hubp_create(ctx, i); 1279 if (pool->hubps[i] == NULL) { 1280 BREAK_TO_DEBUGGER(); 1281 dm_error("DC: failed to create hubps!\n"); 1282 goto create_fail; 1283 } 1284 1285 pool->dpps[i] = dcn303_dpp_create(ctx, i); 1286 if (pool->dpps[i] == NULL) { 1287 BREAK_TO_DEBUGGER(); 1288 dm_error("DC: failed to create dpps!\n"); 1289 goto create_fail; 1290 } 1291 } 1292 1293 for (i = 0; i < pool->res_cap->num_opp; i++) { 1294 pool->opps[i] = dcn303_opp_create(ctx, i); 1295 if (pool->opps[i] == NULL) { 1296 BREAK_TO_DEBUGGER(); 1297 dm_error("DC: failed to create output pixel processor!\n"); 1298 goto create_fail; 1299 } 1300 } 1301 1302 for (i = 0; i < pool->res_cap->num_timing_generator; i++) { 1303 pool->timing_generators[i] = dcn303_timing_generator_create(ctx, i); 1304 if (pool->timing_generators[i] == NULL) { 1305 BREAK_TO_DEBUGGER(); 1306 dm_error("DC: failed to create tg!\n"); 1307 goto create_fail; 1308 } 1309 } 1310 pool->timing_generator_count = i; 1311 1312 /* PSR */ 1313 pool->psr = dmub_psr_create(ctx); 1314 if (pool->psr == NULL) { 1315 dm_error("DC: failed to create psr!\n"); 1316 BREAK_TO_DEBUGGER(); 1317 goto create_fail; 1318 } 1319 1320 /* ABM */ 1321 for (i = 0; i < pool->res_cap->num_timing_generator; i++) { 1322 pool->multiple_abms[i] = dmub_abm_create(ctx, &abm_regs[i], &abm_shift, &abm_mask); 1323 if (pool->multiple_abms[i] == NULL) { 1324 dm_error("DC: failed to create abm for pipe %d!\n", i); 1325 BREAK_TO_DEBUGGER(); 1326 goto create_fail; 1327 } 1328 } 1329 1330 /* MPC and DSC */ 1331 pool->mpc = dcn303_mpc_create(ctx, pool->mpcc_count, pool->res_cap->num_mpc_3dlut); 1332 if (pool->mpc == NULL) { 1333 BREAK_TO_DEBUGGER(); 1334 dm_error("DC: failed to create mpc!\n"); 1335 goto create_fail; 1336 } 1337 1338 for (i = 0; i < pool->res_cap->num_dsc; i++) { 1339 pool->dscs[i] = dcn303_dsc_create(ctx, i); 1340 if (pool->dscs[i] == NULL) { 1341 BREAK_TO_DEBUGGER(); 1342 dm_error("DC: failed to create display stream compressor %d!\n", i); 1343 goto create_fail; 1344 } 1345 } 1346 1347 /* DWB and MMHUBBUB */ 1348 if (!dcn303_dwbc_create(ctx, pool)) { 1349 BREAK_TO_DEBUGGER(); 1350 dm_error("DC: failed to create dwbc!\n"); 1351 goto create_fail; 1352 } 1353 1354 if (!dcn303_mmhubbub_create(ctx, pool)) { 1355 BREAK_TO_DEBUGGER(); 1356 dm_error("DC: failed to create mcif_wb!\n"); 1357 goto create_fail; 1358 } 1359 1360 /* AUX and I2C */ 1361 for (i = 0; i < pool->res_cap->num_ddc; i++) { 1362 pool->engines[i] = dcn303_aux_engine_create(ctx, i); 1363 if (pool->engines[i] == NULL) { 1364 BREAK_TO_DEBUGGER(); 1365 dm_error("DC:failed to create aux engine!!\n"); 1366 goto create_fail; 1367 } 1368 pool->hw_i2cs[i] = dcn303_i2c_hw_create(ctx, i); 1369 if (pool->hw_i2cs[i] == NULL) { 1370 BREAK_TO_DEBUGGER(); 1371 dm_error("DC:failed to create hw i2c!!\n"); 1372 goto create_fail; 1373 } 1374 pool->sw_i2cs[i] = NULL; 1375 } 1376 1377 /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */ 1378 if (!resource_construct(num_virtual_links, dc, pool, 1379 &res_create_funcs)) 1380 goto create_fail; 1381 1382 /* HW Sequencer and Plane caps */ 1383 dcn303_hw_sequencer_construct(dc); 1384 1385 dc->caps.max_planes = pool->pipe_count; 1386 1387 for (i = 0; i < dc->caps.max_planes; ++i) 1388 dc->caps.planes[i] = plane_cap; 1389 1390 dc->cap_funcs = cap_funcs; 1391 1392 if (dc->ctx->dc_bios->fw_info.oem_i2c_present) { 1393 ddc_init_data.ctx = dc->ctx; 1394 ddc_init_data.link = NULL; 1395 ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id; 1396 ddc_init_data.id.enum_id = 0; 1397 ddc_init_data.id.type = OBJECT_TYPE_GENERIC; 1398 pool->oem_device = dc->link_srv->create_ddc_service(&ddc_init_data); 1399 } else { 1400 pool->oem_device = NULL; 1401 } 1402 1403 return true; 1404 1405 create_fail: 1406 1407 dcn303_resource_destruct(pool); 1408 1409 return false; 1410 } 1411 1412 struct resource_pool *dcn303_create_resource_pool(const struct dc_init_data *init_data, struct dc *dc) 1413 { 1414 struct resource_pool *pool = kzalloc(sizeof(struct resource_pool), GFP_KERNEL); 1415 1416 if (!pool) 1417 return NULL; 1418 1419 if (dcn303_resource_construct(init_data->num_virtual_links, dc, pool)) 1420 return pool; 1421 1422 BREAK_TO_DEBUGGER(); 1423 kfree(pool); 1424 return NULL; 1425 } 1426