1 // SPDX-License-Identifier: MIT
2 /*
3  * Copyright (C) 2021 Advanced Micro Devices, Inc.
4  *
5  * Authors: AMD
6  */
7 
8 #include "dcn303_init.h"
9 #include "dcn303_resource.h"
10 #include "dcn303_dccg.h"
11 #include "irq/dcn303/irq_service_dcn303.h"
12 
13 #include "dcn30/dcn30_dio_link_encoder.h"
14 #include "dcn30/dcn30_dio_stream_encoder.h"
15 #include "dcn30/dcn30_dpp.h"
16 #include "dcn30/dcn30_dwb.h"
17 #include "dcn30/dcn30_hubbub.h"
18 #include "dcn30/dcn30_hubp.h"
19 #include "dcn30/dcn30_mmhubbub.h"
20 #include "dcn30/dcn30_mpc.h"
21 #include "dcn30/dcn30_opp.h"
22 #include "dcn30/dcn30_optc.h"
23 #include "dcn30/dcn30_resource.h"
24 
25 #include "dcn20/dcn20_dsc.h"
26 #include "dcn20/dcn20_resource.h"
27 
28 #include "dml/dcn30/dcn30_fpu.h"
29 
30 #include "dcn10/dcn10_resource.h"
31 
32 #include "link.h"
33 
34 #include "dce/dce_abm.h"
35 #include "dce/dce_audio.h"
36 #include "dce/dce_aux.h"
37 #include "dce/dce_clock_source.h"
38 #include "dce/dce_hwseq.h"
39 #include "dce/dce_i2c_hw.h"
40 #include "dce/dce_panel_cntl.h"
41 #include "dce/dmub_abm.h"
42 #include "dce/dmub_psr.h"
43 #include "clk_mgr.h"
44 
45 #include "hw_sequencer_private.h"
46 #include "reg_helper.h"
47 #include "resource.h"
48 #include "vm_helper.h"
49 
50 #include "sienna_cichlid_ip_offset.h"
51 #include "dcn/dcn_3_0_3_offset.h"
52 #include "dcn/dcn_3_0_3_sh_mask.h"
53 #include "dpcs/dpcs_3_0_3_offset.h"
54 #include "dpcs/dpcs_3_0_3_sh_mask.h"
55 #include "nbio/nbio_2_3_offset.h"
56 
57 #include "dml/dcn303/dcn303_fpu.h"
58 
59 #define DC_LOGGER_INIT(logger)
60 
61 
62 static const struct dc_debug_options debug_defaults_drv = {
63 		.disable_dmcu = true,
64 		.force_abm_enable = false,
65 		.timing_trace = false,
66 		.clock_trace = true,
67 		.disable_pplib_clock_request = true,
68 		.pipe_split_policy = MPC_SPLIT_DYNAMIC,
69 		.force_single_disp_pipe_split = false,
70 		.disable_dcc = DCC_ENABLE,
71 		.vsr_support = true,
72 		.performance_trace = false,
73 		.max_downscale_src_width = 7680,/*upto 8K*/
74 		.disable_pplib_wm_range = false,
75 		.scl_reset_length10 = true,
76 		.sanity_checks = false,
77 		.underflow_assert_delay_us = 0xFFFFFFFF,
78 		.dwb_fi_phase = -1, // -1 = disable,
79 		.dmub_command_table = true,
80 		.exit_idle_opt_for_cursor_updates = true,
81 		.disable_idle_power_optimizations = false,
82 };
83 
84 static const struct dc_debug_options debug_defaults_diags = {
85 		.disable_dmcu = true,
86 		.force_abm_enable = false,
87 		.timing_trace = true,
88 		.clock_trace = true,
89 		.disable_dpp_power_gate = true,
90 		.disable_hubp_power_gate = true,
91 		.disable_clock_gate = true,
92 		.disable_pplib_clock_request = true,
93 		.disable_pplib_wm_range = true,
94 		.disable_stutter = false,
95 		.scl_reset_length10 = true,
96 		.dwb_fi_phase = -1, // -1 = disable
97 		.dmub_command_table = true,
98 		.enable_tri_buf = true,
99 };
100 
101 static const struct dc_panel_config panel_config_defaults = {
102 		.psr = {
103 			.disable_psr = false,
104 			.disallow_psrsu = false,
105 		},
106 };
107 
108 enum dcn303_clk_src_array_id {
109 	DCN303_CLK_SRC_PLL0,
110 	DCN303_CLK_SRC_PLL1,
111 	DCN303_CLK_SRC_TOTAL
112 };
113 
114 static const struct resource_caps res_cap_dcn303 = {
115 		.num_timing_generator = 2,
116 		.num_opp = 2,
117 		.num_video_plane = 2,
118 		.num_audio = 2,
119 		.num_stream_encoder = 2,
120 		.num_dwb = 1,
121 		.num_ddc = 2,
122 		.num_vmid = 16,
123 		.num_mpc_3dlut = 1,
124 		.num_dsc = 2,
125 };
126 
127 static const struct dc_plane_cap plane_cap = {
128 		.type = DC_PLANE_TYPE_DCN_UNIVERSAL,
129 		.per_pixel_alpha = true,
130 		.pixel_format_support = {
131 				.argb8888 = true,
132 				.nv12 = true,
133 				.fp16 = true,
134 				.p010 = true,
135 				.ayuv = false,
136 		},
137 		.max_upscale_factor = {
138 				.argb8888 = 16000,
139 				.nv12 = 16000,
140 				.fp16 = 16000
141 		},
142 		.max_downscale_factor = {
143 				.argb8888 = 600,
144 				.nv12 = 600,
145 				.fp16 = 600
146 		},
147 		16,
148 		16
149 };
150 
151 /* NBIO */
152 #define NBIO_BASE_INNER(seg) \
153 		NBIO_BASE__INST0_SEG ## seg
154 
155 #define NBIO_BASE(seg) \
156 		NBIO_BASE_INNER(seg)
157 
158 #define NBIO_SR(reg_name)\
159 		.reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
160 		mm ## reg_name
161 
162 /* DCN */
163 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
164 
165 #define BASE(seg) BASE_INNER(seg)
166 
167 #define SR(reg_name)\
168 		.reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
169 
170 #define SF(reg_name, field_name, post_fix)\
171 		.field_name = reg_name ## __ ## field_name ## post_fix
172 
173 #define SRI(reg_name, block, id)\
174 		.reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + mm ## block ## id ## _ ## reg_name
175 
176 #define SRI2(reg_name, block, id)\
177 		.reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
178 
179 #define SRII(reg_name, block, id)\
180 		.reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
181 		mm ## block ## id ## _ ## reg_name
182 
183 #define DCCG_SRII(reg_name, block, id)\
184 		.block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
185 		mm ## block ## id ## _ ## reg_name
186 
187 #define VUPDATE_SRII(reg_name, block, id)\
188 		.reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
189 		mm ## reg_name ## _ ## block ## id
190 
191 #define SRII_DWB(reg_name, temp_name, block, id)\
192 		.reg_name[id] = BASE(mm ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
193 		mm ## block ## id ## _ ## temp_name
194 
195 #define SF_DWB2(reg_name, block, id, field_name, post_fix)	\
196 	.field_name = reg_name ## __ ## field_name ## post_fix
197 
198 #define SRII_MPC_RMU(reg_name, block, id)\
199 		.RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
200 		mm ## block ## id ## _ ## reg_name
201 
202 static const struct dcn_hubbub_registers hubbub_reg = {
203 		HUBBUB_REG_LIST_DCN30(0)
204 };
205 
206 static const struct dcn_hubbub_shift hubbub_shift = {
207 		HUBBUB_MASK_SH_LIST_DCN30(__SHIFT)
208 };
209 
210 static const struct dcn_hubbub_mask hubbub_mask = {
211 		HUBBUB_MASK_SH_LIST_DCN30(_MASK)
212 };
213 
214 #define vmid_regs(id)\
215 		[id] = { DCN20_VMID_REG_LIST(id) }
216 
217 static const struct dcn_vmid_registers vmid_regs[] = {
218 		vmid_regs(0),
219 		vmid_regs(1),
220 		vmid_regs(2),
221 		vmid_regs(3),
222 		vmid_regs(4),
223 		vmid_regs(5),
224 		vmid_regs(6),
225 		vmid_regs(7),
226 		vmid_regs(8),
227 		vmid_regs(9),
228 		vmid_regs(10),
229 		vmid_regs(11),
230 		vmid_regs(12),
231 		vmid_regs(13),
232 		vmid_regs(14),
233 		vmid_regs(15)
234 };
235 
236 static const struct dcn20_vmid_shift vmid_shifts = {
237 		DCN20_VMID_MASK_SH_LIST(__SHIFT)
238 };
239 
240 static const struct dcn20_vmid_mask vmid_masks = {
241 		DCN20_VMID_MASK_SH_LIST(_MASK)
242 };
243 
244 static struct hubbub *dcn303_hubbub_create(struct dc_context *ctx)
245 {
246 	int i;
247 
248 	struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub), GFP_KERNEL);
249 
250 	if (!hubbub3)
251 		return NULL;
252 
253 	hubbub3_construct(hubbub3, ctx, &hubbub_reg, &hubbub_shift, &hubbub_mask);
254 
255 	for (i = 0; i < res_cap_dcn303.num_vmid; i++) {
256 		struct dcn20_vmid *vmid = &hubbub3->vmid[i];
257 
258 		vmid->ctx = ctx;
259 
260 		vmid->regs = &vmid_regs[i];
261 		vmid->shifts = &vmid_shifts;
262 		vmid->masks = &vmid_masks;
263 	}
264 
265 	return &hubbub3->base;
266 }
267 
268 #define vpg_regs(id)\
269 		[id] = { VPG_DCN3_REG_LIST(id) }
270 
271 static const struct dcn30_vpg_registers vpg_regs[] = {
272 		vpg_regs(0),
273 		vpg_regs(1),
274 		vpg_regs(2)
275 };
276 
277 static const struct dcn30_vpg_shift vpg_shift = {
278 		DCN3_VPG_MASK_SH_LIST(__SHIFT)
279 };
280 
281 static const struct dcn30_vpg_mask vpg_mask = {
282 		DCN3_VPG_MASK_SH_LIST(_MASK)
283 };
284 
285 static struct vpg *dcn303_vpg_create(struct dc_context *ctx, uint32_t inst)
286 {
287 	struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL);
288 
289 	if (!vpg3)
290 		return NULL;
291 
292 	vpg3_construct(vpg3, ctx, inst, &vpg_regs[inst], &vpg_shift, &vpg_mask);
293 
294 	return &vpg3->base;
295 }
296 
297 #define afmt_regs(id)\
298 		[id] = { AFMT_DCN3_REG_LIST(id) }
299 
300 static const struct dcn30_afmt_registers afmt_regs[] = {
301 		afmt_regs(0),
302 		afmt_regs(1),
303 		afmt_regs(2)
304 };
305 
306 static const struct dcn30_afmt_shift afmt_shift = {
307 		DCN3_AFMT_MASK_SH_LIST(__SHIFT)
308 };
309 
310 static const struct dcn30_afmt_mask afmt_mask = {
311 		DCN3_AFMT_MASK_SH_LIST(_MASK)
312 };
313 
314 static struct afmt *dcn303_afmt_create(struct dc_context *ctx, uint32_t inst)
315 {
316 	struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL);
317 
318 	if (!afmt3)
319 		return NULL;
320 
321 	afmt3_construct(afmt3, ctx, inst, &afmt_regs[inst], &afmt_shift, &afmt_mask);
322 
323 	return &afmt3->base;
324 }
325 
326 #define audio_regs(id)\
327 		[id] = { AUD_COMMON_REG_LIST(id) }
328 
329 static const struct dce_audio_registers audio_regs[] = {
330 		audio_regs(0),
331 		audio_regs(1),
332 		audio_regs(2),
333 		audio_regs(3),
334 		audio_regs(4),
335 		audio_regs(5),
336 		audio_regs(6)
337 };
338 
339 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
340 		SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
341 		SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
342 		AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
343 
344 static const struct dce_audio_shift audio_shift = {
345 		DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
346 };
347 
348 static const struct dce_audio_mask audio_mask = {
349 		DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
350 };
351 
352 static struct audio *dcn303_create_audio(struct dc_context *ctx, unsigned int inst)
353 {
354 	return dce_audio_create(ctx, inst, &audio_regs[inst], &audio_shift, &audio_mask);
355 }
356 
357 #define stream_enc_regs(id)\
358 		[id] = { SE_DCN3_REG_LIST(id) }
359 
360 static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
361 		stream_enc_regs(0),
362 		stream_enc_regs(1)
363 };
364 
365 static const struct dcn10_stream_encoder_shift se_shift = {
366 		SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
367 };
368 
369 static const struct dcn10_stream_encoder_mask se_mask = {
370 		SE_COMMON_MASK_SH_LIST_DCN30(_MASK)
371 };
372 
373 static struct stream_encoder *dcn303_stream_encoder_create(enum engine_id eng_id, struct dc_context *ctx)
374 {
375 	struct dcn10_stream_encoder *enc1;
376 	struct vpg *vpg;
377 	struct afmt *afmt;
378 	int vpg_inst;
379 	int afmt_inst;
380 
381 	/* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
382 	if (eng_id <= ENGINE_ID_DIGB) {
383 		vpg_inst = eng_id;
384 		afmt_inst = eng_id;
385 	} else
386 		return NULL;
387 
388 	enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
389 	vpg = dcn303_vpg_create(ctx, vpg_inst);
390 	afmt = dcn303_afmt_create(ctx, afmt_inst);
391 
392 	if (!enc1 || !vpg || !afmt) {
393 		kfree(enc1);
394 		kfree(vpg);
395 		kfree(afmt);
396 		return NULL;
397 	}
398 
399 	dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id, vpg, afmt, &stream_enc_regs[eng_id],
400 			&se_shift, &se_mask);
401 
402 	return &enc1->base;
403 }
404 
405 #define clk_src_regs(index, pllid)\
406 		[index] = { CS_COMMON_REG_LIST_DCN3_03(index, pllid) }
407 
408 static const struct dce110_clk_src_regs clk_src_regs[] = {
409 		clk_src_regs(0, A),
410 		clk_src_regs(1, B)
411 };
412 
413 static const struct dce110_clk_src_shift cs_shift = {
414 		CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
415 };
416 
417 static const struct dce110_clk_src_mask cs_mask = {
418 		CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
419 };
420 
421 static struct clock_source *dcn303_clock_source_create(struct dc_context *ctx, struct dc_bios *bios,
422 		enum clock_source_id id, const struct dce110_clk_src_regs *regs, bool dp_clk_src)
423 {
424 	struct dce110_clk_src *clk_src = kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
425 
426 	if (!clk_src)
427 		return NULL;
428 
429 	if (dcn3_clk_src_construct(clk_src, ctx, bios, id, regs, &cs_shift, &cs_mask)) {
430 		clk_src->base.dp_clk_src = dp_clk_src;
431 		return &clk_src->base;
432 	}
433 
434 	kfree(clk_src);
435 	BREAK_TO_DEBUGGER();
436 	return NULL;
437 }
438 
439 static const struct dce_hwseq_registers hwseq_reg = {
440 		HWSEQ_DCN303_REG_LIST()
441 };
442 
443 static const struct dce_hwseq_shift hwseq_shift = {
444 		HWSEQ_DCN303_MASK_SH_LIST(__SHIFT)
445 };
446 
447 static const struct dce_hwseq_mask hwseq_mask = {
448 		HWSEQ_DCN303_MASK_SH_LIST(_MASK)
449 };
450 
451 static struct dce_hwseq *dcn303_hwseq_create(struct dc_context *ctx)
452 {
453 	struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
454 
455 	if (hws) {
456 		hws->ctx = ctx;
457 		hws->regs = &hwseq_reg;
458 		hws->shifts = &hwseq_shift;
459 		hws->masks = &hwseq_mask;
460 	}
461 	return hws;
462 }
463 
464 #define hubp_regs(id)\
465 		[id] = { HUBP_REG_LIST_DCN30(id) }
466 
467 static const struct dcn_hubp2_registers hubp_regs[] = {
468 		hubp_regs(0),
469 		hubp_regs(1)
470 };
471 
472 static const struct dcn_hubp2_shift hubp_shift = {
473 		HUBP_MASK_SH_LIST_DCN30(__SHIFT)
474 };
475 
476 static const struct dcn_hubp2_mask hubp_mask = {
477 		HUBP_MASK_SH_LIST_DCN30(_MASK)
478 };
479 
480 static struct hubp *dcn303_hubp_create(struct dc_context *ctx, uint32_t inst)
481 {
482 	struct dcn20_hubp *hubp2 = kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
483 
484 	if (!hubp2)
485 		return NULL;
486 
487 	if (hubp3_construct(hubp2, ctx, inst, &hubp_regs[inst], &hubp_shift, &hubp_mask))
488 		return &hubp2->base;
489 
490 	BREAK_TO_DEBUGGER();
491 	kfree(hubp2);
492 	return NULL;
493 }
494 
495 #define dpp_regs(id)\
496 		[id] = { DPP_REG_LIST_DCN30(id) }
497 
498 static const struct dcn3_dpp_registers dpp_regs[] = {
499 		dpp_regs(0),
500 		dpp_regs(1)
501 };
502 
503 static const struct dcn3_dpp_shift tf_shift = {
504 		DPP_REG_LIST_SH_MASK_DCN30(__SHIFT)
505 };
506 
507 static const struct dcn3_dpp_mask tf_mask = {
508 		DPP_REG_LIST_SH_MASK_DCN30(_MASK)
509 };
510 
511 static struct dpp *dcn303_dpp_create(struct dc_context *ctx, uint32_t inst)
512 {
513 	struct dcn3_dpp *dpp = kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);
514 
515 	if (!dpp)
516 		return NULL;
517 
518 	if (dpp3_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, &tf_mask))
519 		return &dpp->base;
520 
521 	BREAK_TO_DEBUGGER();
522 	kfree(dpp);
523 	return NULL;
524 }
525 
526 #define opp_regs(id)\
527 		[id] = { OPP_REG_LIST_DCN30(id) }
528 
529 static const struct dcn20_opp_registers opp_regs[] = {
530 		opp_regs(0),
531 		opp_regs(1)
532 };
533 
534 static const struct dcn20_opp_shift opp_shift = {
535 		OPP_MASK_SH_LIST_DCN20(__SHIFT)
536 };
537 
538 static const struct dcn20_opp_mask opp_mask = {
539 		OPP_MASK_SH_LIST_DCN20(_MASK)
540 };
541 
542 static struct output_pixel_processor *dcn303_opp_create(struct dc_context *ctx, uint32_t inst)
543 {
544 	struct dcn20_opp *opp = kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
545 
546 	if (!opp) {
547 		BREAK_TO_DEBUGGER();
548 		return NULL;
549 	}
550 
551 	dcn20_opp_construct(opp, ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);
552 	return &opp->base;
553 }
554 
555 #define optc_regs(id)\
556 		[id] = { OPTC_COMMON_REG_LIST_DCN3_0(id) }
557 
558 static const struct dcn_optc_registers optc_regs[] = {
559 		optc_regs(0),
560 		optc_regs(1)
561 };
562 
563 static const struct dcn_optc_shift optc_shift = {
564 		OPTC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
565 };
566 
567 static const struct dcn_optc_mask optc_mask = {
568 		OPTC_COMMON_MASK_SH_LIST_DCN30(_MASK)
569 };
570 
571 static struct timing_generator *dcn303_timing_generator_create(struct dc_context *ctx, uint32_t instance)
572 {
573 	struct optc *tgn10 = kzalloc(sizeof(struct optc), GFP_KERNEL);
574 
575 	if (!tgn10)
576 		return NULL;
577 
578 	tgn10->base.inst = instance;
579 	tgn10->base.ctx = ctx;
580 
581 	tgn10->tg_regs = &optc_regs[instance];
582 	tgn10->tg_shift = &optc_shift;
583 	tgn10->tg_mask = &optc_mask;
584 
585 	dcn30_timing_generator_init(tgn10);
586 
587 	return &tgn10->base;
588 }
589 
590 static const struct dcn30_mpc_registers mpc_regs = {
591 		MPC_REG_LIST_DCN3_0(0),
592 		MPC_REG_LIST_DCN3_0(1),
593 		MPC_OUT_MUX_REG_LIST_DCN3_0(0),
594 		MPC_OUT_MUX_REG_LIST_DCN3_0(1),
595 		MPC_RMU_GLOBAL_REG_LIST_DCN3AG,
596 		MPC_RMU_REG_LIST_DCN3AG(0),
597 		MPC_DWB_MUX_REG_LIST_DCN3_0(0),
598 };
599 
600 static const struct dcn30_mpc_shift mpc_shift = {
601 		MPC_COMMON_MASK_SH_LIST_DCN303(__SHIFT)
602 };
603 
604 static const struct dcn30_mpc_mask mpc_mask = {
605 		MPC_COMMON_MASK_SH_LIST_DCN303(_MASK)
606 };
607 
608 static struct mpc *dcn303_mpc_create(struct dc_context *ctx, int num_mpcc, int num_rmu)
609 {
610 	struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), GFP_KERNEL);
611 
612 	if (!mpc30)
613 		return NULL;
614 
615 	dcn30_mpc_construct(mpc30, ctx, &mpc_regs, &mpc_shift, &mpc_mask, num_mpcc, num_rmu);
616 
617 	return &mpc30->base;
618 }
619 
620 #define dsc_regsDCN20(id)\
621 [id] = { DSC_REG_LIST_DCN20(id) }
622 
623 static const struct dcn20_dsc_registers dsc_regs[] = {
624 		dsc_regsDCN20(0),
625 		dsc_regsDCN20(1)
626 };
627 
628 static const struct dcn20_dsc_shift dsc_shift = {
629 		DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
630 };
631 
632 static const struct dcn20_dsc_mask dsc_mask = {
633 		DSC_REG_LIST_SH_MASK_DCN20(_MASK)
634 };
635 
636 static struct display_stream_compressor *dcn303_dsc_create(struct dc_context *ctx, uint32_t inst)
637 {
638 	struct dcn20_dsc *dsc = kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
639 
640 	if (!dsc) {
641 		BREAK_TO_DEBUGGER();
642 		return NULL;
643 	}
644 
645 	dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
646 	return &dsc->base;
647 }
648 
649 #define dwbc_regs_dcn3(id)\
650 [id] = { DWBC_COMMON_REG_LIST_DCN30(id) }
651 
652 static const struct dcn30_dwbc_registers dwbc30_regs[] = {
653 		dwbc_regs_dcn3(0)
654 };
655 
656 static const struct dcn30_dwbc_shift dwbc30_shift = {
657 		DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
658 };
659 
660 static const struct dcn30_dwbc_mask dwbc30_mask = {
661 		DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
662 };
663 
664 static bool dcn303_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
665 {
666 	int i;
667 	uint32_t pipe_count = pool->res_cap->num_dwb;
668 
669 	for (i = 0; i < pipe_count; i++) {
670 		struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), GFP_KERNEL);
671 
672 		if (!dwbc30) {
673 			dm_error("DC: failed to create dwbc30!\n");
674 			return false;
675 		}
676 
677 		dcn30_dwbc_construct(dwbc30, ctx, &dwbc30_regs[i], &dwbc30_shift, &dwbc30_mask, i);
678 
679 		pool->dwbc[i] = &dwbc30->base;
680 	}
681 	return true;
682 }
683 
684 #define mcif_wb_regs_dcn3(id)\
685 [id] = { MCIF_WB_COMMON_REG_LIST_DCN30(id) }
686 
687 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = {
688 		mcif_wb_regs_dcn3(0)
689 };
690 
691 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
692 		MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
693 };
694 
695 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
696 		MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK)
697 };
698 
699 static bool dcn303_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
700 {
701 	int i;
702 	uint32_t pipe_count = pool->res_cap->num_dwb;
703 
704 	for (i = 0; i < pipe_count; i++) {
705 		struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), GFP_KERNEL);
706 
707 		if (!mcif_wb30) {
708 			dm_error("DC: failed to create mcif_wb30!\n");
709 			return false;
710 		}
711 
712 		dcn30_mmhubbub_construct(mcif_wb30, ctx, &mcif_wb30_regs[i], &mcif_wb30_shift, &mcif_wb30_mask, i);
713 
714 		pool->mcif_wb[i] = &mcif_wb30->base;
715 	}
716 	return true;
717 }
718 
719 #define aux_engine_regs(id)\
720 [id] = {\
721 		AUX_COMMON_REG_LIST0(id), \
722 		.AUXN_IMPCAL = 0, \
723 		.AUXP_IMPCAL = 0, \
724 		.AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
725 }
726 
727 static const struct dce110_aux_registers aux_engine_regs[] = {
728 		aux_engine_regs(0),
729 		aux_engine_regs(1)
730 };
731 
732 static const struct dce110_aux_registers_shift aux_shift = {
733 		DCN_AUX_MASK_SH_LIST(__SHIFT)
734 };
735 
736 static const struct dce110_aux_registers_mask aux_mask = {
737 		DCN_AUX_MASK_SH_LIST(_MASK)
738 };
739 
740 static struct dce_aux *dcn303_aux_engine_create(struct dc_context *ctx, uint32_t inst)
741 {
742 	struct aux_engine_dce110 *aux_engine = kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
743 
744 	if (!aux_engine)
745 		return NULL;
746 
747 	dce110_aux_engine_construct(aux_engine, ctx, inst, SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
748 			&aux_engine_regs[inst], &aux_mask, &aux_shift, ctx->dc->caps.extended_aux_timeout_support);
749 
750 	return &aux_engine->base;
751 }
752 
753 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
754 
755 static const struct dce_i2c_registers i2c_hw_regs[] = {
756 		i2c_inst_regs(1),
757 		i2c_inst_regs(2)
758 };
759 
760 static const struct dce_i2c_shift i2c_shifts = {
761 		I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT)
762 };
763 
764 static const struct dce_i2c_mask i2c_masks = {
765 		I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)
766 };
767 
768 static struct dce_i2c_hw *dcn303_i2c_hw_create(struct dc_context *ctx, uint32_t inst)
769 {
770 	struct dce_i2c_hw *dce_i2c_hw = kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
771 
772 	if (!dce_i2c_hw)
773 		return NULL;
774 
775 	dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
776 
777 	return dce_i2c_hw;
778 }
779 
780 static const struct encoder_feature_support link_enc_feature = {
781 		.max_hdmi_deep_color = COLOR_DEPTH_121212,
782 		.max_hdmi_pixel_clock = 600000,
783 		.hdmi_ycbcr420_supported = true,
784 		.dp_ycbcr420_supported = true,
785 		.fec_supported = true,
786 		.flags.bits.IS_HBR2_CAPABLE = true,
787 		.flags.bits.IS_HBR3_CAPABLE = true,
788 		.flags.bits.IS_TPS3_CAPABLE = true,
789 		.flags.bits.IS_TPS4_CAPABLE = true
790 };
791 
792 #define link_regs(id, phyid)\
793 		[id] = {\
794 				LE_DCN3_REG_LIST(id), \
795 				UNIPHY_DCN2_REG_LIST(phyid), \
796 				SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
797 		}
798 
799 static const struct dcn10_link_enc_registers link_enc_regs[] = {
800 		link_regs(0, A),
801 		link_regs(1, B)
802 };
803 
804 static const struct dcn10_link_enc_shift le_shift = {
805 		LINK_ENCODER_MASK_SH_LIST_DCN30(__SHIFT),
806 		DPCS_DCN2_MASK_SH_LIST(__SHIFT)
807 };
808 
809 static const struct dcn10_link_enc_mask le_mask = {
810 		LINK_ENCODER_MASK_SH_LIST_DCN30(_MASK),
811 		DPCS_DCN2_MASK_SH_LIST(_MASK)
812 };
813 
814 #define aux_regs(id)\
815 		[id] = { DCN2_AUX_REG_LIST(id) }
816 
817 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
818 		aux_regs(0),
819 		aux_regs(1)
820 };
821 
822 #define hpd_regs(id)\
823 		[id] = { HPD_REG_LIST(id) }
824 
825 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
826 		hpd_regs(0),
827 		hpd_regs(1)
828 };
829 
830 static struct link_encoder *dcn303_link_encoder_create(
831 	struct dc_context *ctx,
832 	const struct encoder_init_data *enc_init_data)
833 {
834 	struct dcn20_link_encoder *enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
835 
836 	if (!enc20)
837 		return NULL;
838 
839 	dcn30_link_encoder_construct(enc20, enc_init_data, &link_enc_feature,
840 			&link_enc_regs[enc_init_data->transmitter], &link_enc_aux_regs[enc_init_data->channel - 1],
841 			&link_enc_hpd_regs[enc_init_data->hpd_source], &le_shift, &le_mask);
842 
843 	return &enc20->enc10.base;
844 }
845 
846 static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
847 		{ DCN_PANEL_CNTL_REG_LIST() }
848 };
849 
850 static const struct dce_panel_cntl_shift panel_cntl_shift = {
851 		DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
852 };
853 
854 static const struct dce_panel_cntl_mask panel_cntl_mask = {
855 		DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
856 };
857 
858 static struct panel_cntl *dcn303_panel_cntl_create(const struct panel_cntl_init_data *init_data)
859 {
860 	struct dce_panel_cntl *panel_cntl = kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
861 
862 	if (!panel_cntl)
863 		return NULL;
864 
865 	dce_panel_cntl_construct(panel_cntl, init_data, &panel_cntl_regs[init_data->inst],
866 			&panel_cntl_shift, &panel_cntl_mask);
867 
868 	return &panel_cntl->base;
869 }
870 
871 static void read_dce_straps(struct dc_context *ctx, struct resource_straps *straps)
872 {
873 	generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
874 			FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
875 }
876 
877 static const struct resource_create_funcs res_create_funcs = {
878 		.read_dce_straps = read_dce_straps,
879 		.create_audio = dcn303_create_audio,
880 		.create_stream_encoder = dcn303_stream_encoder_create,
881 		.create_hwseq = dcn303_hwseq_create,
882 };
883 
884 static const struct resource_create_funcs res_create_maximus_funcs = {
885 		.read_dce_straps = NULL,
886 		.create_audio = NULL,
887 		.create_stream_encoder = NULL,
888 		.create_hwseq = dcn303_hwseq_create,
889 };
890 
891 static bool is_soc_bounding_box_valid(struct dc *dc)
892 {
893 	uint32_t hw_internal_rev = dc->ctx->asic_id.hw_internal_rev;
894 
895 	if (ASICREV_IS_BEIGE_GOBY_P(hw_internal_rev))
896 		return true;
897 
898 	return false;
899 }
900 
901 static bool init_soc_bounding_box(struct dc *dc,  struct resource_pool *pool)
902 {
903 	struct _vcs_dpi_soc_bounding_box_st *loaded_bb = &dcn3_03_soc;
904 	struct _vcs_dpi_ip_params_st *loaded_ip = &dcn3_03_ip;
905 
906 	DC_LOGGER_INIT(dc->ctx->logger);
907 
908 	if (!is_soc_bounding_box_valid(dc)) {
909 		DC_LOG_ERROR("%s: not valid soc bounding box/n", __func__);
910 		return false;
911 	}
912 
913 	loaded_ip->max_num_otg = pool->pipe_count;
914 	loaded_ip->max_num_dpp = pool->pipe_count;
915 	loaded_ip->clamp_min_dcfclk = dc->config.clamp_min_dcfclk;
916 	DC_FP_START();
917 	dcn20_patch_bounding_box(dc, loaded_bb);
918 	DC_FP_END();
919 
920 	if (dc->ctx->dc_bios->funcs->get_soc_bb_info) {
921 		struct bp_soc_bb_info bb_info = { 0 };
922 
923 		if (dc->ctx->dc_bios->funcs->get_soc_bb_info(
924 			    dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) {
925 					DC_FP_START();
926 					dcn303_fpu_init_soc_bounding_box(bb_info);
927 					DC_FP_END();
928 		}
929 	}
930 
931 	return true;
932 }
933 
934 static void dcn303_resource_destruct(struct resource_pool *pool)
935 {
936 	unsigned int i;
937 
938 	for (i = 0; i < pool->stream_enc_count; i++) {
939 		if (pool->stream_enc[i] != NULL) {
940 			if (pool->stream_enc[i]->vpg != NULL) {
941 				kfree(DCN30_VPG_FROM_VPG(pool->stream_enc[i]->vpg));
942 				pool->stream_enc[i]->vpg = NULL;
943 			}
944 			if (pool->stream_enc[i]->afmt != NULL) {
945 				kfree(DCN30_AFMT_FROM_AFMT(pool->stream_enc[i]->afmt));
946 				pool->stream_enc[i]->afmt = NULL;
947 			}
948 			kfree(DCN10STRENC_FROM_STRENC(pool->stream_enc[i]));
949 			pool->stream_enc[i] = NULL;
950 		}
951 	}
952 
953 	for (i = 0; i < pool->res_cap->num_dsc; i++) {
954 		if (pool->dscs[i] != NULL)
955 			dcn20_dsc_destroy(&pool->dscs[i]);
956 	}
957 
958 	if (pool->mpc != NULL) {
959 		kfree(TO_DCN20_MPC(pool->mpc));
960 		pool->mpc = NULL;
961 	}
962 
963 	if (pool->hubbub != NULL) {
964 		kfree(pool->hubbub);
965 		pool->hubbub = NULL;
966 	}
967 
968 	for (i = 0; i < pool->pipe_count; i++) {
969 		if (pool->dpps[i] != NULL) {
970 			kfree(TO_DCN20_DPP(pool->dpps[i]));
971 			pool->dpps[i] = NULL;
972 		}
973 
974 		if (pool->hubps[i] != NULL) {
975 			kfree(TO_DCN20_HUBP(pool->hubps[i]));
976 			pool->hubps[i] = NULL;
977 		}
978 
979 		if (pool->irqs != NULL)
980 			dal_irq_service_destroy(&pool->irqs);
981 	}
982 
983 	for (i = 0; i < pool->res_cap->num_ddc; i++) {
984 		if (pool->engines[i] != NULL)
985 			dce110_engine_destroy(&pool->engines[i]);
986 		if (pool->hw_i2cs[i] != NULL) {
987 			kfree(pool->hw_i2cs[i]);
988 			pool->hw_i2cs[i] = NULL;
989 		}
990 		if (pool->sw_i2cs[i] != NULL) {
991 			kfree(pool->sw_i2cs[i]);
992 			pool->sw_i2cs[i] = NULL;
993 		}
994 	}
995 
996 	for (i = 0; i < pool->res_cap->num_opp; i++) {
997 		if (pool->opps[i] != NULL)
998 			pool->opps[i]->funcs->opp_destroy(&pool->opps[i]);
999 	}
1000 
1001 	for (i = 0; i < pool->res_cap->num_timing_generator; i++) {
1002 		if (pool->timing_generators[i] != NULL)	{
1003 			kfree(DCN10TG_FROM_TG(pool->timing_generators[i]));
1004 			pool->timing_generators[i] = NULL;
1005 		}
1006 	}
1007 
1008 	for (i = 0; i < pool->res_cap->num_dwb; i++) {
1009 		if (pool->dwbc[i] != NULL) {
1010 			kfree(TO_DCN30_DWBC(pool->dwbc[i]));
1011 			pool->dwbc[i] = NULL;
1012 		}
1013 		if (pool->mcif_wb[i] != NULL) {
1014 			kfree(TO_DCN30_MMHUBBUB(pool->mcif_wb[i]));
1015 			pool->mcif_wb[i] = NULL;
1016 		}
1017 	}
1018 
1019 	for (i = 0; i < pool->audio_count; i++) {
1020 		if (pool->audios[i])
1021 			dce_aud_destroy(&pool->audios[i]);
1022 	}
1023 
1024 	for (i = 0; i < pool->clk_src_count; i++) {
1025 		if (pool->clock_sources[i] != NULL)
1026 			dcn20_clock_source_destroy(&pool->clock_sources[i]);
1027 	}
1028 
1029 	if (pool->dp_clock_source != NULL)
1030 		dcn20_clock_source_destroy(&pool->dp_clock_source);
1031 
1032 	for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) {
1033 		if (pool->mpc_lut[i] != NULL) {
1034 			dc_3dlut_func_release(pool->mpc_lut[i]);
1035 			pool->mpc_lut[i] = NULL;
1036 		}
1037 		if (pool->mpc_shaper[i] != NULL) {
1038 			dc_transfer_func_release(pool->mpc_shaper[i]);
1039 			pool->mpc_shaper[i] = NULL;
1040 		}
1041 	}
1042 
1043 	for (i = 0; i < pool->pipe_count; i++) {
1044 		if (pool->multiple_abms[i] != NULL)
1045 			dce_abm_destroy(&pool->multiple_abms[i]);
1046 	}
1047 
1048 	if (pool->psr != NULL)
1049 		dmub_psr_destroy(&pool->psr);
1050 
1051 	if (pool->dccg != NULL)
1052 		dcn_dccg_destroy(&pool->dccg);
1053 
1054 	if (pool->oem_device != NULL) {
1055 		struct dc *dc = pool->oem_device->ctx->dc;
1056 
1057 		dc->link_srv->destroy_ddc_service(&pool->oem_device);
1058 	}
1059 }
1060 
1061 static void dcn303_destroy_resource_pool(struct resource_pool **pool)
1062 {
1063 	dcn303_resource_destruct(*pool);
1064 	kfree(*pool);
1065 	*pool = NULL;
1066 }
1067 
1068 static void dcn303_get_panel_config_defaults(struct dc_panel_config *panel_config)
1069 {
1070 	*panel_config = panel_config_defaults;
1071 }
1072 
1073 void dcn303_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
1074 {
1075 	DC_FP_START();
1076 	dcn303_fpu_update_bw_bounding_box(dc, bw_params);
1077 	DC_FP_END();
1078 }
1079 
1080 static struct resource_funcs dcn303_res_pool_funcs = {
1081 		.destroy = dcn303_destroy_resource_pool,
1082 		.link_enc_create = dcn303_link_encoder_create,
1083 		.panel_cntl_create = dcn303_panel_cntl_create,
1084 		.validate_bandwidth = dcn30_validate_bandwidth,
1085 		.calculate_wm_and_dlg = dcn30_calculate_wm_and_dlg,
1086 		.update_soc_for_wm_a = dcn30_update_soc_for_wm_a,
1087 		.populate_dml_pipes = dcn30_populate_dml_pipes_from_context,
1088 		.acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
1089 		.add_stream_to_ctx = dcn30_add_stream_to_ctx,
1090 		.add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
1091 		.remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1092 		.populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
1093 		.set_mcif_arb_params = dcn30_set_mcif_arb_params,
1094 		.find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1095 		.acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
1096 		.release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
1097 		.update_bw_bounding_box = dcn303_update_bw_bounding_box,
1098 		.patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
1099 		.get_panel_config_defaults = dcn303_get_panel_config_defaults,
1100 };
1101 
1102 static struct dc_cap_funcs cap_funcs = {
1103 		.get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1104 };
1105 
1106 static const struct bios_registers bios_regs = {
1107 		NBIO_SR(BIOS_SCRATCH_3),
1108 		NBIO_SR(BIOS_SCRATCH_6)
1109 };
1110 
1111 static const struct dccg_registers dccg_regs = {
1112 		DCCG_REG_LIST_DCN3_03()
1113 };
1114 
1115 static const struct dccg_shift dccg_shift = {
1116 		DCCG_MASK_SH_LIST_DCN3_03(__SHIFT)
1117 };
1118 
1119 static const struct dccg_mask dccg_mask = {
1120 		DCCG_MASK_SH_LIST_DCN3_03(_MASK)
1121 };
1122 
1123 #define abm_regs(id)\
1124 		[id] = { ABM_DCN302_REG_LIST(id) }
1125 
1126 static const struct dce_abm_registers abm_regs[] = {
1127 		abm_regs(0),
1128 		abm_regs(1)
1129 };
1130 
1131 static const struct dce_abm_shift abm_shift = {
1132 		ABM_MASK_SH_LIST_DCN30(__SHIFT)
1133 };
1134 
1135 static const struct dce_abm_mask abm_mask = {
1136 		ABM_MASK_SH_LIST_DCN30(_MASK)
1137 };
1138 
1139 static bool dcn303_resource_construct(
1140 		uint8_t num_virtual_links,
1141 		struct dc *dc,
1142 		struct resource_pool *pool)
1143 {
1144 	int i;
1145 	struct dc_context *ctx = dc->ctx;
1146 	struct irq_service_init_data init_data;
1147 	struct ddc_service_init_data ddc_init_data;
1148 
1149 	ctx->dc_bios->regs = &bios_regs;
1150 
1151 	pool->res_cap = &res_cap_dcn303;
1152 
1153 	pool->funcs = &dcn303_res_pool_funcs;
1154 
1155 	/*************************************************
1156 	 *  Resource + asic cap harcoding                *
1157 	 *************************************************/
1158 	pool->underlay_pipe_index = NO_UNDERLAY_PIPE;
1159 	pool->pipe_count = pool->res_cap->num_timing_generator;
1160 	pool->mpcc_count = pool->res_cap->num_timing_generator;
1161 	dc->caps.max_downscale_ratio = 600;
1162 	dc->caps.i2c_speed_in_khz = 100;
1163 	dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by derfault*/
1164 	dc->caps.max_cursor_size = 256;
1165 	dc->caps.min_horizontal_blanking_period = 80;
1166 	dc->caps.dmdata_alloc_size = 2048;
1167 	dc->caps.mall_size_per_mem_channel = 4;
1168 	/* total size = mall per channel * num channels * 1024 * 1024 */
1169 	dc->caps.mall_size_total = dc->caps.mall_size_per_mem_channel *
1170 				   dc->ctx->dc_bios->vram_info.num_chans *
1171 				   1024 * 1024;
1172 	dc->caps.cursor_cache_size =
1173 		dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8;
1174 	dc->caps.max_slave_planes = 1;
1175 	dc->caps.post_blend_color_processing = true;
1176 	dc->caps.force_dp_tps4_for_cp2520 = true;
1177 	dc->caps.extended_aux_timeout_support = true;
1178 	dc->caps.dmcub_support = true;
1179 
1180 	/* Color pipeline capabilities */
1181 	dc->caps.color.dpp.dcn_arch = 1;
1182 	dc->caps.color.dpp.input_lut_shared = 0;
1183 	dc->caps.color.dpp.icsc = 1;
1184 	dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
1185 	dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1186 	dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1187 	dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
1188 	dc->caps.color.dpp.dgam_rom_caps.pq = 1;
1189 	dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
1190 	dc->caps.color.dpp.post_csc = 1;
1191 	dc->caps.color.dpp.gamma_corr = 1;
1192 	dc->caps.color.dpp.dgam_rom_for_yuv = 0;
1193 
1194 	dc->caps.color.dpp.hw_3d_lut = 1;
1195 	dc->caps.color.dpp.ogam_ram = 1;
1196 	// no OGAM ROM on DCN3
1197 	dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
1198 	dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
1199 	dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
1200 	dc->caps.color.dpp.ogam_rom_caps.pq = 0;
1201 	dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
1202 	dc->caps.color.dpp.ocsc = 0;
1203 
1204 	dc->caps.color.mpc.gamut_remap = 1;
1205 	dc->caps.color.mpc.num_3dluts = pool->res_cap->num_mpc_3dlut; //3
1206 	dc->caps.color.mpc.ogam_ram = 1;
1207 	dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
1208 	dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
1209 	dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
1210 	dc->caps.color.mpc.ogam_rom_caps.pq = 0;
1211 	dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1212 	dc->caps.color.mpc.ocsc = 1;
1213 
1214 	dc->caps.dp_hdmi21_pcon_support = true;
1215 
1216 	/* read VBIOS LTTPR caps */
1217 	if (ctx->dc_bios->funcs->get_lttpr_caps) {
1218 		enum bp_result bp_query_result;
1219 		uint8_t is_vbios_lttpr_enable = 0;
1220 
1221 		bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
1222 		dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
1223 	}
1224 
1225 	if (ctx->dc_bios->funcs->get_lttpr_interop) {
1226 		enum bp_result bp_query_result;
1227 		uint8_t is_vbios_interop_enabled = 0;
1228 
1229 		bp_query_result = ctx->dc_bios->funcs->get_lttpr_interop(ctx->dc_bios, &is_vbios_interop_enabled);
1230 		dc->caps.vbios_lttpr_aware = (bp_query_result == BP_RESULT_OK) && !!is_vbios_interop_enabled;
1231 	}
1232 
1233 	if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1234 		dc->debug = debug_defaults_drv;
1235 	else
1236 		dc->debug = debug_defaults_diags;
1237 
1238 	// Init the vm_helper
1239 	if (dc->vm_helper)
1240 		vm_helper_init(dc->vm_helper, 16);
1241 
1242 	/*************************************************
1243 	 *  Create resources                             *
1244 	 *************************************************/
1245 
1246 	/* Clock Sources for Pixel Clock*/
1247 	pool->clock_sources[DCN303_CLK_SRC_PLL0] =
1248 			dcn303_clock_source_create(ctx, ctx->dc_bios,
1249 					CLOCK_SOURCE_COMBO_PHY_PLL0,
1250 					&clk_src_regs[0], false);
1251 	pool->clock_sources[DCN303_CLK_SRC_PLL1] =
1252 			dcn303_clock_source_create(ctx, ctx->dc_bios,
1253 					CLOCK_SOURCE_COMBO_PHY_PLL1,
1254 					&clk_src_regs[1], false);
1255 
1256 	pool->clk_src_count = DCN303_CLK_SRC_TOTAL;
1257 
1258 	/* todo: not reuse phy_pll registers */
1259 	pool->dp_clock_source =
1260 			dcn303_clock_source_create(ctx, ctx->dc_bios,
1261 					CLOCK_SOURCE_ID_DP_DTO,
1262 					&clk_src_regs[0], true);
1263 
1264 	for (i = 0; i < pool->clk_src_count; i++) {
1265 		if (pool->clock_sources[i] == NULL) {
1266 			dm_error("DC: failed to create clock sources!\n");
1267 			BREAK_TO_DEBUGGER();
1268 			goto create_fail;
1269 		}
1270 	}
1271 
1272 	/* DCCG */
1273 	pool->dccg = dccg30_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
1274 	if (pool->dccg == NULL) {
1275 		dm_error("DC: failed to create dccg!\n");
1276 		BREAK_TO_DEBUGGER();
1277 		goto create_fail;
1278 	}
1279 
1280 	/* PP Lib and SMU interfaces */
1281 	init_soc_bounding_box(dc, pool);
1282 
1283 	/* DML */
1284 	dml_init_instance(&dc->dml, &dcn3_03_soc, &dcn3_03_ip, DML_PROJECT_DCN30);
1285 
1286 	/* IRQ */
1287 	init_data.ctx = dc->ctx;
1288 	pool->irqs = dal_irq_service_dcn303_create(&init_data);
1289 	if (!pool->irqs)
1290 		goto create_fail;
1291 
1292 	/* HUBBUB */
1293 	pool->hubbub = dcn303_hubbub_create(ctx);
1294 	if (pool->hubbub == NULL) {
1295 		BREAK_TO_DEBUGGER();
1296 		dm_error("DC: failed to create hubbub!\n");
1297 		goto create_fail;
1298 	}
1299 
1300 	/* HUBPs, DPPs, OPPs and TGs */
1301 	for (i = 0; i < pool->pipe_count; i++) {
1302 		pool->hubps[i] = dcn303_hubp_create(ctx, i);
1303 		if (pool->hubps[i] == NULL) {
1304 			BREAK_TO_DEBUGGER();
1305 			dm_error("DC: failed to create hubps!\n");
1306 			goto create_fail;
1307 		}
1308 
1309 		pool->dpps[i] = dcn303_dpp_create(ctx, i);
1310 		if (pool->dpps[i] == NULL) {
1311 			BREAK_TO_DEBUGGER();
1312 			dm_error("DC: failed to create dpps!\n");
1313 			goto create_fail;
1314 		}
1315 	}
1316 
1317 	for (i = 0; i < pool->res_cap->num_opp; i++) {
1318 		pool->opps[i] = dcn303_opp_create(ctx, i);
1319 		if (pool->opps[i] == NULL) {
1320 			BREAK_TO_DEBUGGER();
1321 			dm_error("DC: failed to create output pixel processor!\n");
1322 			goto create_fail;
1323 		}
1324 	}
1325 
1326 	for (i = 0; i < pool->res_cap->num_timing_generator; i++) {
1327 		pool->timing_generators[i] = dcn303_timing_generator_create(ctx, i);
1328 		if (pool->timing_generators[i] == NULL) {
1329 			BREAK_TO_DEBUGGER();
1330 			dm_error("DC: failed to create tg!\n");
1331 			goto create_fail;
1332 		}
1333 	}
1334 	pool->timing_generator_count = i;
1335 
1336 	/* PSR */
1337 	pool->psr = dmub_psr_create(ctx);
1338 	if (pool->psr == NULL) {
1339 		dm_error("DC: failed to create psr!\n");
1340 		BREAK_TO_DEBUGGER();
1341 		goto create_fail;
1342 	}
1343 
1344 	/* ABM */
1345 	for (i = 0; i < pool->res_cap->num_timing_generator; i++) {
1346 		pool->multiple_abms[i] = dmub_abm_create(ctx, &abm_regs[i], &abm_shift, &abm_mask);
1347 		if (pool->multiple_abms[i] == NULL) {
1348 			dm_error("DC: failed to create abm for pipe %d!\n", i);
1349 			BREAK_TO_DEBUGGER();
1350 			goto create_fail;
1351 		}
1352 	}
1353 
1354 	/* MPC and DSC */
1355 	pool->mpc = dcn303_mpc_create(ctx, pool->mpcc_count, pool->res_cap->num_mpc_3dlut);
1356 	if (pool->mpc == NULL) {
1357 		BREAK_TO_DEBUGGER();
1358 		dm_error("DC: failed to create mpc!\n");
1359 		goto create_fail;
1360 	}
1361 
1362 	for (i = 0; i < pool->res_cap->num_dsc; i++) {
1363 		pool->dscs[i] = dcn303_dsc_create(ctx, i);
1364 		if (pool->dscs[i] == NULL) {
1365 			BREAK_TO_DEBUGGER();
1366 			dm_error("DC: failed to create display stream compressor %d!\n", i);
1367 			goto create_fail;
1368 		}
1369 	}
1370 
1371 	/* DWB and MMHUBBUB */
1372 	if (!dcn303_dwbc_create(ctx, pool)) {
1373 		BREAK_TO_DEBUGGER();
1374 		dm_error("DC: failed to create dwbc!\n");
1375 		goto create_fail;
1376 	}
1377 
1378 	if (!dcn303_mmhubbub_create(ctx, pool)) {
1379 		BREAK_TO_DEBUGGER();
1380 		dm_error("DC: failed to create mcif_wb!\n");
1381 		goto create_fail;
1382 	}
1383 
1384 	/* AUX and I2C */
1385 	for (i = 0; i < pool->res_cap->num_ddc; i++) {
1386 		pool->engines[i] = dcn303_aux_engine_create(ctx, i);
1387 		if (pool->engines[i] == NULL) {
1388 			BREAK_TO_DEBUGGER();
1389 			dm_error("DC:failed to create aux engine!!\n");
1390 			goto create_fail;
1391 		}
1392 		pool->hw_i2cs[i] = dcn303_i2c_hw_create(ctx, i);
1393 		if (pool->hw_i2cs[i] == NULL) {
1394 			BREAK_TO_DEBUGGER();
1395 			dm_error("DC:failed to create hw i2c!!\n");
1396 			goto create_fail;
1397 		}
1398 		pool->sw_i2cs[i] = NULL;
1399 	}
1400 
1401 	/* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */
1402 	if (!resource_construct(num_virtual_links, dc, pool,
1403 			(!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
1404 					&res_create_funcs : &res_create_maximus_funcs)))
1405 		goto create_fail;
1406 
1407 	/* HW Sequencer and Plane caps */
1408 	dcn303_hw_sequencer_construct(dc);
1409 
1410 	dc->caps.max_planes =  pool->pipe_count;
1411 
1412 	for (i = 0; i < dc->caps.max_planes; ++i)
1413 		dc->caps.planes[i] = plane_cap;
1414 
1415 	dc->cap_funcs = cap_funcs;
1416 
1417 	if (dc->ctx->dc_bios->fw_info.oem_i2c_present) {
1418 		ddc_init_data.ctx = dc->ctx;
1419 		ddc_init_data.link = NULL;
1420 		ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id;
1421 		ddc_init_data.id.enum_id = 0;
1422 		ddc_init_data.id.type = OBJECT_TYPE_GENERIC;
1423 		pool->oem_device = dc->link_srv->create_ddc_service(&ddc_init_data);
1424 	} else {
1425 		pool->oem_device = NULL;
1426 	}
1427 
1428 	return true;
1429 
1430 create_fail:
1431 
1432 	dcn303_resource_destruct(pool);
1433 
1434 	return false;
1435 }
1436 
1437 struct resource_pool *dcn303_create_resource_pool(const struct dc_init_data *init_data, struct dc *dc)
1438 {
1439 	struct resource_pool *pool = kzalloc(sizeof(struct resource_pool), GFP_KERNEL);
1440 
1441 	if (!pool)
1442 		return NULL;
1443 
1444 	if (dcn303_resource_construct(init_data->num_virtual_links, dc, pool))
1445 		return pool;
1446 
1447 	BREAK_TO_DEBUGGER();
1448 	kfree(pool);
1449 	return NULL;
1450 }
1451