1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright (C) 2021 Advanced Micro Devices, Inc. 4 * 5 * Authors: AMD 6 */ 7 8 #include "dcn303_init.h" 9 #include "dcn303_resource.h" 10 #include "dcn303_dccg.h" 11 #include "irq/dcn303/irq_service_dcn303.h" 12 13 #include "dcn30/dcn30_dio_link_encoder.h" 14 #include "dcn30/dcn30_dio_stream_encoder.h" 15 #include "dcn30/dcn30_dpp.h" 16 #include "dcn30/dcn30_dwb.h" 17 #include "dcn30/dcn30_hubbub.h" 18 #include "dcn30/dcn30_hubp.h" 19 #include "dcn30/dcn30_mmhubbub.h" 20 #include "dcn30/dcn30_mpc.h" 21 #include "dcn30/dcn30_opp.h" 22 #include "dcn30/dcn30_optc.h" 23 #include "dcn30/dcn30_resource.h" 24 25 #include "dcn20/dcn20_dsc.h" 26 #include "dcn20/dcn20_resource.h" 27 28 #include "dml/dcn30/dcn30_fpu.h" 29 30 #include "dcn10/dcn10_resource.h" 31 32 #include "dc_link_ddc.h" 33 34 #include "dce/dce_abm.h" 35 #include "dce/dce_audio.h" 36 #include "dce/dce_aux.h" 37 #include "dce/dce_clock_source.h" 38 #include "dce/dce_hwseq.h" 39 #include "dce/dce_i2c_hw.h" 40 #include "dce/dce_panel_cntl.h" 41 #include "dce/dmub_abm.h" 42 #include "dce/dmub_psr.h" 43 #include "clk_mgr.h" 44 45 #include "hw_sequencer_private.h" 46 #include "reg_helper.h" 47 #include "resource.h" 48 #include "vm_helper.h" 49 50 #include "sienna_cichlid_ip_offset.h" 51 #include "dcn/dcn_3_0_3_offset.h" 52 #include "dcn/dcn_3_0_3_sh_mask.h" 53 #include "dpcs/dpcs_3_0_3_offset.h" 54 #include "dpcs/dpcs_3_0_3_sh_mask.h" 55 #include "nbio/nbio_2_3_offset.h" 56 57 #include "dml/dcn303/dcn303_fpu.h" 58 59 #define DC_LOGGER_INIT(logger) 60 61 62 static const struct dc_debug_options debug_defaults_drv = { 63 .disable_dmcu = true, 64 .force_abm_enable = false, 65 .timing_trace = false, 66 .clock_trace = true, 67 .disable_pplib_clock_request = true, 68 .pipe_split_policy = MPC_SPLIT_DYNAMIC, 69 .force_single_disp_pipe_split = false, 70 .disable_dcc = DCC_ENABLE, 71 .vsr_support = true, 72 .performance_trace = false, 73 .max_downscale_src_width = 7680,/*upto 8K*/ 74 .disable_pplib_wm_range = false, 75 .scl_reset_length10 = true, 76 .sanity_checks = false, 77 .underflow_assert_delay_us = 0xFFFFFFFF, 78 .dwb_fi_phase = -1, // -1 = disable, 79 .dmub_command_table = true, 80 .exit_idle_opt_for_cursor_updates = true, 81 .disable_idle_power_optimizations = false, 82 }; 83 84 static const struct dc_debug_options debug_defaults_diags = { 85 .disable_dmcu = true, 86 .force_abm_enable = false, 87 .timing_trace = true, 88 .clock_trace = true, 89 .disable_dpp_power_gate = true, 90 .disable_hubp_power_gate = true, 91 .disable_clock_gate = true, 92 .disable_pplib_clock_request = true, 93 .disable_pplib_wm_range = true, 94 .disable_stutter = false, 95 .scl_reset_length10 = true, 96 .dwb_fi_phase = -1, // -1 = disable 97 .dmub_command_table = true, 98 .enable_tri_buf = true, 99 .disable_psr = true, 100 }; 101 102 enum dcn303_clk_src_array_id { 103 DCN303_CLK_SRC_PLL0, 104 DCN303_CLK_SRC_PLL1, 105 DCN303_CLK_SRC_TOTAL 106 }; 107 108 static const struct resource_caps res_cap_dcn303 = { 109 .num_timing_generator = 2, 110 .num_opp = 2, 111 .num_video_plane = 2, 112 .num_audio = 2, 113 .num_stream_encoder = 2, 114 .num_dwb = 1, 115 .num_ddc = 2, 116 .num_vmid = 16, 117 .num_mpc_3dlut = 1, 118 .num_dsc = 2, 119 }; 120 121 static const struct dc_plane_cap plane_cap = { 122 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 123 .blends_with_above = true, 124 .blends_with_below = true, 125 .per_pixel_alpha = true, 126 .pixel_format_support = { 127 .argb8888 = true, 128 .nv12 = true, 129 .fp16 = true, 130 .p010 = true, 131 .ayuv = false, 132 }, 133 .max_upscale_factor = { 134 .argb8888 = 16000, 135 .nv12 = 16000, 136 .fp16 = 16000 137 }, 138 .max_downscale_factor = { 139 .argb8888 = 600, 140 .nv12 = 600, 141 .fp16 = 600 142 }, 143 16, 144 16 145 }; 146 147 /* NBIO */ 148 #define NBIO_BASE_INNER(seg) \ 149 NBIO_BASE__INST0_SEG ## seg 150 151 #define NBIO_BASE(seg) \ 152 NBIO_BASE_INNER(seg) 153 154 #define NBIO_SR(reg_name)\ 155 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \ 156 mm ## reg_name 157 158 /* DCN */ 159 #undef BASE_INNER 160 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg 161 162 #define BASE(seg) BASE_INNER(seg) 163 164 #define SR(reg_name)\ 165 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name 166 167 #define SF(reg_name, field_name, post_fix)\ 168 .field_name = reg_name ## __ ## field_name ## post_fix 169 170 #define SRI(reg_name, block, id)\ 171 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + mm ## block ## id ## _ ## reg_name 172 173 #define SRI2(reg_name, block, id)\ 174 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name 175 176 #define SRII(reg_name, block, id)\ 177 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 178 mm ## block ## id ## _ ## reg_name 179 180 #define DCCG_SRII(reg_name, block, id)\ 181 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 182 mm ## block ## id ## _ ## reg_name 183 184 #define VUPDATE_SRII(reg_name, block, id)\ 185 .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \ 186 mm ## reg_name ## _ ## block ## id 187 188 #define SRII_DWB(reg_name, temp_name, block, id)\ 189 .reg_name[id] = BASE(mm ## block ## id ## _ ## temp_name ## _BASE_IDX) + \ 190 mm ## block ## id ## _ ## temp_name 191 192 #define SRII_MPC_RMU(reg_name, block, id)\ 193 .RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 194 mm ## block ## id ## _ ## reg_name 195 196 static const struct dcn_hubbub_registers hubbub_reg = { 197 HUBBUB_REG_LIST_DCN30(0) 198 }; 199 200 static const struct dcn_hubbub_shift hubbub_shift = { 201 HUBBUB_MASK_SH_LIST_DCN30(__SHIFT) 202 }; 203 204 static const struct dcn_hubbub_mask hubbub_mask = { 205 HUBBUB_MASK_SH_LIST_DCN30(_MASK) 206 }; 207 208 #define vmid_regs(id)\ 209 [id] = { DCN20_VMID_REG_LIST(id) } 210 211 static const struct dcn_vmid_registers vmid_regs[] = { 212 vmid_regs(0), 213 vmid_regs(1), 214 vmid_regs(2), 215 vmid_regs(3), 216 vmid_regs(4), 217 vmid_regs(5), 218 vmid_regs(6), 219 vmid_regs(7), 220 vmid_regs(8), 221 vmid_regs(9), 222 vmid_regs(10), 223 vmid_regs(11), 224 vmid_regs(12), 225 vmid_regs(13), 226 vmid_regs(14), 227 vmid_regs(15) 228 }; 229 230 static const struct dcn20_vmid_shift vmid_shifts = { 231 DCN20_VMID_MASK_SH_LIST(__SHIFT) 232 }; 233 234 static const struct dcn20_vmid_mask vmid_masks = { 235 DCN20_VMID_MASK_SH_LIST(_MASK) 236 }; 237 238 static struct hubbub *dcn303_hubbub_create(struct dc_context *ctx) 239 { 240 int i; 241 242 struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub), GFP_KERNEL); 243 244 if (!hubbub3) 245 return NULL; 246 247 hubbub3_construct(hubbub3, ctx, &hubbub_reg, &hubbub_shift, &hubbub_mask); 248 249 for (i = 0; i < res_cap_dcn303.num_vmid; i++) { 250 struct dcn20_vmid *vmid = &hubbub3->vmid[i]; 251 252 vmid->ctx = ctx; 253 254 vmid->regs = &vmid_regs[i]; 255 vmid->shifts = &vmid_shifts; 256 vmid->masks = &vmid_masks; 257 } 258 259 return &hubbub3->base; 260 } 261 262 #define vpg_regs(id)\ 263 [id] = { VPG_DCN3_REG_LIST(id) } 264 265 static const struct dcn30_vpg_registers vpg_regs[] = { 266 vpg_regs(0), 267 vpg_regs(1), 268 vpg_regs(2) 269 }; 270 271 static const struct dcn30_vpg_shift vpg_shift = { 272 DCN3_VPG_MASK_SH_LIST(__SHIFT) 273 }; 274 275 static const struct dcn30_vpg_mask vpg_mask = { 276 DCN3_VPG_MASK_SH_LIST(_MASK) 277 }; 278 279 static struct vpg *dcn303_vpg_create(struct dc_context *ctx, uint32_t inst) 280 { 281 struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL); 282 283 if (!vpg3) 284 return NULL; 285 286 vpg3_construct(vpg3, ctx, inst, &vpg_regs[inst], &vpg_shift, &vpg_mask); 287 288 return &vpg3->base; 289 } 290 291 #define afmt_regs(id)\ 292 [id] = { AFMT_DCN3_REG_LIST(id) } 293 294 static const struct dcn30_afmt_registers afmt_regs[] = { 295 afmt_regs(0), 296 afmt_regs(1), 297 afmt_regs(2) 298 }; 299 300 static const struct dcn30_afmt_shift afmt_shift = { 301 DCN3_AFMT_MASK_SH_LIST(__SHIFT) 302 }; 303 304 static const struct dcn30_afmt_mask afmt_mask = { 305 DCN3_AFMT_MASK_SH_LIST(_MASK) 306 }; 307 308 static struct afmt *dcn303_afmt_create(struct dc_context *ctx, uint32_t inst) 309 { 310 struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL); 311 312 if (!afmt3) 313 return NULL; 314 315 afmt3_construct(afmt3, ctx, inst, &afmt_regs[inst], &afmt_shift, &afmt_mask); 316 317 return &afmt3->base; 318 } 319 320 #define audio_regs(id)\ 321 [id] = { AUD_COMMON_REG_LIST(id) } 322 323 static const struct dce_audio_registers audio_regs[] = { 324 audio_regs(0), 325 audio_regs(1), 326 audio_regs(2), 327 audio_regs(3), 328 audio_regs(4), 329 audio_regs(5), 330 audio_regs(6) 331 }; 332 333 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 334 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 335 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 336 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 337 338 static const struct dce_audio_shift audio_shift = { 339 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 340 }; 341 342 static const struct dce_audio_mask audio_mask = { 343 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 344 }; 345 346 static struct audio *dcn303_create_audio(struct dc_context *ctx, unsigned int inst) 347 { 348 return dce_audio_create(ctx, inst, &audio_regs[inst], &audio_shift, &audio_mask); 349 } 350 351 #define stream_enc_regs(id)\ 352 [id] = { SE_DCN3_REG_LIST(id) } 353 354 static const struct dcn10_stream_enc_registers stream_enc_regs[] = { 355 stream_enc_regs(0), 356 stream_enc_regs(1) 357 }; 358 359 static const struct dcn10_stream_encoder_shift se_shift = { 360 SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 361 }; 362 363 static const struct dcn10_stream_encoder_mask se_mask = { 364 SE_COMMON_MASK_SH_LIST_DCN30(_MASK) 365 }; 366 367 static struct stream_encoder *dcn303_stream_encoder_create(enum engine_id eng_id, struct dc_context *ctx) 368 { 369 struct dcn10_stream_encoder *enc1; 370 struct vpg *vpg; 371 struct afmt *afmt; 372 int vpg_inst; 373 int afmt_inst; 374 375 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */ 376 if (eng_id <= ENGINE_ID_DIGB) { 377 vpg_inst = eng_id; 378 afmt_inst = eng_id; 379 } else 380 return NULL; 381 382 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 383 vpg = dcn303_vpg_create(ctx, vpg_inst); 384 afmt = dcn303_afmt_create(ctx, afmt_inst); 385 386 if (!enc1 || !vpg || !afmt) { 387 kfree(enc1); 388 kfree(vpg); 389 kfree(afmt); 390 return NULL; 391 } 392 393 dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id, vpg, afmt, &stream_enc_regs[eng_id], 394 &se_shift, &se_mask); 395 396 return &enc1->base; 397 } 398 399 #define clk_src_regs(index, pllid)\ 400 [index] = { CS_COMMON_REG_LIST_DCN3_03(index, pllid) } 401 402 static const struct dce110_clk_src_regs clk_src_regs[] = { 403 clk_src_regs(0, A), 404 clk_src_regs(1, B) 405 }; 406 407 static const struct dce110_clk_src_shift cs_shift = { 408 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 409 }; 410 411 static const struct dce110_clk_src_mask cs_mask = { 412 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 413 }; 414 415 static struct clock_source *dcn303_clock_source_create(struct dc_context *ctx, struct dc_bios *bios, 416 enum clock_source_id id, const struct dce110_clk_src_regs *regs, bool dp_clk_src) 417 { 418 struct dce110_clk_src *clk_src = kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 419 420 if (!clk_src) 421 return NULL; 422 423 if (dcn3_clk_src_construct(clk_src, ctx, bios, id, regs, &cs_shift, &cs_mask)) { 424 clk_src->base.dp_clk_src = dp_clk_src; 425 return &clk_src->base; 426 } 427 428 BREAK_TO_DEBUGGER(); 429 return NULL; 430 } 431 432 static const struct dce_hwseq_registers hwseq_reg = { 433 HWSEQ_DCN303_REG_LIST() 434 }; 435 436 static const struct dce_hwseq_shift hwseq_shift = { 437 HWSEQ_DCN303_MASK_SH_LIST(__SHIFT) 438 }; 439 440 static const struct dce_hwseq_mask hwseq_mask = { 441 HWSEQ_DCN303_MASK_SH_LIST(_MASK) 442 }; 443 444 static struct dce_hwseq *dcn303_hwseq_create(struct dc_context *ctx) 445 { 446 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 447 448 if (hws) { 449 hws->ctx = ctx; 450 hws->regs = &hwseq_reg; 451 hws->shifts = &hwseq_shift; 452 hws->masks = &hwseq_mask; 453 } 454 return hws; 455 } 456 457 #define hubp_regs(id)\ 458 [id] = { HUBP_REG_LIST_DCN30(id) } 459 460 static const struct dcn_hubp2_registers hubp_regs[] = { 461 hubp_regs(0), 462 hubp_regs(1) 463 }; 464 465 static const struct dcn_hubp2_shift hubp_shift = { 466 HUBP_MASK_SH_LIST_DCN30(__SHIFT) 467 }; 468 469 static const struct dcn_hubp2_mask hubp_mask = { 470 HUBP_MASK_SH_LIST_DCN30(_MASK) 471 }; 472 473 static struct hubp *dcn303_hubp_create(struct dc_context *ctx, uint32_t inst) 474 { 475 struct dcn20_hubp *hubp2 = kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL); 476 477 if (!hubp2) 478 return NULL; 479 480 if (hubp3_construct(hubp2, ctx, inst, &hubp_regs[inst], &hubp_shift, &hubp_mask)) 481 return &hubp2->base; 482 483 BREAK_TO_DEBUGGER(); 484 kfree(hubp2); 485 return NULL; 486 } 487 488 #define dpp_regs(id)\ 489 [id] = { DPP_REG_LIST_DCN30(id) } 490 491 static const struct dcn3_dpp_registers dpp_regs[] = { 492 dpp_regs(0), 493 dpp_regs(1) 494 }; 495 496 static const struct dcn3_dpp_shift tf_shift = { 497 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT) 498 }; 499 500 static const struct dcn3_dpp_mask tf_mask = { 501 DPP_REG_LIST_SH_MASK_DCN30(_MASK) 502 }; 503 504 static struct dpp *dcn303_dpp_create(struct dc_context *ctx, uint32_t inst) 505 { 506 struct dcn3_dpp *dpp = kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL); 507 508 if (!dpp) 509 return NULL; 510 511 if (dpp3_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, &tf_mask)) 512 return &dpp->base; 513 514 BREAK_TO_DEBUGGER(); 515 kfree(dpp); 516 return NULL; 517 } 518 519 #define opp_regs(id)\ 520 [id] = { OPP_REG_LIST_DCN30(id) } 521 522 static const struct dcn20_opp_registers opp_regs[] = { 523 opp_regs(0), 524 opp_regs(1) 525 }; 526 527 static const struct dcn20_opp_shift opp_shift = { 528 OPP_MASK_SH_LIST_DCN20(__SHIFT) 529 }; 530 531 static const struct dcn20_opp_mask opp_mask = { 532 OPP_MASK_SH_LIST_DCN20(_MASK) 533 }; 534 535 static struct output_pixel_processor *dcn303_opp_create(struct dc_context *ctx, uint32_t inst) 536 { 537 struct dcn20_opp *opp = kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); 538 539 if (!opp) { 540 BREAK_TO_DEBUGGER(); 541 return NULL; 542 } 543 544 dcn20_opp_construct(opp, ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask); 545 return &opp->base; 546 } 547 548 #define optc_regs(id)\ 549 [id] = { OPTC_COMMON_REG_LIST_DCN3_0(id) } 550 551 static const struct dcn_optc_registers optc_regs[] = { 552 optc_regs(0), 553 optc_regs(1) 554 }; 555 556 static const struct dcn_optc_shift optc_shift = { 557 OPTC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 558 }; 559 560 static const struct dcn_optc_mask optc_mask = { 561 OPTC_COMMON_MASK_SH_LIST_DCN30(_MASK) 562 }; 563 564 static struct timing_generator *dcn303_timing_generator_create(struct dc_context *ctx, uint32_t instance) 565 { 566 struct optc *tgn10 = kzalloc(sizeof(struct optc), GFP_KERNEL); 567 568 if (!tgn10) 569 return NULL; 570 571 tgn10->base.inst = instance; 572 tgn10->base.ctx = ctx; 573 574 tgn10->tg_regs = &optc_regs[instance]; 575 tgn10->tg_shift = &optc_shift; 576 tgn10->tg_mask = &optc_mask; 577 578 dcn30_timing_generator_init(tgn10); 579 580 return &tgn10->base; 581 } 582 583 static const struct dcn30_mpc_registers mpc_regs = { 584 MPC_REG_LIST_DCN3_0(0), 585 MPC_REG_LIST_DCN3_0(1), 586 MPC_OUT_MUX_REG_LIST_DCN3_0(0), 587 MPC_OUT_MUX_REG_LIST_DCN3_0(1), 588 MPC_RMU_GLOBAL_REG_LIST_DCN3AG, 589 MPC_RMU_REG_LIST_DCN3AG(0), 590 MPC_DWB_MUX_REG_LIST_DCN3_0(0), 591 }; 592 593 static const struct dcn30_mpc_shift mpc_shift = { 594 MPC_COMMON_MASK_SH_LIST_DCN303(__SHIFT) 595 }; 596 597 static const struct dcn30_mpc_mask mpc_mask = { 598 MPC_COMMON_MASK_SH_LIST_DCN303(_MASK) 599 }; 600 601 static struct mpc *dcn303_mpc_create(struct dc_context *ctx, int num_mpcc, int num_rmu) 602 { 603 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), GFP_KERNEL); 604 605 if (!mpc30) 606 return NULL; 607 608 dcn30_mpc_construct(mpc30, ctx, &mpc_regs, &mpc_shift, &mpc_mask, num_mpcc, num_rmu); 609 610 return &mpc30->base; 611 } 612 613 #define dsc_regsDCN20(id)\ 614 [id] = { DSC_REG_LIST_DCN20(id) } 615 616 static const struct dcn20_dsc_registers dsc_regs[] = { 617 dsc_regsDCN20(0), 618 dsc_regsDCN20(1) 619 }; 620 621 static const struct dcn20_dsc_shift dsc_shift = { 622 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) 623 }; 624 625 static const struct dcn20_dsc_mask dsc_mask = { 626 DSC_REG_LIST_SH_MASK_DCN20(_MASK) 627 }; 628 629 static struct display_stream_compressor *dcn303_dsc_create(struct dc_context *ctx, uint32_t inst) 630 { 631 struct dcn20_dsc *dsc = kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); 632 633 if (!dsc) { 634 BREAK_TO_DEBUGGER(); 635 return NULL; 636 } 637 638 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 639 return &dsc->base; 640 } 641 642 #define dwbc_regs_dcn3(id)\ 643 [id] = { DWBC_COMMON_REG_LIST_DCN30(id) } 644 645 static const struct dcn30_dwbc_registers dwbc30_regs[] = { 646 dwbc_regs_dcn3(0) 647 }; 648 649 static const struct dcn30_dwbc_shift dwbc30_shift = { 650 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 651 }; 652 653 static const struct dcn30_dwbc_mask dwbc30_mask = { 654 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK) 655 }; 656 657 static bool dcn303_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) 658 { 659 int i; 660 uint32_t pipe_count = pool->res_cap->num_dwb; 661 662 for (i = 0; i < pipe_count; i++) { 663 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), GFP_KERNEL); 664 665 if (!dwbc30) { 666 dm_error("DC: failed to create dwbc30!\n"); 667 return false; 668 } 669 670 dcn30_dwbc_construct(dwbc30, ctx, &dwbc30_regs[i], &dwbc30_shift, &dwbc30_mask, i); 671 672 pool->dwbc[i] = &dwbc30->base; 673 } 674 return true; 675 } 676 677 #define mcif_wb_regs_dcn3(id)\ 678 [id] = { MCIF_WB_COMMON_REG_LIST_DCN30(id) } 679 680 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = { 681 mcif_wb_regs_dcn3(0) 682 }; 683 684 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = { 685 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 686 }; 687 688 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { 689 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK) 690 }; 691 692 static bool dcn303_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) 693 { 694 int i; 695 uint32_t pipe_count = pool->res_cap->num_dwb; 696 697 for (i = 0; i < pipe_count; i++) { 698 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), GFP_KERNEL); 699 700 if (!mcif_wb30) { 701 dm_error("DC: failed to create mcif_wb30!\n"); 702 return false; 703 } 704 705 dcn30_mmhubbub_construct(mcif_wb30, ctx, &mcif_wb30_regs[i], &mcif_wb30_shift, &mcif_wb30_mask, i); 706 707 pool->mcif_wb[i] = &mcif_wb30->base; 708 } 709 return true; 710 } 711 712 #define aux_engine_regs(id)\ 713 [id] = {\ 714 AUX_COMMON_REG_LIST0(id), \ 715 .AUXN_IMPCAL = 0, \ 716 .AUXP_IMPCAL = 0, \ 717 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \ 718 } 719 720 static const struct dce110_aux_registers aux_engine_regs[] = { 721 aux_engine_regs(0), 722 aux_engine_regs(1) 723 }; 724 725 static const struct dce110_aux_registers_shift aux_shift = { 726 DCN_AUX_MASK_SH_LIST(__SHIFT) 727 }; 728 729 static const struct dce110_aux_registers_mask aux_mask = { 730 DCN_AUX_MASK_SH_LIST(_MASK) 731 }; 732 733 static struct dce_aux *dcn303_aux_engine_create(struct dc_context *ctx, uint32_t inst) 734 { 735 struct aux_engine_dce110 *aux_engine = kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 736 737 if (!aux_engine) 738 return NULL; 739 740 dce110_aux_engine_construct(aux_engine, ctx, inst, SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 741 &aux_engine_regs[inst], &aux_mask, &aux_shift, ctx->dc->caps.extended_aux_timeout_support); 742 743 return &aux_engine->base; 744 } 745 746 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 747 748 static const struct dce_i2c_registers i2c_hw_regs[] = { 749 i2c_inst_regs(1), 750 i2c_inst_regs(2) 751 }; 752 753 static const struct dce_i2c_shift i2c_shifts = { 754 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT) 755 }; 756 757 static const struct dce_i2c_mask i2c_masks = { 758 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK) 759 }; 760 761 static struct dce_i2c_hw *dcn303_i2c_hw_create(struct dc_context *ctx, uint32_t inst) 762 { 763 struct dce_i2c_hw *dce_i2c_hw = kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 764 765 if (!dce_i2c_hw) 766 return NULL; 767 768 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 769 770 return dce_i2c_hw; 771 } 772 773 static const struct encoder_feature_support link_enc_feature = { 774 .max_hdmi_deep_color = COLOR_DEPTH_121212, 775 .max_hdmi_pixel_clock = 600000, 776 .hdmi_ycbcr420_supported = true, 777 .dp_ycbcr420_supported = true, 778 .fec_supported = true, 779 .flags.bits.IS_HBR2_CAPABLE = true, 780 .flags.bits.IS_HBR3_CAPABLE = true, 781 .flags.bits.IS_TPS3_CAPABLE = true, 782 .flags.bits.IS_TPS4_CAPABLE = true 783 }; 784 785 #define link_regs(id, phyid)\ 786 [id] = {\ 787 LE_DCN3_REG_LIST(id), \ 788 UNIPHY_DCN2_REG_LIST(phyid), \ 789 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \ 790 } 791 792 static const struct dcn10_link_enc_registers link_enc_regs[] = { 793 link_regs(0, A), 794 link_regs(1, B) 795 }; 796 797 static const struct dcn10_link_enc_shift le_shift = { 798 LINK_ENCODER_MASK_SH_LIST_DCN30(__SHIFT), 799 DPCS_DCN2_MASK_SH_LIST(__SHIFT) 800 }; 801 802 static const struct dcn10_link_enc_mask le_mask = { 803 LINK_ENCODER_MASK_SH_LIST_DCN30(_MASK), 804 DPCS_DCN2_MASK_SH_LIST(_MASK) 805 }; 806 807 #define aux_regs(id)\ 808 [id] = { DCN2_AUX_REG_LIST(id) } 809 810 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { 811 aux_regs(0), 812 aux_regs(1) 813 }; 814 815 #define hpd_regs(id)\ 816 [id] = { HPD_REG_LIST(id) } 817 818 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { 819 hpd_regs(0), 820 hpd_regs(1) 821 }; 822 823 static struct link_encoder *dcn303_link_encoder_create( 824 struct dc_context *ctx, 825 const struct encoder_init_data *enc_init_data) 826 { 827 struct dcn20_link_encoder *enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 828 829 if (!enc20) 830 return NULL; 831 832 dcn30_link_encoder_construct(enc20, enc_init_data, &link_enc_feature, 833 &link_enc_regs[enc_init_data->transmitter], &link_enc_aux_regs[enc_init_data->channel - 1], 834 &link_enc_hpd_regs[enc_init_data->hpd_source], &le_shift, &le_mask); 835 836 return &enc20->enc10.base; 837 } 838 839 static const struct dce_panel_cntl_registers panel_cntl_regs[] = { 840 { DCN_PANEL_CNTL_REG_LIST() } 841 }; 842 843 static const struct dce_panel_cntl_shift panel_cntl_shift = { 844 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT) 845 }; 846 847 static const struct dce_panel_cntl_mask panel_cntl_mask = { 848 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK) 849 }; 850 851 static struct panel_cntl *dcn303_panel_cntl_create(const struct panel_cntl_init_data *init_data) 852 { 853 struct dce_panel_cntl *panel_cntl = kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL); 854 855 if (!panel_cntl) 856 return NULL; 857 858 dce_panel_cntl_construct(panel_cntl, init_data, &panel_cntl_regs[init_data->inst], 859 &panel_cntl_shift, &panel_cntl_mask); 860 861 return &panel_cntl->base; 862 } 863 864 static void read_dce_straps(struct dc_context *ctx, struct resource_straps *straps) 865 { 866 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX), 867 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 868 } 869 870 static const struct resource_create_funcs res_create_funcs = { 871 .read_dce_straps = read_dce_straps, 872 .create_audio = dcn303_create_audio, 873 .create_stream_encoder = dcn303_stream_encoder_create, 874 .create_hwseq = dcn303_hwseq_create, 875 }; 876 877 static const struct resource_create_funcs res_create_maximus_funcs = { 878 .read_dce_straps = NULL, 879 .create_audio = NULL, 880 .create_stream_encoder = NULL, 881 .create_hwseq = dcn303_hwseq_create, 882 }; 883 884 static bool is_soc_bounding_box_valid(struct dc *dc) 885 { 886 uint32_t hw_internal_rev = dc->ctx->asic_id.hw_internal_rev; 887 888 if (ASICREV_IS_BEIGE_GOBY_P(hw_internal_rev)) 889 return true; 890 891 return false; 892 } 893 894 static bool init_soc_bounding_box(struct dc *dc, struct resource_pool *pool) 895 { 896 struct _vcs_dpi_soc_bounding_box_st *loaded_bb = &dcn3_03_soc; 897 struct _vcs_dpi_ip_params_st *loaded_ip = &dcn3_03_ip; 898 899 DC_LOGGER_INIT(dc->ctx->logger); 900 901 if (!is_soc_bounding_box_valid(dc)) { 902 DC_LOG_ERROR("%s: not valid soc bounding box/n", __func__); 903 return false; 904 } 905 906 loaded_ip->max_num_otg = pool->pipe_count; 907 loaded_ip->max_num_dpp = pool->pipe_count; 908 loaded_ip->clamp_min_dcfclk = dc->config.clamp_min_dcfclk; 909 DC_FP_START(); 910 dcn20_patch_bounding_box(dc, loaded_bb); 911 DC_FP_END(); 912 913 if (dc->ctx->dc_bios->funcs->get_soc_bb_info) { 914 struct bp_soc_bb_info bb_info = { 0 }; 915 916 if (dc->ctx->dc_bios->funcs->get_soc_bb_info( 917 dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) { 918 DC_FP_START(); 919 dcn303_fpu_init_soc_bounding_box(bb_info); 920 DC_FP_END(); 921 } 922 } 923 924 return true; 925 } 926 927 static void dcn303_resource_destruct(struct resource_pool *pool) 928 { 929 unsigned int i; 930 931 for (i = 0; i < pool->stream_enc_count; i++) { 932 if (pool->stream_enc[i] != NULL) { 933 if (pool->stream_enc[i]->vpg != NULL) { 934 kfree(DCN30_VPG_FROM_VPG(pool->stream_enc[i]->vpg)); 935 pool->stream_enc[i]->vpg = NULL; 936 } 937 if (pool->stream_enc[i]->afmt != NULL) { 938 kfree(DCN30_AFMT_FROM_AFMT(pool->stream_enc[i]->afmt)); 939 pool->stream_enc[i]->afmt = NULL; 940 } 941 kfree(DCN10STRENC_FROM_STRENC(pool->stream_enc[i])); 942 pool->stream_enc[i] = NULL; 943 } 944 } 945 946 for (i = 0; i < pool->res_cap->num_dsc; i++) { 947 if (pool->dscs[i] != NULL) 948 dcn20_dsc_destroy(&pool->dscs[i]); 949 } 950 951 if (pool->mpc != NULL) { 952 kfree(TO_DCN20_MPC(pool->mpc)); 953 pool->mpc = NULL; 954 } 955 956 if (pool->hubbub != NULL) { 957 kfree(pool->hubbub); 958 pool->hubbub = NULL; 959 } 960 961 for (i = 0; i < pool->pipe_count; i++) { 962 if (pool->dpps[i] != NULL) { 963 kfree(TO_DCN20_DPP(pool->dpps[i])); 964 pool->dpps[i] = NULL; 965 } 966 967 if (pool->hubps[i] != NULL) { 968 kfree(TO_DCN20_HUBP(pool->hubps[i])); 969 pool->hubps[i] = NULL; 970 } 971 972 if (pool->irqs != NULL) 973 dal_irq_service_destroy(&pool->irqs); 974 } 975 976 for (i = 0; i < pool->res_cap->num_ddc; i++) { 977 if (pool->engines[i] != NULL) 978 dce110_engine_destroy(&pool->engines[i]); 979 if (pool->hw_i2cs[i] != NULL) { 980 kfree(pool->hw_i2cs[i]); 981 pool->hw_i2cs[i] = NULL; 982 } 983 if (pool->sw_i2cs[i] != NULL) { 984 kfree(pool->sw_i2cs[i]); 985 pool->sw_i2cs[i] = NULL; 986 } 987 } 988 989 for (i = 0; i < pool->res_cap->num_opp; i++) { 990 if (pool->opps[i] != NULL) 991 pool->opps[i]->funcs->opp_destroy(&pool->opps[i]); 992 } 993 994 for (i = 0; i < pool->res_cap->num_timing_generator; i++) { 995 if (pool->timing_generators[i] != NULL) { 996 kfree(DCN10TG_FROM_TG(pool->timing_generators[i])); 997 pool->timing_generators[i] = NULL; 998 } 999 } 1000 1001 for (i = 0; i < pool->res_cap->num_dwb; i++) { 1002 if (pool->dwbc[i] != NULL) { 1003 kfree(TO_DCN30_DWBC(pool->dwbc[i])); 1004 pool->dwbc[i] = NULL; 1005 } 1006 if (pool->mcif_wb[i] != NULL) { 1007 kfree(TO_DCN30_MMHUBBUB(pool->mcif_wb[i])); 1008 pool->mcif_wb[i] = NULL; 1009 } 1010 } 1011 1012 for (i = 0; i < pool->audio_count; i++) { 1013 if (pool->audios[i]) 1014 dce_aud_destroy(&pool->audios[i]); 1015 } 1016 1017 for (i = 0; i < pool->clk_src_count; i++) { 1018 if (pool->clock_sources[i] != NULL) 1019 dcn20_clock_source_destroy(&pool->clock_sources[i]); 1020 } 1021 1022 if (pool->dp_clock_source != NULL) 1023 dcn20_clock_source_destroy(&pool->dp_clock_source); 1024 1025 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { 1026 if (pool->mpc_lut[i] != NULL) { 1027 dc_3dlut_func_release(pool->mpc_lut[i]); 1028 pool->mpc_lut[i] = NULL; 1029 } 1030 if (pool->mpc_shaper[i] != NULL) { 1031 dc_transfer_func_release(pool->mpc_shaper[i]); 1032 pool->mpc_shaper[i] = NULL; 1033 } 1034 } 1035 1036 for (i = 0; i < pool->pipe_count; i++) { 1037 if (pool->multiple_abms[i] != NULL) 1038 dce_abm_destroy(&pool->multiple_abms[i]); 1039 } 1040 1041 if (pool->psr != NULL) 1042 dmub_psr_destroy(&pool->psr); 1043 1044 if (pool->dccg != NULL) 1045 dcn_dccg_destroy(&pool->dccg); 1046 1047 if (pool->oem_device != NULL) 1048 dal_ddc_service_destroy(&pool->oem_device); 1049 } 1050 1051 static void dcn303_destroy_resource_pool(struct resource_pool **pool) 1052 { 1053 dcn303_resource_destruct(*pool); 1054 kfree(*pool); 1055 *pool = NULL; 1056 } 1057 1058 1059 void dcn303_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) 1060 { 1061 DC_FP_START(); 1062 dcn303_fpu_update_bw_bounding_box(dc, bw_params); 1063 DC_FP_END(); 1064 } 1065 1066 static struct resource_funcs dcn303_res_pool_funcs = { 1067 .destroy = dcn303_destroy_resource_pool, 1068 .link_enc_create = dcn303_link_encoder_create, 1069 .panel_cntl_create = dcn303_panel_cntl_create, 1070 .validate_bandwidth = dcn30_validate_bandwidth, 1071 .calculate_wm_and_dlg = dcn30_calculate_wm_and_dlg, 1072 .update_soc_for_wm_a = dcn30_update_soc_for_wm_a, 1073 .populate_dml_pipes = dcn30_populate_dml_pipes_from_context, 1074 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer, 1075 .add_stream_to_ctx = dcn30_add_stream_to_ctx, 1076 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, 1077 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 1078 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, 1079 .set_mcif_arb_params = dcn30_set_mcif_arb_params, 1080 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, 1081 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut, 1082 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut, 1083 .update_bw_bounding_box = dcn303_update_bw_bounding_box, 1084 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, 1085 }; 1086 1087 static struct dc_cap_funcs cap_funcs = { 1088 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap 1089 }; 1090 1091 static const struct bios_registers bios_regs = { 1092 NBIO_SR(BIOS_SCRATCH_3), 1093 NBIO_SR(BIOS_SCRATCH_6) 1094 }; 1095 1096 static const struct dccg_registers dccg_regs = { 1097 DCCG_REG_LIST_DCN3_03() 1098 }; 1099 1100 static const struct dccg_shift dccg_shift = { 1101 DCCG_MASK_SH_LIST_DCN3_03(__SHIFT) 1102 }; 1103 1104 static const struct dccg_mask dccg_mask = { 1105 DCCG_MASK_SH_LIST_DCN3_03(_MASK) 1106 }; 1107 1108 #define abm_regs(id)\ 1109 [id] = { ABM_DCN302_REG_LIST(id) } 1110 1111 static const struct dce_abm_registers abm_regs[] = { 1112 abm_regs(0), 1113 abm_regs(1) 1114 }; 1115 1116 static const struct dce_abm_shift abm_shift = { 1117 ABM_MASK_SH_LIST_DCN30(__SHIFT) 1118 }; 1119 1120 static const struct dce_abm_mask abm_mask = { 1121 ABM_MASK_SH_LIST_DCN30(_MASK) 1122 }; 1123 1124 static bool dcn303_resource_construct( 1125 uint8_t num_virtual_links, 1126 struct dc *dc, 1127 struct resource_pool *pool) 1128 { 1129 int i; 1130 struct dc_context *ctx = dc->ctx; 1131 struct irq_service_init_data init_data; 1132 struct ddc_service_init_data ddc_init_data; 1133 1134 ctx->dc_bios->regs = &bios_regs; 1135 1136 pool->res_cap = &res_cap_dcn303; 1137 1138 pool->funcs = &dcn303_res_pool_funcs; 1139 1140 /************************************************* 1141 * Resource + asic cap harcoding * 1142 *************************************************/ 1143 pool->underlay_pipe_index = NO_UNDERLAY_PIPE; 1144 pool->pipe_count = pool->res_cap->num_timing_generator; 1145 pool->mpcc_count = pool->res_cap->num_timing_generator; 1146 dc->caps.max_downscale_ratio = 600; 1147 dc->caps.i2c_speed_in_khz = 100; 1148 dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by derfault*/ 1149 dc->caps.max_cursor_size = 256; 1150 dc->caps.min_horizontal_blanking_period = 80; 1151 dc->caps.dmdata_alloc_size = 2048; 1152 #if defined(CONFIG_DRM_AMD_DC_DCN) 1153 dc->caps.mall_size_per_mem_channel = 4; 1154 /* total size = mall per channel * num channels * 1024 * 1024 */ 1155 dc->caps.mall_size_total = dc->caps.mall_size_per_mem_channel * 1156 dc->ctx->dc_bios->vram_info.num_chans * 1157 1024 * 1024; 1158 dc->caps.cursor_cache_size = 1159 dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8; 1160 #endif 1161 dc->caps.max_slave_planes = 1; 1162 dc->caps.post_blend_color_processing = true; 1163 dc->caps.force_dp_tps4_for_cp2520 = true; 1164 dc->caps.extended_aux_timeout_support = true; 1165 dc->caps.dmcub_support = true; 1166 1167 /* Color pipeline capabilities */ 1168 dc->caps.color.dpp.dcn_arch = 1; 1169 dc->caps.color.dpp.input_lut_shared = 0; 1170 dc->caps.color.dpp.icsc = 1; 1171 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr 1172 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; 1173 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; 1174 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1; 1175 dc->caps.color.dpp.dgam_rom_caps.pq = 1; 1176 dc->caps.color.dpp.dgam_rom_caps.hlg = 1; 1177 dc->caps.color.dpp.post_csc = 1; 1178 dc->caps.color.dpp.gamma_corr = 1; 1179 dc->caps.color.dpp.dgam_rom_for_yuv = 0; 1180 1181 dc->caps.color.dpp.hw_3d_lut = 1; 1182 dc->caps.color.dpp.ogam_ram = 1; 1183 // no OGAM ROM on DCN3 1184 dc->caps.color.dpp.ogam_rom_caps.srgb = 0; 1185 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; 1186 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; 1187 dc->caps.color.dpp.ogam_rom_caps.pq = 0; 1188 dc->caps.color.dpp.ogam_rom_caps.hlg = 0; 1189 dc->caps.color.dpp.ocsc = 0; 1190 1191 dc->caps.color.mpc.gamut_remap = 1; 1192 dc->caps.color.mpc.num_3dluts = pool->res_cap->num_mpc_3dlut; //3 1193 dc->caps.color.mpc.ogam_ram = 1; 1194 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; 1195 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; 1196 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; 1197 dc->caps.color.mpc.ogam_rom_caps.pq = 0; 1198 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 1199 dc->caps.color.mpc.ocsc = 1; 1200 1201 /* read VBIOS LTTPR caps */ 1202 if (ctx->dc_bios->funcs->get_lttpr_caps) { 1203 enum bp_result bp_query_result; 1204 uint8_t is_vbios_lttpr_enable = 0; 1205 1206 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable); 1207 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable; 1208 } 1209 1210 if (ctx->dc_bios->funcs->get_lttpr_interop) { 1211 enum bp_result bp_query_result; 1212 uint8_t is_vbios_interop_enabled = 0; 1213 1214 bp_query_result = ctx->dc_bios->funcs->get_lttpr_interop(ctx->dc_bios, &is_vbios_interop_enabled); 1215 dc->caps.vbios_lttpr_aware = (bp_query_result == BP_RESULT_OK) && !!is_vbios_interop_enabled; 1216 } 1217 1218 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 1219 dc->debug = debug_defaults_drv; 1220 else 1221 dc->debug = debug_defaults_diags; 1222 1223 // Init the vm_helper 1224 if (dc->vm_helper) 1225 vm_helper_init(dc->vm_helper, 16); 1226 1227 /************************************************* 1228 * Create resources * 1229 *************************************************/ 1230 1231 /* Clock Sources for Pixel Clock*/ 1232 pool->clock_sources[DCN303_CLK_SRC_PLL0] = 1233 dcn303_clock_source_create(ctx, ctx->dc_bios, 1234 CLOCK_SOURCE_COMBO_PHY_PLL0, 1235 &clk_src_regs[0], false); 1236 pool->clock_sources[DCN303_CLK_SRC_PLL1] = 1237 dcn303_clock_source_create(ctx, ctx->dc_bios, 1238 CLOCK_SOURCE_COMBO_PHY_PLL1, 1239 &clk_src_regs[1], false); 1240 1241 pool->clk_src_count = DCN303_CLK_SRC_TOTAL; 1242 1243 /* todo: not reuse phy_pll registers */ 1244 pool->dp_clock_source = 1245 dcn303_clock_source_create(ctx, ctx->dc_bios, 1246 CLOCK_SOURCE_ID_DP_DTO, 1247 &clk_src_regs[0], true); 1248 1249 for (i = 0; i < pool->clk_src_count; i++) { 1250 if (pool->clock_sources[i] == NULL) { 1251 dm_error("DC: failed to create clock sources!\n"); 1252 BREAK_TO_DEBUGGER(); 1253 goto create_fail; 1254 } 1255 } 1256 1257 /* DCCG */ 1258 pool->dccg = dccg30_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 1259 if (pool->dccg == NULL) { 1260 dm_error("DC: failed to create dccg!\n"); 1261 BREAK_TO_DEBUGGER(); 1262 goto create_fail; 1263 } 1264 1265 /* PP Lib and SMU interfaces */ 1266 init_soc_bounding_box(dc, pool); 1267 1268 /* DML */ 1269 dml_init_instance(&dc->dml, &dcn3_03_soc, &dcn3_03_ip, DML_PROJECT_DCN30); 1270 1271 /* IRQ */ 1272 init_data.ctx = dc->ctx; 1273 pool->irqs = dal_irq_service_dcn303_create(&init_data); 1274 if (!pool->irqs) 1275 goto create_fail; 1276 1277 /* HUBBUB */ 1278 pool->hubbub = dcn303_hubbub_create(ctx); 1279 if (pool->hubbub == NULL) { 1280 BREAK_TO_DEBUGGER(); 1281 dm_error("DC: failed to create hubbub!\n"); 1282 goto create_fail; 1283 } 1284 1285 /* HUBPs, DPPs, OPPs and TGs */ 1286 for (i = 0; i < pool->pipe_count; i++) { 1287 pool->hubps[i] = dcn303_hubp_create(ctx, i); 1288 if (pool->hubps[i] == NULL) { 1289 BREAK_TO_DEBUGGER(); 1290 dm_error("DC: failed to create hubps!\n"); 1291 goto create_fail; 1292 } 1293 1294 pool->dpps[i] = dcn303_dpp_create(ctx, i); 1295 if (pool->dpps[i] == NULL) { 1296 BREAK_TO_DEBUGGER(); 1297 dm_error("DC: failed to create dpps!\n"); 1298 goto create_fail; 1299 } 1300 } 1301 1302 for (i = 0; i < pool->res_cap->num_opp; i++) { 1303 pool->opps[i] = dcn303_opp_create(ctx, i); 1304 if (pool->opps[i] == NULL) { 1305 BREAK_TO_DEBUGGER(); 1306 dm_error("DC: failed to create output pixel processor!\n"); 1307 goto create_fail; 1308 } 1309 } 1310 1311 for (i = 0; i < pool->res_cap->num_timing_generator; i++) { 1312 pool->timing_generators[i] = dcn303_timing_generator_create(ctx, i); 1313 if (pool->timing_generators[i] == NULL) { 1314 BREAK_TO_DEBUGGER(); 1315 dm_error("DC: failed to create tg!\n"); 1316 goto create_fail; 1317 } 1318 } 1319 pool->timing_generator_count = i; 1320 1321 /* PSR */ 1322 pool->psr = dmub_psr_create(ctx); 1323 if (pool->psr == NULL) { 1324 dm_error("DC: failed to create psr!\n"); 1325 BREAK_TO_DEBUGGER(); 1326 goto create_fail; 1327 } 1328 1329 /* ABM */ 1330 for (i = 0; i < pool->res_cap->num_timing_generator; i++) { 1331 pool->multiple_abms[i] = dmub_abm_create(ctx, &abm_regs[i], &abm_shift, &abm_mask); 1332 if (pool->multiple_abms[i] == NULL) { 1333 dm_error("DC: failed to create abm for pipe %d!\n", i); 1334 BREAK_TO_DEBUGGER(); 1335 goto create_fail; 1336 } 1337 } 1338 1339 /* MPC and DSC */ 1340 pool->mpc = dcn303_mpc_create(ctx, pool->mpcc_count, pool->res_cap->num_mpc_3dlut); 1341 if (pool->mpc == NULL) { 1342 BREAK_TO_DEBUGGER(); 1343 dm_error("DC: failed to create mpc!\n"); 1344 goto create_fail; 1345 } 1346 1347 for (i = 0; i < pool->res_cap->num_dsc; i++) { 1348 pool->dscs[i] = dcn303_dsc_create(ctx, i); 1349 if (pool->dscs[i] == NULL) { 1350 BREAK_TO_DEBUGGER(); 1351 dm_error("DC: failed to create display stream compressor %d!\n", i); 1352 goto create_fail; 1353 } 1354 } 1355 1356 /* DWB and MMHUBBUB */ 1357 if (!dcn303_dwbc_create(ctx, pool)) { 1358 BREAK_TO_DEBUGGER(); 1359 dm_error("DC: failed to create dwbc!\n"); 1360 goto create_fail; 1361 } 1362 1363 if (!dcn303_mmhubbub_create(ctx, pool)) { 1364 BREAK_TO_DEBUGGER(); 1365 dm_error("DC: failed to create mcif_wb!\n"); 1366 goto create_fail; 1367 } 1368 1369 /* AUX and I2C */ 1370 for (i = 0; i < pool->res_cap->num_ddc; i++) { 1371 pool->engines[i] = dcn303_aux_engine_create(ctx, i); 1372 if (pool->engines[i] == NULL) { 1373 BREAK_TO_DEBUGGER(); 1374 dm_error("DC:failed to create aux engine!!\n"); 1375 goto create_fail; 1376 } 1377 pool->hw_i2cs[i] = dcn303_i2c_hw_create(ctx, i); 1378 if (pool->hw_i2cs[i] == NULL) { 1379 BREAK_TO_DEBUGGER(); 1380 dm_error("DC:failed to create hw i2c!!\n"); 1381 goto create_fail; 1382 } 1383 pool->sw_i2cs[i] = NULL; 1384 } 1385 1386 /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */ 1387 if (!resource_construct(num_virtual_links, dc, pool, 1388 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? 1389 &res_create_funcs : &res_create_maximus_funcs))) 1390 goto create_fail; 1391 1392 /* HW Sequencer and Plane caps */ 1393 dcn303_hw_sequencer_construct(dc); 1394 1395 dc->caps.max_planes = pool->pipe_count; 1396 1397 for (i = 0; i < dc->caps.max_planes; ++i) 1398 dc->caps.planes[i] = plane_cap; 1399 1400 dc->cap_funcs = cap_funcs; 1401 1402 if (dc->ctx->dc_bios->fw_info.oem_i2c_present) { 1403 ddc_init_data.ctx = dc->ctx; 1404 ddc_init_data.link = NULL; 1405 ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id; 1406 ddc_init_data.id.enum_id = 0; 1407 ddc_init_data.id.type = OBJECT_TYPE_GENERIC; 1408 pool->oem_device = dal_ddc_service_create(&ddc_init_data); 1409 } else { 1410 pool->oem_device = NULL; 1411 } 1412 1413 return true; 1414 1415 create_fail: 1416 1417 dcn303_resource_destruct(pool); 1418 1419 return false; 1420 } 1421 1422 struct resource_pool *dcn303_create_resource_pool(const struct dc_init_data *init_data, struct dc *dc) 1423 { 1424 struct resource_pool *pool = kzalloc(sizeof(struct resource_pool), GFP_KERNEL); 1425 1426 if (!pool) 1427 return NULL; 1428 1429 if (dcn303_resource_construct(init_data->num_virtual_links, dc, pool)) 1430 return pool; 1431 1432 BREAK_TO_DEBUGGER(); 1433 kfree(pool); 1434 return NULL; 1435 } 1436