1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright (C) 2021 Advanced Micro Devices, Inc. 4 * 5 * Authors: AMD 6 */ 7 8 #include "dcn303_init.h" 9 #include "dcn303_resource.h" 10 #include "dcn303_dccg.h" 11 #include "irq/dcn303/irq_service_dcn303.h" 12 13 #include "dcn30/dcn30_dio_link_encoder.h" 14 #include "dcn30/dcn30_dio_stream_encoder.h" 15 #include "dcn30/dcn30_dpp.h" 16 #include "dcn30/dcn30_dwb.h" 17 #include "dcn30/dcn30_hubbub.h" 18 #include "dcn30/dcn30_hubp.h" 19 #include "dcn30/dcn30_mmhubbub.h" 20 #include "dcn30/dcn30_mpc.h" 21 #include "dcn30/dcn30_opp.h" 22 #include "dcn30/dcn30_optc.h" 23 #include "dcn30/dcn30_resource.h" 24 25 #include "dcn20/dcn20_dsc.h" 26 #include "dcn20/dcn20_resource.h" 27 28 #include "dcn10/dcn10_resource.h" 29 30 #include "dc_link_ddc.h" 31 32 #include "dce/dce_abm.h" 33 #include "dce/dce_audio.h" 34 #include "dce/dce_aux.h" 35 #include "dce/dce_clock_source.h" 36 #include "dce/dce_hwseq.h" 37 #include "dce/dce_i2c_hw.h" 38 #include "dce/dce_panel_cntl.h" 39 #include "dce/dmub_abm.h" 40 #include "dce/dmub_psr.h" 41 #include "clk_mgr.h" 42 43 #include "hw_sequencer_private.h" 44 #include "reg_helper.h" 45 #include "resource.h" 46 #include "vm_helper.h" 47 48 #include "sienna_cichlid_ip_offset.h" 49 #include "dcn/dcn_3_0_3_offset.h" 50 #include "dcn/dcn_3_0_3_sh_mask.h" 51 #include "dcn/dpcs_3_0_3_offset.h" 52 #include "dcn/dpcs_3_0_3_sh_mask.h" 53 #include "nbio/nbio_2_3_offset.h" 54 55 #define DC_LOGGER_INIT(logger) 56 57 struct _vcs_dpi_ip_params_st dcn3_03_ip = { 58 .use_min_dcfclk = 0, 59 .clamp_min_dcfclk = 0, 60 .odm_capable = 1, 61 .gpuvm_enable = 1, 62 .hostvm_enable = 0, 63 .gpuvm_max_page_table_levels = 4, 64 .hostvm_max_page_table_levels = 4, 65 .hostvm_cached_page_table_levels = 0, 66 .pte_group_size_bytes = 2048, 67 .num_dsc = 2, 68 .rob_buffer_size_kbytes = 184, 69 .det_buffer_size_kbytes = 184, 70 .dpte_buffer_size_in_pte_reqs_luma = 64, 71 .dpte_buffer_size_in_pte_reqs_chroma = 34, 72 .pde_proc_buffer_size_64k_reqs = 48, 73 .dpp_output_buffer_pixels = 2560, 74 .opp_output_buffer_lines = 1, 75 .pixel_chunk_size_kbytes = 8, 76 .pte_enable = 1, 77 .max_page_table_levels = 2, 78 .pte_chunk_size_kbytes = 2, // ? 79 .meta_chunk_size_kbytes = 2, 80 .writeback_chunk_size_kbytes = 8, 81 .line_buffer_size_bits = 789504, 82 .is_line_buffer_bpp_fixed = 0, // ? 83 .line_buffer_fixed_bpp = 0, // ? 84 .dcc_supported = true, 85 .writeback_interface_buffer_size_kbytes = 90, 86 .writeback_line_buffer_buffer_size = 0, 87 .max_line_buffer_lines = 12, 88 .writeback_luma_buffer_size_kbytes = 12, // writeback_line_buffer_buffer_size = 656640 89 .writeback_chroma_buffer_size_kbytes = 8, 90 .writeback_chroma_line_buffer_width_pixels = 4, 91 .writeback_max_hscl_ratio = 1, 92 .writeback_max_vscl_ratio = 1, 93 .writeback_min_hscl_ratio = 1, 94 .writeback_min_vscl_ratio = 1, 95 .writeback_max_hscl_taps = 1, 96 .writeback_max_vscl_taps = 1, 97 .writeback_line_buffer_luma_buffer_size = 0, 98 .writeback_line_buffer_chroma_buffer_size = 14643, 99 .cursor_buffer_size = 8, 100 .cursor_chunk_size = 2, 101 .max_num_otg = 2, 102 .max_num_dpp = 2, 103 .max_num_wb = 1, 104 .max_dchub_pscl_bw_pix_per_clk = 4, 105 .max_pscl_lb_bw_pix_per_clk = 2, 106 .max_lb_vscl_bw_pix_per_clk = 4, 107 .max_vscl_hscl_bw_pix_per_clk = 4, 108 .max_hscl_ratio = 6, 109 .max_vscl_ratio = 6, 110 .hscl_mults = 4, 111 .vscl_mults = 4, 112 .max_hscl_taps = 8, 113 .max_vscl_taps = 8, 114 .dispclk_ramp_margin_percent = 1, 115 .underscan_factor = 1.11, 116 .min_vblank_lines = 32, 117 .dppclk_delay_subtotal = 46, 118 .dynamic_metadata_vm_enabled = true, 119 .dppclk_delay_scl_lb_only = 16, 120 .dppclk_delay_scl = 50, 121 .dppclk_delay_cnvc_formatter = 27, 122 .dppclk_delay_cnvc_cursor = 6, 123 .dispclk_delay_subtotal = 119, 124 .dcfclk_cstate_latency = 5.2, // SRExitTime 125 .max_inter_dcn_tile_repeaters = 8, 126 .max_num_hdmi_frl_outputs = 1, 127 .odm_combine_4to1_supported = false, 128 .xfc_supported = false, 129 .xfc_fill_bw_overhead_percent = 10.0, 130 .xfc_fill_constant_bytes = 0, 131 .gfx7_compat_tiling_supported = 0, 132 .number_of_cursors = 1, 133 }; 134 135 struct _vcs_dpi_soc_bounding_box_st dcn3_03_soc = { 136 .clock_limits = { 137 { 138 .state = 0, 139 .dispclk_mhz = 1217.0, 140 .dppclk_mhz = 1217.0, 141 .phyclk_mhz = 810.0, 142 .phyclk_d18_mhz = 667.0, 143 .dscclk_mhz = 405.6, 144 }, 145 }, 146 147 .min_dcfclk = 500.0, /* TODO: set this to actual min DCFCLK */ 148 .num_states = 1, 149 .sr_exit_time_us = 26.5, 150 .sr_enter_plus_exit_time_us = 31, 151 .urgent_latency_us = 4.0, 152 .urgent_latency_pixel_data_only_us = 4.0, 153 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0, 154 .urgent_latency_vm_data_only_us = 4.0, 155 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096, 156 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096, 157 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096, 158 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 80.0, 159 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0, 160 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0, 161 .max_avg_sdp_bw_use_normal_percent = 60.0, 162 .max_avg_dram_bw_use_normal_percent = 40.0, 163 .writeback_latency_us = 12.0, 164 .max_request_size_bytes = 256, 165 .fabric_datapath_to_dcn_data_return_bytes = 64, 166 .dcn_downspread_percent = 0.5, 167 .downspread_percent = 0.38, 168 .dram_page_open_time_ns = 50.0, 169 .dram_rw_turnaround_time_ns = 17.5, 170 .dram_return_buffer_per_channel_bytes = 8192, 171 .round_trip_ping_latency_dcfclk_cycles = 156, 172 .urgent_out_of_order_return_per_channel_bytes = 4096, 173 .channel_interleave_bytes = 256, 174 .num_banks = 8, 175 .gpuvm_min_page_size_bytes = 4096, 176 .hostvm_min_page_size_bytes = 4096, 177 .dram_clock_change_latency_us = 404, 178 .dummy_pstate_latency_us = 5, 179 .writeback_dram_clock_change_latency_us = 23.0, 180 .return_bus_width_bytes = 64, 181 .dispclk_dppclk_vco_speed_mhz = 3650, 182 .xfc_bus_transport_time_us = 20, // ? 183 .xfc_xbuf_latency_tolerance_us = 4, // ? 184 .use_urgent_burst_bw = 1, // ? 185 .do_urgent_latency_adjustment = true, 186 .urgent_latency_adjustment_fabric_clock_component_us = 1.0, 187 .urgent_latency_adjustment_fabric_clock_reference_mhz = 1000, 188 }; 189 190 static const struct dc_debug_options debug_defaults_drv = { 191 .disable_dmcu = true, 192 .force_abm_enable = false, 193 .timing_trace = false, 194 .clock_trace = true, 195 .disable_pplib_clock_request = true, 196 .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP, 197 .force_single_disp_pipe_split = false, 198 .disable_dcc = DCC_ENABLE, 199 .vsr_support = true, 200 .performance_trace = false, 201 .max_downscale_src_width = 7680,/*upto 8K*/ 202 .disable_pplib_wm_range = false, 203 .scl_reset_length10 = true, 204 .sanity_checks = false, 205 .underflow_assert_delay_us = 0xFFFFFFFF, 206 .dwb_fi_phase = -1, // -1 = disable, 207 .dmub_command_table = true, 208 .disable_idle_power_optimizations = false, 209 }; 210 211 static const struct dc_debug_options debug_defaults_diags = { 212 .disable_dmcu = true, 213 .force_abm_enable = false, 214 .timing_trace = true, 215 .clock_trace = true, 216 .disable_dpp_power_gate = true, 217 .disable_hubp_power_gate = true, 218 .disable_clock_gate = true, 219 .disable_pplib_clock_request = true, 220 .disable_pplib_wm_range = true, 221 .disable_stutter = false, 222 .scl_reset_length10 = true, 223 .dwb_fi_phase = -1, // -1 = disable 224 .dmub_command_table = true, 225 .enable_tri_buf = true, 226 .disable_psr = true, 227 }; 228 229 enum dcn303_clk_src_array_id { 230 DCN303_CLK_SRC_PLL0, 231 DCN303_CLK_SRC_PLL1, 232 DCN303_CLK_SRC_TOTAL 233 }; 234 235 static const struct resource_caps res_cap_dcn303 = { 236 .num_timing_generator = 2, 237 .num_opp = 2, 238 .num_video_plane = 2, 239 .num_audio = 2, 240 .num_stream_encoder = 2, 241 .num_dwb = 1, 242 .num_ddc = 2, 243 .num_vmid = 16, 244 .num_mpc_3dlut = 1, 245 .num_dsc = 2, 246 }; 247 248 static const struct dc_plane_cap plane_cap = { 249 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 250 .blends_with_above = true, 251 .blends_with_below = true, 252 .per_pixel_alpha = true, 253 .pixel_format_support = { 254 .argb8888 = true, 255 .nv12 = true, 256 .fp16 = true, 257 .p010 = false, 258 .ayuv = false, 259 }, 260 .max_upscale_factor = { 261 .argb8888 = 16000, 262 .nv12 = 16000, 263 .fp16 = 16000 264 }, 265 .max_downscale_factor = { 266 .argb8888 = 600, 267 .nv12 = 600, 268 .fp16 = 600 269 }, 270 16, 271 16 272 }; 273 274 /* NBIO */ 275 #define NBIO_BASE_INNER(seg) \ 276 NBIO_BASE__INST0_SEG ## seg 277 278 #define NBIO_BASE(seg) \ 279 NBIO_BASE_INNER(seg) 280 281 #define NBIO_SR(reg_name)\ 282 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \ 283 mm ## reg_name 284 285 /* DCN */ 286 #undef BASE_INNER 287 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg 288 289 #define BASE(seg) BASE_INNER(seg) 290 291 #define SR(reg_name)\ 292 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name 293 294 #define SF(reg_name, field_name, post_fix)\ 295 .field_name = reg_name ## __ ## field_name ## post_fix 296 297 #define SRI(reg_name, block, id)\ 298 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + mm ## block ## id ## _ ## reg_name 299 300 #define SRI2(reg_name, block, id)\ 301 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name 302 303 #define SRII(reg_name, block, id)\ 304 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 305 mm ## block ## id ## _ ## reg_name 306 307 #define DCCG_SRII(reg_name, block, id)\ 308 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 309 mm ## block ## id ## _ ## reg_name 310 311 #define VUPDATE_SRII(reg_name, block, id)\ 312 .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \ 313 mm ## reg_name ## _ ## block ## id 314 315 #define SRII_DWB(reg_name, temp_name, block, id)\ 316 .reg_name[id] = BASE(mm ## block ## id ## _ ## temp_name ## _BASE_IDX) + \ 317 mm ## block ## id ## _ ## temp_name 318 319 #define SRII_MPC_RMU(reg_name, block, id)\ 320 .RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 321 mm ## block ## id ## _ ## reg_name 322 323 static const struct dcn_hubbub_registers hubbub_reg = { 324 HUBBUB_REG_LIST_DCN30(0) 325 }; 326 327 static const struct dcn_hubbub_shift hubbub_shift = { 328 HUBBUB_MASK_SH_LIST_DCN30(__SHIFT) 329 }; 330 331 static const struct dcn_hubbub_mask hubbub_mask = { 332 HUBBUB_MASK_SH_LIST_DCN30(_MASK) 333 }; 334 335 #define vmid_regs(id)\ 336 [id] = { DCN20_VMID_REG_LIST(id) } 337 338 static const struct dcn_vmid_registers vmid_regs[] = { 339 vmid_regs(0), 340 vmid_regs(1), 341 vmid_regs(2), 342 vmid_regs(3), 343 vmid_regs(4), 344 vmid_regs(5), 345 vmid_regs(6), 346 vmid_regs(7), 347 vmid_regs(8), 348 vmid_regs(9), 349 vmid_regs(10), 350 vmid_regs(11), 351 vmid_regs(12), 352 vmid_regs(13), 353 vmid_regs(14), 354 vmid_regs(15) 355 }; 356 357 static const struct dcn20_vmid_shift vmid_shifts = { 358 DCN20_VMID_MASK_SH_LIST(__SHIFT) 359 }; 360 361 static const struct dcn20_vmid_mask vmid_masks = { 362 DCN20_VMID_MASK_SH_LIST(_MASK) 363 }; 364 365 static struct hubbub *dcn303_hubbub_create(struct dc_context *ctx) 366 { 367 int i; 368 369 struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub), GFP_KERNEL); 370 371 if (!hubbub3) 372 return NULL; 373 374 hubbub3_construct(hubbub3, ctx, &hubbub_reg, &hubbub_shift, &hubbub_mask); 375 376 for (i = 0; i < res_cap_dcn303.num_vmid; i++) { 377 struct dcn20_vmid *vmid = &hubbub3->vmid[i]; 378 379 vmid->ctx = ctx; 380 381 vmid->regs = &vmid_regs[i]; 382 vmid->shifts = &vmid_shifts; 383 vmid->masks = &vmid_masks; 384 } 385 386 return &hubbub3->base; 387 } 388 389 #define vpg_regs(id)\ 390 [id] = { VPG_DCN3_REG_LIST(id) } 391 392 static const struct dcn30_vpg_registers vpg_regs[] = { 393 vpg_regs(0), 394 vpg_regs(1), 395 vpg_regs(2) 396 }; 397 398 static const struct dcn30_vpg_shift vpg_shift = { 399 DCN3_VPG_MASK_SH_LIST(__SHIFT) 400 }; 401 402 static const struct dcn30_vpg_mask vpg_mask = { 403 DCN3_VPG_MASK_SH_LIST(_MASK) 404 }; 405 406 static struct vpg *dcn303_vpg_create(struct dc_context *ctx, uint32_t inst) 407 { 408 struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL); 409 410 if (!vpg3) 411 return NULL; 412 413 vpg3_construct(vpg3, ctx, inst, &vpg_regs[inst], &vpg_shift, &vpg_mask); 414 415 return &vpg3->base; 416 } 417 418 #define afmt_regs(id)\ 419 [id] = { AFMT_DCN3_REG_LIST(id) } 420 421 static const struct dcn30_afmt_registers afmt_regs[] = { 422 afmt_regs(0), 423 afmt_regs(1), 424 afmt_regs(2) 425 }; 426 427 static const struct dcn30_afmt_shift afmt_shift = { 428 DCN3_AFMT_MASK_SH_LIST(__SHIFT) 429 }; 430 431 static const struct dcn30_afmt_mask afmt_mask = { 432 DCN3_AFMT_MASK_SH_LIST(_MASK) 433 }; 434 435 static struct afmt *dcn303_afmt_create(struct dc_context *ctx, uint32_t inst) 436 { 437 struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL); 438 439 if (!afmt3) 440 return NULL; 441 442 afmt3_construct(afmt3, ctx, inst, &afmt_regs[inst], &afmt_shift, &afmt_mask); 443 444 return &afmt3->base; 445 } 446 447 #define audio_regs(id)\ 448 [id] = { AUD_COMMON_REG_LIST(id) } 449 450 static const struct dce_audio_registers audio_regs[] = { 451 audio_regs(0), 452 audio_regs(1), 453 audio_regs(2), 454 audio_regs(3), 455 audio_regs(4), 456 audio_regs(5), 457 audio_regs(6) 458 }; 459 460 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 461 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 462 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 463 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 464 465 static const struct dce_audio_shift audio_shift = { 466 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 467 }; 468 469 static const struct dce_audio_mask audio_mask = { 470 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 471 }; 472 473 static struct audio *dcn303_create_audio(struct dc_context *ctx, unsigned int inst) 474 { 475 return dce_audio_create(ctx, inst, &audio_regs[inst], &audio_shift, &audio_mask); 476 } 477 478 #define stream_enc_regs(id)\ 479 [id] = { SE_DCN3_REG_LIST(id) } 480 481 static const struct dcn10_stream_enc_registers stream_enc_regs[] = { 482 stream_enc_regs(0), 483 stream_enc_regs(1) 484 }; 485 486 static const struct dcn10_stream_encoder_shift se_shift = { 487 SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 488 }; 489 490 static const struct dcn10_stream_encoder_mask se_mask = { 491 SE_COMMON_MASK_SH_LIST_DCN30(_MASK) 492 }; 493 494 static struct stream_encoder *dcn303_stream_encoder_create(enum engine_id eng_id, struct dc_context *ctx) 495 { 496 struct dcn10_stream_encoder *enc1; 497 struct vpg *vpg; 498 struct afmt *afmt; 499 int vpg_inst; 500 int afmt_inst; 501 502 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */ 503 if (eng_id <= ENGINE_ID_DIGE) { 504 vpg_inst = eng_id; 505 afmt_inst = eng_id; 506 } else 507 return NULL; 508 509 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 510 vpg = dcn303_vpg_create(ctx, vpg_inst); 511 afmt = dcn303_afmt_create(ctx, afmt_inst); 512 513 if (!enc1 || !vpg || !afmt) 514 return NULL; 515 516 dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id, vpg, afmt, &stream_enc_regs[eng_id], 517 &se_shift, &se_mask); 518 519 return &enc1->base; 520 } 521 522 #define clk_src_regs(index, pllid)\ 523 [index] = { CS_COMMON_REG_LIST_DCN3_03(index, pllid) } 524 525 static const struct dce110_clk_src_regs clk_src_regs[] = { 526 clk_src_regs(0, A), 527 clk_src_regs(1, B) 528 }; 529 530 static const struct dce110_clk_src_shift cs_shift = { 531 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 532 }; 533 534 static const struct dce110_clk_src_mask cs_mask = { 535 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 536 }; 537 538 static struct clock_source *dcn303_clock_source_create(struct dc_context *ctx, struct dc_bios *bios, 539 enum clock_source_id id, const struct dce110_clk_src_regs *regs, bool dp_clk_src) 540 { 541 struct dce110_clk_src *clk_src = kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 542 543 if (!clk_src) 544 return NULL; 545 546 if (dcn3_clk_src_construct(clk_src, ctx, bios, id, regs, &cs_shift, &cs_mask)) { 547 clk_src->base.dp_clk_src = dp_clk_src; 548 return &clk_src->base; 549 } 550 551 BREAK_TO_DEBUGGER(); 552 return NULL; 553 } 554 555 static const struct dce_hwseq_registers hwseq_reg = { 556 HWSEQ_DCN303_REG_LIST() 557 }; 558 559 static const struct dce_hwseq_shift hwseq_shift = { 560 HWSEQ_DCN303_MASK_SH_LIST(__SHIFT) 561 }; 562 563 static const struct dce_hwseq_mask hwseq_mask = { 564 HWSEQ_DCN303_MASK_SH_LIST(_MASK) 565 }; 566 567 static struct dce_hwseq *dcn303_hwseq_create(struct dc_context *ctx) 568 { 569 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 570 571 if (hws) { 572 hws->ctx = ctx; 573 hws->regs = &hwseq_reg; 574 hws->shifts = &hwseq_shift; 575 hws->masks = &hwseq_mask; 576 } 577 return hws; 578 } 579 580 #define hubp_regs(id)\ 581 [id] = { HUBP_REG_LIST_DCN30(id) } 582 583 static const struct dcn_hubp2_registers hubp_regs[] = { 584 hubp_regs(0), 585 hubp_regs(1) 586 }; 587 588 static const struct dcn_hubp2_shift hubp_shift = { 589 HUBP_MASK_SH_LIST_DCN30(__SHIFT) 590 }; 591 592 static const struct dcn_hubp2_mask hubp_mask = { 593 HUBP_MASK_SH_LIST_DCN30(_MASK) 594 }; 595 596 static struct hubp *dcn303_hubp_create(struct dc_context *ctx, uint32_t inst) 597 { 598 struct dcn20_hubp *hubp2 = kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL); 599 600 if (!hubp2) 601 return NULL; 602 603 if (hubp3_construct(hubp2, ctx, inst, &hubp_regs[inst], &hubp_shift, &hubp_mask)) 604 return &hubp2->base; 605 606 BREAK_TO_DEBUGGER(); 607 kfree(hubp2); 608 return NULL; 609 } 610 611 #define dpp_regs(id)\ 612 [id] = { DPP_REG_LIST_DCN30(id) } 613 614 static const struct dcn3_dpp_registers dpp_regs[] = { 615 dpp_regs(0), 616 dpp_regs(1) 617 }; 618 619 static const struct dcn3_dpp_shift tf_shift = { 620 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT) 621 }; 622 623 static const struct dcn3_dpp_mask tf_mask = { 624 DPP_REG_LIST_SH_MASK_DCN30(_MASK) 625 }; 626 627 static struct dpp *dcn303_dpp_create(struct dc_context *ctx, uint32_t inst) 628 { 629 struct dcn3_dpp *dpp = kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL); 630 631 if (!dpp) 632 return NULL; 633 634 if (dpp3_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, &tf_mask)) 635 return &dpp->base; 636 637 BREAK_TO_DEBUGGER(); 638 kfree(dpp); 639 return NULL; 640 } 641 642 #define opp_regs(id)\ 643 [id] = { OPP_REG_LIST_DCN30(id) } 644 645 static const struct dcn20_opp_registers opp_regs[] = { 646 opp_regs(0), 647 opp_regs(1) 648 }; 649 650 static const struct dcn20_opp_shift opp_shift = { 651 OPP_MASK_SH_LIST_DCN20(__SHIFT) 652 }; 653 654 static const struct dcn20_opp_mask opp_mask = { 655 OPP_MASK_SH_LIST_DCN20(_MASK) 656 }; 657 658 static struct output_pixel_processor *dcn303_opp_create(struct dc_context *ctx, uint32_t inst) 659 { 660 struct dcn20_opp *opp = kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); 661 662 if (!opp) { 663 BREAK_TO_DEBUGGER(); 664 return NULL; 665 } 666 667 dcn20_opp_construct(opp, ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask); 668 return &opp->base; 669 } 670 671 #define optc_regs(id)\ 672 [id] = { OPTC_COMMON_REG_LIST_DCN3_0(id) } 673 674 static const struct dcn_optc_registers optc_regs[] = { 675 optc_regs(0), 676 optc_regs(1) 677 }; 678 679 static const struct dcn_optc_shift optc_shift = { 680 OPTC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 681 }; 682 683 static const struct dcn_optc_mask optc_mask = { 684 OPTC_COMMON_MASK_SH_LIST_DCN30(_MASK) 685 }; 686 687 static struct timing_generator *dcn303_timing_generator_create(struct dc_context *ctx, uint32_t instance) 688 { 689 struct optc *tgn10 = kzalloc(sizeof(struct optc), GFP_KERNEL); 690 691 if (!tgn10) 692 return NULL; 693 694 tgn10->base.inst = instance; 695 tgn10->base.ctx = ctx; 696 697 tgn10->tg_regs = &optc_regs[instance]; 698 tgn10->tg_shift = &optc_shift; 699 tgn10->tg_mask = &optc_mask; 700 701 dcn30_timing_generator_init(tgn10); 702 703 return &tgn10->base; 704 } 705 706 static const struct dcn30_mpc_registers mpc_regs = { 707 MPC_REG_LIST_DCN3_0(0), 708 MPC_REG_LIST_DCN3_0(1), 709 MPC_OUT_MUX_REG_LIST_DCN3_0(0), 710 MPC_OUT_MUX_REG_LIST_DCN3_0(1), 711 MPC_RMU_GLOBAL_REG_LIST_DCN3AG, 712 MPC_RMU_REG_LIST_DCN3AG(0), 713 MPC_DWB_MUX_REG_LIST_DCN3_0(0), 714 }; 715 716 static const struct dcn30_mpc_shift mpc_shift = { 717 MPC_COMMON_MASK_SH_LIST_DCN303(__SHIFT) 718 }; 719 720 static const struct dcn30_mpc_mask mpc_mask = { 721 MPC_COMMON_MASK_SH_LIST_DCN303(_MASK) 722 }; 723 724 static struct mpc *dcn303_mpc_create(struct dc_context *ctx, int num_mpcc, int num_rmu) 725 { 726 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), GFP_KERNEL); 727 728 if (!mpc30) 729 return NULL; 730 731 dcn30_mpc_construct(mpc30, ctx, &mpc_regs, &mpc_shift, &mpc_mask, num_mpcc, num_rmu); 732 733 return &mpc30->base; 734 } 735 736 #define dsc_regsDCN20(id)\ 737 [id] = { DSC_REG_LIST_DCN20(id) } 738 739 static const struct dcn20_dsc_registers dsc_regs[] = { 740 dsc_regsDCN20(0), 741 dsc_regsDCN20(1) 742 }; 743 744 static const struct dcn20_dsc_shift dsc_shift = { 745 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) 746 }; 747 748 static const struct dcn20_dsc_mask dsc_mask = { 749 DSC_REG_LIST_SH_MASK_DCN20(_MASK) 750 }; 751 752 static struct display_stream_compressor *dcn303_dsc_create(struct dc_context *ctx, uint32_t inst) 753 { 754 struct dcn20_dsc *dsc = kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); 755 756 if (!dsc) { 757 BREAK_TO_DEBUGGER(); 758 return NULL; 759 } 760 761 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 762 return &dsc->base; 763 } 764 765 #define dwbc_regs_dcn3(id)\ 766 [id] = { DWBC_COMMON_REG_LIST_DCN30(id) } 767 768 static const struct dcn30_dwbc_registers dwbc30_regs[] = { 769 dwbc_regs_dcn3(0) 770 }; 771 772 static const struct dcn30_dwbc_shift dwbc30_shift = { 773 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 774 }; 775 776 static const struct dcn30_dwbc_mask dwbc30_mask = { 777 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK) 778 }; 779 780 static bool dcn303_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) 781 { 782 int i; 783 uint32_t pipe_count = pool->res_cap->num_dwb; 784 785 for (i = 0; i < pipe_count; i++) { 786 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), GFP_KERNEL); 787 788 if (!dwbc30) { 789 dm_error("DC: failed to create dwbc30!\n"); 790 return false; 791 } 792 793 dcn30_dwbc_construct(dwbc30, ctx, &dwbc30_regs[i], &dwbc30_shift, &dwbc30_mask, i); 794 795 pool->dwbc[i] = &dwbc30->base; 796 } 797 return true; 798 } 799 800 #define mcif_wb_regs_dcn3(id)\ 801 [id] = { MCIF_WB_COMMON_REG_LIST_DCN30(id) } 802 803 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = { 804 mcif_wb_regs_dcn3(0) 805 }; 806 807 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = { 808 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 809 }; 810 811 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { 812 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK) 813 }; 814 815 static bool dcn303_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) 816 { 817 int i; 818 uint32_t pipe_count = pool->res_cap->num_dwb; 819 820 for (i = 0; i < pipe_count; i++) { 821 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), GFP_KERNEL); 822 823 if (!mcif_wb30) { 824 dm_error("DC: failed to create mcif_wb30!\n"); 825 return false; 826 } 827 828 dcn30_mmhubbub_construct(mcif_wb30, ctx, &mcif_wb30_regs[i], &mcif_wb30_shift, &mcif_wb30_mask, i); 829 830 pool->mcif_wb[i] = &mcif_wb30->base; 831 } 832 return true; 833 } 834 835 #define aux_engine_regs(id)\ 836 [id] = {\ 837 AUX_COMMON_REG_LIST0(id), \ 838 .AUXN_IMPCAL = 0, \ 839 .AUXP_IMPCAL = 0, \ 840 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \ 841 } 842 843 static const struct dce110_aux_registers aux_engine_regs[] = { 844 aux_engine_regs(0), 845 aux_engine_regs(1) 846 }; 847 848 static const struct dce110_aux_registers_shift aux_shift = { 849 DCN_AUX_MASK_SH_LIST(__SHIFT) 850 }; 851 852 static const struct dce110_aux_registers_mask aux_mask = { 853 DCN_AUX_MASK_SH_LIST(_MASK) 854 }; 855 856 static struct dce_aux *dcn303_aux_engine_create(struct dc_context *ctx, uint32_t inst) 857 { 858 struct aux_engine_dce110 *aux_engine = kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 859 860 if (!aux_engine) 861 return NULL; 862 863 dce110_aux_engine_construct(aux_engine, ctx, inst, SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 864 &aux_engine_regs[inst], &aux_mask, &aux_shift, ctx->dc->caps.extended_aux_timeout_support); 865 866 return &aux_engine->base; 867 } 868 869 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 870 871 static const struct dce_i2c_registers i2c_hw_regs[] = { 872 i2c_inst_regs(1), 873 i2c_inst_regs(2) 874 }; 875 876 static const struct dce_i2c_shift i2c_shifts = { 877 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT) 878 }; 879 880 static const struct dce_i2c_mask i2c_masks = { 881 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK) 882 }; 883 884 static struct dce_i2c_hw *dcn303_i2c_hw_create(struct dc_context *ctx, uint32_t inst) 885 { 886 struct dce_i2c_hw *dce_i2c_hw = kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 887 888 if (!dce_i2c_hw) 889 return NULL; 890 891 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 892 893 return dce_i2c_hw; 894 } 895 896 static const struct encoder_feature_support link_enc_feature = { 897 .max_hdmi_deep_color = COLOR_DEPTH_121212, 898 .max_hdmi_pixel_clock = 600000, 899 .hdmi_ycbcr420_supported = true, 900 .dp_ycbcr420_supported = true, 901 .fec_supported = true, 902 .flags.bits.IS_HBR2_CAPABLE = true, 903 .flags.bits.IS_HBR3_CAPABLE = true, 904 .flags.bits.IS_TPS3_CAPABLE = true, 905 .flags.bits.IS_TPS4_CAPABLE = true 906 }; 907 908 #define link_regs(id, phyid)\ 909 [id] = {\ 910 LE_DCN3_REG_LIST(id), \ 911 UNIPHY_DCN2_REG_LIST(phyid), \ 912 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \ 913 } 914 915 static const struct dcn10_link_enc_registers link_enc_regs[] = { 916 link_regs(0, A), 917 link_regs(1, B) 918 }; 919 920 static const struct dcn10_link_enc_shift le_shift = { 921 LINK_ENCODER_MASK_SH_LIST_DCN30(__SHIFT), 922 DPCS_DCN2_MASK_SH_LIST(__SHIFT) 923 }; 924 925 static const struct dcn10_link_enc_mask le_mask = { 926 LINK_ENCODER_MASK_SH_LIST_DCN30(_MASK), 927 DPCS_DCN2_MASK_SH_LIST(_MASK) 928 }; 929 930 #define aux_regs(id)\ 931 [id] = { DCN2_AUX_REG_LIST(id) } 932 933 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { 934 aux_regs(0), 935 aux_regs(1) 936 }; 937 938 #define hpd_regs(id)\ 939 [id] = { HPD_REG_LIST(id) } 940 941 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { 942 hpd_regs(0), 943 hpd_regs(1) 944 }; 945 946 static struct link_encoder *dcn303_link_encoder_create(const struct encoder_init_data *enc_init_data) 947 { 948 struct dcn20_link_encoder *enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 949 950 if (!enc20) 951 return NULL; 952 953 dcn30_link_encoder_construct(enc20, enc_init_data, &link_enc_feature, 954 &link_enc_regs[enc_init_data->transmitter], &link_enc_aux_regs[enc_init_data->channel - 1], 955 &link_enc_hpd_regs[enc_init_data->hpd_source], &le_shift, &le_mask); 956 957 return &enc20->enc10.base; 958 } 959 960 static const struct dce_panel_cntl_registers panel_cntl_regs[] = { 961 { DCN_PANEL_CNTL_REG_LIST() } 962 }; 963 964 static const struct dce_panel_cntl_shift panel_cntl_shift = { 965 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT) 966 }; 967 968 static const struct dce_panel_cntl_mask panel_cntl_mask = { 969 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK) 970 }; 971 972 static struct panel_cntl *dcn303_panel_cntl_create(const struct panel_cntl_init_data *init_data) 973 { 974 struct dce_panel_cntl *panel_cntl = kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL); 975 976 if (!panel_cntl) 977 return NULL; 978 979 dce_panel_cntl_construct(panel_cntl, init_data, &panel_cntl_regs[init_data->inst], 980 &panel_cntl_shift, &panel_cntl_mask); 981 982 return &panel_cntl->base; 983 } 984 985 static void read_dce_straps(struct dc_context *ctx, struct resource_straps *straps) 986 { 987 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX), 988 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 989 } 990 991 static const struct resource_create_funcs res_create_funcs = { 992 .read_dce_straps = read_dce_straps, 993 .create_audio = dcn303_create_audio, 994 .create_stream_encoder = dcn303_stream_encoder_create, 995 .create_hwseq = dcn303_hwseq_create, 996 }; 997 998 static const struct resource_create_funcs res_create_maximus_funcs = { 999 .read_dce_straps = NULL, 1000 .create_audio = NULL, 1001 .create_stream_encoder = NULL, 1002 .create_hwseq = dcn303_hwseq_create, 1003 }; 1004 1005 static bool is_soc_bounding_box_valid(struct dc *dc) 1006 { 1007 uint32_t hw_internal_rev = dc->ctx->asic_id.hw_internal_rev; 1008 1009 if (ASICREV_IS_BEIGE_GOBY_P(hw_internal_rev)) 1010 return true; 1011 1012 return false; 1013 } 1014 1015 static bool init_soc_bounding_box(struct dc *dc, struct resource_pool *pool) 1016 { 1017 struct _vcs_dpi_soc_bounding_box_st *loaded_bb = &dcn3_03_soc; 1018 struct _vcs_dpi_ip_params_st *loaded_ip = &dcn3_03_ip; 1019 1020 DC_LOGGER_INIT(dc->ctx->logger); 1021 1022 if (!is_soc_bounding_box_valid(dc)) { 1023 DC_LOG_ERROR("%s: not valid soc bounding box/n", __func__); 1024 return false; 1025 } 1026 1027 loaded_ip->max_num_otg = pool->pipe_count; 1028 loaded_ip->max_num_dpp = pool->pipe_count; 1029 loaded_ip->clamp_min_dcfclk = dc->config.clamp_min_dcfclk; 1030 dcn20_patch_bounding_box(dc, loaded_bb); 1031 1032 if (dc->ctx->dc_bios->funcs->get_soc_bb_info) { 1033 struct bp_soc_bb_info bb_info = { 0 }; 1034 1035 if (dc->ctx->dc_bios->funcs->get_soc_bb_info( 1036 dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) { 1037 if (bb_info.dram_clock_change_latency_100ns > 0) 1038 dcn3_03_soc.dram_clock_change_latency_us = 1039 bb_info.dram_clock_change_latency_100ns * 10; 1040 1041 if (bb_info.dram_sr_enter_exit_latency_100ns > 0) 1042 dcn3_03_soc.sr_enter_plus_exit_time_us = 1043 bb_info.dram_sr_enter_exit_latency_100ns * 10; 1044 1045 if (bb_info.dram_sr_exit_latency_100ns > 0) 1046 dcn3_03_soc.sr_exit_time_us = 1047 bb_info.dram_sr_exit_latency_100ns * 10; 1048 } 1049 } 1050 1051 return true; 1052 } 1053 1054 static void dcn303_resource_destruct(struct resource_pool *pool) 1055 { 1056 unsigned int i; 1057 1058 for (i = 0; i < pool->stream_enc_count; i++) { 1059 if (pool->stream_enc[i] != NULL) { 1060 if (pool->stream_enc[i]->vpg != NULL) { 1061 kfree(DCN30_VPG_FROM_VPG(pool->stream_enc[i]->vpg)); 1062 pool->stream_enc[i]->vpg = NULL; 1063 } 1064 if (pool->stream_enc[i]->afmt != NULL) { 1065 kfree(DCN30_AFMT_FROM_AFMT(pool->stream_enc[i]->afmt)); 1066 pool->stream_enc[i]->afmt = NULL; 1067 } 1068 kfree(DCN10STRENC_FROM_STRENC(pool->stream_enc[i])); 1069 pool->stream_enc[i] = NULL; 1070 } 1071 } 1072 1073 for (i = 0; i < pool->res_cap->num_dsc; i++) { 1074 if (pool->dscs[i] != NULL) 1075 dcn20_dsc_destroy(&pool->dscs[i]); 1076 } 1077 1078 if (pool->mpc != NULL) { 1079 kfree(TO_DCN20_MPC(pool->mpc)); 1080 pool->mpc = NULL; 1081 } 1082 1083 if (pool->hubbub != NULL) { 1084 kfree(pool->hubbub); 1085 pool->hubbub = NULL; 1086 } 1087 1088 for (i = 0; i < pool->pipe_count; i++) { 1089 if (pool->dpps[i] != NULL) { 1090 kfree(TO_DCN20_DPP(pool->dpps[i])); 1091 pool->dpps[i] = NULL; 1092 } 1093 1094 if (pool->hubps[i] != NULL) { 1095 kfree(TO_DCN20_HUBP(pool->hubps[i])); 1096 pool->hubps[i] = NULL; 1097 } 1098 1099 if (pool->irqs != NULL) 1100 dal_irq_service_destroy(&pool->irqs); 1101 } 1102 1103 for (i = 0; i < pool->res_cap->num_ddc; i++) { 1104 if (pool->engines[i] != NULL) 1105 dce110_engine_destroy(&pool->engines[i]); 1106 if (pool->hw_i2cs[i] != NULL) { 1107 kfree(pool->hw_i2cs[i]); 1108 pool->hw_i2cs[i] = NULL; 1109 } 1110 if (pool->sw_i2cs[i] != NULL) { 1111 kfree(pool->sw_i2cs[i]); 1112 pool->sw_i2cs[i] = NULL; 1113 } 1114 } 1115 1116 for (i = 0; i < pool->res_cap->num_opp; i++) { 1117 if (pool->opps[i] != NULL) 1118 pool->opps[i]->funcs->opp_destroy(&pool->opps[i]); 1119 } 1120 1121 for (i = 0; i < pool->res_cap->num_timing_generator; i++) { 1122 if (pool->timing_generators[i] != NULL) { 1123 kfree(DCN10TG_FROM_TG(pool->timing_generators[i])); 1124 pool->timing_generators[i] = NULL; 1125 } 1126 } 1127 1128 for (i = 0; i < pool->res_cap->num_dwb; i++) { 1129 if (pool->dwbc[i] != NULL) { 1130 kfree(TO_DCN30_DWBC(pool->dwbc[i])); 1131 pool->dwbc[i] = NULL; 1132 } 1133 if (pool->mcif_wb[i] != NULL) { 1134 kfree(TO_DCN30_MMHUBBUB(pool->mcif_wb[i])); 1135 pool->mcif_wb[i] = NULL; 1136 } 1137 } 1138 1139 for (i = 0; i < pool->audio_count; i++) { 1140 if (pool->audios[i]) 1141 dce_aud_destroy(&pool->audios[i]); 1142 } 1143 1144 for (i = 0; i < pool->clk_src_count; i++) { 1145 if (pool->clock_sources[i] != NULL) 1146 dcn20_clock_source_destroy(&pool->clock_sources[i]); 1147 } 1148 1149 if (pool->dp_clock_source != NULL) 1150 dcn20_clock_source_destroy(&pool->dp_clock_source); 1151 1152 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { 1153 if (pool->mpc_lut[i] != NULL) { 1154 dc_3dlut_func_release(pool->mpc_lut[i]); 1155 pool->mpc_lut[i] = NULL; 1156 } 1157 if (pool->mpc_shaper[i] != NULL) { 1158 dc_transfer_func_release(pool->mpc_shaper[i]); 1159 pool->mpc_shaper[i] = NULL; 1160 } 1161 } 1162 1163 for (i = 0; i < pool->pipe_count; i++) { 1164 if (pool->multiple_abms[i] != NULL) 1165 dce_abm_destroy(&pool->multiple_abms[i]); 1166 } 1167 1168 if (pool->psr != NULL) 1169 dmub_psr_destroy(&pool->psr); 1170 1171 if (pool->dccg != NULL) 1172 dcn_dccg_destroy(&pool->dccg); 1173 1174 if (pool->oem_device != NULL) 1175 dal_ddc_service_destroy(&pool->oem_device); 1176 } 1177 1178 static void dcn303_destroy_resource_pool(struct resource_pool **pool) 1179 { 1180 dcn303_resource_destruct(*pool); 1181 kfree(*pool); 1182 *pool = NULL; 1183 } 1184 1185 static void dcn303_get_optimal_dcfclk_fclk_for_uclk(unsigned int uclk_mts, 1186 unsigned int *optimal_dcfclk, 1187 unsigned int *optimal_fclk) 1188 { 1189 double bw_from_dram, bw_from_dram1, bw_from_dram2; 1190 1191 bw_from_dram1 = uclk_mts * dcn3_03_soc.num_chans * 1192 dcn3_03_soc.dram_channel_width_bytes * (dcn3_03_soc.max_avg_dram_bw_use_normal_percent / 100); 1193 bw_from_dram2 = uclk_mts * dcn3_03_soc.num_chans * 1194 dcn3_03_soc.dram_channel_width_bytes * (dcn3_03_soc.max_avg_sdp_bw_use_normal_percent / 100); 1195 1196 bw_from_dram = (bw_from_dram1 < bw_from_dram2) ? bw_from_dram1 : bw_from_dram2; 1197 1198 if (optimal_fclk) 1199 *optimal_fclk = bw_from_dram / 1200 (dcn3_03_soc.fabric_datapath_to_dcn_data_return_bytes * 1201 (dcn3_03_soc.max_avg_sdp_bw_use_normal_percent / 100)); 1202 1203 if (optimal_dcfclk) 1204 *optimal_dcfclk = bw_from_dram / 1205 (dcn3_03_soc.return_bus_width_bytes * (dcn3_03_soc.max_avg_sdp_bw_use_normal_percent / 100)); 1206 } 1207 1208 void dcn303_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) 1209 { 1210 unsigned int i, j; 1211 unsigned int num_states = 0; 1212 1213 unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0}; 1214 unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0}; 1215 unsigned int optimal_uclk_for_dcfclk_sta_targets[DC__VOLTAGE_STATES] = {0}; 1216 unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0}; 1217 1218 unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {694, 875, 1000, 1200}; 1219 unsigned int num_dcfclk_sta_targets = 4; 1220 unsigned int num_uclk_states; 1221 1222 1223 if (dc->ctx->dc_bios->vram_info.num_chans) 1224 dcn3_03_soc.num_chans = dc->ctx->dc_bios->vram_info.num_chans; 1225 1226 if (dc->ctx->dc_bios->vram_info.dram_channel_width_bytes) 1227 dcn3_03_soc.dram_channel_width_bytes = dc->ctx->dc_bios->vram_info.dram_channel_width_bytes; 1228 1229 dcn3_03_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0; 1230 dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0; 1231 1232 if (bw_params->clk_table.entries[0].memclk_mhz) { 1233 int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0, max_phyclk_mhz = 0; 1234 1235 for (i = 0; i < MAX_NUM_DPM_LVL; i++) { 1236 if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz) 1237 max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; 1238 if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz) 1239 max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz; 1240 if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz) 1241 max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz; 1242 if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz) 1243 max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz; 1244 } 1245 if (!max_dcfclk_mhz) 1246 max_dcfclk_mhz = dcn3_03_soc.clock_limits[0].dcfclk_mhz; 1247 if (!max_dispclk_mhz) 1248 max_dispclk_mhz = dcn3_03_soc.clock_limits[0].dispclk_mhz; 1249 if (!max_dppclk_mhz) 1250 max_dppclk_mhz = dcn3_03_soc.clock_limits[0].dppclk_mhz; 1251 if (!max_phyclk_mhz) 1252 max_phyclk_mhz = dcn3_03_soc.clock_limits[0].phyclk_mhz; 1253 1254 if (max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { 1255 dcfclk_sta_targets[num_dcfclk_sta_targets] = max_dcfclk_mhz; 1256 num_dcfclk_sta_targets++; 1257 } else if (max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { 1258 for (i = 0; i < num_dcfclk_sta_targets; i++) { 1259 if (dcfclk_sta_targets[i] > max_dcfclk_mhz) { 1260 dcfclk_sta_targets[i] = max_dcfclk_mhz; 1261 break; 1262 } 1263 } 1264 /* Update size of array since we "removed" duplicates */ 1265 num_dcfclk_sta_targets = i + 1; 1266 } 1267 1268 num_uclk_states = bw_params->clk_table.num_entries; 1269 1270 /* Calculate optimal dcfclk for each uclk */ 1271 for (i = 0; i < num_uclk_states; i++) { 1272 dcn303_get_optimal_dcfclk_fclk_for_uclk(bw_params->clk_table.entries[i].memclk_mhz * 16, 1273 &optimal_dcfclk_for_uclk[i], NULL); 1274 if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz) 1275 optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz; 1276 } 1277 1278 /* Calculate optimal uclk for each dcfclk sta target */ 1279 for (i = 0; i < num_dcfclk_sta_targets; i++) { 1280 for (j = 0; j < num_uclk_states; j++) { 1281 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) { 1282 optimal_uclk_for_dcfclk_sta_targets[i] = 1283 bw_params->clk_table.entries[j].memclk_mhz * 16; 1284 break; 1285 } 1286 } 1287 } 1288 1289 i = 0; 1290 j = 0; 1291 /* create the final dcfclk and uclk table */ 1292 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { 1293 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) { 1294 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; 1295 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; 1296 } else { 1297 if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) { 1298 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; 1299 dram_speed_mts[num_states++] = 1300 bw_params->clk_table.entries[j++].memclk_mhz * 16; 1301 } else { 1302 j = num_uclk_states; 1303 } 1304 } 1305 } 1306 1307 while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) { 1308 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; 1309 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; 1310 } 1311 1312 while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES && 1313 optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) { 1314 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; 1315 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16; 1316 } 1317 1318 dcn3_03_soc.num_states = num_states; 1319 for (i = 0; i < dcn3_03_soc.num_states; i++) { 1320 dcn3_03_soc.clock_limits[i].state = i; 1321 dcn3_03_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i]; 1322 dcn3_03_soc.clock_limits[i].fabricclk_mhz = dcfclk_mhz[i]; 1323 dcn3_03_soc.clock_limits[i].dram_speed_mts = dram_speed_mts[i]; 1324 1325 /* Fill all states with max values of all other clocks */ 1326 dcn3_03_soc.clock_limits[i].dispclk_mhz = max_dispclk_mhz; 1327 dcn3_03_soc.clock_limits[i].dppclk_mhz = max_dppclk_mhz; 1328 dcn3_03_soc.clock_limits[i].phyclk_mhz = max_phyclk_mhz; 1329 dcn3_03_soc.clock_limits[i].dtbclk_mhz = dcn3_03_soc.clock_limits[0].dtbclk_mhz; 1330 /* These clocks cannot come from bw_params, always fill from dcn3_03_soc[1] */ 1331 /* FCLK, PHYCLK_D18, SOCCLK, DSCCLK */ 1332 dcn3_03_soc.clock_limits[i].phyclk_d18_mhz = dcn3_03_soc.clock_limits[0].phyclk_d18_mhz; 1333 dcn3_03_soc.clock_limits[i].socclk_mhz = dcn3_03_soc.clock_limits[0].socclk_mhz; 1334 dcn3_03_soc.clock_limits[i].dscclk_mhz = dcn3_03_soc.clock_limits[0].dscclk_mhz; 1335 } 1336 /* re-init DML with updated bb */ 1337 dml_init_instance(&dc->dml, &dcn3_03_soc, &dcn3_03_ip, DML_PROJECT_DCN30); 1338 if (dc->current_state) 1339 dml_init_instance(&dc->current_state->bw_ctx.dml, &dcn3_03_soc, &dcn3_03_ip, DML_PROJECT_DCN30); 1340 } 1341 } 1342 1343 static struct resource_funcs dcn303_res_pool_funcs = { 1344 .destroy = dcn303_destroy_resource_pool, 1345 .link_enc_create = dcn303_link_encoder_create, 1346 .panel_cntl_create = dcn303_panel_cntl_create, 1347 .validate_bandwidth = dcn30_validate_bandwidth, 1348 .calculate_wm_and_dlg = dcn30_calculate_wm_and_dlg, 1349 .update_soc_for_wm_a = dcn30_update_soc_for_wm_a, 1350 .populate_dml_pipes = dcn30_populate_dml_pipes_from_context, 1351 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer, 1352 .add_stream_to_ctx = dcn30_add_stream_to_ctx, 1353 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, 1354 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 1355 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, 1356 .set_mcif_arb_params = dcn30_set_mcif_arb_params, 1357 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, 1358 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut, 1359 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut, 1360 .update_bw_bounding_box = dcn303_update_bw_bounding_box, 1361 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, 1362 }; 1363 1364 static struct dc_cap_funcs cap_funcs = { 1365 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap 1366 }; 1367 1368 static const struct bios_registers bios_regs = { 1369 NBIO_SR(BIOS_SCRATCH_3), 1370 NBIO_SR(BIOS_SCRATCH_6) 1371 }; 1372 1373 static const struct dccg_registers dccg_regs = { 1374 DCCG_REG_LIST_DCN3_03() 1375 }; 1376 1377 static const struct dccg_shift dccg_shift = { 1378 DCCG_MASK_SH_LIST_DCN3_03(__SHIFT) 1379 }; 1380 1381 static const struct dccg_mask dccg_mask = { 1382 DCCG_MASK_SH_LIST_DCN3_03(_MASK) 1383 }; 1384 1385 #define abm_regs(id)\ 1386 [id] = { ABM_DCN301_REG_LIST(id) } 1387 1388 static const struct dce_abm_registers abm_regs[] = { 1389 abm_regs(0), 1390 abm_regs(1) 1391 }; 1392 1393 static const struct dce_abm_shift abm_shift = { 1394 ABM_MASK_SH_LIST_DCN30(__SHIFT) 1395 }; 1396 1397 static const struct dce_abm_mask abm_mask = { 1398 ABM_MASK_SH_LIST_DCN30(_MASK) 1399 }; 1400 1401 static bool dcn303_resource_construct( 1402 uint8_t num_virtual_links, 1403 struct dc *dc, 1404 struct resource_pool *pool) 1405 { 1406 int i; 1407 struct dc_context *ctx = dc->ctx; 1408 struct irq_service_init_data init_data; 1409 struct ddc_service_init_data ddc_init_data; 1410 1411 ctx->dc_bios->regs = &bios_regs; 1412 1413 pool->res_cap = &res_cap_dcn303; 1414 1415 pool->funcs = &dcn303_res_pool_funcs; 1416 1417 /************************************************* 1418 * Resource + asic cap harcoding * 1419 *************************************************/ 1420 pool->underlay_pipe_index = NO_UNDERLAY_PIPE; 1421 pool->pipe_count = pool->res_cap->num_timing_generator; 1422 pool->mpcc_count = pool->res_cap->num_timing_generator; 1423 dc->caps.max_downscale_ratio = 600; 1424 dc->caps.i2c_speed_in_khz = 100; 1425 dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by derfault*/ 1426 dc->caps.max_cursor_size = 256; 1427 dc->caps.min_horizontal_blanking_period = 80; 1428 dc->caps.dmdata_alloc_size = 2048; 1429 #if defined(CONFIG_DRM_AMD_DC_DCN) 1430 dc->caps.mall_size_per_mem_channel = 4; 1431 /* total size = mall per channel * num channels * 1024 * 1024 */ 1432 dc->caps.mall_size_total = dc->caps.mall_size_per_mem_channel * 1433 dc->ctx->dc_bios->vram_info.num_chans * 1434 1024 * 1024; 1435 dc->caps.cursor_cache_size = 1436 dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8; 1437 #endif 1438 dc->caps.max_slave_planes = 1; 1439 dc->caps.post_blend_color_processing = true; 1440 dc->caps.force_dp_tps4_for_cp2520 = true; 1441 dc->caps.extended_aux_timeout_support = true; 1442 dc->caps.dmcub_support = true; 1443 1444 /* Color pipeline capabilities */ 1445 dc->caps.color.dpp.dcn_arch = 1; 1446 dc->caps.color.dpp.input_lut_shared = 0; 1447 dc->caps.color.dpp.icsc = 1; 1448 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr 1449 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; 1450 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; 1451 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1; 1452 dc->caps.color.dpp.dgam_rom_caps.pq = 1; 1453 dc->caps.color.dpp.dgam_rom_caps.hlg = 1; 1454 dc->caps.color.dpp.post_csc = 1; 1455 dc->caps.color.dpp.gamma_corr = 1; 1456 dc->caps.color.dpp.dgam_rom_for_yuv = 0; 1457 1458 dc->caps.color.dpp.hw_3d_lut = 1; 1459 dc->caps.color.dpp.ogam_ram = 1; 1460 // no OGAM ROM on DCN3 1461 dc->caps.color.dpp.ogam_rom_caps.srgb = 0; 1462 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; 1463 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; 1464 dc->caps.color.dpp.ogam_rom_caps.pq = 0; 1465 dc->caps.color.dpp.ogam_rom_caps.hlg = 0; 1466 dc->caps.color.dpp.ocsc = 0; 1467 1468 dc->caps.color.mpc.gamut_remap = 1; 1469 dc->caps.color.mpc.num_3dluts = pool->res_cap->num_mpc_3dlut; //3 1470 dc->caps.color.mpc.ogam_ram = 1; 1471 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; 1472 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; 1473 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; 1474 dc->caps.color.mpc.ogam_rom_caps.pq = 0; 1475 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 1476 dc->caps.color.mpc.ocsc = 1; 1477 1478 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 1479 dc->debug = debug_defaults_drv; 1480 else 1481 dc->debug = debug_defaults_diags; 1482 1483 // Init the vm_helper 1484 if (dc->vm_helper) 1485 vm_helper_init(dc->vm_helper, 16); 1486 1487 /************************************************* 1488 * Create resources * 1489 *************************************************/ 1490 1491 /* Clock Sources for Pixel Clock*/ 1492 pool->clock_sources[DCN303_CLK_SRC_PLL0] = 1493 dcn303_clock_source_create(ctx, ctx->dc_bios, 1494 CLOCK_SOURCE_COMBO_PHY_PLL0, 1495 &clk_src_regs[0], false); 1496 pool->clock_sources[DCN303_CLK_SRC_PLL1] = 1497 dcn303_clock_source_create(ctx, ctx->dc_bios, 1498 CLOCK_SOURCE_COMBO_PHY_PLL1, 1499 &clk_src_regs[1], false); 1500 1501 pool->clk_src_count = DCN303_CLK_SRC_TOTAL; 1502 1503 /* todo: not reuse phy_pll registers */ 1504 pool->dp_clock_source = 1505 dcn303_clock_source_create(ctx, ctx->dc_bios, 1506 CLOCK_SOURCE_ID_DP_DTO, 1507 &clk_src_regs[0], true); 1508 1509 for (i = 0; i < pool->clk_src_count; i++) { 1510 if (pool->clock_sources[i] == NULL) { 1511 dm_error("DC: failed to create clock sources!\n"); 1512 BREAK_TO_DEBUGGER(); 1513 goto create_fail; 1514 } 1515 } 1516 1517 /* DCCG */ 1518 pool->dccg = dccg30_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 1519 if (pool->dccg == NULL) { 1520 dm_error("DC: failed to create dccg!\n"); 1521 BREAK_TO_DEBUGGER(); 1522 goto create_fail; 1523 } 1524 1525 /* PP Lib and SMU interfaces */ 1526 init_soc_bounding_box(dc, pool); 1527 1528 /* DML */ 1529 dml_init_instance(&dc->dml, &dcn3_03_soc, &dcn3_03_ip, DML_PROJECT_DCN30); 1530 1531 /* IRQ */ 1532 init_data.ctx = dc->ctx; 1533 pool->irqs = dal_irq_service_dcn303_create(&init_data); 1534 if (!pool->irqs) 1535 goto create_fail; 1536 1537 /* HUBBUB */ 1538 pool->hubbub = dcn303_hubbub_create(ctx); 1539 if (pool->hubbub == NULL) { 1540 BREAK_TO_DEBUGGER(); 1541 dm_error("DC: failed to create hubbub!\n"); 1542 goto create_fail; 1543 } 1544 1545 /* HUBPs, DPPs, OPPs and TGs */ 1546 for (i = 0; i < pool->pipe_count; i++) { 1547 pool->hubps[i] = dcn303_hubp_create(ctx, i); 1548 if (pool->hubps[i] == NULL) { 1549 BREAK_TO_DEBUGGER(); 1550 dm_error("DC: failed to create hubps!\n"); 1551 goto create_fail; 1552 } 1553 1554 pool->dpps[i] = dcn303_dpp_create(ctx, i); 1555 if (pool->dpps[i] == NULL) { 1556 BREAK_TO_DEBUGGER(); 1557 dm_error("DC: failed to create dpps!\n"); 1558 goto create_fail; 1559 } 1560 } 1561 1562 for (i = 0; i < pool->res_cap->num_opp; i++) { 1563 pool->opps[i] = dcn303_opp_create(ctx, i); 1564 if (pool->opps[i] == NULL) { 1565 BREAK_TO_DEBUGGER(); 1566 dm_error("DC: failed to create output pixel processor!\n"); 1567 goto create_fail; 1568 } 1569 } 1570 1571 for (i = 0; i < pool->res_cap->num_timing_generator; i++) { 1572 pool->timing_generators[i] = dcn303_timing_generator_create(ctx, i); 1573 if (pool->timing_generators[i] == NULL) { 1574 BREAK_TO_DEBUGGER(); 1575 dm_error("DC: failed to create tg!\n"); 1576 goto create_fail; 1577 } 1578 } 1579 pool->timing_generator_count = i; 1580 1581 /* PSR */ 1582 pool->psr = dmub_psr_create(ctx); 1583 if (pool->psr == NULL) { 1584 dm_error("DC: failed to create psr!\n"); 1585 BREAK_TO_DEBUGGER(); 1586 goto create_fail; 1587 } 1588 1589 /* ABM */ 1590 for (i = 0; i < pool->res_cap->num_timing_generator; i++) { 1591 pool->multiple_abms[i] = dmub_abm_create(ctx, &abm_regs[i], &abm_shift, &abm_mask); 1592 if (pool->multiple_abms[i] == NULL) { 1593 dm_error("DC: failed to create abm for pipe %d!\n", i); 1594 BREAK_TO_DEBUGGER(); 1595 goto create_fail; 1596 } 1597 } 1598 1599 /* MPC and DSC */ 1600 pool->mpc = dcn303_mpc_create(ctx, pool->mpcc_count, pool->res_cap->num_mpc_3dlut); 1601 if (pool->mpc == NULL) { 1602 BREAK_TO_DEBUGGER(); 1603 dm_error("DC: failed to create mpc!\n"); 1604 goto create_fail; 1605 } 1606 1607 for (i = 0; i < pool->res_cap->num_dsc; i++) { 1608 pool->dscs[i] = dcn303_dsc_create(ctx, i); 1609 if (pool->dscs[i] == NULL) { 1610 BREAK_TO_DEBUGGER(); 1611 dm_error("DC: failed to create display stream compressor %d!\n", i); 1612 goto create_fail; 1613 } 1614 } 1615 1616 /* DWB and MMHUBBUB */ 1617 if (!dcn303_dwbc_create(ctx, pool)) { 1618 BREAK_TO_DEBUGGER(); 1619 dm_error("DC: failed to create dwbc!\n"); 1620 goto create_fail; 1621 } 1622 1623 if (!dcn303_mmhubbub_create(ctx, pool)) { 1624 BREAK_TO_DEBUGGER(); 1625 dm_error("DC: failed to create mcif_wb!\n"); 1626 goto create_fail; 1627 } 1628 1629 /* AUX and I2C */ 1630 for (i = 0; i < pool->res_cap->num_ddc; i++) { 1631 pool->engines[i] = dcn303_aux_engine_create(ctx, i); 1632 if (pool->engines[i] == NULL) { 1633 BREAK_TO_DEBUGGER(); 1634 dm_error("DC:failed to create aux engine!!\n"); 1635 goto create_fail; 1636 } 1637 pool->hw_i2cs[i] = dcn303_i2c_hw_create(ctx, i); 1638 if (pool->hw_i2cs[i] == NULL) { 1639 BREAK_TO_DEBUGGER(); 1640 dm_error("DC:failed to create hw i2c!!\n"); 1641 goto create_fail; 1642 } 1643 pool->sw_i2cs[i] = NULL; 1644 } 1645 1646 /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */ 1647 if (!resource_construct(num_virtual_links, dc, pool, 1648 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? 1649 &res_create_funcs : &res_create_maximus_funcs))) 1650 goto create_fail; 1651 1652 /* HW Sequencer and Plane caps */ 1653 dcn303_hw_sequencer_construct(dc); 1654 1655 dc->caps.max_planes = pool->pipe_count; 1656 1657 for (i = 0; i < dc->caps.max_planes; ++i) 1658 dc->caps.planes[i] = plane_cap; 1659 1660 dc->cap_funcs = cap_funcs; 1661 1662 if (dc->ctx->dc_bios->fw_info.oem_i2c_present) { 1663 ddc_init_data.ctx = dc->ctx; 1664 ddc_init_data.link = NULL; 1665 ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id; 1666 ddc_init_data.id.enum_id = 0; 1667 ddc_init_data.id.type = OBJECT_TYPE_GENERIC; 1668 pool->oem_device = dal_ddc_service_create(&ddc_init_data); 1669 } else { 1670 pool->oem_device = NULL; 1671 } 1672 1673 return true; 1674 1675 create_fail: 1676 1677 dcn303_resource_destruct(pool); 1678 1679 return false; 1680 } 1681 1682 struct resource_pool *dcn303_create_resource_pool(const struct dc_init_data *init_data, struct dc *dc) 1683 { 1684 struct resource_pool *pool = kzalloc(sizeof(struct resource_pool), GFP_KERNEL); 1685 1686 if (!pool) 1687 return NULL; 1688 1689 if (dcn303_resource_construct(init_data->num_virtual_links, dc, pool)) 1690 return pool; 1691 1692 BREAK_TO_DEBUGGER(); 1693 kfree(pool); 1694 return NULL; 1695 } 1696