1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright (C) 2021 Advanced Micro Devices, Inc. 4 * 5 * Authors: AMD 6 */ 7 8 #include "dcn303_init.h" 9 #include "dcn303_resource.h" 10 #include "dcn303_dccg.h" 11 #include "irq/dcn303/irq_service_dcn303.h" 12 13 #include "dcn30/dcn30_dio_link_encoder.h" 14 #include "dcn30/dcn30_dio_stream_encoder.h" 15 #include "dcn30/dcn30_dpp.h" 16 #include "dcn30/dcn30_dwb.h" 17 #include "dcn30/dcn30_hubbub.h" 18 #include "dcn30/dcn30_hubp.h" 19 #include "dcn30/dcn30_mmhubbub.h" 20 #include "dcn30/dcn30_mpc.h" 21 #include "dcn30/dcn30_opp.h" 22 #include "dcn30/dcn30_optc.h" 23 #include "dcn30/dcn30_resource.h" 24 25 #include "dcn20/dcn20_dsc.h" 26 #include "dcn20/dcn20_resource.h" 27 28 #include "dml/dcn30/dcn30_fpu.h" 29 30 #include "dcn10/dcn10_resource.h" 31 32 #include "dc_link_ddc.h" 33 34 #include "dce/dce_abm.h" 35 #include "dce/dce_audio.h" 36 #include "dce/dce_aux.h" 37 #include "dce/dce_clock_source.h" 38 #include "dce/dce_hwseq.h" 39 #include "dce/dce_i2c_hw.h" 40 #include "dce/dce_panel_cntl.h" 41 #include "dce/dmub_abm.h" 42 #include "dce/dmub_psr.h" 43 #include "clk_mgr.h" 44 45 #include "hw_sequencer_private.h" 46 #include "reg_helper.h" 47 #include "resource.h" 48 #include "vm_helper.h" 49 50 #include "sienna_cichlid_ip_offset.h" 51 #include "dcn/dcn_3_0_3_offset.h" 52 #include "dcn/dcn_3_0_3_sh_mask.h" 53 #include "dpcs/dpcs_3_0_3_offset.h" 54 #include "dpcs/dpcs_3_0_3_sh_mask.h" 55 #include "nbio/nbio_2_3_offset.h" 56 57 #include "dml/dcn303/dcn303_fpu.h" 58 59 #define DC_LOGGER_INIT(logger) 60 61 62 static const struct dc_debug_options debug_defaults_drv = { 63 .disable_dmcu = true, 64 .force_abm_enable = false, 65 .timing_trace = false, 66 .clock_trace = true, 67 .disable_pplib_clock_request = true, 68 .pipe_split_policy = MPC_SPLIT_DYNAMIC, 69 .force_single_disp_pipe_split = false, 70 .disable_dcc = DCC_ENABLE, 71 .vsr_support = true, 72 .performance_trace = false, 73 .max_downscale_src_width = 7680,/*upto 8K*/ 74 .disable_pplib_wm_range = false, 75 .scl_reset_length10 = true, 76 .sanity_checks = false, 77 .underflow_assert_delay_us = 0xFFFFFFFF, 78 .dwb_fi_phase = -1, // -1 = disable, 79 .dmub_command_table = true, 80 .exit_idle_opt_for_cursor_updates = true, 81 .disable_idle_power_optimizations = false, 82 }; 83 84 static const struct dc_debug_options debug_defaults_diags = { 85 .disable_dmcu = true, 86 .force_abm_enable = false, 87 .timing_trace = true, 88 .clock_trace = true, 89 .disable_dpp_power_gate = true, 90 .disable_hubp_power_gate = true, 91 .disable_clock_gate = true, 92 .disable_pplib_clock_request = true, 93 .disable_pplib_wm_range = true, 94 .disable_stutter = false, 95 .scl_reset_length10 = true, 96 .dwb_fi_phase = -1, // -1 = disable 97 .dmub_command_table = true, 98 .enable_tri_buf = true, 99 }; 100 101 static const struct dc_panel_config panel_config_defaults = { 102 .psr = { 103 .disable_psr = false, 104 .disallow_psrsu = false, 105 }, 106 }; 107 108 enum dcn303_clk_src_array_id { 109 DCN303_CLK_SRC_PLL0, 110 DCN303_CLK_SRC_PLL1, 111 DCN303_CLK_SRC_TOTAL 112 }; 113 114 static const struct resource_caps res_cap_dcn303 = { 115 .num_timing_generator = 2, 116 .num_opp = 2, 117 .num_video_plane = 2, 118 .num_audio = 2, 119 .num_stream_encoder = 2, 120 .num_dwb = 1, 121 .num_ddc = 2, 122 .num_vmid = 16, 123 .num_mpc_3dlut = 1, 124 .num_dsc = 2, 125 }; 126 127 static const struct dc_plane_cap plane_cap = { 128 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 129 .blends_with_above = true, 130 .blends_with_below = true, 131 .per_pixel_alpha = true, 132 .pixel_format_support = { 133 .argb8888 = true, 134 .nv12 = true, 135 .fp16 = true, 136 .p010 = true, 137 .ayuv = false, 138 }, 139 .max_upscale_factor = { 140 .argb8888 = 16000, 141 .nv12 = 16000, 142 .fp16 = 16000 143 }, 144 .max_downscale_factor = { 145 .argb8888 = 600, 146 .nv12 = 600, 147 .fp16 = 600 148 }, 149 16, 150 16 151 }; 152 153 /* NBIO */ 154 #define NBIO_BASE_INNER(seg) \ 155 NBIO_BASE__INST0_SEG ## seg 156 157 #define NBIO_BASE(seg) \ 158 NBIO_BASE_INNER(seg) 159 160 #define NBIO_SR(reg_name)\ 161 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \ 162 mm ## reg_name 163 164 /* DCN */ 165 #undef BASE_INNER 166 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg 167 168 #define BASE(seg) BASE_INNER(seg) 169 170 #define SR(reg_name)\ 171 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name 172 173 #define SF(reg_name, field_name, post_fix)\ 174 .field_name = reg_name ## __ ## field_name ## post_fix 175 176 #define SRI(reg_name, block, id)\ 177 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + mm ## block ## id ## _ ## reg_name 178 179 #define SRI2(reg_name, block, id)\ 180 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name 181 182 #define SRII(reg_name, block, id)\ 183 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 184 mm ## block ## id ## _ ## reg_name 185 186 #define DCCG_SRII(reg_name, block, id)\ 187 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 188 mm ## block ## id ## _ ## reg_name 189 190 #define VUPDATE_SRII(reg_name, block, id)\ 191 .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \ 192 mm ## reg_name ## _ ## block ## id 193 194 #define SRII_DWB(reg_name, temp_name, block, id)\ 195 .reg_name[id] = BASE(mm ## block ## id ## _ ## temp_name ## _BASE_IDX) + \ 196 mm ## block ## id ## _ ## temp_name 197 198 #define SRII_MPC_RMU(reg_name, block, id)\ 199 .RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 200 mm ## block ## id ## _ ## reg_name 201 202 static const struct dcn_hubbub_registers hubbub_reg = { 203 HUBBUB_REG_LIST_DCN30(0) 204 }; 205 206 static const struct dcn_hubbub_shift hubbub_shift = { 207 HUBBUB_MASK_SH_LIST_DCN30(__SHIFT) 208 }; 209 210 static const struct dcn_hubbub_mask hubbub_mask = { 211 HUBBUB_MASK_SH_LIST_DCN30(_MASK) 212 }; 213 214 #define vmid_regs(id)\ 215 [id] = { DCN20_VMID_REG_LIST(id) } 216 217 static const struct dcn_vmid_registers vmid_regs[] = { 218 vmid_regs(0), 219 vmid_regs(1), 220 vmid_regs(2), 221 vmid_regs(3), 222 vmid_regs(4), 223 vmid_regs(5), 224 vmid_regs(6), 225 vmid_regs(7), 226 vmid_regs(8), 227 vmid_regs(9), 228 vmid_regs(10), 229 vmid_regs(11), 230 vmid_regs(12), 231 vmid_regs(13), 232 vmid_regs(14), 233 vmid_regs(15) 234 }; 235 236 static const struct dcn20_vmid_shift vmid_shifts = { 237 DCN20_VMID_MASK_SH_LIST(__SHIFT) 238 }; 239 240 static const struct dcn20_vmid_mask vmid_masks = { 241 DCN20_VMID_MASK_SH_LIST(_MASK) 242 }; 243 244 static struct hubbub *dcn303_hubbub_create(struct dc_context *ctx) 245 { 246 int i; 247 248 struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub), GFP_KERNEL); 249 250 if (!hubbub3) 251 return NULL; 252 253 hubbub3_construct(hubbub3, ctx, &hubbub_reg, &hubbub_shift, &hubbub_mask); 254 255 for (i = 0; i < res_cap_dcn303.num_vmid; i++) { 256 struct dcn20_vmid *vmid = &hubbub3->vmid[i]; 257 258 vmid->ctx = ctx; 259 260 vmid->regs = &vmid_regs[i]; 261 vmid->shifts = &vmid_shifts; 262 vmid->masks = &vmid_masks; 263 } 264 265 return &hubbub3->base; 266 } 267 268 #define vpg_regs(id)\ 269 [id] = { VPG_DCN3_REG_LIST(id) } 270 271 static const struct dcn30_vpg_registers vpg_regs[] = { 272 vpg_regs(0), 273 vpg_regs(1), 274 vpg_regs(2) 275 }; 276 277 static const struct dcn30_vpg_shift vpg_shift = { 278 DCN3_VPG_MASK_SH_LIST(__SHIFT) 279 }; 280 281 static const struct dcn30_vpg_mask vpg_mask = { 282 DCN3_VPG_MASK_SH_LIST(_MASK) 283 }; 284 285 static struct vpg *dcn303_vpg_create(struct dc_context *ctx, uint32_t inst) 286 { 287 struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL); 288 289 if (!vpg3) 290 return NULL; 291 292 vpg3_construct(vpg3, ctx, inst, &vpg_regs[inst], &vpg_shift, &vpg_mask); 293 294 return &vpg3->base; 295 } 296 297 #define afmt_regs(id)\ 298 [id] = { AFMT_DCN3_REG_LIST(id) } 299 300 static const struct dcn30_afmt_registers afmt_regs[] = { 301 afmt_regs(0), 302 afmt_regs(1), 303 afmt_regs(2) 304 }; 305 306 static const struct dcn30_afmt_shift afmt_shift = { 307 DCN3_AFMT_MASK_SH_LIST(__SHIFT) 308 }; 309 310 static const struct dcn30_afmt_mask afmt_mask = { 311 DCN3_AFMT_MASK_SH_LIST(_MASK) 312 }; 313 314 static struct afmt *dcn303_afmt_create(struct dc_context *ctx, uint32_t inst) 315 { 316 struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL); 317 318 if (!afmt3) 319 return NULL; 320 321 afmt3_construct(afmt3, ctx, inst, &afmt_regs[inst], &afmt_shift, &afmt_mask); 322 323 return &afmt3->base; 324 } 325 326 #define audio_regs(id)\ 327 [id] = { AUD_COMMON_REG_LIST(id) } 328 329 static const struct dce_audio_registers audio_regs[] = { 330 audio_regs(0), 331 audio_regs(1), 332 audio_regs(2), 333 audio_regs(3), 334 audio_regs(4), 335 audio_regs(5), 336 audio_regs(6) 337 }; 338 339 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 340 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 341 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 342 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 343 344 static const struct dce_audio_shift audio_shift = { 345 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 346 }; 347 348 static const struct dce_audio_mask audio_mask = { 349 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 350 }; 351 352 static struct audio *dcn303_create_audio(struct dc_context *ctx, unsigned int inst) 353 { 354 return dce_audio_create(ctx, inst, &audio_regs[inst], &audio_shift, &audio_mask); 355 } 356 357 #define stream_enc_regs(id)\ 358 [id] = { SE_DCN3_REG_LIST(id) } 359 360 static const struct dcn10_stream_enc_registers stream_enc_regs[] = { 361 stream_enc_regs(0), 362 stream_enc_regs(1) 363 }; 364 365 static const struct dcn10_stream_encoder_shift se_shift = { 366 SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 367 }; 368 369 static const struct dcn10_stream_encoder_mask se_mask = { 370 SE_COMMON_MASK_SH_LIST_DCN30(_MASK) 371 }; 372 373 static struct stream_encoder *dcn303_stream_encoder_create(enum engine_id eng_id, struct dc_context *ctx) 374 { 375 struct dcn10_stream_encoder *enc1; 376 struct vpg *vpg; 377 struct afmt *afmt; 378 int vpg_inst; 379 int afmt_inst; 380 381 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */ 382 if (eng_id <= ENGINE_ID_DIGB) { 383 vpg_inst = eng_id; 384 afmt_inst = eng_id; 385 } else 386 return NULL; 387 388 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 389 vpg = dcn303_vpg_create(ctx, vpg_inst); 390 afmt = dcn303_afmt_create(ctx, afmt_inst); 391 392 if (!enc1 || !vpg || !afmt) { 393 kfree(enc1); 394 kfree(vpg); 395 kfree(afmt); 396 return NULL; 397 } 398 399 dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id, vpg, afmt, &stream_enc_regs[eng_id], 400 &se_shift, &se_mask); 401 402 return &enc1->base; 403 } 404 405 #define clk_src_regs(index, pllid)\ 406 [index] = { CS_COMMON_REG_LIST_DCN3_03(index, pllid) } 407 408 static const struct dce110_clk_src_regs clk_src_regs[] = { 409 clk_src_regs(0, A), 410 clk_src_regs(1, B) 411 }; 412 413 static const struct dce110_clk_src_shift cs_shift = { 414 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 415 }; 416 417 static const struct dce110_clk_src_mask cs_mask = { 418 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 419 }; 420 421 static struct clock_source *dcn303_clock_source_create(struct dc_context *ctx, struct dc_bios *bios, 422 enum clock_source_id id, const struct dce110_clk_src_regs *regs, bool dp_clk_src) 423 { 424 struct dce110_clk_src *clk_src = kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 425 426 if (!clk_src) 427 return NULL; 428 429 if (dcn3_clk_src_construct(clk_src, ctx, bios, id, regs, &cs_shift, &cs_mask)) { 430 clk_src->base.dp_clk_src = dp_clk_src; 431 return &clk_src->base; 432 } 433 434 BREAK_TO_DEBUGGER(); 435 return NULL; 436 } 437 438 static const struct dce_hwseq_registers hwseq_reg = { 439 HWSEQ_DCN303_REG_LIST() 440 }; 441 442 static const struct dce_hwseq_shift hwseq_shift = { 443 HWSEQ_DCN303_MASK_SH_LIST(__SHIFT) 444 }; 445 446 static const struct dce_hwseq_mask hwseq_mask = { 447 HWSEQ_DCN303_MASK_SH_LIST(_MASK) 448 }; 449 450 static struct dce_hwseq *dcn303_hwseq_create(struct dc_context *ctx) 451 { 452 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 453 454 if (hws) { 455 hws->ctx = ctx; 456 hws->regs = &hwseq_reg; 457 hws->shifts = &hwseq_shift; 458 hws->masks = &hwseq_mask; 459 } 460 return hws; 461 } 462 463 #define hubp_regs(id)\ 464 [id] = { HUBP_REG_LIST_DCN30(id) } 465 466 static const struct dcn_hubp2_registers hubp_regs[] = { 467 hubp_regs(0), 468 hubp_regs(1) 469 }; 470 471 static const struct dcn_hubp2_shift hubp_shift = { 472 HUBP_MASK_SH_LIST_DCN30(__SHIFT) 473 }; 474 475 static const struct dcn_hubp2_mask hubp_mask = { 476 HUBP_MASK_SH_LIST_DCN30(_MASK) 477 }; 478 479 static struct hubp *dcn303_hubp_create(struct dc_context *ctx, uint32_t inst) 480 { 481 struct dcn20_hubp *hubp2 = kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL); 482 483 if (!hubp2) 484 return NULL; 485 486 if (hubp3_construct(hubp2, ctx, inst, &hubp_regs[inst], &hubp_shift, &hubp_mask)) 487 return &hubp2->base; 488 489 BREAK_TO_DEBUGGER(); 490 kfree(hubp2); 491 return NULL; 492 } 493 494 #define dpp_regs(id)\ 495 [id] = { DPP_REG_LIST_DCN30(id) } 496 497 static const struct dcn3_dpp_registers dpp_regs[] = { 498 dpp_regs(0), 499 dpp_regs(1) 500 }; 501 502 static const struct dcn3_dpp_shift tf_shift = { 503 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT) 504 }; 505 506 static const struct dcn3_dpp_mask tf_mask = { 507 DPP_REG_LIST_SH_MASK_DCN30(_MASK) 508 }; 509 510 static struct dpp *dcn303_dpp_create(struct dc_context *ctx, uint32_t inst) 511 { 512 struct dcn3_dpp *dpp = kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL); 513 514 if (!dpp) 515 return NULL; 516 517 if (dpp3_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, &tf_mask)) 518 return &dpp->base; 519 520 BREAK_TO_DEBUGGER(); 521 kfree(dpp); 522 return NULL; 523 } 524 525 #define opp_regs(id)\ 526 [id] = { OPP_REG_LIST_DCN30(id) } 527 528 static const struct dcn20_opp_registers opp_regs[] = { 529 opp_regs(0), 530 opp_regs(1) 531 }; 532 533 static const struct dcn20_opp_shift opp_shift = { 534 OPP_MASK_SH_LIST_DCN20(__SHIFT) 535 }; 536 537 static const struct dcn20_opp_mask opp_mask = { 538 OPP_MASK_SH_LIST_DCN20(_MASK) 539 }; 540 541 static struct output_pixel_processor *dcn303_opp_create(struct dc_context *ctx, uint32_t inst) 542 { 543 struct dcn20_opp *opp = kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); 544 545 if (!opp) { 546 BREAK_TO_DEBUGGER(); 547 return NULL; 548 } 549 550 dcn20_opp_construct(opp, ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask); 551 return &opp->base; 552 } 553 554 #define optc_regs(id)\ 555 [id] = { OPTC_COMMON_REG_LIST_DCN3_0(id) } 556 557 static const struct dcn_optc_registers optc_regs[] = { 558 optc_regs(0), 559 optc_regs(1) 560 }; 561 562 static const struct dcn_optc_shift optc_shift = { 563 OPTC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 564 }; 565 566 static const struct dcn_optc_mask optc_mask = { 567 OPTC_COMMON_MASK_SH_LIST_DCN30(_MASK) 568 }; 569 570 static struct timing_generator *dcn303_timing_generator_create(struct dc_context *ctx, uint32_t instance) 571 { 572 struct optc *tgn10 = kzalloc(sizeof(struct optc), GFP_KERNEL); 573 574 if (!tgn10) 575 return NULL; 576 577 tgn10->base.inst = instance; 578 tgn10->base.ctx = ctx; 579 580 tgn10->tg_regs = &optc_regs[instance]; 581 tgn10->tg_shift = &optc_shift; 582 tgn10->tg_mask = &optc_mask; 583 584 dcn30_timing_generator_init(tgn10); 585 586 return &tgn10->base; 587 } 588 589 static const struct dcn30_mpc_registers mpc_regs = { 590 MPC_REG_LIST_DCN3_0(0), 591 MPC_REG_LIST_DCN3_0(1), 592 MPC_OUT_MUX_REG_LIST_DCN3_0(0), 593 MPC_OUT_MUX_REG_LIST_DCN3_0(1), 594 MPC_RMU_GLOBAL_REG_LIST_DCN3AG, 595 MPC_RMU_REG_LIST_DCN3AG(0), 596 MPC_DWB_MUX_REG_LIST_DCN3_0(0), 597 }; 598 599 static const struct dcn30_mpc_shift mpc_shift = { 600 MPC_COMMON_MASK_SH_LIST_DCN303(__SHIFT) 601 }; 602 603 static const struct dcn30_mpc_mask mpc_mask = { 604 MPC_COMMON_MASK_SH_LIST_DCN303(_MASK) 605 }; 606 607 static struct mpc *dcn303_mpc_create(struct dc_context *ctx, int num_mpcc, int num_rmu) 608 { 609 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), GFP_KERNEL); 610 611 if (!mpc30) 612 return NULL; 613 614 dcn30_mpc_construct(mpc30, ctx, &mpc_regs, &mpc_shift, &mpc_mask, num_mpcc, num_rmu); 615 616 return &mpc30->base; 617 } 618 619 #define dsc_regsDCN20(id)\ 620 [id] = { DSC_REG_LIST_DCN20(id) } 621 622 static const struct dcn20_dsc_registers dsc_regs[] = { 623 dsc_regsDCN20(0), 624 dsc_regsDCN20(1) 625 }; 626 627 static const struct dcn20_dsc_shift dsc_shift = { 628 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) 629 }; 630 631 static const struct dcn20_dsc_mask dsc_mask = { 632 DSC_REG_LIST_SH_MASK_DCN20(_MASK) 633 }; 634 635 static struct display_stream_compressor *dcn303_dsc_create(struct dc_context *ctx, uint32_t inst) 636 { 637 struct dcn20_dsc *dsc = kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); 638 639 if (!dsc) { 640 BREAK_TO_DEBUGGER(); 641 return NULL; 642 } 643 644 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 645 return &dsc->base; 646 } 647 648 #define dwbc_regs_dcn3(id)\ 649 [id] = { DWBC_COMMON_REG_LIST_DCN30(id) } 650 651 static const struct dcn30_dwbc_registers dwbc30_regs[] = { 652 dwbc_regs_dcn3(0) 653 }; 654 655 static const struct dcn30_dwbc_shift dwbc30_shift = { 656 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 657 }; 658 659 static const struct dcn30_dwbc_mask dwbc30_mask = { 660 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK) 661 }; 662 663 static bool dcn303_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) 664 { 665 int i; 666 uint32_t pipe_count = pool->res_cap->num_dwb; 667 668 for (i = 0; i < pipe_count; i++) { 669 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), GFP_KERNEL); 670 671 if (!dwbc30) { 672 dm_error("DC: failed to create dwbc30!\n"); 673 return false; 674 } 675 676 dcn30_dwbc_construct(dwbc30, ctx, &dwbc30_regs[i], &dwbc30_shift, &dwbc30_mask, i); 677 678 pool->dwbc[i] = &dwbc30->base; 679 } 680 return true; 681 } 682 683 #define mcif_wb_regs_dcn3(id)\ 684 [id] = { MCIF_WB_COMMON_REG_LIST_DCN30(id) } 685 686 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = { 687 mcif_wb_regs_dcn3(0) 688 }; 689 690 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = { 691 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 692 }; 693 694 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { 695 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK) 696 }; 697 698 static bool dcn303_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) 699 { 700 int i; 701 uint32_t pipe_count = pool->res_cap->num_dwb; 702 703 for (i = 0; i < pipe_count; i++) { 704 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), GFP_KERNEL); 705 706 if (!mcif_wb30) { 707 dm_error("DC: failed to create mcif_wb30!\n"); 708 return false; 709 } 710 711 dcn30_mmhubbub_construct(mcif_wb30, ctx, &mcif_wb30_regs[i], &mcif_wb30_shift, &mcif_wb30_mask, i); 712 713 pool->mcif_wb[i] = &mcif_wb30->base; 714 } 715 return true; 716 } 717 718 #define aux_engine_regs(id)\ 719 [id] = {\ 720 AUX_COMMON_REG_LIST0(id), \ 721 .AUXN_IMPCAL = 0, \ 722 .AUXP_IMPCAL = 0, \ 723 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \ 724 } 725 726 static const struct dce110_aux_registers aux_engine_regs[] = { 727 aux_engine_regs(0), 728 aux_engine_regs(1) 729 }; 730 731 static const struct dce110_aux_registers_shift aux_shift = { 732 DCN_AUX_MASK_SH_LIST(__SHIFT) 733 }; 734 735 static const struct dce110_aux_registers_mask aux_mask = { 736 DCN_AUX_MASK_SH_LIST(_MASK) 737 }; 738 739 static struct dce_aux *dcn303_aux_engine_create(struct dc_context *ctx, uint32_t inst) 740 { 741 struct aux_engine_dce110 *aux_engine = kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 742 743 if (!aux_engine) 744 return NULL; 745 746 dce110_aux_engine_construct(aux_engine, ctx, inst, SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 747 &aux_engine_regs[inst], &aux_mask, &aux_shift, ctx->dc->caps.extended_aux_timeout_support); 748 749 return &aux_engine->base; 750 } 751 752 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 753 754 static const struct dce_i2c_registers i2c_hw_regs[] = { 755 i2c_inst_regs(1), 756 i2c_inst_regs(2) 757 }; 758 759 static const struct dce_i2c_shift i2c_shifts = { 760 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT) 761 }; 762 763 static const struct dce_i2c_mask i2c_masks = { 764 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK) 765 }; 766 767 static struct dce_i2c_hw *dcn303_i2c_hw_create(struct dc_context *ctx, uint32_t inst) 768 { 769 struct dce_i2c_hw *dce_i2c_hw = kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 770 771 if (!dce_i2c_hw) 772 return NULL; 773 774 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 775 776 return dce_i2c_hw; 777 } 778 779 static const struct encoder_feature_support link_enc_feature = { 780 .max_hdmi_deep_color = COLOR_DEPTH_121212, 781 .max_hdmi_pixel_clock = 600000, 782 .hdmi_ycbcr420_supported = true, 783 .dp_ycbcr420_supported = true, 784 .fec_supported = true, 785 .flags.bits.IS_HBR2_CAPABLE = true, 786 .flags.bits.IS_HBR3_CAPABLE = true, 787 .flags.bits.IS_TPS3_CAPABLE = true, 788 .flags.bits.IS_TPS4_CAPABLE = true 789 }; 790 791 #define link_regs(id, phyid)\ 792 [id] = {\ 793 LE_DCN3_REG_LIST(id), \ 794 UNIPHY_DCN2_REG_LIST(phyid), \ 795 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \ 796 } 797 798 static const struct dcn10_link_enc_registers link_enc_regs[] = { 799 link_regs(0, A), 800 link_regs(1, B) 801 }; 802 803 static const struct dcn10_link_enc_shift le_shift = { 804 LINK_ENCODER_MASK_SH_LIST_DCN30(__SHIFT), 805 DPCS_DCN2_MASK_SH_LIST(__SHIFT) 806 }; 807 808 static const struct dcn10_link_enc_mask le_mask = { 809 LINK_ENCODER_MASK_SH_LIST_DCN30(_MASK), 810 DPCS_DCN2_MASK_SH_LIST(_MASK) 811 }; 812 813 #define aux_regs(id)\ 814 [id] = { DCN2_AUX_REG_LIST(id) } 815 816 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { 817 aux_regs(0), 818 aux_regs(1) 819 }; 820 821 #define hpd_regs(id)\ 822 [id] = { HPD_REG_LIST(id) } 823 824 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { 825 hpd_regs(0), 826 hpd_regs(1) 827 }; 828 829 static struct link_encoder *dcn303_link_encoder_create( 830 struct dc_context *ctx, 831 const struct encoder_init_data *enc_init_data) 832 { 833 struct dcn20_link_encoder *enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 834 835 if (!enc20) 836 return NULL; 837 838 dcn30_link_encoder_construct(enc20, enc_init_data, &link_enc_feature, 839 &link_enc_regs[enc_init_data->transmitter], &link_enc_aux_regs[enc_init_data->channel - 1], 840 &link_enc_hpd_regs[enc_init_data->hpd_source], &le_shift, &le_mask); 841 842 return &enc20->enc10.base; 843 } 844 845 static const struct dce_panel_cntl_registers panel_cntl_regs[] = { 846 { DCN_PANEL_CNTL_REG_LIST() } 847 }; 848 849 static const struct dce_panel_cntl_shift panel_cntl_shift = { 850 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT) 851 }; 852 853 static const struct dce_panel_cntl_mask panel_cntl_mask = { 854 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK) 855 }; 856 857 static struct panel_cntl *dcn303_panel_cntl_create(const struct panel_cntl_init_data *init_data) 858 { 859 struct dce_panel_cntl *panel_cntl = kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL); 860 861 if (!panel_cntl) 862 return NULL; 863 864 dce_panel_cntl_construct(panel_cntl, init_data, &panel_cntl_regs[init_data->inst], 865 &panel_cntl_shift, &panel_cntl_mask); 866 867 return &panel_cntl->base; 868 } 869 870 static void read_dce_straps(struct dc_context *ctx, struct resource_straps *straps) 871 { 872 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX), 873 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 874 } 875 876 static const struct resource_create_funcs res_create_funcs = { 877 .read_dce_straps = read_dce_straps, 878 .create_audio = dcn303_create_audio, 879 .create_stream_encoder = dcn303_stream_encoder_create, 880 .create_hwseq = dcn303_hwseq_create, 881 }; 882 883 static const struct resource_create_funcs res_create_maximus_funcs = { 884 .read_dce_straps = NULL, 885 .create_audio = NULL, 886 .create_stream_encoder = NULL, 887 .create_hwseq = dcn303_hwseq_create, 888 }; 889 890 static bool is_soc_bounding_box_valid(struct dc *dc) 891 { 892 uint32_t hw_internal_rev = dc->ctx->asic_id.hw_internal_rev; 893 894 if (ASICREV_IS_BEIGE_GOBY_P(hw_internal_rev)) 895 return true; 896 897 return false; 898 } 899 900 static bool init_soc_bounding_box(struct dc *dc, struct resource_pool *pool) 901 { 902 struct _vcs_dpi_soc_bounding_box_st *loaded_bb = &dcn3_03_soc; 903 struct _vcs_dpi_ip_params_st *loaded_ip = &dcn3_03_ip; 904 905 DC_LOGGER_INIT(dc->ctx->logger); 906 907 if (!is_soc_bounding_box_valid(dc)) { 908 DC_LOG_ERROR("%s: not valid soc bounding box/n", __func__); 909 return false; 910 } 911 912 loaded_ip->max_num_otg = pool->pipe_count; 913 loaded_ip->max_num_dpp = pool->pipe_count; 914 loaded_ip->clamp_min_dcfclk = dc->config.clamp_min_dcfclk; 915 DC_FP_START(); 916 dcn20_patch_bounding_box(dc, loaded_bb); 917 DC_FP_END(); 918 919 if (dc->ctx->dc_bios->funcs->get_soc_bb_info) { 920 struct bp_soc_bb_info bb_info = { 0 }; 921 922 if (dc->ctx->dc_bios->funcs->get_soc_bb_info( 923 dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) { 924 DC_FP_START(); 925 dcn303_fpu_init_soc_bounding_box(bb_info); 926 DC_FP_END(); 927 } 928 } 929 930 return true; 931 } 932 933 static void dcn303_resource_destruct(struct resource_pool *pool) 934 { 935 unsigned int i; 936 937 for (i = 0; i < pool->stream_enc_count; i++) { 938 if (pool->stream_enc[i] != NULL) { 939 if (pool->stream_enc[i]->vpg != NULL) { 940 kfree(DCN30_VPG_FROM_VPG(pool->stream_enc[i]->vpg)); 941 pool->stream_enc[i]->vpg = NULL; 942 } 943 if (pool->stream_enc[i]->afmt != NULL) { 944 kfree(DCN30_AFMT_FROM_AFMT(pool->stream_enc[i]->afmt)); 945 pool->stream_enc[i]->afmt = NULL; 946 } 947 kfree(DCN10STRENC_FROM_STRENC(pool->stream_enc[i])); 948 pool->stream_enc[i] = NULL; 949 } 950 } 951 952 for (i = 0; i < pool->res_cap->num_dsc; i++) { 953 if (pool->dscs[i] != NULL) 954 dcn20_dsc_destroy(&pool->dscs[i]); 955 } 956 957 if (pool->mpc != NULL) { 958 kfree(TO_DCN20_MPC(pool->mpc)); 959 pool->mpc = NULL; 960 } 961 962 if (pool->hubbub != NULL) { 963 kfree(pool->hubbub); 964 pool->hubbub = NULL; 965 } 966 967 for (i = 0; i < pool->pipe_count; i++) { 968 if (pool->dpps[i] != NULL) { 969 kfree(TO_DCN20_DPP(pool->dpps[i])); 970 pool->dpps[i] = NULL; 971 } 972 973 if (pool->hubps[i] != NULL) { 974 kfree(TO_DCN20_HUBP(pool->hubps[i])); 975 pool->hubps[i] = NULL; 976 } 977 978 if (pool->irqs != NULL) 979 dal_irq_service_destroy(&pool->irqs); 980 } 981 982 for (i = 0; i < pool->res_cap->num_ddc; i++) { 983 if (pool->engines[i] != NULL) 984 dce110_engine_destroy(&pool->engines[i]); 985 if (pool->hw_i2cs[i] != NULL) { 986 kfree(pool->hw_i2cs[i]); 987 pool->hw_i2cs[i] = NULL; 988 } 989 if (pool->sw_i2cs[i] != NULL) { 990 kfree(pool->sw_i2cs[i]); 991 pool->sw_i2cs[i] = NULL; 992 } 993 } 994 995 for (i = 0; i < pool->res_cap->num_opp; i++) { 996 if (pool->opps[i] != NULL) 997 pool->opps[i]->funcs->opp_destroy(&pool->opps[i]); 998 } 999 1000 for (i = 0; i < pool->res_cap->num_timing_generator; i++) { 1001 if (pool->timing_generators[i] != NULL) { 1002 kfree(DCN10TG_FROM_TG(pool->timing_generators[i])); 1003 pool->timing_generators[i] = NULL; 1004 } 1005 } 1006 1007 for (i = 0; i < pool->res_cap->num_dwb; i++) { 1008 if (pool->dwbc[i] != NULL) { 1009 kfree(TO_DCN30_DWBC(pool->dwbc[i])); 1010 pool->dwbc[i] = NULL; 1011 } 1012 if (pool->mcif_wb[i] != NULL) { 1013 kfree(TO_DCN30_MMHUBBUB(pool->mcif_wb[i])); 1014 pool->mcif_wb[i] = NULL; 1015 } 1016 } 1017 1018 for (i = 0; i < pool->audio_count; i++) { 1019 if (pool->audios[i]) 1020 dce_aud_destroy(&pool->audios[i]); 1021 } 1022 1023 for (i = 0; i < pool->clk_src_count; i++) { 1024 if (pool->clock_sources[i] != NULL) 1025 dcn20_clock_source_destroy(&pool->clock_sources[i]); 1026 } 1027 1028 if (pool->dp_clock_source != NULL) 1029 dcn20_clock_source_destroy(&pool->dp_clock_source); 1030 1031 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { 1032 if (pool->mpc_lut[i] != NULL) { 1033 dc_3dlut_func_release(pool->mpc_lut[i]); 1034 pool->mpc_lut[i] = NULL; 1035 } 1036 if (pool->mpc_shaper[i] != NULL) { 1037 dc_transfer_func_release(pool->mpc_shaper[i]); 1038 pool->mpc_shaper[i] = NULL; 1039 } 1040 } 1041 1042 for (i = 0; i < pool->pipe_count; i++) { 1043 if (pool->multiple_abms[i] != NULL) 1044 dce_abm_destroy(&pool->multiple_abms[i]); 1045 } 1046 1047 if (pool->psr != NULL) 1048 dmub_psr_destroy(&pool->psr); 1049 1050 if (pool->dccg != NULL) 1051 dcn_dccg_destroy(&pool->dccg); 1052 1053 if (pool->oem_device != NULL) 1054 dal_ddc_service_destroy(&pool->oem_device); 1055 } 1056 1057 static void dcn303_destroy_resource_pool(struct resource_pool **pool) 1058 { 1059 dcn303_resource_destruct(*pool); 1060 kfree(*pool); 1061 *pool = NULL; 1062 } 1063 1064 static void dcn303_get_panel_config_defaults(struct dc_panel_config *panel_config) 1065 { 1066 *panel_config = panel_config_defaults; 1067 } 1068 1069 void dcn303_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) 1070 { 1071 DC_FP_START(); 1072 dcn303_fpu_update_bw_bounding_box(dc, bw_params); 1073 DC_FP_END(); 1074 } 1075 1076 static struct resource_funcs dcn303_res_pool_funcs = { 1077 .destroy = dcn303_destroy_resource_pool, 1078 .link_enc_create = dcn303_link_encoder_create, 1079 .panel_cntl_create = dcn303_panel_cntl_create, 1080 .validate_bandwidth = dcn30_validate_bandwidth, 1081 .calculate_wm_and_dlg = dcn30_calculate_wm_and_dlg, 1082 .update_soc_for_wm_a = dcn30_update_soc_for_wm_a, 1083 .populate_dml_pipes = dcn30_populate_dml_pipes_from_context, 1084 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer, 1085 .add_stream_to_ctx = dcn30_add_stream_to_ctx, 1086 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, 1087 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 1088 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, 1089 .set_mcif_arb_params = dcn30_set_mcif_arb_params, 1090 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, 1091 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut, 1092 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut, 1093 .update_bw_bounding_box = dcn303_update_bw_bounding_box, 1094 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, 1095 .get_panel_config_defaults = dcn303_get_panel_config_defaults, 1096 }; 1097 1098 static struct dc_cap_funcs cap_funcs = { 1099 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap 1100 }; 1101 1102 static const struct bios_registers bios_regs = { 1103 NBIO_SR(BIOS_SCRATCH_3), 1104 NBIO_SR(BIOS_SCRATCH_6) 1105 }; 1106 1107 static const struct dccg_registers dccg_regs = { 1108 DCCG_REG_LIST_DCN3_03() 1109 }; 1110 1111 static const struct dccg_shift dccg_shift = { 1112 DCCG_MASK_SH_LIST_DCN3_03(__SHIFT) 1113 }; 1114 1115 static const struct dccg_mask dccg_mask = { 1116 DCCG_MASK_SH_LIST_DCN3_03(_MASK) 1117 }; 1118 1119 #define abm_regs(id)\ 1120 [id] = { ABM_DCN302_REG_LIST(id) } 1121 1122 static const struct dce_abm_registers abm_regs[] = { 1123 abm_regs(0), 1124 abm_regs(1) 1125 }; 1126 1127 static const struct dce_abm_shift abm_shift = { 1128 ABM_MASK_SH_LIST_DCN30(__SHIFT) 1129 }; 1130 1131 static const struct dce_abm_mask abm_mask = { 1132 ABM_MASK_SH_LIST_DCN30(_MASK) 1133 }; 1134 1135 static bool dcn303_resource_construct( 1136 uint8_t num_virtual_links, 1137 struct dc *dc, 1138 struct resource_pool *pool) 1139 { 1140 int i; 1141 struct dc_context *ctx = dc->ctx; 1142 struct irq_service_init_data init_data; 1143 struct ddc_service_init_data ddc_init_data; 1144 1145 ctx->dc_bios->regs = &bios_regs; 1146 1147 pool->res_cap = &res_cap_dcn303; 1148 1149 pool->funcs = &dcn303_res_pool_funcs; 1150 1151 /************************************************* 1152 * Resource + asic cap harcoding * 1153 *************************************************/ 1154 pool->underlay_pipe_index = NO_UNDERLAY_PIPE; 1155 pool->pipe_count = pool->res_cap->num_timing_generator; 1156 pool->mpcc_count = pool->res_cap->num_timing_generator; 1157 dc->caps.max_downscale_ratio = 600; 1158 dc->caps.i2c_speed_in_khz = 100; 1159 dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by derfault*/ 1160 dc->caps.max_cursor_size = 256; 1161 dc->caps.min_horizontal_blanking_period = 80; 1162 dc->caps.dmdata_alloc_size = 2048; 1163 #if defined(CONFIG_DRM_AMD_DC_DCN) 1164 dc->caps.mall_size_per_mem_channel = 4; 1165 /* total size = mall per channel * num channels * 1024 * 1024 */ 1166 dc->caps.mall_size_total = dc->caps.mall_size_per_mem_channel * 1167 dc->ctx->dc_bios->vram_info.num_chans * 1168 1024 * 1024; 1169 dc->caps.cursor_cache_size = 1170 dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8; 1171 #endif 1172 dc->caps.max_slave_planes = 1; 1173 dc->caps.post_blend_color_processing = true; 1174 dc->caps.force_dp_tps4_for_cp2520 = true; 1175 dc->caps.extended_aux_timeout_support = true; 1176 dc->caps.dmcub_support = true; 1177 1178 /* Color pipeline capabilities */ 1179 dc->caps.color.dpp.dcn_arch = 1; 1180 dc->caps.color.dpp.input_lut_shared = 0; 1181 dc->caps.color.dpp.icsc = 1; 1182 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr 1183 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; 1184 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; 1185 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1; 1186 dc->caps.color.dpp.dgam_rom_caps.pq = 1; 1187 dc->caps.color.dpp.dgam_rom_caps.hlg = 1; 1188 dc->caps.color.dpp.post_csc = 1; 1189 dc->caps.color.dpp.gamma_corr = 1; 1190 dc->caps.color.dpp.dgam_rom_for_yuv = 0; 1191 1192 dc->caps.color.dpp.hw_3d_lut = 1; 1193 dc->caps.color.dpp.ogam_ram = 1; 1194 // no OGAM ROM on DCN3 1195 dc->caps.color.dpp.ogam_rom_caps.srgb = 0; 1196 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; 1197 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; 1198 dc->caps.color.dpp.ogam_rom_caps.pq = 0; 1199 dc->caps.color.dpp.ogam_rom_caps.hlg = 0; 1200 dc->caps.color.dpp.ocsc = 0; 1201 1202 dc->caps.color.mpc.gamut_remap = 1; 1203 dc->caps.color.mpc.num_3dluts = pool->res_cap->num_mpc_3dlut; //3 1204 dc->caps.color.mpc.ogam_ram = 1; 1205 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; 1206 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; 1207 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; 1208 dc->caps.color.mpc.ogam_rom_caps.pq = 0; 1209 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 1210 dc->caps.color.mpc.ocsc = 1; 1211 1212 /* read VBIOS LTTPR caps */ 1213 if (ctx->dc_bios->funcs->get_lttpr_caps) { 1214 enum bp_result bp_query_result; 1215 uint8_t is_vbios_lttpr_enable = 0; 1216 1217 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable); 1218 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable; 1219 } 1220 1221 if (ctx->dc_bios->funcs->get_lttpr_interop) { 1222 enum bp_result bp_query_result; 1223 uint8_t is_vbios_interop_enabled = 0; 1224 1225 bp_query_result = ctx->dc_bios->funcs->get_lttpr_interop(ctx->dc_bios, &is_vbios_interop_enabled); 1226 dc->caps.vbios_lttpr_aware = (bp_query_result == BP_RESULT_OK) && !!is_vbios_interop_enabled; 1227 } 1228 1229 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 1230 dc->debug = debug_defaults_drv; 1231 else 1232 dc->debug = debug_defaults_diags; 1233 1234 // Init the vm_helper 1235 if (dc->vm_helper) 1236 vm_helper_init(dc->vm_helper, 16); 1237 1238 /************************************************* 1239 * Create resources * 1240 *************************************************/ 1241 1242 /* Clock Sources for Pixel Clock*/ 1243 pool->clock_sources[DCN303_CLK_SRC_PLL0] = 1244 dcn303_clock_source_create(ctx, ctx->dc_bios, 1245 CLOCK_SOURCE_COMBO_PHY_PLL0, 1246 &clk_src_regs[0], false); 1247 pool->clock_sources[DCN303_CLK_SRC_PLL1] = 1248 dcn303_clock_source_create(ctx, ctx->dc_bios, 1249 CLOCK_SOURCE_COMBO_PHY_PLL1, 1250 &clk_src_regs[1], false); 1251 1252 pool->clk_src_count = DCN303_CLK_SRC_TOTAL; 1253 1254 /* todo: not reuse phy_pll registers */ 1255 pool->dp_clock_source = 1256 dcn303_clock_source_create(ctx, ctx->dc_bios, 1257 CLOCK_SOURCE_ID_DP_DTO, 1258 &clk_src_regs[0], true); 1259 1260 for (i = 0; i < pool->clk_src_count; i++) { 1261 if (pool->clock_sources[i] == NULL) { 1262 dm_error("DC: failed to create clock sources!\n"); 1263 BREAK_TO_DEBUGGER(); 1264 goto create_fail; 1265 } 1266 } 1267 1268 /* DCCG */ 1269 pool->dccg = dccg30_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 1270 if (pool->dccg == NULL) { 1271 dm_error("DC: failed to create dccg!\n"); 1272 BREAK_TO_DEBUGGER(); 1273 goto create_fail; 1274 } 1275 1276 /* PP Lib and SMU interfaces */ 1277 init_soc_bounding_box(dc, pool); 1278 1279 /* DML */ 1280 dml_init_instance(&dc->dml, &dcn3_03_soc, &dcn3_03_ip, DML_PROJECT_DCN30); 1281 1282 /* IRQ */ 1283 init_data.ctx = dc->ctx; 1284 pool->irqs = dal_irq_service_dcn303_create(&init_data); 1285 if (!pool->irqs) 1286 goto create_fail; 1287 1288 /* HUBBUB */ 1289 pool->hubbub = dcn303_hubbub_create(ctx); 1290 if (pool->hubbub == NULL) { 1291 BREAK_TO_DEBUGGER(); 1292 dm_error("DC: failed to create hubbub!\n"); 1293 goto create_fail; 1294 } 1295 1296 /* HUBPs, DPPs, OPPs and TGs */ 1297 for (i = 0; i < pool->pipe_count; i++) { 1298 pool->hubps[i] = dcn303_hubp_create(ctx, i); 1299 if (pool->hubps[i] == NULL) { 1300 BREAK_TO_DEBUGGER(); 1301 dm_error("DC: failed to create hubps!\n"); 1302 goto create_fail; 1303 } 1304 1305 pool->dpps[i] = dcn303_dpp_create(ctx, i); 1306 if (pool->dpps[i] == NULL) { 1307 BREAK_TO_DEBUGGER(); 1308 dm_error("DC: failed to create dpps!\n"); 1309 goto create_fail; 1310 } 1311 } 1312 1313 for (i = 0; i < pool->res_cap->num_opp; i++) { 1314 pool->opps[i] = dcn303_opp_create(ctx, i); 1315 if (pool->opps[i] == NULL) { 1316 BREAK_TO_DEBUGGER(); 1317 dm_error("DC: failed to create output pixel processor!\n"); 1318 goto create_fail; 1319 } 1320 } 1321 1322 for (i = 0; i < pool->res_cap->num_timing_generator; i++) { 1323 pool->timing_generators[i] = dcn303_timing_generator_create(ctx, i); 1324 if (pool->timing_generators[i] == NULL) { 1325 BREAK_TO_DEBUGGER(); 1326 dm_error("DC: failed to create tg!\n"); 1327 goto create_fail; 1328 } 1329 } 1330 pool->timing_generator_count = i; 1331 1332 /* PSR */ 1333 pool->psr = dmub_psr_create(ctx); 1334 if (pool->psr == NULL) { 1335 dm_error("DC: failed to create psr!\n"); 1336 BREAK_TO_DEBUGGER(); 1337 goto create_fail; 1338 } 1339 1340 /* ABM */ 1341 for (i = 0; i < pool->res_cap->num_timing_generator; i++) { 1342 pool->multiple_abms[i] = dmub_abm_create(ctx, &abm_regs[i], &abm_shift, &abm_mask); 1343 if (pool->multiple_abms[i] == NULL) { 1344 dm_error("DC: failed to create abm for pipe %d!\n", i); 1345 BREAK_TO_DEBUGGER(); 1346 goto create_fail; 1347 } 1348 } 1349 1350 /* MPC and DSC */ 1351 pool->mpc = dcn303_mpc_create(ctx, pool->mpcc_count, pool->res_cap->num_mpc_3dlut); 1352 if (pool->mpc == NULL) { 1353 BREAK_TO_DEBUGGER(); 1354 dm_error("DC: failed to create mpc!\n"); 1355 goto create_fail; 1356 } 1357 1358 for (i = 0; i < pool->res_cap->num_dsc; i++) { 1359 pool->dscs[i] = dcn303_dsc_create(ctx, i); 1360 if (pool->dscs[i] == NULL) { 1361 BREAK_TO_DEBUGGER(); 1362 dm_error("DC: failed to create display stream compressor %d!\n", i); 1363 goto create_fail; 1364 } 1365 } 1366 1367 /* DWB and MMHUBBUB */ 1368 if (!dcn303_dwbc_create(ctx, pool)) { 1369 BREAK_TO_DEBUGGER(); 1370 dm_error("DC: failed to create dwbc!\n"); 1371 goto create_fail; 1372 } 1373 1374 if (!dcn303_mmhubbub_create(ctx, pool)) { 1375 BREAK_TO_DEBUGGER(); 1376 dm_error("DC: failed to create mcif_wb!\n"); 1377 goto create_fail; 1378 } 1379 1380 /* AUX and I2C */ 1381 for (i = 0; i < pool->res_cap->num_ddc; i++) { 1382 pool->engines[i] = dcn303_aux_engine_create(ctx, i); 1383 if (pool->engines[i] == NULL) { 1384 BREAK_TO_DEBUGGER(); 1385 dm_error("DC:failed to create aux engine!!\n"); 1386 goto create_fail; 1387 } 1388 pool->hw_i2cs[i] = dcn303_i2c_hw_create(ctx, i); 1389 if (pool->hw_i2cs[i] == NULL) { 1390 BREAK_TO_DEBUGGER(); 1391 dm_error("DC:failed to create hw i2c!!\n"); 1392 goto create_fail; 1393 } 1394 pool->sw_i2cs[i] = NULL; 1395 } 1396 1397 /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */ 1398 if (!resource_construct(num_virtual_links, dc, pool, 1399 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? 1400 &res_create_funcs : &res_create_maximus_funcs))) 1401 goto create_fail; 1402 1403 /* HW Sequencer and Plane caps */ 1404 dcn303_hw_sequencer_construct(dc); 1405 1406 dc->caps.max_planes = pool->pipe_count; 1407 1408 for (i = 0; i < dc->caps.max_planes; ++i) 1409 dc->caps.planes[i] = plane_cap; 1410 1411 dc->cap_funcs = cap_funcs; 1412 1413 if (dc->ctx->dc_bios->fw_info.oem_i2c_present) { 1414 ddc_init_data.ctx = dc->ctx; 1415 ddc_init_data.link = NULL; 1416 ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id; 1417 ddc_init_data.id.enum_id = 0; 1418 ddc_init_data.id.type = OBJECT_TYPE_GENERIC; 1419 pool->oem_device = dal_ddc_service_create(&ddc_init_data); 1420 } else { 1421 pool->oem_device = NULL; 1422 } 1423 1424 return true; 1425 1426 create_fail: 1427 1428 dcn303_resource_destruct(pool); 1429 1430 return false; 1431 } 1432 1433 struct resource_pool *dcn303_create_resource_pool(const struct dc_init_data *init_data, struct dc *dc) 1434 { 1435 struct resource_pool *pool = kzalloc(sizeof(struct resource_pool), GFP_KERNEL); 1436 1437 if (!pool) 1438 return NULL; 1439 1440 if (dcn303_resource_construct(init_data->num_virtual_links, dc, pool)) 1441 return pool; 1442 1443 BREAK_TO_DEBUGGER(); 1444 kfree(pool); 1445 return NULL; 1446 } 1447