1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright (C) 2021 Advanced Micro Devices, Inc. 4 * 5 * Authors: AMD 6 */ 7 8 #include "dcn303_init.h" 9 #include "dcn303_resource.h" 10 #include "dcn303_dccg.h" 11 #include "irq/dcn303/irq_service_dcn303.h" 12 13 #include "dcn30/dcn30_dio_link_encoder.h" 14 #include "dcn30/dcn30_dio_stream_encoder.h" 15 #include "dcn30/dcn30_dpp.h" 16 #include "dcn30/dcn30_dwb.h" 17 #include "dcn30/dcn30_hubbub.h" 18 #include "dcn30/dcn30_hubp.h" 19 #include "dcn30/dcn30_mmhubbub.h" 20 #include "dcn30/dcn30_mpc.h" 21 #include "dcn30/dcn30_opp.h" 22 #include "dcn30/dcn30_optc.h" 23 #include "dcn30/dcn30_resource.h" 24 25 #include "dcn20/dcn20_dsc.h" 26 #include "dcn20/dcn20_resource.h" 27 28 #include "dcn10/dcn10_resource.h" 29 30 #include "dc_link_ddc.h" 31 32 #include "dce/dce_abm.h" 33 #include "dce/dce_audio.h" 34 #include "dce/dce_aux.h" 35 #include "dce/dce_clock_source.h" 36 #include "dce/dce_hwseq.h" 37 #include "dce/dce_i2c_hw.h" 38 #include "dce/dce_panel_cntl.h" 39 #include "dce/dmub_abm.h" 40 #include "dce/dmub_psr.h" 41 #include "clk_mgr.h" 42 43 #include "hw_sequencer_private.h" 44 #include "reg_helper.h" 45 #include "resource.h" 46 #include "vm_helper.h" 47 48 #include "sienna_cichlid_ip_offset.h" 49 #include "dcn/dcn_3_0_3_offset.h" 50 #include "dcn/dcn_3_0_3_sh_mask.h" 51 #include "dpcs/dpcs_3_0_3_offset.h" 52 #include "dpcs/dpcs_3_0_3_sh_mask.h" 53 #include "nbio/nbio_2_3_offset.h" 54 55 #include "dml/dcn303/dcn303_fpu.h" 56 57 #define DC_LOGGER_INIT(logger) 58 59 60 static const struct dc_debug_options debug_defaults_drv = { 61 .disable_dmcu = true, 62 .force_abm_enable = false, 63 .timing_trace = false, 64 .clock_trace = true, 65 .disable_pplib_clock_request = true, 66 .pipe_split_policy = MPC_SPLIT_DYNAMIC, 67 .force_single_disp_pipe_split = false, 68 .disable_dcc = DCC_ENABLE, 69 .vsr_support = true, 70 .performance_trace = false, 71 .max_downscale_src_width = 7680,/*upto 8K*/ 72 .disable_pplib_wm_range = false, 73 .scl_reset_length10 = true, 74 .sanity_checks = false, 75 .underflow_assert_delay_us = 0xFFFFFFFF, 76 .dwb_fi_phase = -1, // -1 = disable, 77 .dmub_command_table = true, 78 .disable_idle_power_optimizations = false, 79 }; 80 81 static const struct dc_debug_options debug_defaults_diags = { 82 .disable_dmcu = true, 83 .force_abm_enable = false, 84 .timing_trace = true, 85 .clock_trace = true, 86 .disable_dpp_power_gate = true, 87 .disable_hubp_power_gate = true, 88 .disable_clock_gate = true, 89 .disable_pplib_clock_request = true, 90 .disable_pplib_wm_range = true, 91 .disable_stutter = false, 92 .scl_reset_length10 = true, 93 .dwb_fi_phase = -1, // -1 = disable 94 .dmub_command_table = true, 95 .enable_tri_buf = true, 96 .disable_psr = true, 97 }; 98 99 enum dcn303_clk_src_array_id { 100 DCN303_CLK_SRC_PLL0, 101 DCN303_CLK_SRC_PLL1, 102 DCN303_CLK_SRC_TOTAL 103 }; 104 105 static const struct resource_caps res_cap_dcn303 = { 106 .num_timing_generator = 2, 107 .num_opp = 2, 108 .num_video_plane = 2, 109 .num_audio = 2, 110 .num_stream_encoder = 2, 111 .num_dwb = 1, 112 .num_ddc = 2, 113 .num_vmid = 16, 114 .num_mpc_3dlut = 1, 115 .num_dsc = 2, 116 }; 117 118 static const struct dc_plane_cap plane_cap = { 119 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 120 .blends_with_above = true, 121 .blends_with_below = true, 122 .per_pixel_alpha = true, 123 .pixel_format_support = { 124 .argb8888 = true, 125 .nv12 = true, 126 .fp16 = true, 127 .p010 = true, 128 .ayuv = false, 129 }, 130 .max_upscale_factor = { 131 .argb8888 = 16000, 132 .nv12 = 16000, 133 .fp16 = 16000 134 }, 135 .max_downscale_factor = { 136 .argb8888 = 600, 137 .nv12 = 600, 138 .fp16 = 600 139 }, 140 16, 141 16 142 }; 143 144 /* NBIO */ 145 #define NBIO_BASE_INNER(seg) \ 146 NBIO_BASE__INST0_SEG ## seg 147 148 #define NBIO_BASE(seg) \ 149 NBIO_BASE_INNER(seg) 150 151 #define NBIO_SR(reg_name)\ 152 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \ 153 mm ## reg_name 154 155 /* DCN */ 156 #undef BASE_INNER 157 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg 158 159 #define BASE(seg) BASE_INNER(seg) 160 161 #define SR(reg_name)\ 162 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name 163 164 #define SF(reg_name, field_name, post_fix)\ 165 .field_name = reg_name ## __ ## field_name ## post_fix 166 167 #define SRI(reg_name, block, id)\ 168 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + mm ## block ## id ## _ ## reg_name 169 170 #define SRI2(reg_name, block, id)\ 171 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name 172 173 #define SRII(reg_name, block, id)\ 174 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 175 mm ## block ## id ## _ ## reg_name 176 177 #define DCCG_SRII(reg_name, block, id)\ 178 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 179 mm ## block ## id ## _ ## reg_name 180 181 #define VUPDATE_SRII(reg_name, block, id)\ 182 .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \ 183 mm ## reg_name ## _ ## block ## id 184 185 #define SRII_DWB(reg_name, temp_name, block, id)\ 186 .reg_name[id] = BASE(mm ## block ## id ## _ ## temp_name ## _BASE_IDX) + \ 187 mm ## block ## id ## _ ## temp_name 188 189 #define SRII_MPC_RMU(reg_name, block, id)\ 190 .RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 191 mm ## block ## id ## _ ## reg_name 192 193 static const struct dcn_hubbub_registers hubbub_reg = { 194 HUBBUB_REG_LIST_DCN30(0) 195 }; 196 197 static const struct dcn_hubbub_shift hubbub_shift = { 198 HUBBUB_MASK_SH_LIST_DCN30(__SHIFT) 199 }; 200 201 static const struct dcn_hubbub_mask hubbub_mask = { 202 HUBBUB_MASK_SH_LIST_DCN30(_MASK) 203 }; 204 205 #define vmid_regs(id)\ 206 [id] = { DCN20_VMID_REG_LIST(id) } 207 208 static const struct dcn_vmid_registers vmid_regs[] = { 209 vmid_regs(0), 210 vmid_regs(1), 211 vmid_regs(2), 212 vmid_regs(3), 213 vmid_regs(4), 214 vmid_regs(5), 215 vmid_regs(6), 216 vmid_regs(7), 217 vmid_regs(8), 218 vmid_regs(9), 219 vmid_regs(10), 220 vmid_regs(11), 221 vmid_regs(12), 222 vmid_regs(13), 223 vmid_regs(14), 224 vmid_regs(15) 225 }; 226 227 static const struct dcn20_vmid_shift vmid_shifts = { 228 DCN20_VMID_MASK_SH_LIST(__SHIFT) 229 }; 230 231 static const struct dcn20_vmid_mask vmid_masks = { 232 DCN20_VMID_MASK_SH_LIST(_MASK) 233 }; 234 235 static struct hubbub *dcn303_hubbub_create(struct dc_context *ctx) 236 { 237 int i; 238 239 struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub), GFP_KERNEL); 240 241 if (!hubbub3) 242 return NULL; 243 244 hubbub3_construct(hubbub3, ctx, &hubbub_reg, &hubbub_shift, &hubbub_mask); 245 246 for (i = 0; i < res_cap_dcn303.num_vmid; i++) { 247 struct dcn20_vmid *vmid = &hubbub3->vmid[i]; 248 249 vmid->ctx = ctx; 250 251 vmid->regs = &vmid_regs[i]; 252 vmid->shifts = &vmid_shifts; 253 vmid->masks = &vmid_masks; 254 } 255 256 return &hubbub3->base; 257 } 258 259 #define vpg_regs(id)\ 260 [id] = { VPG_DCN3_REG_LIST(id) } 261 262 static const struct dcn30_vpg_registers vpg_regs[] = { 263 vpg_regs(0), 264 vpg_regs(1), 265 vpg_regs(2) 266 }; 267 268 static const struct dcn30_vpg_shift vpg_shift = { 269 DCN3_VPG_MASK_SH_LIST(__SHIFT) 270 }; 271 272 static const struct dcn30_vpg_mask vpg_mask = { 273 DCN3_VPG_MASK_SH_LIST(_MASK) 274 }; 275 276 static struct vpg *dcn303_vpg_create(struct dc_context *ctx, uint32_t inst) 277 { 278 struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL); 279 280 if (!vpg3) 281 return NULL; 282 283 vpg3_construct(vpg3, ctx, inst, &vpg_regs[inst], &vpg_shift, &vpg_mask); 284 285 return &vpg3->base; 286 } 287 288 #define afmt_regs(id)\ 289 [id] = { AFMT_DCN3_REG_LIST(id) } 290 291 static const struct dcn30_afmt_registers afmt_regs[] = { 292 afmt_regs(0), 293 afmt_regs(1), 294 afmt_regs(2) 295 }; 296 297 static const struct dcn30_afmt_shift afmt_shift = { 298 DCN3_AFMT_MASK_SH_LIST(__SHIFT) 299 }; 300 301 static const struct dcn30_afmt_mask afmt_mask = { 302 DCN3_AFMT_MASK_SH_LIST(_MASK) 303 }; 304 305 static struct afmt *dcn303_afmt_create(struct dc_context *ctx, uint32_t inst) 306 { 307 struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL); 308 309 if (!afmt3) 310 return NULL; 311 312 afmt3_construct(afmt3, ctx, inst, &afmt_regs[inst], &afmt_shift, &afmt_mask); 313 314 return &afmt3->base; 315 } 316 317 #define audio_regs(id)\ 318 [id] = { AUD_COMMON_REG_LIST(id) } 319 320 static const struct dce_audio_registers audio_regs[] = { 321 audio_regs(0), 322 audio_regs(1), 323 audio_regs(2), 324 audio_regs(3), 325 audio_regs(4), 326 audio_regs(5), 327 audio_regs(6) 328 }; 329 330 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 331 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 332 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 333 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 334 335 static const struct dce_audio_shift audio_shift = { 336 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 337 }; 338 339 static const struct dce_audio_mask audio_mask = { 340 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 341 }; 342 343 static struct audio *dcn303_create_audio(struct dc_context *ctx, unsigned int inst) 344 { 345 return dce_audio_create(ctx, inst, &audio_regs[inst], &audio_shift, &audio_mask); 346 } 347 348 #define stream_enc_regs(id)\ 349 [id] = { SE_DCN3_REG_LIST(id) } 350 351 static const struct dcn10_stream_enc_registers stream_enc_regs[] = { 352 stream_enc_regs(0), 353 stream_enc_regs(1) 354 }; 355 356 static const struct dcn10_stream_encoder_shift se_shift = { 357 SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 358 }; 359 360 static const struct dcn10_stream_encoder_mask se_mask = { 361 SE_COMMON_MASK_SH_LIST_DCN30(_MASK) 362 }; 363 364 static struct stream_encoder *dcn303_stream_encoder_create(enum engine_id eng_id, struct dc_context *ctx) 365 { 366 struct dcn10_stream_encoder *enc1; 367 struct vpg *vpg; 368 struct afmt *afmt; 369 int vpg_inst; 370 int afmt_inst; 371 372 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */ 373 if (eng_id <= ENGINE_ID_DIGE) { 374 vpg_inst = eng_id; 375 afmt_inst = eng_id; 376 } else 377 return NULL; 378 379 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 380 vpg = dcn303_vpg_create(ctx, vpg_inst); 381 afmt = dcn303_afmt_create(ctx, afmt_inst); 382 383 if (!enc1 || !vpg || !afmt) { 384 kfree(enc1); 385 kfree(vpg); 386 kfree(afmt); 387 return NULL; 388 } 389 390 dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id, vpg, afmt, &stream_enc_regs[eng_id], 391 &se_shift, &se_mask); 392 393 return &enc1->base; 394 } 395 396 #define clk_src_regs(index, pllid)\ 397 [index] = { CS_COMMON_REG_LIST_DCN3_03(index, pllid) } 398 399 static const struct dce110_clk_src_regs clk_src_regs[] = { 400 clk_src_regs(0, A), 401 clk_src_regs(1, B) 402 }; 403 404 static const struct dce110_clk_src_shift cs_shift = { 405 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 406 }; 407 408 static const struct dce110_clk_src_mask cs_mask = { 409 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 410 }; 411 412 static struct clock_source *dcn303_clock_source_create(struct dc_context *ctx, struct dc_bios *bios, 413 enum clock_source_id id, const struct dce110_clk_src_regs *regs, bool dp_clk_src) 414 { 415 struct dce110_clk_src *clk_src = kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 416 417 if (!clk_src) 418 return NULL; 419 420 if (dcn3_clk_src_construct(clk_src, ctx, bios, id, regs, &cs_shift, &cs_mask)) { 421 clk_src->base.dp_clk_src = dp_clk_src; 422 return &clk_src->base; 423 } 424 425 BREAK_TO_DEBUGGER(); 426 return NULL; 427 } 428 429 static const struct dce_hwseq_registers hwseq_reg = { 430 HWSEQ_DCN303_REG_LIST() 431 }; 432 433 static const struct dce_hwseq_shift hwseq_shift = { 434 HWSEQ_DCN303_MASK_SH_LIST(__SHIFT) 435 }; 436 437 static const struct dce_hwseq_mask hwseq_mask = { 438 HWSEQ_DCN303_MASK_SH_LIST(_MASK) 439 }; 440 441 static struct dce_hwseq *dcn303_hwseq_create(struct dc_context *ctx) 442 { 443 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 444 445 if (hws) { 446 hws->ctx = ctx; 447 hws->regs = &hwseq_reg; 448 hws->shifts = &hwseq_shift; 449 hws->masks = &hwseq_mask; 450 } 451 return hws; 452 } 453 454 #define hubp_regs(id)\ 455 [id] = { HUBP_REG_LIST_DCN30(id) } 456 457 static const struct dcn_hubp2_registers hubp_regs[] = { 458 hubp_regs(0), 459 hubp_regs(1) 460 }; 461 462 static const struct dcn_hubp2_shift hubp_shift = { 463 HUBP_MASK_SH_LIST_DCN30(__SHIFT) 464 }; 465 466 static const struct dcn_hubp2_mask hubp_mask = { 467 HUBP_MASK_SH_LIST_DCN30(_MASK) 468 }; 469 470 static struct hubp *dcn303_hubp_create(struct dc_context *ctx, uint32_t inst) 471 { 472 struct dcn20_hubp *hubp2 = kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL); 473 474 if (!hubp2) 475 return NULL; 476 477 if (hubp3_construct(hubp2, ctx, inst, &hubp_regs[inst], &hubp_shift, &hubp_mask)) 478 return &hubp2->base; 479 480 BREAK_TO_DEBUGGER(); 481 kfree(hubp2); 482 return NULL; 483 } 484 485 #define dpp_regs(id)\ 486 [id] = { DPP_REG_LIST_DCN30(id) } 487 488 static const struct dcn3_dpp_registers dpp_regs[] = { 489 dpp_regs(0), 490 dpp_regs(1) 491 }; 492 493 static const struct dcn3_dpp_shift tf_shift = { 494 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT) 495 }; 496 497 static const struct dcn3_dpp_mask tf_mask = { 498 DPP_REG_LIST_SH_MASK_DCN30(_MASK) 499 }; 500 501 static struct dpp *dcn303_dpp_create(struct dc_context *ctx, uint32_t inst) 502 { 503 struct dcn3_dpp *dpp = kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL); 504 505 if (!dpp) 506 return NULL; 507 508 if (dpp3_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, &tf_mask)) 509 return &dpp->base; 510 511 BREAK_TO_DEBUGGER(); 512 kfree(dpp); 513 return NULL; 514 } 515 516 #define opp_regs(id)\ 517 [id] = { OPP_REG_LIST_DCN30(id) } 518 519 static const struct dcn20_opp_registers opp_regs[] = { 520 opp_regs(0), 521 opp_regs(1) 522 }; 523 524 static const struct dcn20_opp_shift opp_shift = { 525 OPP_MASK_SH_LIST_DCN20(__SHIFT) 526 }; 527 528 static const struct dcn20_opp_mask opp_mask = { 529 OPP_MASK_SH_LIST_DCN20(_MASK) 530 }; 531 532 static struct output_pixel_processor *dcn303_opp_create(struct dc_context *ctx, uint32_t inst) 533 { 534 struct dcn20_opp *opp = kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); 535 536 if (!opp) { 537 BREAK_TO_DEBUGGER(); 538 return NULL; 539 } 540 541 dcn20_opp_construct(opp, ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask); 542 return &opp->base; 543 } 544 545 #define optc_regs(id)\ 546 [id] = { OPTC_COMMON_REG_LIST_DCN3_0(id) } 547 548 static const struct dcn_optc_registers optc_regs[] = { 549 optc_regs(0), 550 optc_regs(1) 551 }; 552 553 static const struct dcn_optc_shift optc_shift = { 554 OPTC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 555 }; 556 557 static const struct dcn_optc_mask optc_mask = { 558 OPTC_COMMON_MASK_SH_LIST_DCN30(_MASK) 559 }; 560 561 static struct timing_generator *dcn303_timing_generator_create(struct dc_context *ctx, uint32_t instance) 562 { 563 struct optc *tgn10 = kzalloc(sizeof(struct optc), GFP_KERNEL); 564 565 if (!tgn10) 566 return NULL; 567 568 tgn10->base.inst = instance; 569 tgn10->base.ctx = ctx; 570 571 tgn10->tg_regs = &optc_regs[instance]; 572 tgn10->tg_shift = &optc_shift; 573 tgn10->tg_mask = &optc_mask; 574 575 dcn30_timing_generator_init(tgn10); 576 577 return &tgn10->base; 578 } 579 580 static const struct dcn30_mpc_registers mpc_regs = { 581 MPC_REG_LIST_DCN3_0(0), 582 MPC_REG_LIST_DCN3_0(1), 583 MPC_OUT_MUX_REG_LIST_DCN3_0(0), 584 MPC_OUT_MUX_REG_LIST_DCN3_0(1), 585 MPC_RMU_GLOBAL_REG_LIST_DCN3AG, 586 MPC_RMU_REG_LIST_DCN3AG(0), 587 MPC_DWB_MUX_REG_LIST_DCN3_0(0), 588 }; 589 590 static const struct dcn30_mpc_shift mpc_shift = { 591 MPC_COMMON_MASK_SH_LIST_DCN303(__SHIFT) 592 }; 593 594 static const struct dcn30_mpc_mask mpc_mask = { 595 MPC_COMMON_MASK_SH_LIST_DCN303(_MASK) 596 }; 597 598 static struct mpc *dcn303_mpc_create(struct dc_context *ctx, int num_mpcc, int num_rmu) 599 { 600 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), GFP_KERNEL); 601 602 if (!mpc30) 603 return NULL; 604 605 dcn30_mpc_construct(mpc30, ctx, &mpc_regs, &mpc_shift, &mpc_mask, num_mpcc, num_rmu); 606 607 return &mpc30->base; 608 } 609 610 #define dsc_regsDCN20(id)\ 611 [id] = { DSC_REG_LIST_DCN20(id) } 612 613 static const struct dcn20_dsc_registers dsc_regs[] = { 614 dsc_regsDCN20(0), 615 dsc_regsDCN20(1) 616 }; 617 618 static const struct dcn20_dsc_shift dsc_shift = { 619 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) 620 }; 621 622 static const struct dcn20_dsc_mask dsc_mask = { 623 DSC_REG_LIST_SH_MASK_DCN20(_MASK) 624 }; 625 626 static struct display_stream_compressor *dcn303_dsc_create(struct dc_context *ctx, uint32_t inst) 627 { 628 struct dcn20_dsc *dsc = kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); 629 630 if (!dsc) { 631 BREAK_TO_DEBUGGER(); 632 return NULL; 633 } 634 635 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 636 return &dsc->base; 637 } 638 639 #define dwbc_regs_dcn3(id)\ 640 [id] = { DWBC_COMMON_REG_LIST_DCN30(id) } 641 642 static const struct dcn30_dwbc_registers dwbc30_regs[] = { 643 dwbc_regs_dcn3(0) 644 }; 645 646 static const struct dcn30_dwbc_shift dwbc30_shift = { 647 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 648 }; 649 650 static const struct dcn30_dwbc_mask dwbc30_mask = { 651 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK) 652 }; 653 654 static bool dcn303_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) 655 { 656 int i; 657 uint32_t pipe_count = pool->res_cap->num_dwb; 658 659 for (i = 0; i < pipe_count; i++) { 660 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), GFP_KERNEL); 661 662 if (!dwbc30) { 663 dm_error("DC: failed to create dwbc30!\n"); 664 return false; 665 } 666 667 dcn30_dwbc_construct(dwbc30, ctx, &dwbc30_regs[i], &dwbc30_shift, &dwbc30_mask, i); 668 669 pool->dwbc[i] = &dwbc30->base; 670 } 671 return true; 672 } 673 674 #define mcif_wb_regs_dcn3(id)\ 675 [id] = { MCIF_WB_COMMON_REG_LIST_DCN30(id) } 676 677 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = { 678 mcif_wb_regs_dcn3(0) 679 }; 680 681 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = { 682 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 683 }; 684 685 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { 686 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK) 687 }; 688 689 static bool dcn303_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) 690 { 691 int i; 692 uint32_t pipe_count = pool->res_cap->num_dwb; 693 694 for (i = 0; i < pipe_count; i++) { 695 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), GFP_KERNEL); 696 697 if (!mcif_wb30) { 698 dm_error("DC: failed to create mcif_wb30!\n"); 699 return false; 700 } 701 702 dcn30_mmhubbub_construct(mcif_wb30, ctx, &mcif_wb30_regs[i], &mcif_wb30_shift, &mcif_wb30_mask, i); 703 704 pool->mcif_wb[i] = &mcif_wb30->base; 705 } 706 return true; 707 } 708 709 #define aux_engine_regs(id)\ 710 [id] = {\ 711 AUX_COMMON_REG_LIST0(id), \ 712 .AUXN_IMPCAL = 0, \ 713 .AUXP_IMPCAL = 0, \ 714 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \ 715 } 716 717 static const struct dce110_aux_registers aux_engine_regs[] = { 718 aux_engine_regs(0), 719 aux_engine_regs(1) 720 }; 721 722 static const struct dce110_aux_registers_shift aux_shift = { 723 DCN_AUX_MASK_SH_LIST(__SHIFT) 724 }; 725 726 static const struct dce110_aux_registers_mask aux_mask = { 727 DCN_AUX_MASK_SH_LIST(_MASK) 728 }; 729 730 static struct dce_aux *dcn303_aux_engine_create(struct dc_context *ctx, uint32_t inst) 731 { 732 struct aux_engine_dce110 *aux_engine = kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 733 734 if (!aux_engine) 735 return NULL; 736 737 dce110_aux_engine_construct(aux_engine, ctx, inst, SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 738 &aux_engine_regs[inst], &aux_mask, &aux_shift, ctx->dc->caps.extended_aux_timeout_support); 739 740 return &aux_engine->base; 741 } 742 743 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 744 745 static const struct dce_i2c_registers i2c_hw_regs[] = { 746 i2c_inst_regs(1), 747 i2c_inst_regs(2) 748 }; 749 750 static const struct dce_i2c_shift i2c_shifts = { 751 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT) 752 }; 753 754 static const struct dce_i2c_mask i2c_masks = { 755 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK) 756 }; 757 758 static struct dce_i2c_hw *dcn303_i2c_hw_create(struct dc_context *ctx, uint32_t inst) 759 { 760 struct dce_i2c_hw *dce_i2c_hw = kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 761 762 if (!dce_i2c_hw) 763 return NULL; 764 765 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 766 767 return dce_i2c_hw; 768 } 769 770 static const struct encoder_feature_support link_enc_feature = { 771 .max_hdmi_deep_color = COLOR_DEPTH_121212, 772 .max_hdmi_pixel_clock = 600000, 773 .hdmi_ycbcr420_supported = true, 774 .dp_ycbcr420_supported = true, 775 .fec_supported = true, 776 .flags.bits.IS_HBR2_CAPABLE = true, 777 .flags.bits.IS_HBR3_CAPABLE = true, 778 .flags.bits.IS_TPS3_CAPABLE = true, 779 .flags.bits.IS_TPS4_CAPABLE = true 780 }; 781 782 #define link_regs(id, phyid)\ 783 [id] = {\ 784 LE_DCN3_REG_LIST(id), \ 785 UNIPHY_DCN2_REG_LIST(phyid), \ 786 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \ 787 } 788 789 static const struct dcn10_link_enc_registers link_enc_regs[] = { 790 link_regs(0, A), 791 link_regs(1, B) 792 }; 793 794 static const struct dcn10_link_enc_shift le_shift = { 795 LINK_ENCODER_MASK_SH_LIST_DCN30(__SHIFT), 796 DPCS_DCN2_MASK_SH_LIST(__SHIFT) 797 }; 798 799 static const struct dcn10_link_enc_mask le_mask = { 800 LINK_ENCODER_MASK_SH_LIST_DCN30(_MASK), 801 DPCS_DCN2_MASK_SH_LIST(_MASK) 802 }; 803 804 #define aux_regs(id)\ 805 [id] = { DCN2_AUX_REG_LIST(id) } 806 807 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { 808 aux_regs(0), 809 aux_regs(1) 810 }; 811 812 #define hpd_regs(id)\ 813 [id] = { HPD_REG_LIST(id) } 814 815 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { 816 hpd_regs(0), 817 hpd_regs(1) 818 }; 819 820 static struct link_encoder *dcn303_link_encoder_create(const struct encoder_init_data *enc_init_data) 821 { 822 struct dcn20_link_encoder *enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 823 824 if (!enc20) 825 return NULL; 826 827 dcn30_link_encoder_construct(enc20, enc_init_data, &link_enc_feature, 828 &link_enc_regs[enc_init_data->transmitter], &link_enc_aux_regs[enc_init_data->channel - 1], 829 &link_enc_hpd_regs[enc_init_data->hpd_source], &le_shift, &le_mask); 830 831 return &enc20->enc10.base; 832 } 833 834 static const struct dce_panel_cntl_registers panel_cntl_regs[] = { 835 { DCN_PANEL_CNTL_REG_LIST() } 836 }; 837 838 static const struct dce_panel_cntl_shift panel_cntl_shift = { 839 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT) 840 }; 841 842 static const struct dce_panel_cntl_mask panel_cntl_mask = { 843 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK) 844 }; 845 846 static struct panel_cntl *dcn303_panel_cntl_create(const struct panel_cntl_init_data *init_data) 847 { 848 struct dce_panel_cntl *panel_cntl = kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL); 849 850 if (!panel_cntl) 851 return NULL; 852 853 dce_panel_cntl_construct(panel_cntl, init_data, &panel_cntl_regs[init_data->inst], 854 &panel_cntl_shift, &panel_cntl_mask); 855 856 return &panel_cntl->base; 857 } 858 859 static void read_dce_straps(struct dc_context *ctx, struct resource_straps *straps) 860 { 861 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX), 862 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 863 } 864 865 static const struct resource_create_funcs res_create_funcs = { 866 .read_dce_straps = read_dce_straps, 867 .create_audio = dcn303_create_audio, 868 .create_stream_encoder = dcn303_stream_encoder_create, 869 .create_hwseq = dcn303_hwseq_create, 870 }; 871 872 static const struct resource_create_funcs res_create_maximus_funcs = { 873 .read_dce_straps = NULL, 874 .create_audio = NULL, 875 .create_stream_encoder = NULL, 876 .create_hwseq = dcn303_hwseq_create, 877 }; 878 879 static bool is_soc_bounding_box_valid(struct dc *dc) 880 { 881 uint32_t hw_internal_rev = dc->ctx->asic_id.hw_internal_rev; 882 883 if (ASICREV_IS_BEIGE_GOBY_P(hw_internal_rev)) 884 return true; 885 886 return false; 887 } 888 889 static bool init_soc_bounding_box(struct dc *dc, struct resource_pool *pool) 890 { 891 struct _vcs_dpi_soc_bounding_box_st *loaded_bb = &dcn3_03_soc; 892 struct _vcs_dpi_ip_params_st *loaded_ip = &dcn3_03_ip; 893 894 DC_LOGGER_INIT(dc->ctx->logger); 895 896 if (!is_soc_bounding_box_valid(dc)) { 897 DC_LOG_ERROR("%s: not valid soc bounding box/n", __func__); 898 return false; 899 } 900 901 loaded_ip->max_num_otg = pool->pipe_count; 902 loaded_ip->max_num_dpp = pool->pipe_count; 903 loaded_ip->clamp_min_dcfclk = dc->config.clamp_min_dcfclk; 904 DC_FP_START(); 905 dcn20_patch_bounding_box(dc, loaded_bb); 906 DC_FP_END(); 907 908 if (dc->ctx->dc_bios->funcs->get_soc_bb_info) { 909 struct bp_soc_bb_info bb_info = { 0 }; 910 911 if (dc->ctx->dc_bios->funcs->get_soc_bb_info( 912 dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) { 913 DC_FP_START(); 914 dcn303_fpu_init_soc_bounding_box(bb_info); 915 DC_FP_END(); 916 } 917 } 918 919 return true; 920 } 921 922 static void dcn303_resource_destruct(struct resource_pool *pool) 923 { 924 unsigned int i; 925 926 for (i = 0; i < pool->stream_enc_count; i++) { 927 if (pool->stream_enc[i] != NULL) { 928 if (pool->stream_enc[i]->vpg != NULL) { 929 kfree(DCN30_VPG_FROM_VPG(pool->stream_enc[i]->vpg)); 930 pool->stream_enc[i]->vpg = NULL; 931 } 932 if (pool->stream_enc[i]->afmt != NULL) { 933 kfree(DCN30_AFMT_FROM_AFMT(pool->stream_enc[i]->afmt)); 934 pool->stream_enc[i]->afmt = NULL; 935 } 936 kfree(DCN10STRENC_FROM_STRENC(pool->stream_enc[i])); 937 pool->stream_enc[i] = NULL; 938 } 939 } 940 941 for (i = 0; i < pool->res_cap->num_dsc; i++) { 942 if (pool->dscs[i] != NULL) 943 dcn20_dsc_destroy(&pool->dscs[i]); 944 } 945 946 if (pool->mpc != NULL) { 947 kfree(TO_DCN20_MPC(pool->mpc)); 948 pool->mpc = NULL; 949 } 950 951 if (pool->hubbub != NULL) { 952 kfree(pool->hubbub); 953 pool->hubbub = NULL; 954 } 955 956 for (i = 0; i < pool->pipe_count; i++) { 957 if (pool->dpps[i] != NULL) { 958 kfree(TO_DCN20_DPP(pool->dpps[i])); 959 pool->dpps[i] = NULL; 960 } 961 962 if (pool->hubps[i] != NULL) { 963 kfree(TO_DCN20_HUBP(pool->hubps[i])); 964 pool->hubps[i] = NULL; 965 } 966 967 if (pool->irqs != NULL) 968 dal_irq_service_destroy(&pool->irqs); 969 } 970 971 for (i = 0; i < pool->res_cap->num_ddc; i++) { 972 if (pool->engines[i] != NULL) 973 dce110_engine_destroy(&pool->engines[i]); 974 if (pool->hw_i2cs[i] != NULL) { 975 kfree(pool->hw_i2cs[i]); 976 pool->hw_i2cs[i] = NULL; 977 } 978 if (pool->sw_i2cs[i] != NULL) { 979 kfree(pool->sw_i2cs[i]); 980 pool->sw_i2cs[i] = NULL; 981 } 982 } 983 984 for (i = 0; i < pool->res_cap->num_opp; i++) { 985 if (pool->opps[i] != NULL) 986 pool->opps[i]->funcs->opp_destroy(&pool->opps[i]); 987 } 988 989 for (i = 0; i < pool->res_cap->num_timing_generator; i++) { 990 if (pool->timing_generators[i] != NULL) { 991 kfree(DCN10TG_FROM_TG(pool->timing_generators[i])); 992 pool->timing_generators[i] = NULL; 993 } 994 } 995 996 for (i = 0; i < pool->res_cap->num_dwb; i++) { 997 if (pool->dwbc[i] != NULL) { 998 kfree(TO_DCN30_DWBC(pool->dwbc[i])); 999 pool->dwbc[i] = NULL; 1000 } 1001 if (pool->mcif_wb[i] != NULL) { 1002 kfree(TO_DCN30_MMHUBBUB(pool->mcif_wb[i])); 1003 pool->mcif_wb[i] = NULL; 1004 } 1005 } 1006 1007 for (i = 0; i < pool->audio_count; i++) { 1008 if (pool->audios[i]) 1009 dce_aud_destroy(&pool->audios[i]); 1010 } 1011 1012 for (i = 0; i < pool->clk_src_count; i++) { 1013 if (pool->clock_sources[i] != NULL) 1014 dcn20_clock_source_destroy(&pool->clock_sources[i]); 1015 } 1016 1017 if (pool->dp_clock_source != NULL) 1018 dcn20_clock_source_destroy(&pool->dp_clock_source); 1019 1020 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { 1021 if (pool->mpc_lut[i] != NULL) { 1022 dc_3dlut_func_release(pool->mpc_lut[i]); 1023 pool->mpc_lut[i] = NULL; 1024 } 1025 if (pool->mpc_shaper[i] != NULL) { 1026 dc_transfer_func_release(pool->mpc_shaper[i]); 1027 pool->mpc_shaper[i] = NULL; 1028 } 1029 } 1030 1031 for (i = 0; i < pool->pipe_count; i++) { 1032 if (pool->multiple_abms[i] != NULL) 1033 dce_abm_destroy(&pool->multiple_abms[i]); 1034 } 1035 1036 if (pool->psr != NULL) 1037 dmub_psr_destroy(&pool->psr); 1038 1039 if (pool->dccg != NULL) 1040 dcn_dccg_destroy(&pool->dccg); 1041 1042 if (pool->oem_device != NULL) 1043 dal_ddc_service_destroy(&pool->oem_device); 1044 } 1045 1046 static void dcn303_destroy_resource_pool(struct resource_pool **pool) 1047 { 1048 dcn303_resource_destruct(*pool); 1049 kfree(*pool); 1050 *pool = NULL; 1051 } 1052 1053 1054 void dcn303_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) 1055 { 1056 DC_FP_START(); 1057 dcn303_fpu_update_bw_bounding_box(dc, bw_params); 1058 DC_FP_END(); 1059 } 1060 1061 static struct resource_funcs dcn303_res_pool_funcs = { 1062 .destroy = dcn303_destroy_resource_pool, 1063 .link_enc_create = dcn303_link_encoder_create, 1064 .panel_cntl_create = dcn303_panel_cntl_create, 1065 .validate_bandwidth = dcn30_validate_bandwidth, 1066 .calculate_wm_and_dlg = dcn30_calculate_wm_and_dlg, 1067 .update_soc_for_wm_a = dcn30_update_soc_for_wm_a, 1068 .populate_dml_pipes = dcn30_populate_dml_pipes_from_context, 1069 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer, 1070 .add_stream_to_ctx = dcn30_add_stream_to_ctx, 1071 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, 1072 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 1073 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, 1074 .set_mcif_arb_params = dcn30_set_mcif_arb_params, 1075 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, 1076 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut, 1077 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut, 1078 .update_bw_bounding_box = dcn303_update_bw_bounding_box, 1079 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, 1080 }; 1081 1082 static struct dc_cap_funcs cap_funcs = { 1083 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap 1084 }; 1085 1086 static const struct bios_registers bios_regs = { 1087 NBIO_SR(BIOS_SCRATCH_3), 1088 NBIO_SR(BIOS_SCRATCH_6) 1089 }; 1090 1091 static const struct dccg_registers dccg_regs = { 1092 DCCG_REG_LIST_DCN3_03() 1093 }; 1094 1095 static const struct dccg_shift dccg_shift = { 1096 DCCG_MASK_SH_LIST_DCN3_03(__SHIFT) 1097 }; 1098 1099 static const struct dccg_mask dccg_mask = { 1100 DCCG_MASK_SH_LIST_DCN3_03(_MASK) 1101 }; 1102 1103 #define abm_regs(id)\ 1104 [id] = { ABM_DCN302_REG_LIST(id) } 1105 1106 static const struct dce_abm_registers abm_regs[] = { 1107 abm_regs(0), 1108 abm_regs(1) 1109 }; 1110 1111 static const struct dce_abm_shift abm_shift = { 1112 ABM_MASK_SH_LIST_DCN30(__SHIFT) 1113 }; 1114 1115 static const struct dce_abm_mask abm_mask = { 1116 ABM_MASK_SH_LIST_DCN30(_MASK) 1117 }; 1118 1119 static bool dcn303_resource_construct( 1120 uint8_t num_virtual_links, 1121 struct dc *dc, 1122 struct resource_pool *pool) 1123 { 1124 int i; 1125 struct dc_context *ctx = dc->ctx; 1126 struct irq_service_init_data init_data; 1127 struct ddc_service_init_data ddc_init_data; 1128 1129 ctx->dc_bios->regs = &bios_regs; 1130 1131 pool->res_cap = &res_cap_dcn303; 1132 1133 pool->funcs = &dcn303_res_pool_funcs; 1134 1135 /************************************************* 1136 * Resource + asic cap harcoding * 1137 *************************************************/ 1138 pool->underlay_pipe_index = NO_UNDERLAY_PIPE; 1139 pool->pipe_count = pool->res_cap->num_timing_generator; 1140 pool->mpcc_count = pool->res_cap->num_timing_generator; 1141 dc->caps.max_downscale_ratio = 600; 1142 dc->caps.i2c_speed_in_khz = 100; 1143 dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by derfault*/ 1144 dc->caps.max_cursor_size = 256; 1145 dc->caps.min_horizontal_blanking_period = 80; 1146 dc->caps.dmdata_alloc_size = 2048; 1147 #if defined(CONFIG_DRM_AMD_DC_DCN) 1148 dc->caps.mall_size_per_mem_channel = 4; 1149 /* total size = mall per channel * num channels * 1024 * 1024 */ 1150 dc->caps.mall_size_total = dc->caps.mall_size_per_mem_channel * 1151 dc->ctx->dc_bios->vram_info.num_chans * 1152 1024 * 1024; 1153 dc->caps.cursor_cache_size = 1154 dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8; 1155 #endif 1156 dc->caps.max_slave_planes = 1; 1157 dc->caps.post_blend_color_processing = true; 1158 dc->caps.force_dp_tps4_for_cp2520 = true; 1159 dc->caps.extended_aux_timeout_support = true; 1160 dc->caps.dmcub_support = true; 1161 1162 /* Color pipeline capabilities */ 1163 dc->caps.color.dpp.dcn_arch = 1; 1164 dc->caps.color.dpp.input_lut_shared = 0; 1165 dc->caps.color.dpp.icsc = 1; 1166 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr 1167 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; 1168 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; 1169 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1; 1170 dc->caps.color.dpp.dgam_rom_caps.pq = 1; 1171 dc->caps.color.dpp.dgam_rom_caps.hlg = 1; 1172 dc->caps.color.dpp.post_csc = 1; 1173 dc->caps.color.dpp.gamma_corr = 1; 1174 dc->caps.color.dpp.dgam_rom_for_yuv = 0; 1175 1176 dc->caps.color.dpp.hw_3d_lut = 1; 1177 dc->caps.color.dpp.ogam_ram = 1; 1178 // no OGAM ROM on DCN3 1179 dc->caps.color.dpp.ogam_rom_caps.srgb = 0; 1180 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; 1181 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; 1182 dc->caps.color.dpp.ogam_rom_caps.pq = 0; 1183 dc->caps.color.dpp.ogam_rom_caps.hlg = 0; 1184 dc->caps.color.dpp.ocsc = 0; 1185 1186 dc->caps.color.mpc.gamut_remap = 1; 1187 dc->caps.color.mpc.num_3dluts = pool->res_cap->num_mpc_3dlut; //3 1188 dc->caps.color.mpc.ogam_ram = 1; 1189 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; 1190 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; 1191 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; 1192 dc->caps.color.mpc.ogam_rom_caps.pq = 0; 1193 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 1194 dc->caps.color.mpc.ocsc = 1; 1195 1196 /* read VBIOS LTTPR caps */ 1197 if (ctx->dc_bios->funcs->get_lttpr_caps) { 1198 enum bp_result bp_query_result; 1199 uint8_t is_vbios_lttpr_enable = 0; 1200 1201 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable); 1202 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable; 1203 } 1204 1205 if (ctx->dc_bios->funcs->get_lttpr_interop) { 1206 enum bp_result bp_query_result; 1207 uint8_t is_vbios_interop_enabled = 0; 1208 1209 bp_query_result = ctx->dc_bios->funcs->get_lttpr_interop(ctx->dc_bios, &is_vbios_interop_enabled); 1210 dc->caps.vbios_lttpr_aware = (bp_query_result == BP_RESULT_OK) && !!is_vbios_interop_enabled; 1211 } 1212 1213 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 1214 dc->debug = debug_defaults_drv; 1215 else 1216 dc->debug = debug_defaults_diags; 1217 1218 // Init the vm_helper 1219 if (dc->vm_helper) 1220 vm_helper_init(dc->vm_helper, 16); 1221 1222 /************************************************* 1223 * Create resources * 1224 *************************************************/ 1225 1226 /* Clock Sources for Pixel Clock*/ 1227 pool->clock_sources[DCN303_CLK_SRC_PLL0] = 1228 dcn303_clock_source_create(ctx, ctx->dc_bios, 1229 CLOCK_SOURCE_COMBO_PHY_PLL0, 1230 &clk_src_regs[0], false); 1231 pool->clock_sources[DCN303_CLK_SRC_PLL1] = 1232 dcn303_clock_source_create(ctx, ctx->dc_bios, 1233 CLOCK_SOURCE_COMBO_PHY_PLL1, 1234 &clk_src_regs[1], false); 1235 1236 pool->clk_src_count = DCN303_CLK_SRC_TOTAL; 1237 1238 /* todo: not reuse phy_pll registers */ 1239 pool->dp_clock_source = 1240 dcn303_clock_source_create(ctx, ctx->dc_bios, 1241 CLOCK_SOURCE_ID_DP_DTO, 1242 &clk_src_regs[0], true); 1243 1244 for (i = 0; i < pool->clk_src_count; i++) { 1245 if (pool->clock_sources[i] == NULL) { 1246 dm_error("DC: failed to create clock sources!\n"); 1247 BREAK_TO_DEBUGGER(); 1248 goto create_fail; 1249 } 1250 } 1251 1252 /* DCCG */ 1253 pool->dccg = dccg30_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 1254 if (pool->dccg == NULL) { 1255 dm_error("DC: failed to create dccg!\n"); 1256 BREAK_TO_DEBUGGER(); 1257 goto create_fail; 1258 } 1259 1260 /* PP Lib and SMU interfaces */ 1261 init_soc_bounding_box(dc, pool); 1262 1263 /* DML */ 1264 dml_init_instance(&dc->dml, &dcn3_03_soc, &dcn3_03_ip, DML_PROJECT_DCN30); 1265 1266 /* IRQ */ 1267 init_data.ctx = dc->ctx; 1268 pool->irqs = dal_irq_service_dcn303_create(&init_data); 1269 if (!pool->irqs) 1270 goto create_fail; 1271 1272 /* HUBBUB */ 1273 pool->hubbub = dcn303_hubbub_create(ctx); 1274 if (pool->hubbub == NULL) { 1275 BREAK_TO_DEBUGGER(); 1276 dm_error("DC: failed to create hubbub!\n"); 1277 goto create_fail; 1278 } 1279 1280 /* HUBPs, DPPs, OPPs and TGs */ 1281 for (i = 0; i < pool->pipe_count; i++) { 1282 pool->hubps[i] = dcn303_hubp_create(ctx, i); 1283 if (pool->hubps[i] == NULL) { 1284 BREAK_TO_DEBUGGER(); 1285 dm_error("DC: failed to create hubps!\n"); 1286 goto create_fail; 1287 } 1288 1289 pool->dpps[i] = dcn303_dpp_create(ctx, i); 1290 if (pool->dpps[i] == NULL) { 1291 BREAK_TO_DEBUGGER(); 1292 dm_error("DC: failed to create dpps!\n"); 1293 goto create_fail; 1294 } 1295 } 1296 1297 for (i = 0; i < pool->res_cap->num_opp; i++) { 1298 pool->opps[i] = dcn303_opp_create(ctx, i); 1299 if (pool->opps[i] == NULL) { 1300 BREAK_TO_DEBUGGER(); 1301 dm_error("DC: failed to create output pixel processor!\n"); 1302 goto create_fail; 1303 } 1304 } 1305 1306 for (i = 0; i < pool->res_cap->num_timing_generator; i++) { 1307 pool->timing_generators[i] = dcn303_timing_generator_create(ctx, i); 1308 if (pool->timing_generators[i] == NULL) { 1309 BREAK_TO_DEBUGGER(); 1310 dm_error("DC: failed to create tg!\n"); 1311 goto create_fail; 1312 } 1313 } 1314 pool->timing_generator_count = i; 1315 1316 /* PSR */ 1317 pool->psr = dmub_psr_create(ctx); 1318 if (pool->psr == NULL) { 1319 dm_error("DC: failed to create psr!\n"); 1320 BREAK_TO_DEBUGGER(); 1321 goto create_fail; 1322 } 1323 1324 /* ABM */ 1325 for (i = 0; i < pool->res_cap->num_timing_generator; i++) { 1326 pool->multiple_abms[i] = dmub_abm_create(ctx, &abm_regs[i], &abm_shift, &abm_mask); 1327 if (pool->multiple_abms[i] == NULL) { 1328 dm_error("DC: failed to create abm for pipe %d!\n", i); 1329 BREAK_TO_DEBUGGER(); 1330 goto create_fail; 1331 } 1332 } 1333 1334 /* MPC and DSC */ 1335 pool->mpc = dcn303_mpc_create(ctx, pool->mpcc_count, pool->res_cap->num_mpc_3dlut); 1336 if (pool->mpc == NULL) { 1337 BREAK_TO_DEBUGGER(); 1338 dm_error("DC: failed to create mpc!\n"); 1339 goto create_fail; 1340 } 1341 1342 for (i = 0; i < pool->res_cap->num_dsc; i++) { 1343 pool->dscs[i] = dcn303_dsc_create(ctx, i); 1344 if (pool->dscs[i] == NULL) { 1345 BREAK_TO_DEBUGGER(); 1346 dm_error("DC: failed to create display stream compressor %d!\n", i); 1347 goto create_fail; 1348 } 1349 } 1350 1351 /* DWB and MMHUBBUB */ 1352 if (!dcn303_dwbc_create(ctx, pool)) { 1353 BREAK_TO_DEBUGGER(); 1354 dm_error("DC: failed to create dwbc!\n"); 1355 goto create_fail; 1356 } 1357 1358 if (!dcn303_mmhubbub_create(ctx, pool)) { 1359 BREAK_TO_DEBUGGER(); 1360 dm_error("DC: failed to create mcif_wb!\n"); 1361 goto create_fail; 1362 } 1363 1364 /* AUX and I2C */ 1365 for (i = 0; i < pool->res_cap->num_ddc; i++) { 1366 pool->engines[i] = dcn303_aux_engine_create(ctx, i); 1367 if (pool->engines[i] == NULL) { 1368 BREAK_TO_DEBUGGER(); 1369 dm_error("DC:failed to create aux engine!!\n"); 1370 goto create_fail; 1371 } 1372 pool->hw_i2cs[i] = dcn303_i2c_hw_create(ctx, i); 1373 if (pool->hw_i2cs[i] == NULL) { 1374 BREAK_TO_DEBUGGER(); 1375 dm_error("DC:failed to create hw i2c!!\n"); 1376 goto create_fail; 1377 } 1378 pool->sw_i2cs[i] = NULL; 1379 } 1380 1381 /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */ 1382 if (!resource_construct(num_virtual_links, dc, pool, 1383 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? 1384 &res_create_funcs : &res_create_maximus_funcs))) 1385 goto create_fail; 1386 1387 /* HW Sequencer and Plane caps */ 1388 dcn303_hw_sequencer_construct(dc); 1389 1390 dc->caps.max_planes = pool->pipe_count; 1391 1392 for (i = 0; i < dc->caps.max_planes; ++i) 1393 dc->caps.planes[i] = plane_cap; 1394 1395 dc->cap_funcs = cap_funcs; 1396 1397 if (dc->ctx->dc_bios->fw_info.oem_i2c_present) { 1398 ddc_init_data.ctx = dc->ctx; 1399 ddc_init_data.link = NULL; 1400 ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id; 1401 ddc_init_data.id.enum_id = 0; 1402 ddc_init_data.id.type = OBJECT_TYPE_GENERIC; 1403 pool->oem_device = dal_ddc_service_create(&ddc_init_data); 1404 } else { 1405 pool->oem_device = NULL; 1406 } 1407 1408 return true; 1409 1410 create_fail: 1411 1412 dcn303_resource_destruct(pool); 1413 1414 return false; 1415 } 1416 1417 struct resource_pool *dcn303_create_resource_pool(const struct dc_init_data *init_data, struct dc *dc) 1418 { 1419 struct resource_pool *pool = kzalloc(sizeof(struct resource_pool), GFP_KERNEL); 1420 1421 if (!pool) 1422 return NULL; 1423 1424 if (dcn303_resource_construct(init_data->num_virtual_links, dc, pool)) 1425 return pool; 1426 1427 BREAK_TO_DEBUGGER(); 1428 kfree(pool); 1429 return NULL; 1430 } 1431