1*cd6d421eSAurabindo Pillai /* 2*cd6d421eSAurabindo Pillai * Copyright 2021 Advanced Micro Devices, Inc. 3*cd6d421eSAurabindo Pillai * 4*cd6d421eSAurabindo Pillai * Permission is hereby granted, free of charge, to any person obtaining a 5*cd6d421eSAurabindo Pillai * copy of this software and associated documentation files (the "Software"), 6*cd6d421eSAurabindo Pillai * to deal in the Software without restriction, including without limitation 7*cd6d421eSAurabindo Pillai * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*cd6d421eSAurabindo Pillai * and/or sell copies of the Software, and to permit persons to whom the 9*cd6d421eSAurabindo Pillai * Software is furnished to do so, subject to the following conditions: 10*cd6d421eSAurabindo Pillai * 11*cd6d421eSAurabindo Pillai * The above copyright notice and this permission notice shall be included in 12*cd6d421eSAurabindo Pillai * all copies or substantial portions of the Software. 13*cd6d421eSAurabindo Pillai * 14*cd6d421eSAurabindo Pillai * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*cd6d421eSAurabindo Pillai * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*cd6d421eSAurabindo Pillai * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*cd6d421eSAurabindo Pillai * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*cd6d421eSAurabindo Pillai * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*cd6d421eSAurabindo Pillai * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*cd6d421eSAurabindo Pillai * OTHER DEALINGS IN THE SOFTWARE. 21*cd6d421eSAurabindo Pillai * 22*cd6d421eSAurabindo Pillai * Authors: AMD 23*cd6d421eSAurabindo Pillai * 24*cd6d421eSAurabindo Pillai */ 25*cd6d421eSAurabindo Pillai 26*cd6d421eSAurabindo Pillai #ifndef __DCN303_DCCG_H__ 27*cd6d421eSAurabindo Pillai #define __DCN303_DCCG_H__ 28*cd6d421eSAurabindo Pillai 29*cd6d421eSAurabindo Pillai #include "dcn30/dcn30_dccg.h" 30*cd6d421eSAurabindo Pillai 31*cd6d421eSAurabindo Pillai 32*cd6d421eSAurabindo Pillai #define DCCG_REG_LIST_DCN3_03() \ 33*cd6d421eSAurabindo Pillai SR(DPPCLK_DTO_CTRL),\ 34*cd6d421eSAurabindo Pillai DCCG_SRII(DTO_PARAM, DPPCLK, 0),\ 35*cd6d421eSAurabindo Pillai DCCG_SRII(DTO_PARAM, DPPCLK, 1),\ 36*cd6d421eSAurabindo Pillai SR(REFCLK_CNTL) 37*cd6d421eSAurabindo Pillai 38*cd6d421eSAurabindo Pillai #define DCCG_MASK_SH_LIST_DCN3_03(mask_sh) \ 39*cd6d421eSAurabindo Pillai DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 0, mask_sh),\ 40*cd6d421eSAurabindo Pillai DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 0, mask_sh),\ 41*cd6d421eSAurabindo Pillai DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 1, mask_sh),\ 42*cd6d421eSAurabindo Pillai DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 1, mask_sh),\ 43*cd6d421eSAurabindo Pillai DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_PHASE, mask_sh),\ 44*cd6d421eSAurabindo Pillai DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_MODULO, mask_sh),\ 45*cd6d421eSAurabindo Pillai DCCG_SF(REFCLK_CNTL, REFCLK_CLOCK_EN, mask_sh),\ 46*cd6d421eSAurabindo Pillai DCCG_SF(REFCLK_CNTL, REFCLK_SRC_SEL, mask_sh) 47*cd6d421eSAurabindo Pillai 48*cd6d421eSAurabindo Pillai #endif //__DCN303_DCCG_H__ 49