1 /* 2 * Copyright 2019-2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 27 #include "dm_services.h" 28 #include "dc.h" 29 30 #include "dcn301_init.h" 31 32 #include "resource.h" 33 #include "include/irq_service_interface.h" 34 #include "dcn30/dcn30_resource.h" 35 #include "dcn301_resource.h" 36 37 #include "dcn20/dcn20_resource.h" 38 39 #include "dcn10/dcn10_ipp.h" 40 #include "dcn301/dcn301_hubbub.h" 41 #include "dcn30/dcn30_mpc.h" 42 #include "dcn30/dcn30_hubp.h" 43 #include "irq/dcn30/irq_service_dcn30.h" 44 #include "dcn30/dcn30_dpp.h" 45 #include "dcn30/dcn30_optc.h" 46 #include "dcn20/dcn20_hwseq.h" 47 #include "dcn30/dcn30_hwseq.h" 48 #include "dce110/dce110_hw_sequencer.h" 49 #include "dcn30/dcn30_opp.h" 50 #include "dcn20/dcn20_dsc.h" 51 #include "dcn30/dcn30_vpg.h" 52 #include "dcn30/dcn30_afmt.h" 53 #include "dce/dce_clock_source.h" 54 #include "dce/dce_audio.h" 55 #include "dce/dce_hwseq.h" 56 #include "clk_mgr.h" 57 #include "virtual/virtual_stream_encoder.h" 58 #include "dce110/dce110_resource.h" 59 #include "dml/display_mode_vba.h" 60 #include "dcn301/dcn301_dccg.h" 61 #include "dcn10/dcn10_resource.h" 62 #include "dcn30/dcn30_dio_stream_encoder.h" 63 #include "dcn301/dcn301_dio_link_encoder.h" 64 #include "dcn301_panel_cntl.h" 65 66 #include "vangogh_ip_offset.h" 67 68 #include "dcn30/dcn30_dwb.h" 69 #include "dcn30/dcn30_mmhubbub.h" 70 71 #include "dcn/dcn_3_0_1_offset.h" 72 #include "dcn/dcn_3_0_1_sh_mask.h" 73 74 #include "nbio/nbio_7_2_0_offset.h" 75 76 #include "dcn/dpcs_3_0_0_offset.h" 77 #include "dcn/dpcs_3_0_0_sh_mask.h" 78 79 #include "reg_helper.h" 80 #include "dce/dmub_abm.h" 81 #include "dce/dce_aux.h" 82 #include "dce/dce_i2c.h" 83 84 #include "dml/dcn30/display_mode_vba_30.h" 85 #include "vm_helper.h" 86 #include "dcn20/dcn20_vmid.h" 87 #include "amdgpu_socbb.h" 88 89 #define TO_DCN301_RES_POOL(pool)\ 90 container_of(pool, struct dcn301_resource_pool, base) 91 92 #define DC_LOGGER_INIT(logger) 93 94 struct _vcs_dpi_ip_params_st dcn3_01_ip = { 95 .odm_capable = 1, 96 .gpuvm_enable = 1, 97 .hostvm_enable = 1, 98 .gpuvm_max_page_table_levels = 1, 99 .hostvm_max_page_table_levels = 2, 100 .hostvm_cached_page_table_levels = 0, 101 .pte_group_size_bytes = 2048, 102 .num_dsc = 3, 103 .rob_buffer_size_kbytes = 184, 104 .det_buffer_size_kbytes = 184, 105 .dpte_buffer_size_in_pte_reqs_luma = 64, 106 .dpte_buffer_size_in_pte_reqs_chroma = 32, 107 .pde_proc_buffer_size_64k_reqs = 48, 108 .dpp_output_buffer_pixels = 2560, 109 .opp_output_buffer_lines = 1, 110 .pixel_chunk_size_kbytes = 8, 111 .meta_chunk_size_kbytes = 2, 112 .writeback_chunk_size_kbytes = 8, 113 .line_buffer_size_bits = 789504, 114 .is_line_buffer_bpp_fixed = 0, // ? 115 .line_buffer_fixed_bpp = 48, // ? 116 .dcc_supported = true, 117 .writeback_interface_buffer_size_kbytes = 90, 118 .writeback_line_buffer_buffer_size = 656640, 119 .max_line_buffer_lines = 12, 120 .writeback_luma_buffer_size_kbytes = 12, // writeback_line_buffer_buffer_size = 656640 121 .writeback_chroma_buffer_size_kbytes = 8, 122 .writeback_chroma_line_buffer_width_pixels = 4, 123 .writeback_max_hscl_ratio = 1, 124 .writeback_max_vscl_ratio = 1, 125 .writeback_min_hscl_ratio = 1, 126 .writeback_min_vscl_ratio = 1, 127 .writeback_max_hscl_taps = 1, 128 .writeback_max_vscl_taps = 1, 129 .writeback_line_buffer_luma_buffer_size = 0, 130 .writeback_line_buffer_chroma_buffer_size = 14643, 131 .cursor_buffer_size = 8, 132 .cursor_chunk_size = 2, 133 .max_num_otg = 4, 134 .max_num_dpp = 4, 135 .max_num_wb = 1, 136 .max_dchub_pscl_bw_pix_per_clk = 4, 137 .max_pscl_lb_bw_pix_per_clk = 2, 138 .max_lb_vscl_bw_pix_per_clk = 4, 139 .max_vscl_hscl_bw_pix_per_clk = 4, 140 .max_hscl_ratio = 6, 141 .max_vscl_ratio = 6, 142 .hscl_mults = 4, 143 .vscl_mults = 4, 144 .max_hscl_taps = 8, 145 .max_vscl_taps = 8, 146 .dispclk_ramp_margin_percent = 1, 147 .underscan_factor = 1.11, 148 .min_vblank_lines = 32, 149 .dppclk_delay_subtotal = 46, 150 .dynamic_metadata_vm_enabled = true, 151 .dppclk_delay_scl_lb_only = 16, 152 .dppclk_delay_scl = 50, 153 .dppclk_delay_cnvc_formatter = 27, 154 .dppclk_delay_cnvc_cursor = 6, 155 .dispclk_delay_subtotal = 119, 156 .dcfclk_cstate_latency = 5.2, // SRExitTime 157 .max_inter_dcn_tile_repeaters = 8, 158 .max_num_hdmi_frl_outputs = 0, 159 .odm_combine_4to1_supported = true, 160 161 .xfc_supported = false, 162 .xfc_fill_bw_overhead_percent = 10.0, 163 .xfc_fill_constant_bytes = 0, 164 .gfx7_compat_tiling_supported = 0, 165 .number_of_cursors = 1, 166 }; 167 168 struct _vcs_dpi_soc_bounding_box_st dcn3_01_soc = { 169 .clock_limits = { 170 { 171 .state = 0, 172 .dram_speed_mts = 2400.0, 173 .fabricclk_mhz = 600, 174 .socclk_mhz = 278.0, 175 .dcfclk_mhz = 400.0, 176 .dscclk_mhz = 206.0, 177 .dppclk_mhz = 1015.0, 178 .dispclk_mhz = 1015.0, 179 .phyclk_mhz = 600.0, 180 }, 181 { 182 .state = 1, 183 .dram_speed_mts = 2400.0, 184 .fabricclk_mhz = 688, 185 .socclk_mhz = 278.0, 186 .dcfclk_mhz = 400.0, 187 .dscclk_mhz = 206.0, 188 .dppclk_mhz = 1015.0, 189 .dispclk_mhz = 1015.0, 190 .phyclk_mhz = 600.0, 191 }, 192 { 193 .state = 2, 194 .dram_speed_mts = 4267.0, 195 .fabricclk_mhz = 1067, 196 .socclk_mhz = 278.0, 197 .dcfclk_mhz = 608.0, 198 .dscclk_mhz = 296.0, 199 .dppclk_mhz = 1015.0, 200 .dispclk_mhz = 1015.0, 201 .phyclk_mhz = 810.0, 202 }, 203 204 { 205 .state = 3, 206 .dram_speed_mts = 4267.0, 207 .fabricclk_mhz = 1067, 208 .socclk_mhz = 715.0, 209 .dcfclk_mhz = 676.0, 210 .dscclk_mhz = 338.0, 211 .dppclk_mhz = 1015.0, 212 .dispclk_mhz = 1015.0, 213 .phyclk_mhz = 810.0, 214 }, 215 216 { 217 .state = 4, 218 .dram_speed_mts = 4267.0, 219 .fabricclk_mhz = 1067, 220 .socclk_mhz = 953.0, 221 .dcfclk_mhz = 810.0, 222 .dscclk_mhz = 338.0, 223 .dppclk_mhz = 1015.0, 224 .dispclk_mhz = 1015.0, 225 .phyclk_mhz = 810.0, 226 }, 227 }, 228 229 .sr_exit_time_us = 9.0, 230 .sr_enter_plus_exit_time_us = 11.0, 231 .urgent_latency_us = 4.0, 232 .urgent_latency_pixel_data_only_us = 4.0, 233 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0, 234 .urgent_latency_vm_data_only_us = 4.0, 235 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096, 236 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096, 237 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096, 238 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 80.0, 239 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 75.0, 240 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0, 241 .max_avg_sdp_bw_use_normal_percent = 60.0, 242 .max_avg_dram_bw_use_normal_percent = 60.0, 243 .writeback_latency_us = 12.0, 244 .max_request_size_bytes = 256, 245 .dram_channel_width_bytes = 4, 246 .fabric_datapath_to_dcn_data_return_bytes = 32, 247 .dcn_downspread_percent = 0.5, 248 .downspread_percent = 0.38, 249 .dram_page_open_time_ns = 50.0, 250 .dram_rw_turnaround_time_ns = 17.5, 251 .dram_return_buffer_per_channel_bytes = 8192, 252 .round_trip_ping_latency_dcfclk_cycles = 191, 253 .urgent_out_of_order_return_per_channel_bytes = 4096, 254 .channel_interleave_bytes = 256, 255 .num_banks = 8, 256 .num_chans = 4, 257 .gpuvm_min_page_size_bytes = 4096, 258 .hostvm_min_page_size_bytes = 4096, 259 .dram_clock_change_latency_us = 23.84, 260 .writeback_dram_clock_change_latency_us = 23.0, 261 .return_bus_width_bytes = 64, 262 .dispclk_dppclk_vco_speed_mhz = 3550, 263 .xfc_bus_transport_time_us = 20, // ? 264 .xfc_xbuf_latency_tolerance_us = 4, // ? 265 .use_urgent_burst_bw = 1, // ? 266 .num_states = 5, 267 .do_urgent_latency_adjustment = false, 268 .urgent_latency_adjustment_fabric_clock_component_us = 0, 269 .urgent_latency_adjustment_fabric_clock_reference_mhz = 0, 270 }; 271 272 enum dcn301_clk_src_array_id { 273 DCN301_CLK_SRC_PLL0, 274 DCN301_CLK_SRC_PLL1, 275 DCN301_CLK_SRC_PLL2, 276 DCN301_CLK_SRC_PLL3, 277 DCN301_CLK_SRC_TOTAL 278 }; 279 280 /* begin ********************* 281 * macros to expend register list macro defined in HW object header file 282 */ 283 284 /* DCN */ 285 /* TODO awful hack. fixup dcn20_dwb.h */ 286 #undef BASE_INNER 287 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg 288 289 #define BASE(seg) BASE_INNER(seg) 290 291 #define SR(reg_name)\ 292 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ 293 mm ## reg_name 294 295 #define SRI(reg_name, block, id)\ 296 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 297 mm ## block ## id ## _ ## reg_name 298 299 #define SRI2(reg_name, block, id)\ 300 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ 301 mm ## reg_name 302 303 #define SRIR(var_name, reg_name, block, id)\ 304 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 305 mm ## block ## id ## _ ## reg_name 306 307 #define SRII(reg_name, block, id)\ 308 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 309 mm ## block ## id ## _ ## reg_name 310 311 #define SRII2(reg_name_pre, reg_name_post, id)\ 312 .reg_name_pre ## _ ## reg_name_post[id] = BASE(mm ## reg_name_pre \ 313 ## id ## _ ## reg_name_post ## _BASE_IDX) + \ 314 mm ## reg_name_pre ## id ## _ ## reg_name_post 315 316 #define SRII_MPC_RMU(reg_name, block, id)\ 317 .RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 318 mm ## block ## id ## _ ## reg_name 319 320 #define SRII_DWB(reg_name, temp_name, block, id)\ 321 .reg_name[id] = BASE(mm ## block ## id ## _ ## temp_name ## _BASE_IDX) + \ 322 mm ## block ## id ## _ ## temp_name 323 324 #define DCCG_SRII(reg_name, block, id)\ 325 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 326 mm ## block ## id ## _ ## reg_name 327 328 #define VUPDATE_SRII(reg_name, block, id)\ 329 .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \ 330 mm ## reg_name ## _ ## block ## id 331 332 /* NBIO */ 333 #define NBIO_BASE_INNER(seg) \ 334 NBIO_BASE__INST0_SEG ## seg 335 336 #define NBIO_BASE(seg) \ 337 NBIO_BASE_INNER(seg) 338 339 #define NBIO_SR(reg_name)\ 340 .reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \ 341 regBIF_BX0_ ## reg_name 342 343 /* MMHUB */ 344 #define MMHUB_BASE_INNER(seg) \ 345 MMHUB_BASE__INST0_SEG ## seg 346 347 #define MMHUB_BASE(seg) \ 348 MMHUB_BASE_INNER(seg) 349 350 #define MMHUB_SR(reg_name)\ 351 .reg_name = MMHUB_BASE(regMM ## reg_name ## _BASE_IDX) + \ 352 regMM ## reg_name 353 354 /* CLOCK */ 355 #define CLK_BASE_INNER(seg) \ 356 CLK_BASE__INST0_SEG ## seg 357 358 #define CLK_BASE(seg) \ 359 CLK_BASE_INNER(seg) 360 361 #define CLK_SRI(reg_name, block, inst)\ 362 .reg_name = CLK_BASE(mm ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \ 363 mm ## block ## _ ## inst ## _ ## reg_name 364 365 static const struct bios_registers bios_regs = { 366 NBIO_SR(BIOS_SCRATCH_3), 367 NBIO_SR(BIOS_SCRATCH_6) 368 }; 369 370 #define clk_src_regs(index, pllid)\ 371 [index] = {\ 372 CS_COMMON_REG_LIST_DCN3_01(index, pllid),\ 373 } 374 375 static const struct dce110_clk_src_regs clk_src_regs[] = { 376 clk_src_regs(0, A), 377 clk_src_regs(1, B), 378 clk_src_regs(2, C), 379 clk_src_regs(3, D) 380 }; 381 382 static const struct dce110_clk_src_shift cs_shift = { 383 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 384 }; 385 386 static const struct dce110_clk_src_mask cs_mask = { 387 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 388 }; 389 390 #define abm_regs(id)\ 391 [id] = {\ 392 ABM_DCN301_REG_LIST(id)\ 393 } 394 395 static const struct dce_abm_registers abm_regs[] = { 396 abm_regs(0), 397 abm_regs(1), 398 abm_regs(2), 399 abm_regs(3), 400 }; 401 402 static const struct dce_abm_shift abm_shift = { 403 ABM_MASK_SH_LIST_DCN30(__SHIFT) 404 }; 405 406 static const struct dce_abm_mask abm_mask = { 407 ABM_MASK_SH_LIST_DCN30(_MASK) 408 }; 409 410 #define audio_regs(id)\ 411 [id] = {\ 412 AUD_COMMON_REG_LIST(id)\ 413 } 414 415 static const struct dce_audio_registers audio_regs[] = { 416 audio_regs(0), 417 audio_regs(1), 418 audio_regs(2), 419 audio_regs(3), 420 audio_regs(4), 421 audio_regs(5), 422 audio_regs(6) 423 }; 424 425 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 426 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 427 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 428 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 429 430 static const struct dce_audio_shift audio_shift = { 431 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 432 }; 433 434 static const struct dce_audio_mask audio_mask = { 435 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 436 }; 437 438 #define vpg_regs(id)\ 439 [id] = {\ 440 VPG_DCN3_REG_LIST(id)\ 441 } 442 443 static const struct dcn30_vpg_registers vpg_regs[] = { 444 vpg_regs(0), 445 vpg_regs(1), 446 vpg_regs(2), 447 vpg_regs(3), 448 }; 449 450 static const struct dcn30_vpg_shift vpg_shift = { 451 DCN3_VPG_MASK_SH_LIST(__SHIFT) 452 }; 453 454 static const struct dcn30_vpg_mask vpg_mask = { 455 DCN3_VPG_MASK_SH_LIST(_MASK) 456 }; 457 458 #define afmt_regs(id)\ 459 [id] = {\ 460 AFMT_DCN3_REG_LIST(id)\ 461 } 462 463 static const struct dcn30_afmt_registers afmt_regs[] = { 464 afmt_regs(0), 465 afmt_regs(1), 466 afmt_regs(2), 467 afmt_regs(3), 468 }; 469 470 static const struct dcn30_afmt_shift afmt_shift = { 471 DCN3_AFMT_MASK_SH_LIST(__SHIFT) 472 }; 473 474 static const struct dcn30_afmt_mask afmt_mask = { 475 DCN3_AFMT_MASK_SH_LIST(_MASK) 476 }; 477 478 #define stream_enc_regs(id)\ 479 [id] = {\ 480 SE_DCN3_REG_LIST(id)\ 481 } 482 483 static const struct dcn10_stream_enc_registers stream_enc_regs[] = { 484 stream_enc_regs(0), 485 stream_enc_regs(1), 486 stream_enc_regs(2), 487 stream_enc_regs(3), 488 }; 489 490 static const struct dcn10_stream_encoder_shift se_shift = { 491 SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 492 }; 493 494 static const struct dcn10_stream_encoder_mask se_mask = { 495 SE_COMMON_MASK_SH_LIST_DCN30(_MASK) 496 }; 497 498 499 #define aux_regs(id)\ 500 [id] = {\ 501 DCN2_AUX_REG_LIST(id)\ 502 } 503 504 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { 505 aux_regs(0), 506 aux_regs(1), 507 aux_regs(2), 508 aux_regs(3), 509 }; 510 511 #define hpd_regs(id)\ 512 [id] = {\ 513 HPD_REG_LIST(id)\ 514 } 515 516 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { 517 hpd_regs(0), 518 hpd_regs(1), 519 hpd_regs(2), 520 hpd_regs(3), 521 }; 522 523 524 #define link_regs(id, phyid)\ 525 [id] = {\ 526 LE_DCN301_REG_LIST(id), \ 527 UNIPHY_DCN2_REG_LIST(phyid), \ 528 DPCS_DCN2_REG_LIST(id), \ 529 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \ 530 } 531 532 static const struct dce110_aux_registers_shift aux_shift = { 533 DCN_AUX_MASK_SH_LIST(__SHIFT) 534 }; 535 536 static const struct dce110_aux_registers_mask aux_mask = { 537 DCN_AUX_MASK_SH_LIST(_MASK) 538 }; 539 540 static const struct dcn10_link_enc_registers link_enc_regs[] = { 541 link_regs(0, A), 542 link_regs(1, B), 543 link_regs(2, C), 544 link_regs(3, D), 545 }; 546 547 static const struct dcn10_link_enc_shift le_shift = { 548 LINK_ENCODER_MASK_SH_LIST_DCN301(__SHIFT),\ 549 DPCS_DCN2_MASK_SH_LIST(__SHIFT) 550 }; 551 552 static const struct dcn10_link_enc_mask le_mask = { 553 LINK_ENCODER_MASK_SH_LIST_DCN301(_MASK),\ 554 DPCS_DCN2_MASK_SH_LIST(_MASK) 555 }; 556 557 #define panel_cntl_regs(id)\ 558 [id] = {\ 559 DCN301_PANEL_CNTL_REG_LIST(id),\ 560 } 561 562 static const struct dce_panel_cntl_registers panel_cntl_regs[] = { 563 panel_cntl_regs(0), 564 panel_cntl_regs(1), 565 }; 566 567 static const struct dcn301_panel_cntl_shift panel_cntl_shift = { 568 DCN301_PANEL_CNTL_MASK_SH_LIST(__SHIFT) 569 }; 570 571 static const struct dcn301_panel_cntl_mask panel_cntl_mask = { 572 DCN301_PANEL_CNTL_MASK_SH_LIST(_MASK) 573 }; 574 575 #define dpp_regs(id)\ 576 [id] = {\ 577 DPP_REG_LIST_DCN30(id),\ 578 } 579 580 static const struct dcn3_dpp_registers dpp_regs[] = { 581 dpp_regs(0), 582 dpp_regs(1), 583 dpp_regs(2), 584 dpp_regs(3), 585 }; 586 587 static const struct dcn3_dpp_shift tf_shift = { 588 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT) 589 }; 590 591 static const struct dcn3_dpp_mask tf_mask = { 592 DPP_REG_LIST_SH_MASK_DCN30(_MASK) 593 }; 594 595 #define opp_regs(id)\ 596 [id] = {\ 597 OPP_REG_LIST_DCN30(id),\ 598 } 599 600 static const struct dcn20_opp_registers opp_regs[] = { 601 opp_regs(0), 602 opp_regs(1), 603 opp_regs(2), 604 opp_regs(3), 605 }; 606 607 static const struct dcn20_opp_shift opp_shift = { 608 OPP_MASK_SH_LIST_DCN20(__SHIFT) 609 }; 610 611 static const struct dcn20_opp_mask opp_mask = { 612 OPP_MASK_SH_LIST_DCN20(_MASK) 613 }; 614 615 #define aux_engine_regs(id)\ 616 [id] = {\ 617 AUX_COMMON_REG_LIST0(id), \ 618 .AUXN_IMPCAL = 0, \ 619 .AUXP_IMPCAL = 0, \ 620 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \ 621 } 622 623 static const struct dce110_aux_registers aux_engine_regs[] = { 624 aux_engine_regs(0), 625 aux_engine_regs(1), 626 aux_engine_regs(2), 627 aux_engine_regs(3), 628 }; 629 630 #define dwbc_regs_dcn3(id)\ 631 [id] = {\ 632 DWBC_COMMON_REG_LIST_DCN30(id),\ 633 } 634 635 static const struct dcn30_dwbc_registers dwbc30_regs[] = { 636 dwbc_regs_dcn3(0), 637 }; 638 639 static const struct dcn30_dwbc_shift dwbc30_shift = { 640 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 641 }; 642 643 static const struct dcn30_dwbc_mask dwbc30_mask = { 644 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK) 645 }; 646 647 #define mcif_wb_regs_dcn3(id)\ 648 [id] = {\ 649 MCIF_WB_COMMON_REG_LIST_DCN30(id),\ 650 } 651 652 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = { 653 mcif_wb_regs_dcn3(0) 654 }; 655 656 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = { 657 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 658 }; 659 660 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { 661 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK) 662 }; 663 664 #define dsc_regsDCN20(id)\ 665 [id] = {\ 666 DSC_REG_LIST_DCN20(id)\ 667 } 668 669 static const struct dcn20_dsc_registers dsc_regs[] = { 670 dsc_regsDCN20(0), 671 dsc_regsDCN20(1), 672 dsc_regsDCN20(2), 673 }; 674 675 static const struct dcn20_dsc_shift dsc_shift = { 676 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) 677 }; 678 679 static const struct dcn20_dsc_mask dsc_mask = { 680 DSC_REG_LIST_SH_MASK_DCN20(_MASK) 681 }; 682 683 static const struct dcn30_mpc_registers mpc_regs = { 684 MPC_REG_LIST_DCN3_0(0), 685 MPC_REG_LIST_DCN3_0(1), 686 MPC_REG_LIST_DCN3_0(2), 687 MPC_REG_LIST_DCN3_0(3), 688 MPC_OUT_MUX_REG_LIST_DCN3_0(0), 689 MPC_OUT_MUX_REG_LIST_DCN3_0(1), 690 MPC_OUT_MUX_REG_LIST_DCN3_0(2), 691 MPC_OUT_MUX_REG_LIST_DCN3_0(3), 692 MPC_RMU_GLOBAL_REG_LIST_DCN3AG, 693 MPC_RMU_REG_LIST_DCN3AG(0), 694 MPC_RMU_REG_LIST_DCN3AG(1), 695 MPC_DWB_MUX_REG_LIST_DCN3_0(0), 696 }; 697 698 static const struct dcn30_mpc_shift mpc_shift = { 699 MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 700 }; 701 702 static const struct dcn30_mpc_mask mpc_mask = { 703 MPC_COMMON_MASK_SH_LIST_DCN30(_MASK) 704 }; 705 706 #define optc_regs(id)\ 707 [id] = {OPTC_COMMON_REG_LIST_DCN3_0(id)} 708 709 710 static const struct dcn_optc_registers optc_regs[] = { 711 optc_regs(0), 712 optc_regs(1), 713 optc_regs(2), 714 optc_regs(3), 715 }; 716 717 static const struct dcn_optc_shift optc_shift = { 718 OPTC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 719 }; 720 721 static const struct dcn_optc_mask optc_mask = { 722 OPTC_COMMON_MASK_SH_LIST_DCN30(_MASK) 723 }; 724 725 #define hubp_regs(id)\ 726 [id] = {\ 727 HUBP_REG_LIST_DCN30(id)\ 728 } 729 730 static const struct dcn_hubp2_registers hubp_regs[] = { 731 hubp_regs(0), 732 hubp_regs(1), 733 hubp_regs(2), 734 hubp_regs(3), 735 }; 736 737 static const struct dcn_hubp2_shift hubp_shift = { 738 HUBP_MASK_SH_LIST_DCN30(__SHIFT) 739 }; 740 741 static const struct dcn_hubp2_mask hubp_mask = { 742 HUBP_MASK_SH_LIST_DCN30(_MASK) 743 }; 744 745 static const struct dcn_hubbub_registers hubbub_reg = { 746 HUBBUB_REG_LIST_DCN301(0) 747 }; 748 749 static const struct dcn_hubbub_shift hubbub_shift = { 750 HUBBUB_MASK_SH_LIST_DCN301(__SHIFT) 751 }; 752 753 static const struct dcn_hubbub_mask hubbub_mask = { 754 HUBBUB_MASK_SH_LIST_DCN301(_MASK) 755 }; 756 757 static const struct dccg_registers dccg_regs = { 758 DCCG_REG_LIST_DCN301() 759 }; 760 761 static const struct dccg_shift dccg_shift = { 762 DCCG_MASK_SH_LIST_DCN301(__SHIFT) 763 }; 764 765 static const struct dccg_mask dccg_mask = { 766 DCCG_MASK_SH_LIST_DCN301(_MASK) 767 }; 768 769 static const struct dce_hwseq_registers hwseq_reg = { 770 HWSEQ_DCN301_REG_LIST() 771 }; 772 773 static const struct dce_hwseq_shift hwseq_shift = { 774 HWSEQ_DCN301_MASK_SH_LIST(__SHIFT) 775 }; 776 777 static const struct dce_hwseq_mask hwseq_mask = { 778 HWSEQ_DCN301_MASK_SH_LIST(_MASK) 779 }; 780 #define vmid_regs(id)\ 781 [id] = {\ 782 DCN20_VMID_REG_LIST(id)\ 783 } 784 785 static const struct dcn_vmid_registers vmid_regs[] = { 786 vmid_regs(0), 787 vmid_regs(1), 788 vmid_regs(2), 789 vmid_regs(3), 790 vmid_regs(4), 791 vmid_regs(5), 792 vmid_regs(6), 793 vmid_regs(7), 794 vmid_regs(8), 795 vmid_regs(9), 796 vmid_regs(10), 797 vmid_regs(11), 798 vmid_regs(12), 799 vmid_regs(13), 800 vmid_regs(14), 801 vmid_regs(15) 802 }; 803 804 static const struct dcn20_vmid_shift vmid_shifts = { 805 DCN20_VMID_MASK_SH_LIST(__SHIFT) 806 }; 807 808 static const struct dcn20_vmid_mask vmid_masks = { 809 DCN20_VMID_MASK_SH_LIST(_MASK) 810 }; 811 812 static const struct resource_caps res_cap_dcn301 = { 813 .num_timing_generator = 4, 814 .num_opp = 4, 815 .num_video_plane = 4, 816 .num_audio = 4, 817 .num_stream_encoder = 4, 818 .num_pll = 4, 819 .num_dwb = 1, 820 .num_ddc = 4, 821 .num_vmid = 16, 822 .num_mpc_3dlut = 2, 823 .num_dsc = 3, 824 }; 825 826 static const struct dc_plane_cap plane_cap = { 827 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 828 .blends_with_above = true, 829 .blends_with_below = true, 830 .per_pixel_alpha = true, 831 832 .pixel_format_support = { 833 .argb8888 = true, 834 .nv12 = true, 835 .fp16 = true, 836 .p010 = false, 837 .ayuv = false, 838 }, 839 840 .max_upscale_factor = { 841 .argb8888 = 16000, 842 .nv12 = 16000, 843 .fp16 = 16000 844 }, 845 846 .max_downscale_factor = { 847 .argb8888 = 600, 848 .nv12 = 600, 849 .fp16 = 600 850 }, 851 64, 852 64 853 }; 854 855 static const struct dc_debug_options debug_defaults_drv = { 856 .disable_dmcu = true, 857 .force_abm_enable = false, 858 .timing_trace = false, 859 .clock_trace = true, 860 .disable_dpp_power_gate = false, 861 .disable_hubp_power_gate = false, 862 .disable_clock_gate = true, 863 .disable_pplib_clock_request = true, 864 .disable_pplib_wm_range = true, 865 .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP, 866 .force_single_disp_pipe_split = false, 867 .disable_dcc = DCC_ENABLE, 868 .vsr_support = true, 869 .performance_trace = false, 870 .max_downscale_src_width = 7680,/*upto 8K*/ 871 .scl_reset_length10 = true, 872 .sanity_checks = false, 873 .underflow_assert_delay_us = 0xFFFFFFFF, 874 .dwb_fi_phase = -1, // -1 = disable 875 .dmub_command_table = true, 876 .use_max_lb = false, 877 }; 878 879 static const struct dc_debug_options debug_defaults_diags = { 880 .disable_dmcu = true, 881 .force_abm_enable = false, 882 .timing_trace = true, 883 .clock_trace = true, 884 .disable_dpp_power_gate = false, 885 .disable_hubp_power_gate = false, 886 .disable_clock_gate = true, 887 .disable_pplib_clock_request = true, 888 .disable_pplib_wm_range = true, 889 .disable_stutter = true, 890 .scl_reset_length10 = true, 891 .dwb_fi_phase = -1, // -1 = disable 892 .dmub_command_table = true, 893 .use_max_lb = false, 894 }; 895 896 void dcn301_dpp_destroy(struct dpp **dpp) 897 { 898 kfree(TO_DCN20_DPP(*dpp)); 899 *dpp = NULL; 900 } 901 902 struct dpp *dcn301_dpp_create( 903 struct dc_context *ctx, 904 uint32_t inst) 905 { 906 struct dcn3_dpp *dpp = 907 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL); 908 909 if (!dpp) 910 return NULL; 911 912 if (dpp3_construct(dpp, ctx, inst, 913 &dpp_regs[inst], &tf_shift, &tf_mask)) 914 return &dpp->base; 915 916 BREAK_TO_DEBUGGER(); 917 kfree(dpp); 918 return NULL; 919 } 920 struct output_pixel_processor *dcn301_opp_create( 921 struct dc_context *ctx, uint32_t inst) 922 { 923 struct dcn20_opp *opp = 924 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); 925 926 if (!opp) { 927 BREAK_TO_DEBUGGER(); 928 return NULL; 929 } 930 931 dcn20_opp_construct(opp, ctx, inst, 932 &opp_regs[inst], &opp_shift, &opp_mask); 933 return &opp->base; 934 } 935 936 struct dce_aux *dcn301_aux_engine_create( 937 struct dc_context *ctx, 938 uint32_t inst) 939 { 940 struct aux_engine_dce110 *aux_engine = 941 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 942 943 if (!aux_engine) 944 return NULL; 945 946 dce110_aux_engine_construct(aux_engine, ctx, inst, 947 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 948 &aux_engine_regs[inst], 949 &aux_mask, 950 &aux_shift, 951 ctx->dc->caps.extended_aux_timeout_support); 952 953 return &aux_engine->base; 954 } 955 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 956 957 static const struct dce_i2c_registers i2c_hw_regs[] = { 958 i2c_inst_regs(1), 959 i2c_inst_regs(2), 960 i2c_inst_regs(3), 961 i2c_inst_regs(4), 962 }; 963 964 static const struct dce_i2c_shift i2c_shifts = { 965 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT) 966 }; 967 968 static const struct dce_i2c_mask i2c_masks = { 969 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK) 970 }; 971 972 struct dce_i2c_hw *dcn301_i2c_hw_create( 973 struct dc_context *ctx, 974 uint32_t inst) 975 { 976 struct dce_i2c_hw *dce_i2c_hw = 977 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 978 979 if (!dce_i2c_hw) 980 return NULL; 981 982 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, 983 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 984 985 return dce_i2c_hw; 986 } 987 static struct mpc *dcn301_mpc_create( 988 struct dc_context *ctx, 989 int num_mpcc, 990 int num_rmu) 991 { 992 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), 993 GFP_KERNEL); 994 995 if (!mpc30) 996 return NULL; 997 998 dcn30_mpc_construct(mpc30, ctx, 999 &mpc_regs, 1000 &mpc_shift, 1001 &mpc_mask, 1002 num_mpcc, 1003 num_rmu); 1004 1005 return &mpc30->base; 1006 } 1007 1008 struct hubbub *dcn301_hubbub_create(struct dc_context *ctx) 1009 { 1010 int i; 1011 1012 struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub), 1013 GFP_KERNEL); 1014 1015 if (!hubbub3) 1016 return NULL; 1017 1018 hubbub301_construct(hubbub3, ctx, 1019 &hubbub_reg, 1020 &hubbub_shift, 1021 &hubbub_mask); 1022 1023 1024 for (i = 0; i < res_cap_dcn301.num_vmid; i++) { 1025 struct dcn20_vmid *vmid = &hubbub3->vmid[i]; 1026 1027 vmid->ctx = ctx; 1028 1029 vmid->regs = &vmid_regs[i]; 1030 vmid->shifts = &vmid_shifts; 1031 vmid->masks = &vmid_masks; 1032 } 1033 1034 hubbub3->num_vmid = res_cap_dcn301.num_vmid; 1035 1036 return &hubbub3->base; 1037 } 1038 1039 struct timing_generator *dcn301_timing_generator_create( 1040 struct dc_context *ctx, 1041 uint32_t instance) 1042 { 1043 struct optc *tgn10 = 1044 kzalloc(sizeof(struct optc), GFP_KERNEL); 1045 1046 if (!tgn10) 1047 return NULL; 1048 1049 tgn10->base.inst = instance; 1050 tgn10->base.ctx = ctx; 1051 1052 tgn10->tg_regs = &optc_regs[instance]; 1053 tgn10->tg_shift = &optc_shift; 1054 tgn10->tg_mask = &optc_mask; 1055 1056 dcn30_timing_generator_init(tgn10); 1057 1058 return &tgn10->base; 1059 } 1060 1061 static const struct encoder_feature_support link_enc_feature = { 1062 .max_hdmi_deep_color = COLOR_DEPTH_121212, 1063 .max_hdmi_pixel_clock = 600000, 1064 .hdmi_ycbcr420_supported = true, 1065 .dp_ycbcr420_supported = true, 1066 .fec_supported = true, 1067 .flags.bits.IS_HBR2_CAPABLE = true, 1068 .flags.bits.IS_HBR3_CAPABLE = true, 1069 .flags.bits.IS_TPS3_CAPABLE = true, 1070 .flags.bits.IS_TPS4_CAPABLE = true 1071 }; 1072 1073 struct link_encoder *dcn301_link_encoder_create( 1074 const struct encoder_init_data *enc_init_data) 1075 { 1076 struct dcn20_link_encoder *enc20 = 1077 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 1078 1079 if (!enc20) 1080 return NULL; 1081 1082 dcn301_link_encoder_construct(enc20, 1083 enc_init_data, 1084 &link_enc_feature, 1085 &link_enc_regs[enc_init_data->transmitter], 1086 &link_enc_aux_regs[enc_init_data->channel - 1], 1087 &link_enc_hpd_regs[enc_init_data->hpd_source], 1088 &le_shift, 1089 &le_mask); 1090 1091 return &enc20->enc10.base; 1092 } 1093 1094 struct panel_cntl *dcn301_panel_cntl_create(const struct panel_cntl_init_data *init_data) 1095 { 1096 struct dcn301_panel_cntl *panel_cntl = 1097 kzalloc(sizeof(struct dcn301_panel_cntl), GFP_KERNEL); 1098 1099 if (!panel_cntl) 1100 return NULL; 1101 1102 dcn301_panel_cntl_construct(panel_cntl, 1103 init_data, 1104 &panel_cntl_regs[init_data->inst], 1105 &panel_cntl_shift, 1106 &panel_cntl_mask); 1107 1108 return &panel_cntl->base; 1109 } 1110 1111 1112 #define CTX ctx 1113 1114 #define REG(reg_name) \ 1115 (DCN_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name) 1116 1117 static uint32_t read_pipe_fuses(struct dc_context *ctx) 1118 { 1119 uint32_t value = REG_READ(CC_DC_PIPE_DIS); 1120 /* RV1 support max 4 pipes */ 1121 value = value & 0xf; 1122 return value; 1123 } 1124 1125 1126 static void read_dce_straps( 1127 struct dc_context *ctx, 1128 struct resource_straps *straps) 1129 { 1130 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX), 1131 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 1132 1133 } 1134 1135 static struct audio *dcn301_create_audio( 1136 struct dc_context *ctx, unsigned int inst) 1137 { 1138 return dce_audio_create(ctx, inst, 1139 &audio_regs[inst], &audio_shift, &audio_mask); 1140 } 1141 1142 static struct vpg *dcn301_vpg_create( 1143 struct dc_context *ctx, 1144 uint32_t inst) 1145 { 1146 struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL); 1147 1148 if (!vpg3) 1149 return NULL; 1150 1151 vpg3_construct(vpg3, ctx, inst, 1152 &vpg_regs[inst], 1153 &vpg_shift, 1154 &vpg_mask); 1155 1156 return &vpg3->base; 1157 } 1158 1159 static struct afmt *dcn301_afmt_create( 1160 struct dc_context *ctx, 1161 uint32_t inst) 1162 { 1163 struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL); 1164 1165 if (!afmt3) 1166 return NULL; 1167 1168 afmt3_construct(afmt3, ctx, inst, 1169 &afmt_regs[inst], 1170 &afmt_shift, 1171 &afmt_mask); 1172 1173 return &afmt3->base; 1174 } 1175 1176 struct stream_encoder *dcn301_stream_encoder_create( 1177 enum engine_id eng_id, 1178 struct dc_context *ctx) 1179 { 1180 struct dcn10_stream_encoder *enc1; 1181 struct vpg *vpg; 1182 struct afmt *afmt; 1183 int vpg_inst; 1184 int afmt_inst; 1185 1186 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */ 1187 if (eng_id <= ENGINE_ID_DIGF) { 1188 vpg_inst = eng_id; 1189 afmt_inst = eng_id; 1190 } else 1191 return NULL; 1192 1193 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 1194 vpg = dcn301_vpg_create(ctx, vpg_inst); 1195 afmt = dcn301_afmt_create(ctx, afmt_inst); 1196 1197 if (!enc1 || !vpg || !afmt) 1198 return NULL; 1199 1200 dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, 1201 eng_id, vpg, afmt, 1202 &stream_enc_regs[eng_id], 1203 &se_shift, &se_mask); 1204 1205 return &enc1->base; 1206 } 1207 1208 struct dce_hwseq *dcn301_hwseq_create( 1209 struct dc_context *ctx) 1210 { 1211 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 1212 1213 if (hws) { 1214 hws->ctx = ctx; 1215 hws->regs = &hwseq_reg; 1216 hws->shifts = &hwseq_shift; 1217 hws->masks = &hwseq_mask; 1218 } 1219 return hws; 1220 } 1221 static const struct resource_create_funcs res_create_funcs = { 1222 .read_dce_straps = read_dce_straps, 1223 .create_audio = dcn301_create_audio, 1224 .create_stream_encoder = dcn301_stream_encoder_create, 1225 .create_hwseq = dcn301_hwseq_create, 1226 }; 1227 1228 static const struct resource_create_funcs res_create_maximus_funcs = { 1229 .read_dce_straps = NULL, 1230 .create_audio = NULL, 1231 .create_stream_encoder = NULL, 1232 .create_hwseq = dcn301_hwseq_create, 1233 }; 1234 1235 static void dcn301_destruct(struct dcn301_resource_pool *pool) 1236 { 1237 unsigned int i; 1238 1239 for (i = 0; i < pool->base.stream_enc_count; i++) { 1240 if (pool->base.stream_enc[i] != NULL) { 1241 if (pool->base.stream_enc[i]->vpg != NULL) { 1242 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg)); 1243 pool->base.stream_enc[i]->vpg = NULL; 1244 } 1245 if (pool->base.stream_enc[i]->afmt != NULL) { 1246 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt)); 1247 pool->base.stream_enc[i]->afmt = NULL; 1248 } 1249 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); 1250 pool->base.stream_enc[i] = NULL; 1251 } 1252 } 1253 1254 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 1255 if (pool->base.dscs[i] != NULL) 1256 dcn20_dsc_destroy(&pool->base.dscs[i]); 1257 } 1258 1259 if (pool->base.mpc != NULL) { 1260 kfree(TO_DCN20_MPC(pool->base.mpc)); 1261 pool->base.mpc = NULL; 1262 } 1263 if (pool->base.hubbub != NULL) { 1264 kfree(pool->base.hubbub); 1265 pool->base.hubbub = NULL; 1266 } 1267 for (i = 0; i < pool->base.pipe_count; i++) { 1268 if (pool->base.dpps[i] != NULL) 1269 dcn301_dpp_destroy(&pool->base.dpps[i]); 1270 1271 if (pool->base.ipps[i] != NULL) 1272 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); 1273 1274 if (pool->base.hubps[i] != NULL) { 1275 kfree(TO_DCN20_HUBP(pool->base.hubps[i])); 1276 pool->base.hubps[i] = NULL; 1277 } 1278 1279 if (pool->base.irqs != NULL) { 1280 dal_irq_service_destroy(&pool->base.irqs); 1281 } 1282 } 1283 1284 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1285 if (pool->base.engines[i] != NULL) 1286 dce110_engine_destroy(&pool->base.engines[i]); 1287 if (pool->base.hw_i2cs[i] != NULL) { 1288 kfree(pool->base.hw_i2cs[i]); 1289 pool->base.hw_i2cs[i] = NULL; 1290 } 1291 if (pool->base.sw_i2cs[i] != NULL) { 1292 kfree(pool->base.sw_i2cs[i]); 1293 pool->base.sw_i2cs[i] = NULL; 1294 } 1295 } 1296 1297 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 1298 if (pool->base.opps[i] != NULL) 1299 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); 1300 } 1301 1302 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1303 if (pool->base.timing_generators[i] != NULL) { 1304 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); 1305 pool->base.timing_generators[i] = NULL; 1306 } 1307 } 1308 1309 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { 1310 if (pool->base.dwbc[i] != NULL) { 1311 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); 1312 pool->base.dwbc[i] = NULL; 1313 } 1314 if (pool->base.mcif_wb[i] != NULL) { 1315 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i])); 1316 pool->base.mcif_wb[i] = NULL; 1317 } 1318 } 1319 1320 for (i = 0; i < pool->base.audio_count; i++) { 1321 if (pool->base.audios[i]) 1322 dce_aud_destroy(&pool->base.audios[i]); 1323 } 1324 1325 for (i = 0; i < pool->base.clk_src_count; i++) { 1326 if (pool->base.clock_sources[i] != NULL) { 1327 dcn20_clock_source_destroy(&pool->base.clock_sources[i]); 1328 pool->base.clock_sources[i] = NULL; 1329 } 1330 } 1331 1332 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { 1333 if (pool->base.mpc_lut[i] != NULL) { 1334 dc_3dlut_func_release(pool->base.mpc_lut[i]); 1335 pool->base.mpc_lut[i] = NULL; 1336 } 1337 if (pool->base.mpc_shaper[i] != NULL) { 1338 dc_transfer_func_release(pool->base.mpc_shaper[i]); 1339 pool->base.mpc_shaper[i] = NULL; 1340 } 1341 } 1342 1343 if (pool->base.dp_clock_source != NULL) { 1344 dcn20_clock_source_destroy(&pool->base.dp_clock_source); 1345 pool->base.dp_clock_source = NULL; 1346 } 1347 1348 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1349 if (pool->base.multiple_abms[i] != NULL) 1350 dce_abm_destroy(&pool->base.multiple_abms[i]); 1351 } 1352 1353 if (pool->base.dccg != NULL) 1354 dcn_dccg_destroy(&pool->base.dccg); 1355 } 1356 1357 struct hubp *dcn301_hubp_create( 1358 struct dc_context *ctx, 1359 uint32_t inst) 1360 { 1361 struct dcn20_hubp *hubp2 = 1362 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL); 1363 1364 if (!hubp2) 1365 return NULL; 1366 1367 if (hubp3_construct(hubp2, ctx, inst, 1368 &hubp_regs[inst], &hubp_shift, &hubp_mask)) 1369 return &hubp2->base; 1370 1371 BREAK_TO_DEBUGGER(); 1372 kfree(hubp2); 1373 return NULL; 1374 } 1375 1376 bool dcn301_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) 1377 { 1378 int i; 1379 uint32_t pipe_count = pool->res_cap->num_dwb; 1380 1381 for (i = 0; i < pipe_count; i++) { 1382 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), 1383 GFP_KERNEL); 1384 1385 if (!dwbc30) { 1386 dm_error("DC: failed to create dwbc30!\n"); 1387 return false; 1388 } 1389 1390 dcn30_dwbc_construct(dwbc30, ctx, 1391 &dwbc30_regs[i], 1392 &dwbc30_shift, 1393 &dwbc30_mask, 1394 i); 1395 1396 pool->dwbc[i] = &dwbc30->base; 1397 } 1398 return true; 1399 } 1400 1401 bool dcn301_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) 1402 { 1403 int i; 1404 uint32_t pipe_count = pool->res_cap->num_dwb; 1405 1406 for (i = 0; i < pipe_count; i++) { 1407 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), 1408 GFP_KERNEL); 1409 1410 if (!mcif_wb30) { 1411 dm_error("DC: failed to create mcif_wb30!\n"); 1412 return false; 1413 } 1414 1415 dcn30_mmhubbub_construct(mcif_wb30, ctx, 1416 &mcif_wb30_regs[i], 1417 &mcif_wb30_shift, 1418 &mcif_wb30_mask, 1419 i); 1420 1421 pool->mcif_wb[i] = &mcif_wb30->base; 1422 } 1423 return true; 1424 } 1425 1426 static struct display_stream_compressor *dcn301_dsc_create( 1427 struct dc_context *ctx, uint32_t inst) 1428 { 1429 struct dcn20_dsc *dsc = 1430 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); 1431 1432 if (!dsc) { 1433 BREAK_TO_DEBUGGER(); 1434 return NULL; 1435 } 1436 1437 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 1438 return &dsc->base; 1439 } 1440 1441 1442 static void dcn301_destroy_resource_pool(struct resource_pool **pool) 1443 { 1444 struct dcn301_resource_pool *dcn301_pool = TO_DCN301_RES_POOL(*pool); 1445 1446 dcn301_destruct(dcn301_pool); 1447 kfree(dcn301_pool); 1448 *pool = NULL; 1449 } 1450 1451 static struct clock_source *dcn301_clock_source_create( 1452 struct dc_context *ctx, 1453 struct dc_bios *bios, 1454 enum clock_source_id id, 1455 const struct dce110_clk_src_regs *regs, 1456 bool dp_clk_src) 1457 { 1458 struct dce110_clk_src *clk_src = 1459 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 1460 1461 if (!clk_src) 1462 return NULL; 1463 1464 if (dcn301_clk_src_construct(clk_src, ctx, bios, id, 1465 regs, &cs_shift, &cs_mask)) { 1466 clk_src->base.dp_clk_src = dp_clk_src; 1467 return &clk_src->base; 1468 } 1469 1470 BREAK_TO_DEBUGGER(); 1471 return NULL; 1472 } 1473 1474 static struct dc_cap_funcs cap_funcs = { 1475 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap 1476 }; 1477 1478 #define fixed16_to_double(x) (((double) x) / ((double) (1 << 16))) 1479 #define fixed16_to_double_to_cpu(x) fixed16_to_double(le32_to_cpu(x)) 1480 1481 static bool is_soc_bounding_box_valid(struct dc *dc) 1482 { 1483 uint32_t hw_internal_rev = dc->ctx->asic_id.hw_internal_rev; 1484 1485 if (ASICREV_IS_VANGOGH(hw_internal_rev)) 1486 return true; 1487 1488 return false; 1489 } 1490 1491 static bool init_soc_bounding_box(struct dc *dc, 1492 struct dcn301_resource_pool *pool) 1493 { 1494 struct _vcs_dpi_soc_bounding_box_st *loaded_bb = &dcn3_01_soc; 1495 struct _vcs_dpi_ip_params_st *loaded_ip = &dcn3_01_ip; 1496 1497 DC_LOGGER_INIT(dc->ctx->logger); 1498 1499 if (!is_soc_bounding_box_valid(dc)) { 1500 DC_LOG_ERROR("%s: not valid soc bounding box/n", __func__); 1501 return false; 1502 } 1503 1504 loaded_ip->max_num_otg = pool->base.res_cap->num_timing_generator; 1505 loaded_ip->max_num_dpp = pool->base.pipe_count; 1506 dcn20_patch_bounding_box(dc, loaded_bb); 1507 1508 if (dc->ctx->dc_bios->funcs->get_soc_bb_info) { 1509 struct bp_soc_bb_info bb_info = {0}; 1510 1511 if (dc->ctx->dc_bios->funcs->get_soc_bb_info(dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) { 1512 if (bb_info.dram_clock_change_latency_100ns > 0) 1513 dcn3_01_soc.dram_clock_change_latency_us = bb_info.dram_clock_change_latency_100ns * 10; 1514 1515 if (bb_info.dram_sr_enter_exit_latency_100ns > 0) 1516 dcn3_01_soc.sr_enter_plus_exit_time_us = bb_info.dram_sr_enter_exit_latency_100ns * 10; 1517 1518 if (bb_info.dram_sr_exit_latency_100ns > 0) 1519 dcn3_01_soc.sr_exit_time_us = bb_info.dram_sr_exit_latency_100ns * 10; 1520 } 1521 } 1522 1523 return true; 1524 } 1525 1526 static void set_wm_ranges( 1527 struct pp_smu_funcs *pp_smu, 1528 struct _vcs_dpi_soc_bounding_box_st *loaded_bb) 1529 { 1530 struct pp_smu_wm_range_sets ranges = {0}; 1531 int i; 1532 1533 ranges.num_reader_wm_sets = 0; 1534 1535 if (loaded_bb->num_states == 1) { 1536 ranges.reader_wm_sets[0].wm_inst = 0; 1537 ranges.reader_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 1538 ranges.reader_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 1539 ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 1540 ranges.reader_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 1541 1542 ranges.num_reader_wm_sets = 1; 1543 } else if (loaded_bb->num_states > 1) { 1544 for (i = 0; i < 4 && i < loaded_bb->num_states; i++) { 1545 ranges.reader_wm_sets[i].wm_inst = i; 1546 ranges.reader_wm_sets[i].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 1547 ranges.reader_wm_sets[i].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 1548 ranges.reader_wm_sets[i].min_fill_clk_mhz = (i > 0) ? (loaded_bb->clock_limits[i - 1].dram_speed_mts / 16) + 1 : 0; 1549 ranges.reader_wm_sets[i].max_fill_clk_mhz = loaded_bb->clock_limits[i].dram_speed_mts / 16; 1550 1551 ranges.num_reader_wm_sets = i + 1; 1552 } 1553 1554 ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 1555 ranges.reader_wm_sets[ranges.num_reader_wm_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 1556 } 1557 1558 ranges.num_writer_wm_sets = 1; 1559 1560 ranges.writer_wm_sets[0].wm_inst = 0; 1561 ranges.writer_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 1562 ranges.writer_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 1563 ranges.writer_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 1564 ranges.writer_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 1565 1566 /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */ 1567 pp_smu->nv_funcs.set_wm_ranges(&pp_smu->nv_funcs.pp_smu, &ranges); 1568 } 1569 1570 static void dcn301_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) 1571 { 1572 struct dcn301_resource_pool *pool = TO_DCN301_RES_POOL(dc->res_pool); 1573 struct clk_limit_table *clk_table = &bw_params->clk_table; 1574 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES]; 1575 unsigned int i, closest_clk_lvl; 1576 int j; 1577 1578 // Default clock levels are used for diags, which may lead to overclocking. 1579 if (!IS_DIAG_DC(dc->ctx->dce_environment)) { 1580 dcn3_01_ip.max_num_otg = pool->base.res_cap->num_timing_generator; 1581 dcn3_01_ip.max_num_dpp = pool->base.pipe_count; 1582 dcn3_01_soc.num_chans = bw_params->num_channels; 1583 1584 ASSERT(clk_table->num_entries); 1585 for (i = 0; i < clk_table->num_entries; i++) { 1586 /* loop backwards*/ 1587 for (closest_clk_lvl = 0, j = dcn3_01_soc.num_states - 1; j >= 0; j--) { 1588 if ((unsigned int) dcn3_01_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) { 1589 closest_clk_lvl = j; 1590 break; 1591 } 1592 } 1593 1594 clock_limits[i].state = i; 1595 clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; 1596 clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz; 1597 clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz; 1598 clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2; 1599 1600 clock_limits[i].dispclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dispclk_mhz; 1601 clock_limits[i].dppclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dppclk_mhz; 1602 clock_limits[i].dram_bw_per_chan_gbps = dcn3_01_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps; 1603 clock_limits[i].dscclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dscclk_mhz; 1604 clock_limits[i].dtbclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dtbclk_mhz; 1605 clock_limits[i].phyclk_d18_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz; 1606 clock_limits[i].phyclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].phyclk_mhz; 1607 } 1608 for (i = 0; i < clk_table->num_entries; i++) 1609 dcn3_01_soc.clock_limits[i] = clock_limits[i]; 1610 if (clk_table->num_entries) { 1611 dcn3_01_soc.num_states = clk_table->num_entries; 1612 /* duplicate last level */ 1613 dcn3_01_soc.clock_limits[dcn3_01_soc.num_states] = dcn3_01_soc.clock_limits[dcn3_01_soc.num_states - 1]; 1614 dcn3_01_soc.clock_limits[dcn3_01_soc.num_states].state = dcn3_01_soc.num_states; 1615 } 1616 } 1617 1618 dcn3_01_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0; 1619 dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0; 1620 1621 dml_init_instance(&dc->dml, &dcn3_01_soc, &dcn3_01_ip, DML_PROJECT_DCN30); 1622 } 1623 1624 static void calculate_wm_set_for_vlevel( 1625 int vlevel, 1626 struct wm_range_table_entry *table_entry, 1627 struct dcn_watermarks *wm_set, 1628 struct display_mode_lib *dml, 1629 display_e2e_pipe_params_st *pipes, 1630 int pipe_cnt) 1631 { 1632 double dram_clock_change_latency_cached = dml->soc.dram_clock_change_latency_us; 1633 1634 ASSERT(vlevel < dml->soc.num_states); 1635 /* only pipe 0 is read for voltage and dcf/soc clocks */ 1636 pipes[0].clks_cfg.voltage = vlevel; 1637 pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz; 1638 pipes[0].clks_cfg.socclk_mhz = dml->soc.clock_limits[vlevel].socclk_mhz; 1639 1640 dml->soc.dram_clock_change_latency_us = table_entry->pstate_latency_us; 1641 dml->soc.sr_exit_time_us = table_entry->sr_exit_time_us; 1642 dml->soc.sr_enter_plus_exit_time_us = table_entry->sr_enter_plus_exit_time_us; 1643 1644 wm_set->urgent_ns = get_wm_urgent(dml, pipes, pipe_cnt) * 1000; 1645 wm_set->cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(dml, pipes, pipe_cnt) * 1000; 1646 wm_set->cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(dml, pipes, pipe_cnt) * 1000; 1647 wm_set->cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(dml, pipes, pipe_cnt) * 1000; 1648 wm_set->pte_meta_urgent_ns = get_wm_memory_trip(dml, pipes, pipe_cnt) * 1000; 1649 wm_set->frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(dml, pipes, pipe_cnt) * 1000; 1650 wm_set->frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(dml, pipes, pipe_cnt) * 1000; 1651 wm_set->urgent_latency_ns = get_urgent_latency(dml, pipes, pipe_cnt) * 1000; 1652 dml->soc.dram_clock_change_latency_us = dram_clock_change_latency_cached; 1653 1654 } 1655 1656 static void dcn301_calculate_wm_and_dlg( 1657 struct dc *dc, struct dc_state *context, 1658 display_e2e_pipe_params_st *pipes, 1659 int pipe_cnt, 1660 int vlevel_req) 1661 { 1662 int i, pipe_idx; 1663 int vlevel, vlevel_max; 1664 struct wm_range_table_entry *table_entry; 1665 struct clk_bw_params *bw_params = dc->clk_mgr->bw_params; 1666 1667 ASSERT(bw_params); 1668 1669 vlevel_max = bw_params->clk_table.num_entries - 1; 1670 1671 /* WM Set D */ 1672 table_entry = &bw_params->wm_table.entries[WM_D]; 1673 if (table_entry->wm_type == WM_TYPE_RETRAINING) 1674 vlevel = 0; 1675 else 1676 vlevel = vlevel_max; 1677 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.d, 1678 &context->bw_ctx.dml, pipes, pipe_cnt); 1679 /* WM Set C */ 1680 table_entry = &bw_params->wm_table.entries[WM_C]; 1681 vlevel = min(max(vlevel_req, 2), vlevel_max); 1682 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.c, 1683 &context->bw_ctx.dml, pipes, pipe_cnt); 1684 /* WM Set B */ 1685 table_entry = &bw_params->wm_table.entries[WM_B]; 1686 vlevel = min(max(vlevel_req, 1), vlevel_max); 1687 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.b, 1688 &context->bw_ctx.dml, pipes, pipe_cnt); 1689 1690 /* WM Set A */ 1691 table_entry = &bw_params->wm_table.entries[WM_A]; 1692 vlevel = min(vlevel_req, vlevel_max); 1693 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.a, 1694 &context->bw_ctx.dml, pipes, pipe_cnt); 1695 1696 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 1697 if (!context->res_ctx.pipe_ctx[i].stream) 1698 continue; 1699 1700 pipes[pipe_idx].clks_cfg.dispclk_mhz = get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt); 1701 pipes[pipe_idx].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); 1702 1703 if (dc->config.forced_clocks) { 1704 pipes[pipe_idx].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz; 1705 pipes[pipe_idx].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz; 1706 } 1707 if (dc->debug.min_disp_clk_khz > pipes[pipe_idx].clks_cfg.dispclk_mhz * 1000) 1708 pipes[pipe_idx].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0; 1709 if (dc->debug.min_dpp_clk_khz > pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000) 1710 pipes[pipe_idx].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0; 1711 1712 pipe_idx++; 1713 } 1714 1715 dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel); 1716 } 1717 1718 static struct resource_funcs dcn301_res_pool_funcs = { 1719 .destroy = dcn301_destroy_resource_pool, 1720 .link_enc_create = dcn301_link_encoder_create, 1721 .panel_cntl_create = dcn301_panel_cntl_create, 1722 .validate_bandwidth = dcn30_validate_bandwidth, 1723 .calculate_wm_and_dlg = dcn301_calculate_wm_and_dlg, 1724 .update_soc_for_wm_a = dcn30_update_soc_for_wm_a, 1725 .populate_dml_pipes = dcn30_populate_dml_pipes_from_context, 1726 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer, 1727 .add_stream_to_ctx = dcn30_add_stream_to_ctx, 1728 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, 1729 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 1730 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, 1731 .set_mcif_arb_params = dcn30_set_mcif_arb_params, 1732 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, 1733 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut, 1734 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut, 1735 .update_bw_bounding_box = dcn301_update_bw_bounding_box 1736 }; 1737 1738 static bool dcn301_resource_construct( 1739 uint8_t num_virtual_links, 1740 struct dc *dc, 1741 struct dcn301_resource_pool *pool) 1742 { 1743 int i, j; 1744 struct dc_context *ctx = dc->ctx; 1745 struct irq_service_init_data init_data; 1746 uint32_t pipe_fuses = read_pipe_fuses(ctx); 1747 uint32_t num_pipes = 0; 1748 1749 DC_LOGGER_INIT(dc->ctx->logger); 1750 1751 ctx->dc_bios->regs = &bios_regs; 1752 1753 pool->base.res_cap = &res_cap_dcn301; 1754 1755 pool->base.funcs = &dcn301_res_pool_funcs; 1756 1757 /************************************************* 1758 * Resource + asic cap harcoding * 1759 *************************************************/ 1760 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1761 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; 1762 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator; 1763 dc->caps.max_downscale_ratio = 600; 1764 dc->caps.i2c_speed_in_khz = 100; 1765 dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a enabled by default*/ 1766 dc->caps.max_cursor_size = 256; 1767 dc->caps.min_horizontal_blanking_period = 80; 1768 dc->caps.dmdata_alloc_size = 2048; 1769 dc->caps.max_slave_planes = 1; 1770 dc->caps.max_slave_yuv_planes = 1; 1771 dc->caps.max_slave_rgb_planes = 1; 1772 dc->caps.is_apu = true; 1773 dc->caps.post_blend_color_processing = true; 1774 dc->caps.force_dp_tps4_for_cp2520 = true; 1775 dc->caps.extended_aux_timeout_support = true; 1776 #ifdef CONFIG_DRM_AMD_DC_DMUB 1777 dc->caps.dmcub_support = true; 1778 #endif 1779 1780 /* Color pipeline capabilities */ 1781 dc->caps.color.dpp.dcn_arch = 1; 1782 dc->caps.color.dpp.input_lut_shared = 0; 1783 dc->caps.color.dpp.icsc = 1; 1784 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr 1785 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; 1786 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; 1787 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1; 1788 dc->caps.color.dpp.dgam_rom_caps.pq = 1; 1789 dc->caps.color.dpp.dgam_rom_caps.hlg = 1; 1790 dc->caps.color.dpp.post_csc = 1; 1791 dc->caps.color.dpp.gamma_corr = 1; 1792 dc->caps.color.dpp.dgam_rom_for_yuv = 0; 1793 1794 dc->caps.color.dpp.hw_3d_lut = 1; 1795 dc->caps.color.dpp.ogam_ram = 1; 1796 // no OGAM ROM on DCN301 1797 dc->caps.color.dpp.ogam_rom_caps.srgb = 0; 1798 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; 1799 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; 1800 dc->caps.color.dpp.ogam_rom_caps.pq = 0; 1801 dc->caps.color.dpp.ogam_rom_caps.hlg = 0; 1802 dc->caps.color.dpp.ocsc = 0; 1803 1804 dc->caps.color.mpc.gamut_remap = 1; 1805 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2 1806 dc->caps.color.mpc.ogam_ram = 1; 1807 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; 1808 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; 1809 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; 1810 dc->caps.color.mpc.ogam_rom_caps.pq = 0; 1811 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 1812 dc->caps.color.mpc.ocsc = 1; 1813 1814 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 1815 dc->debug = debug_defaults_drv; 1816 else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) { 1817 dc->debug = debug_defaults_diags; 1818 } else 1819 dc->debug = debug_defaults_diags; 1820 // Init the vm_helper 1821 if (dc->vm_helper) 1822 vm_helper_init(dc->vm_helper, 16); 1823 1824 /************************************************* 1825 * Create resources * 1826 *************************************************/ 1827 1828 /* Clock Sources for Pixel Clock*/ 1829 pool->base.clock_sources[DCN301_CLK_SRC_PLL0] = 1830 dcn301_clock_source_create(ctx, ctx->dc_bios, 1831 CLOCK_SOURCE_COMBO_PHY_PLL0, 1832 &clk_src_regs[0], false); 1833 pool->base.clock_sources[DCN301_CLK_SRC_PLL1] = 1834 dcn301_clock_source_create(ctx, ctx->dc_bios, 1835 CLOCK_SOURCE_COMBO_PHY_PLL1, 1836 &clk_src_regs[1], false); 1837 pool->base.clock_sources[DCN301_CLK_SRC_PLL2] = 1838 dcn301_clock_source_create(ctx, ctx->dc_bios, 1839 CLOCK_SOURCE_COMBO_PHY_PLL2, 1840 &clk_src_regs[2], false); 1841 pool->base.clock_sources[DCN301_CLK_SRC_PLL3] = 1842 dcn301_clock_source_create(ctx, ctx->dc_bios, 1843 CLOCK_SOURCE_COMBO_PHY_PLL3, 1844 &clk_src_regs[3], false); 1845 1846 pool->base.clk_src_count = DCN301_CLK_SRC_TOTAL; 1847 1848 /* todo: not reuse phy_pll registers */ 1849 pool->base.dp_clock_source = 1850 dcn301_clock_source_create(ctx, ctx->dc_bios, 1851 CLOCK_SOURCE_ID_DP_DTO, 1852 &clk_src_regs[0], true); 1853 1854 for (i = 0; i < pool->base.clk_src_count; i++) { 1855 if (pool->base.clock_sources[i] == NULL) { 1856 dm_error("DC: failed to create clock sources!\n"); 1857 BREAK_TO_DEBUGGER(); 1858 goto create_fail; 1859 } 1860 } 1861 1862 /* DCCG */ 1863 pool->base.dccg = dccg301_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 1864 if (pool->base.dccg == NULL) { 1865 dm_error("DC: failed to create dccg!\n"); 1866 BREAK_TO_DEBUGGER(); 1867 goto create_fail; 1868 } 1869 1870 init_soc_bounding_box(dc, pool); 1871 1872 if (!dc->debug.disable_pplib_wm_range && pool->base.pp_smu->nv_funcs.set_wm_ranges) 1873 set_wm_ranges(pool->base.pp_smu, &dcn3_01_soc); 1874 1875 num_pipes = dcn3_01_ip.max_num_dpp; 1876 1877 for (i = 0; i < dcn3_01_ip.max_num_dpp; i++) 1878 if (pipe_fuses & 1 << i) 1879 num_pipes--; 1880 dcn3_01_ip.max_num_dpp = num_pipes; 1881 dcn3_01_ip.max_num_otg = num_pipes; 1882 1883 1884 dml_init_instance(&dc->dml, &dcn3_01_soc, &dcn3_01_ip, DML_PROJECT_DCN30); 1885 1886 /* IRQ */ 1887 init_data.ctx = dc->ctx; 1888 pool->base.irqs = dal_irq_service_dcn30_create(&init_data); 1889 if (!pool->base.irqs) 1890 goto create_fail; 1891 1892 /* HUBBUB */ 1893 pool->base.hubbub = dcn301_hubbub_create(ctx); 1894 if (pool->base.hubbub == NULL) { 1895 BREAK_TO_DEBUGGER(); 1896 dm_error("DC: failed to create hubbub!\n"); 1897 goto create_fail; 1898 } 1899 1900 j = 0; 1901 /* HUBPs, DPPs, OPPs and TGs */ 1902 for (i = 0; i < pool->base.pipe_count; i++) { 1903 1904 /* if pipe is disabled, skip instance of HW pipe, 1905 * i.e, skip ASIC register instance 1906 */ 1907 if ((pipe_fuses & (1 << i)) != 0) { 1908 DC_LOG_DEBUG("%s: fusing pipe %d\n", __func__, i); 1909 continue; 1910 } 1911 1912 pool->base.hubps[j] = dcn301_hubp_create(ctx, i); 1913 if (pool->base.hubps[j] == NULL) { 1914 BREAK_TO_DEBUGGER(); 1915 dm_error( 1916 "DC: failed to create hubps!\n"); 1917 goto create_fail; 1918 } 1919 1920 pool->base.dpps[j] = dcn301_dpp_create(ctx, i); 1921 if (pool->base.dpps[j] == NULL) { 1922 BREAK_TO_DEBUGGER(); 1923 dm_error( 1924 "DC: failed to create dpps!\n"); 1925 goto create_fail; 1926 } 1927 1928 pool->base.opps[j] = dcn301_opp_create(ctx, i); 1929 if (pool->base.opps[j] == NULL) { 1930 BREAK_TO_DEBUGGER(); 1931 dm_error( 1932 "DC: failed to create output pixel processor!\n"); 1933 goto create_fail; 1934 } 1935 1936 pool->base.timing_generators[j] = dcn301_timing_generator_create(ctx, i); 1937 if (pool->base.timing_generators[j] == NULL) { 1938 BREAK_TO_DEBUGGER(); 1939 dm_error("DC: failed to create tg!\n"); 1940 goto create_fail; 1941 } 1942 j++; 1943 } 1944 pool->base.timing_generator_count = j; 1945 pool->base.pipe_count = j; 1946 pool->base.mpcc_count = j; 1947 1948 /* ABM (or ABMs for NV2x) */ 1949 /* TODO: */ 1950 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1951 pool->base.multiple_abms[i] = dmub_abm_create(ctx, 1952 &abm_regs[i], 1953 &abm_shift, 1954 &abm_mask); 1955 if (pool->base.multiple_abms[i] == NULL) { 1956 dm_error("DC: failed to create abm for pipe %d!\n", i); 1957 BREAK_TO_DEBUGGER(); 1958 goto create_fail; 1959 } 1960 } 1961 1962 /* MPC and DSC */ 1963 pool->base.mpc = dcn301_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut); 1964 if (pool->base.mpc == NULL) { 1965 BREAK_TO_DEBUGGER(); 1966 dm_error("DC: failed to create mpc!\n"); 1967 goto create_fail; 1968 } 1969 1970 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 1971 pool->base.dscs[i] = dcn301_dsc_create(ctx, i); 1972 if (pool->base.dscs[i] == NULL) { 1973 BREAK_TO_DEBUGGER(); 1974 dm_error("DC: failed to create display stream compressor %d!\n", i); 1975 goto create_fail; 1976 } 1977 } 1978 1979 /* DWB and MMHUBBUB */ 1980 if (!dcn301_dwbc_create(ctx, &pool->base)) { 1981 BREAK_TO_DEBUGGER(); 1982 dm_error("DC: failed to create dwbc!\n"); 1983 goto create_fail; 1984 } 1985 1986 if (!dcn301_mmhubbub_create(ctx, &pool->base)) { 1987 BREAK_TO_DEBUGGER(); 1988 dm_error("DC: failed to create mcif_wb!\n"); 1989 goto create_fail; 1990 } 1991 1992 /* AUX and I2C */ 1993 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1994 pool->base.engines[i] = dcn301_aux_engine_create(ctx, i); 1995 if (pool->base.engines[i] == NULL) { 1996 BREAK_TO_DEBUGGER(); 1997 dm_error( 1998 "DC:failed to create aux engine!!\n"); 1999 goto create_fail; 2000 } 2001 pool->base.hw_i2cs[i] = dcn301_i2c_hw_create(ctx, i); 2002 if (pool->base.hw_i2cs[i] == NULL) { 2003 BREAK_TO_DEBUGGER(); 2004 dm_error( 2005 "DC:failed to create hw i2c!!\n"); 2006 goto create_fail; 2007 } 2008 pool->base.sw_i2cs[i] = NULL; 2009 } 2010 2011 /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */ 2012 if (!resource_construct(num_virtual_links, dc, &pool->base, 2013 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? 2014 &res_create_funcs : &res_create_maximus_funcs))) 2015 goto create_fail; 2016 2017 /* HW Sequencer and Plane caps */ 2018 dcn301_hw_sequencer_construct(dc); 2019 2020 dc->caps.max_planes = pool->base.pipe_count; 2021 2022 for (i = 0; i < dc->caps.max_planes; ++i) 2023 dc->caps.planes[i] = plane_cap; 2024 2025 dc->cap_funcs = cap_funcs; 2026 2027 return true; 2028 2029 create_fail: 2030 2031 dcn301_destruct(pool); 2032 2033 return false; 2034 } 2035 2036 struct resource_pool *dcn301_create_resource_pool( 2037 const struct dc_init_data *init_data, 2038 struct dc *dc) 2039 { 2040 struct dcn301_resource_pool *pool = 2041 kzalloc(sizeof(struct dcn301_resource_pool), GFP_KERNEL); 2042 2043 if (!pool) 2044 return NULL; 2045 2046 if (dcn301_resource_construct(init_data->num_virtual_links, dc, pool)) 2047 return &pool->base; 2048 2049 BREAK_TO_DEBUGGER(); 2050 kfree(pool); 2051 return NULL; 2052 } 2053