1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 27 #include "dm_services.h" 28 #include "dc.h" 29 30 #include "dcn301_init.h" 31 32 #include "resource.h" 33 #include "include/irq_service_interface.h" 34 #include "dcn30/dcn30_resource.h" 35 #include "dcn301_resource.h" 36 37 #include "dcn20/dcn20_resource.h" 38 39 #include "dcn10/dcn10_ipp.h" 40 #include "dcn301/dcn301_hubbub.h" 41 #include "dcn30/dcn30_mpc.h" 42 #include "dcn30/dcn30_hubp.h" 43 #include "irq/dcn30/irq_service_dcn30.h" 44 #include "dcn30/dcn30_dpp.h" 45 #include "dcn30/dcn30_optc.h" 46 #include "dcn20/dcn20_hwseq.h" 47 #include "dcn30/dcn30_hwseq.h" 48 #include "dce110/dce110_hw_sequencer.h" 49 #include "dcn30/dcn30_opp.h" 50 #include "dcn20/dcn20_dsc.h" 51 #include "dcn30/dcn30_vpg.h" 52 #include "dcn30/dcn30_afmt.h" 53 #include "dce/dce_clock_source.h" 54 #include "dce/dce_audio.h" 55 #include "dce/dce_hwseq.h" 56 #include "clk_mgr.h" 57 #include "virtual/virtual_stream_encoder.h" 58 #include "dce110/dce110_resource.h" 59 #include "dml/display_mode_vba.h" 60 #include "dcn301/dcn301_dccg.h" 61 #include "dcn10/dcn10_resource.h" 62 #include "dcn30/dcn30_dio_stream_encoder.h" 63 #include "dcn301/dcn301_dio_link_encoder.h" 64 #include "dcn301_panel_cntl.h" 65 66 #include "vangogh_ip_offset.h" 67 68 #include "dcn30/dcn30_dwb.h" 69 #include "dcn30/dcn30_mmhubbub.h" 70 71 #include "dcn/dcn_3_0_1_offset.h" 72 #include "dcn/dcn_3_0_1_sh_mask.h" 73 74 #include "nbio/nbio_7_2_0_offset.h" 75 76 #include "reg_helper.h" 77 #include "dce/dmub_abm.h" 78 #include "dce/dce_aux.h" 79 #include "dce/dce_i2c.h" 80 81 #include "dml/dcn30/display_mode_vba_30.h" 82 #include "vm_helper.h" 83 #include "dcn20/dcn20_vmid.h" 84 #include "amdgpu_socbb.h" 85 86 #define TO_DCN301_RES_POOL(pool)\ 87 container_of(pool, struct dcn301_resource_pool, base) 88 89 #define DC_LOGGER_INIT(logger) 90 91 struct _vcs_dpi_ip_params_st dcn3_01_ip = { 92 .odm_capable = 1, 93 .gpuvm_enable = 1, 94 .hostvm_enable = 1, 95 .gpuvm_max_page_table_levels = 1, 96 .hostvm_max_page_table_levels = 2, 97 .hostvm_cached_page_table_levels = 0, 98 .pte_group_size_bytes = 2048, 99 .num_dsc = 3, 100 .rob_buffer_size_kbytes = 184, 101 .det_buffer_size_kbytes = 184, 102 .dpte_buffer_size_in_pte_reqs_luma = 64, 103 .dpte_buffer_size_in_pte_reqs_chroma = 32, 104 .pde_proc_buffer_size_64k_reqs = 48, 105 .dpp_output_buffer_pixels = 2560, 106 .opp_output_buffer_lines = 1, 107 .pixel_chunk_size_kbytes = 8, 108 .meta_chunk_size_kbytes = 2, 109 .writeback_chunk_size_kbytes = 8, 110 .line_buffer_size_bits = 789504, 111 .is_line_buffer_bpp_fixed = 0, // ? 112 .line_buffer_fixed_bpp = 48, // ? 113 .dcc_supported = true, 114 .writeback_interface_buffer_size_kbytes = 90, 115 .writeback_line_buffer_buffer_size = 656640, 116 .max_line_buffer_lines = 12, 117 .writeback_luma_buffer_size_kbytes = 12, // writeback_line_buffer_buffer_size = 656640 118 .writeback_chroma_buffer_size_kbytes = 8, 119 .writeback_chroma_line_buffer_width_pixels = 4, 120 .writeback_max_hscl_ratio = 1, 121 .writeback_max_vscl_ratio = 1, 122 .writeback_min_hscl_ratio = 1, 123 .writeback_min_vscl_ratio = 1, 124 .writeback_max_hscl_taps = 1, 125 .writeback_max_vscl_taps = 1, 126 .writeback_line_buffer_luma_buffer_size = 0, 127 .writeback_line_buffer_chroma_buffer_size = 14643, 128 .cursor_buffer_size = 8, 129 .cursor_chunk_size = 2, 130 .max_num_otg = 4, 131 .max_num_dpp = 4, 132 .max_num_wb = 1, 133 .max_dchub_pscl_bw_pix_per_clk = 4, 134 .max_pscl_lb_bw_pix_per_clk = 2, 135 .max_lb_vscl_bw_pix_per_clk = 4, 136 .max_vscl_hscl_bw_pix_per_clk = 4, 137 .max_hscl_ratio = 6, 138 .max_vscl_ratio = 6, 139 .hscl_mults = 4, 140 .vscl_mults = 4, 141 .max_hscl_taps = 8, 142 .max_vscl_taps = 8, 143 .dispclk_ramp_margin_percent = 1, 144 .underscan_factor = 1.11, 145 .min_vblank_lines = 32, 146 .dppclk_delay_subtotal = 46, 147 .dynamic_metadata_vm_enabled = true, 148 .dppclk_delay_scl_lb_only = 16, 149 .dppclk_delay_scl = 50, 150 .dppclk_delay_cnvc_formatter = 27, 151 .dppclk_delay_cnvc_cursor = 6, 152 .dispclk_delay_subtotal = 119, 153 .dcfclk_cstate_latency = 5.2, // SRExitTime 154 .max_inter_dcn_tile_repeaters = 8, 155 .max_num_hdmi_frl_outputs = 0, 156 .odm_combine_4to1_supported = true, 157 158 .xfc_supported = false, 159 .xfc_fill_bw_overhead_percent = 10.0, 160 .xfc_fill_constant_bytes = 0, 161 .gfx7_compat_tiling_supported = 0, 162 .number_of_cursors = 1, 163 }; 164 165 struct _vcs_dpi_soc_bounding_box_st dcn3_01_soc = { 166 .clock_limits = { 167 { 168 .state = 0, 169 .dram_speed_mts = 2400.0, 170 .fabricclk_mhz = 600, 171 .socclk_mhz = 278.0, 172 .dcfclk_mhz = 400.0, 173 .dscclk_mhz = 206.0, 174 .dppclk_mhz = 1015.0, 175 .dispclk_mhz = 1015.0, 176 .phyclk_mhz = 600.0, 177 }, 178 { 179 .state = 1, 180 .dram_speed_mts = 2400.0, 181 .fabricclk_mhz = 688, 182 .socclk_mhz = 278.0, 183 .dcfclk_mhz = 400.0, 184 .dscclk_mhz = 206.0, 185 .dppclk_mhz = 1015.0, 186 .dispclk_mhz = 1015.0, 187 .phyclk_mhz = 600.0, 188 }, 189 { 190 .state = 2, 191 .dram_speed_mts = 4267.0, 192 .fabricclk_mhz = 1067, 193 .socclk_mhz = 278.0, 194 .dcfclk_mhz = 608.0, 195 .dscclk_mhz = 296.0, 196 .dppclk_mhz = 1015.0, 197 .dispclk_mhz = 1015.0, 198 .phyclk_mhz = 810.0, 199 }, 200 201 { 202 .state = 3, 203 .dram_speed_mts = 4267.0, 204 .fabricclk_mhz = 1067, 205 .socclk_mhz = 715.0, 206 .dcfclk_mhz = 676.0, 207 .dscclk_mhz = 338.0, 208 .dppclk_mhz = 1015.0, 209 .dispclk_mhz = 1015.0, 210 .phyclk_mhz = 810.0, 211 }, 212 213 { 214 .state = 4, 215 .dram_speed_mts = 4267.0, 216 .fabricclk_mhz = 1067, 217 .socclk_mhz = 953.0, 218 .dcfclk_mhz = 810.0, 219 .dscclk_mhz = 338.0, 220 .dppclk_mhz = 1015.0, 221 .dispclk_mhz = 1015.0, 222 .phyclk_mhz = 810.0, 223 }, 224 }, 225 226 .sr_exit_time_us = 9.0, 227 .sr_enter_plus_exit_time_us = 11.0, 228 .urgent_latency_us = 4.0, 229 .urgent_latency_pixel_data_only_us = 4.0, 230 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0, 231 .urgent_latency_vm_data_only_us = 4.0, 232 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096, 233 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096, 234 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096, 235 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 80.0, 236 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 75.0, 237 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0, 238 .max_avg_sdp_bw_use_normal_percent = 60.0, 239 .max_avg_dram_bw_use_normal_percent = 60.0, 240 .writeback_latency_us = 12.0, 241 .max_request_size_bytes = 256, 242 .dram_channel_width_bytes = 4, 243 .fabric_datapath_to_dcn_data_return_bytes = 32, 244 .dcn_downspread_percent = 0.5, 245 .downspread_percent = 0.38, 246 .dram_page_open_time_ns = 50.0, 247 .dram_rw_turnaround_time_ns = 17.5, 248 .dram_return_buffer_per_channel_bytes = 8192, 249 .round_trip_ping_latency_dcfclk_cycles = 191, 250 .urgent_out_of_order_return_per_channel_bytes = 4096, 251 .channel_interleave_bytes = 256, 252 .num_banks = 8, 253 .num_chans = 4, 254 .gpuvm_min_page_size_bytes = 4096, 255 .hostvm_min_page_size_bytes = 4096, 256 .dram_clock_change_latency_us = 23.84, 257 .writeback_dram_clock_change_latency_us = 23.0, 258 .return_bus_width_bytes = 64, 259 .dispclk_dppclk_vco_speed_mhz = 3550, 260 .xfc_bus_transport_time_us = 20, // ? 261 .xfc_xbuf_latency_tolerance_us = 4, // ? 262 .use_urgent_burst_bw = 1, // ? 263 .num_states = 5, 264 .do_urgent_latency_adjustment = false, 265 .urgent_latency_adjustment_fabric_clock_component_us = 0, 266 .urgent_latency_adjustment_fabric_clock_reference_mhz = 0, 267 }; 268 269 enum dcn301_clk_src_array_id { 270 DCN301_CLK_SRC_PLL0, 271 DCN301_CLK_SRC_PLL1, 272 DCN301_CLK_SRC_PLL2, 273 DCN301_CLK_SRC_PLL3, 274 DCN301_CLK_SRC_TOTAL 275 }; 276 277 /* begin ********************* 278 * macros to expend register list macro defined in HW object header file 279 */ 280 281 /* DCN */ 282 /* TODO awful hack. fixup dcn20_dwb.h */ 283 #undef BASE_INNER 284 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg 285 286 #define BASE(seg) BASE_INNER(seg) 287 288 #define SR(reg_name)\ 289 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ 290 mm ## reg_name 291 292 #define SRI(reg_name, block, id)\ 293 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 294 mm ## block ## id ## _ ## reg_name 295 296 #define SRI2(reg_name, block, id)\ 297 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ 298 mm ## reg_name 299 300 #define SRIR(var_name, reg_name, block, id)\ 301 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 302 mm ## block ## id ## _ ## reg_name 303 304 #define SRII(reg_name, block, id)\ 305 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 306 mm ## block ## id ## _ ## reg_name 307 308 #define SRII2(reg_name_pre, reg_name_post, id)\ 309 .reg_name_pre ## _ ## reg_name_post[id] = BASE(mm ## reg_name_pre \ 310 ## id ## _ ## reg_name_post ## _BASE_IDX) + \ 311 mm ## reg_name_pre ## id ## _ ## reg_name_post 312 313 #define SRII_MPC_RMU(reg_name, block, id)\ 314 .RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 315 mm ## block ## id ## _ ## reg_name 316 317 #define SRII_DWB(reg_name, temp_name, block, id)\ 318 .reg_name[id] = BASE(mm ## block ## id ## _ ## temp_name ## _BASE_IDX) + \ 319 mm ## block ## id ## _ ## temp_name 320 321 #define DCCG_SRII(reg_name, block, id)\ 322 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 323 mm ## block ## id ## _ ## reg_name 324 325 #define VUPDATE_SRII(reg_name, block, id)\ 326 .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \ 327 mm ## reg_name ## _ ## block ## id 328 329 /* NBIO */ 330 #define NBIO_BASE_INNER(seg) \ 331 NBIO_BASE__INST0_SEG ## seg 332 333 #define NBIO_BASE(seg) \ 334 NBIO_BASE_INNER(seg) 335 336 #define NBIO_SR(reg_name)\ 337 .reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \ 338 regBIF_BX0_ ## reg_name 339 340 /* MMHUB */ 341 #define MMHUB_BASE_INNER(seg) \ 342 MMHUB_BASE__INST0_SEG ## seg 343 344 #define MMHUB_BASE(seg) \ 345 MMHUB_BASE_INNER(seg) 346 347 #define MMHUB_SR(reg_name)\ 348 .reg_name = MMHUB_BASE(regMM ## reg_name ## _BASE_IDX) + \ 349 regMM ## reg_name 350 351 /* CLOCK */ 352 #define CLK_BASE_INNER(seg) \ 353 CLK_BASE__INST0_SEG ## seg 354 355 #define CLK_BASE(seg) \ 356 CLK_BASE_INNER(seg) 357 358 #define CLK_SRI(reg_name, block, inst)\ 359 .reg_name = CLK_BASE(mm ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \ 360 mm ## block ## _ ## inst ## _ ## reg_name 361 362 static const struct bios_registers bios_regs = { 363 NBIO_SR(BIOS_SCRATCH_3), 364 NBIO_SR(BIOS_SCRATCH_6) 365 }; 366 367 #define clk_src_regs(index, pllid)\ 368 [index] = {\ 369 CS_COMMON_REG_LIST_DCN3_01(index, pllid),\ 370 } 371 372 static const struct dce110_clk_src_regs clk_src_regs[] = { 373 clk_src_regs(0, A), 374 clk_src_regs(1, B), 375 clk_src_regs(2, C), 376 clk_src_regs(3, D) 377 }; 378 379 static const struct dce110_clk_src_shift cs_shift = { 380 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 381 }; 382 383 static const struct dce110_clk_src_mask cs_mask = { 384 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 385 }; 386 387 #define abm_regs(id)\ 388 [id] = {\ 389 ABM_DCN301_REG_LIST(id)\ 390 } 391 392 static const struct dce_abm_registers abm_regs[] = { 393 abm_regs(0), 394 abm_regs(1), 395 abm_regs(2), 396 abm_regs(3), 397 }; 398 399 static const struct dce_abm_shift abm_shift = { 400 ABM_MASK_SH_LIST_DCN30(__SHIFT) 401 }; 402 403 static const struct dce_abm_mask abm_mask = { 404 ABM_MASK_SH_LIST_DCN30(_MASK) 405 }; 406 407 #define audio_regs(id)\ 408 [id] = {\ 409 AUD_COMMON_REG_LIST(id)\ 410 } 411 412 static const struct dce_audio_registers audio_regs[] = { 413 audio_regs(0), 414 audio_regs(1), 415 audio_regs(2), 416 audio_regs(3), 417 audio_regs(4), 418 audio_regs(5), 419 audio_regs(6) 420 }; 421 422 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 423 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 424 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 425 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 426 427 static const struct dce_audio_shift audio_shift = { 428 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 429 }; 430 431 static const struct dce_audio_mask audio_mask = { 432 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 433 }; 434 435 #define vpg_regs(id)\ 436 [id] = {\ 437 VPG_DCN3_REG_LIST(id)\ 438 } 439 440 static const struct dcn30_vpg_registers vpg_regs[] = { 441 vpg_regs(0), 442 vpg_regs(1), 443 vpg_regs(2), 444 vpg_regs(3), 445 }; 446 447 static const struct dcn30_vpg_shift vpg_shift = { 448 DCN3_VPG_MASK_SH_LIST(__SHIFT) 449 }; 450 451 static const struct dcn30_vpg_mask vpg_mask = { 452 DCN3_VPG_MASK_SH_LIST(_MASK) 453 }; 454 455 #define afmt_regs(id)\ 456 [id] = {\ 457 AFMT_DCN3_REG_LIST(id)\ 458 } 459 460 static const struct dcn30_afmt_registers afmt_regs[] = { 461 afmt_regs(0), 462 afmt_regs(1), 463 afmt_regs(2), 464 afmt_regs(3), 465 }; 466 467 static const struct dcn30_afmt_shift afmt_shift = { 468 DCN3_AFMT_MASK_SH_LIST(__SHIFT) 469 }; 470 471 static const struct dcn30_afmt_mask afmt_mask = { 472 DCN3_AFMT_MASK_SH_LIST(_MASK) 473 }; 474 475 #define stream_enc_regs(id)\ 476 [id] = {\ 477 SE_DCN3_REG_LIST(id)\ 478 } 479 480 static const struct dcn10_stream_enc_registers stream_enc_regs[] = { 481 stream_enc_regs(0), 482 stream_enc_regs(1), 483 stream_enc_regs(2), 484 stream_enc_regs(3), 485 }; 486 487 static const struct dcn10_stream_encoder_shift se_shift = { 488 SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 489 }; 490 491 static const struct dcn10_stream_encoder_mask se_mask = { 492 SE_COMMON_MASK_SH_LIST_DCN30(_MASK) 493 }; 494 495 496 #define aux_regs(id)\ 497 [id] = {\ 498 DCN2_AUX_REG_LIST(id)\ 499 } 500 501 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { 502 aux_regs(0), 503 aux_regs(1), 504 aux_regs(2), 505 aux_regs(3), 506 }; 507 508 #define hpd_regs(id)\ 509 [id] = {\ 510 HPD_REG_LIST(id)\ 511 } 512 513 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { 514 hpd_regs(0), 515 hpd_regs(1), 516 hpd_regs(2), 517 hpd_regs(3), 518 }; 519 520 #define link_regs(id, phyid)\ 521 [id] = {\ 522 LE_DCN301_REG_LIST(id), \ 523 UNIPHY_DCN2_REG_LIST(phyid), \ 524 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \ 525 } 526 527 static const struct dce110_aux_registers_shift aux_shift = { 528 DCN_AUX_MASK_SH_LIST(__SHIFT) 529 }; 530 531 static const struct dce110_aux_registers_mask aux_mask = { 532 DCN_AUX_MASK_SH_LIST(_MASK) 533 }; 534 535 static const struct dcn10_link_enc_registers link_enc_regs[] = { 536 link_regs(0, A), 537 link_regs(1, B), 538 link_regs(2, C), 539 link_regs(3, D), 540 }; 541 542 static const struct dcn10_link_enc_shift le_shift = { 543 LINK_ENCODER_MASK_SH_LIST_DCN301(__SHIFT) 544 }; 545 546 static const struct dcn10_link_enc_mask le_mask = { 547 LINK_ENCODER_MASK_SH_LIST_DCN301(_MASK) 548 }; 549 550 #define panel_cntl_regs(id)\ 551 [id] = {\ 552 DCN301_PANEL_CNTL_REG_LIST(id),\ 553 } 554 555 static const struct dce_panel_cntl_registers panel_cntl_regs[] = { 556 panel_cntl_regs(0), 557 panel_cntl_regs(1), 558 }; 559 560 static const struct dcn301_panel_cntl_shift panel_cntl_shift = { 561 DCN301_PANEL_CNTL_MASK_SH_LIST(__SHIFT) 562 }; 563 564 static const struct dcn301_panel_cntl_mask panel_cntl_mask = { 565 DCN301_PANEL_CNTL_MASK_SH_LIST(_MASK) 566 }; 567 568 #define dpp_regs(id)\ 569 [id] = {\ 570 DPP_REG_LIST_DCN30(id),\ 571 } 572 573 static const struct dcn3_dpp_registers dpp_regs[] = { 574 dpp_regs(0), 575 dpp_regs(1), 576 dpp_regs(2), 577 dpp_regs(3), 578 }; 579 580 static const struct dcn3_dpp_shift tf_shift = { 581 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT) 582 }; 583 584 static const struct dcn3_dpp_mask tf_mask = { 585 DPP_REG_LIST_SH_MASK_DCN30(_MASK) 586 }; 587 588 #define opp_regs(id)\ 589 [id] = {\ 590 OPP_REG_LIST_DCN30(id),\ 591 } 592 593 static const struct dcn20_opp_registers opp_regs[] = { 594 opp_regs(0), 595 opp_regs(1), 596 opp_regs(2), 597 opp_regs(3), 598 }; 599 600 static const struct dcn20_opp_shift opp_shift = { 601 OPP_MASK_SH_LIST_DCN20(__SHIFT) 602 }; 603 604 static const struct dcn20_opp_mask opp_mask = { 605 OPP_MASK_SH_LIST_DCN20(_MASK) 606 }; 607 608 #define aux_engine_regs(id)\ 609 [id] = {\ 610 AUX_COMMON_REG_LIST0(id), \ 611 .AUXN_IMPCAL = 0, \ 612 .AUXP_IMPCAL = 0, \ 613 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \ 614 } 615 616 static const struct dce110_aux_registers aux_engine_regs[] = { 617 aux_engine_regs(0), 618 aux_engine_regs(1), 619 aux_engine_regs(2), 620 aux_engine_regs(3), 621 }; 622 623 #define dwbc_regs_dcn3(id)\ 624 [id] = {\ 625 DWBC_COMMON_REG_LIST_DCN30(id),\ 626 } 627 628 static const struct dcn30_dwbc_registers dwbc30_regs[] = { 629 dwbc_regs_dcn3(0), 630 }; 631 632 static const struct dcn30_dwbc_shift dwbc30_shift = { 633 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 634 }; 635 636 static const struct dcn30_dwbc_mask dwbc30_mask = { 637 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK) 638 }; 639 640 #define mcif_wb_regs_dcn3(id)\ 641 [id] = {\ 642 MCIF_WB_COMMON_REG_LIST_DCN30(id),\ 643 } 644 645 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = { 646 mcif_wb_regs_dcn3(0) 647 }; 648 649 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = { 650 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 651 }; 652 653 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { 654 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK) 655 }; 656 657 #define dsc_regsDCN20(id)\ 658 [id] = {\ 659 DSC_REG_LIST_DCN20(id)\ 660 } 661 662 static const struct dcn20_dsc_registers dsc_regs[] = { 663 dsc_regsDCN20(0), 664 dsc_regsDCN20(1), 665 dsc_regsDCN20(2), 666 }; 667 668 static const struct dcn20_dsc_shift dsc_shift = { 669 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) 670 }; 671 672 static const struct dcn20_dsc_mask dsc_mask = { 673 DSC_REG_LIST_SH_MASK_DCN20(_MASK) 674 }; 675 676 static const struct dcn30_mpc_registers mpc_regs = { 677 MPC_REG_LIST_DCN3_0(0), 678 MPC_REG_LIST_DCN3_0(1), 679 MPC_REG_LIST_DCN3_0(2), 680 MPC_REG_LIST_DCN3_0(3), 681 MPC_OUT_MUX_REG_LIST_DCN3_0(0), 682 MPC_OUT_MUX_REG_LIST_DCN3_0(1), 683 MPC_OUT_MUX_REG_LIST_DCN3_0(2), 684 MPC_OUT_MUX_REG_LIST_DCN3_0(3), 685 MPC_RMU_GLOBAL_REG_LIST_DCN3AG, 686 MPC_RMU_REG_LIST_DCN3AG(0), 687 MPC_RMU_REG_LIST_DCN3AG(1), 688 MPC_DWB_MUX_REG_LIST_DCN3_0(0), 689 }; 690 691 static const struct dcn30_mpc_shift mpc_shift = { 692 MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 693 }; 694 695 static const struct dcn30_mpc_mask mpc_mask = { 696 MPC_COMMON_MASK_SH_LIST_DCN30(_MASK) 697 }; 698 699 #define optc_regs(id)\ 700 [id] = {OPTC_COMMON_REG_LIST_DCN3_0(id)} 701 702 703 static const struct dcn_optc_registers optc_regs[] = { 704 optc_regs(0), 705 optc_regs(1), 706 optc_regs(2), 707 optc_regs(3), 708 }; 709 710 static const struct dcn_optc_shift optc_shift = { 711 OPTC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 712 }; 713 714 static const struct dcn_optc_mask optc_mask = { 715 OPTC_COMMON_MASK_SH_LIST_DCN30(_MASK) 716 }; 717 718 #define hubp_regs(id)\ 719 [id] = {\ 720 HUBP_REG_LIST_DCN30(id)\ 721 } 722 723 static const struct dcn_hubp2_registers hubp_regs[] = { 724 hubp_regs(0), 725 hubp_regs(1), 726 hubp_regs(2), 727 hubp_regs(3), 728 }; 729 730 static const struct dcn_hubp2_shift hubp_shift = { 731 HUBP_MASK_SH_LIST_DCN30(__SHIFT) 732 }; 733 734 static const struct dcn_hubp2_mask hubp_mask = { 735 HUBP_MASK_SH_LIST_DCN30(_MASK) 736 }; 737 738 static const struct dcn_hubbub_registers hubbub_reg = { 739 HUBBUB_REG_LIST_DCN301(0) 740 }; 741 742 static const struct dcn_hubbub_shift hubbub_shift = { 743 HUBBUB_MASK_SH_LIST_DCN301(__SHIFT) 744 }; 745 746 static const struct dcn_hubbub_mask hubbub_mask = { 747 HUBBUB_MASK_SH_LIST_DCN301(_MASK) 748 }; 749 750 static const struct dccg_registers dccg_regs = { 751 DCCG_REG_LIST_DCN301() 752 }; 753 754 static const struct dccg_shift dccg_shift = { 755 DCCG_MASK_SH_LIST_DCN301(__SHIFT) 756 }; 757 758 static const struct dccg_mask dccg_mask = { 759 DCCG_MASK_SH_LIST_DCN301(_MASK) 760 }; 761 762 static const struct dce_hwseq_registers hwseq_reg = { 763 HWSEQ_DCN301_REG_LIST() 764 }; 765 766 static const struct dce_hwseq_shift hwseq_shift = { 767 HWSEQ_DCN301_MASK_SH_LIST(__SHIFT) 768 }; 769 770 static const struct dce_hwseq_mask hwseq_mask = { 771 HWSEQ_DCN301_MASK_SH_LIST(_MASK) 772 }; 773 #define vmid_regs(id)\ 774 [id] = {\ 775 DCN20_VMID_REG_LIST(id)\ 776 } 777 778 static const struct dcn_vmid_registers vmid_regs[] = { 779 vmid_regs(0), 780 vmid_regs(1), 781 vmid_regs(2), 782 vmid_regs(3), 783 vmid_regs(4), 784 vmid_regs(5), 785 vmid_regs(6), 786 vmid_regs(7), 787 vmid_regs(8), 788 vmid_regs(9), 789 vmid_regs(10), 790 vmid_regs(11), 791 vmid_regs(12), 792 vmid_regs(13), 793 vmid_regs(14), 794 vmid_regs(15) 795 }; 796 797 static const struct dcn20_vmid_shift vmid_shifts = { 798 DCN20_VMID_MASK_SH_LIST(__SHIFT) 799 }; 800 801 static const struct dcn20_vmid_mask vmid_masks = { 802 DCN20_VMID_MASK_SH_LIST(_MASK) 803 }; 804 805 static const struct resource_caps res_cap_dcn301 = { 806 .num_timing_generator = 4, 807 .num_opp = 4, 808 .num_video_plane = 4, 809 .num_audio = 4, 810 .num_stream_encoder = 4, 811 .num_pll = 4, 812 .num_dwb = 1, 813 .num_ddc = 4, 814 .num_vmid = 16, 815 .num_mpc_3dlut = 2, 816 .num_dsc = 3, 817 }; 818 819 static const struct dc_plane_cap plane_cap = { 820 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 821 .blends_with_above = true, 822 .blends_with_below = true, 823 .per_pixel_alpha = true, 824 825 .pixel_format_support = { 826 .argb8888 = true, 827 .nv12 = true, 828 .fp16 = true, 829 .p010 = false, 830 .ayuv = false, 831 }, 832 833 .max_upscale_factor = { 834 .argb8888 = 16000, 835 .nv12 = 16000, 836 .fp16 = 16000 837 }, 838 839 .max_downscale_factor = { 840 .argb8888 = 600, 841 .nv12 = 600, 842 .fp16 = 600 843 }, 844 64, 845 64 846 }; 847 848 static const struct dc_debug_options debug_defaults_drv = { 849 .disable_dmcu = true, 850 .force_abm_enable = false, 851 .timing_trace = false, 852 .clock_trace = true, 853 .disable_dpp_power_gate = false, 854 .disable_hubp_power_gate = false, 855 .disable_clock_gate = true, 856 .disable_pplib_clock_request = true, 857 .disable_pplib_wm_range = true, 858 .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP, 859 .force_single_disp_pipe_split = false, 860 .disable_dcc = DCC_ENABLE, 861 .vsr_support = true, 862 .performance_trace = false, 863 .max_downscale_src_width = 7680,/*upto 8K*/ 864 .scl_reset_length10 = true, 865 .sanity_checks = false, 866 .underflow_assert_delay_us = 0xFFFFFFFF, 867 .dwb_fi_phase = -1, // -1 = disable 868 .dmub_command_table = true, 869 }; 870 871 static const struct dc_debug_options debug_defaults_diags = { 872 .disable_dmcu = true, 873 .force_abm_enable = false, 874 .timing_trace = true, 875 .clock_trace = true, 876 .disable_dpp_power_gate = false, 877 .disable_hubp_power_gate = false, 878 .disable_clock_gate = true, 879 .disable_pplib_clock_request = true, 880 .disable_pplib_wm_range = true, 881 .disable_stutter = true, 882 .scl_reset_length10 = true, 883 .dwb_fi_phase = -1, // -1 = disable 884 .dmub_command_table = true, 885 }; 886 887 void dcn301_dpp_destroy(struct dpp **dpp) 888 { 889 kfree(TO_DCN20_DPP(*dpp)); 890 *dpp = NULL; 891 } 892 893 struct dpp *dcn301_dpp_create( 894 struct dc_context *ctx, 895 uint32_t inst) 896 { 897 struct dcn3_dpp *dpp = 898 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL); 899 900 if (!dpp) 901 return NULL; 902 903 if (dpp3_construct(dpp, ctx, inst, 904 &dpp_regs[inst], &tf_shift, &tf_mask)) 905 return &dpp->base; 906 907 BREAK_TO_DEBUGGER(); 908 kfree(dpp); 909 return NULL; 910 } 911 struct output_pixel_processor *dcn301_opp_create( 912 struct dc_context *ctx, uint32_t inst) 913 { 914 struct dcn20_opp *opp = 915 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); 916 917 if (!opp) { 918 BREAK_TO_DEBUGGER(); 919 return NULL; 920 } 921 922 dcn20_opp_construct(opp, ctx, inst, 923 &opp_regs[inst], &opp_shift, &opp_mask); 924 return &opp->base; 925 } 926 927 struct dce_aux *dcn301_aux_engine_create( 928 struct dc_context *ctx, 929 uint32_t inst) 930 { 931 struct aux_engine_dce110 *aux_engine = 932 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 933 934 if (!aux_engine) 935 return NULL; 936 937 dce110_aux_engine_construct(aux_engine, ctx, inst, 938 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 939 &aux_engine_regs[inst], 940 &aux_mask, 941 &aux_shift, 942 ctx->dc->caps.extended_aux_timeout_support); 943 944 return &aux_engine->base; 945 } 946 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 947 948 static const struct dce_i2c_registers i2c_hw_regs[] = { 949 i2c_inst_regs(1), 950 i2c_inst_regs(2), 951 i2c_inst_regs(3), 952 i2c_inst_regs(4), 953 }; 954 955 static const struct dce_i2c_shift i2c_shifts = { 956 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT) 957 }; 958 959 static const struct dce_i2c_mask i2c_masks = { 960 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK) 961 }; 962 963 struct dce_i2c_hw *dcn301_i2c_hw_create( 964 struct dc_context *ctx, 965 uint32_t inst) 966 { 967 struct dce_i2c_hw *dce_i2c_hw = 968 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 969 970 if (!dce_i2c_hw) 971 return NULL; 972 973 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, 974 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 975 976 return dce_i2c_hw; 977 } 978 static struct mpc *dcn301_mpc_create( 979 struct dc_context *ctx, 980 int num_mpcc, 981 int num_rmu) 982 { 983 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), 984 GFP_KERNEL); 985 986 if (!mpc30) 987 return NULL; 988 989 dcn30_mpc_construct(mpc30, ctx, 990 &mpc_regs, 991 &mpc_shift, 992 &mpc_mask, 993 num_mpcc, 994 num_rmu); 995 996 return &mpc30->base; 997 } 998 999 struct hubbub *dcn301_hubbub_create(struct dc_context *ctx) 1000 { 1001 int i; 1002 1003 struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub), 1004 GFP_KERNEL); 1005 1006 if (!hubbub3) 1007 return NULL; 1008 1009 hubbub301_construct(hubbub3, ctx, 1010 &hubbub_reg, 1011 &hubbub_shift, 1012 &hubbub_mask); 1013 1014 1015 for (i = 0; i < res_cap_dcn301.num_vmid; i++) { 1016 struct dcn20_vmid *vmid = &hubbub3->vmid[i]; 1017 1018 vmid->ctx = ctx; 1019 1020 vmid->regs = &vmid_regs[i]; 1021 vmid->shifts = &vmid_shifts; 1022 vmid->masks = &vmid_masks; 1023 } 1024 1025 hubbub3->num_vmid = res_cap_dcn301.num_vmid; 1026 1027 return &hubbub3->base; 1028 } 1029 1030 struct timing_generator *dcn301_timing_generator_create( 1031 struct dc_context *ctx, 1032 uint32_t instance) 1033 { 1034 struct optc *tgn10 = 1035 kzalloc(sizeof(struct optc), GFP_KERNEL); 1036 1037 if (!tgn10) 1038 return NULL; 1039 1040 tgn10->base.inst = instance; 1041 tgn10->base.ctx = ctx; 1042 1043 tgn10->tg_regs = &optc_regs[instance]; 1044 tgn10->tg_shift = &optc_shift; 1045 tgn10->tg_mask = &optc_mask; 1046 1047 dcn30_timing_generator_init(tgn10); 1048 1049 return &tgn10->base; 1050 } 1051 1052 static const struct encoder_feature_support link_enc_feature = { 1053 .max_hdmi_deep_color = COLOR_DEPTH_121212, 1054 .max_hdmi_pixel_clock = 600000, 1055 .hdmi_ycbcr420_supported = true, 1056 .dp_ycbcr420_supported = true, 1057 .fec_supported = true, 1058 .flags.bits.IS_HBR2_CAPABLE = true, 1059 .flags.bits.IS_HBR3_CAPABLE = true, 1060 .flags.bits.IS_TPS3_CAPABLE = true, 1061 .flags.bits.IS_TPS4_CAPABLE = true 1062 }; 1063 1064 struct link_encoder *dcn301_link_encoder_create( 1065 const struct encoder_init_data *enc_init_data) 1066 { 1067 struct dcn20_link_encoder *enc20 = 1068 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 1069 1070 if (!enc20) 1071 return NULL; 1072 1073 dcn301_link_encoder_construct(enc20, 1074 enc_init_data, 1075 &link_enc_feature, 1076 &link_enc_regs[enc_init_data->transmitter], 1077 &link_enc_aux_regs[enc_init_data->channel - 1], 1078 &link_enc_hpd_regs[enc_init_data->hpd_source], 1079 &le_shift, 1080 &le_mask); 1081 1082 return &enc20->enc10.base; 1083 } 1084 1085 struct panel_cntl *dcn301_panel_cntl_create(const struct panel_cntl_init_data *init_data) 1086 { 1087 struct dcn301_panel_cntl *panel_cntl = 1088 kzalloc(sizeof(struct dcn301_panel_cntl), GFP_KERNEL); 1089 1090 if (!panel_cntl) 1091 return NULL; 1092 1093 dcn301_panel_cntl_construct(panel_cntl, 1094 init_data, 1095 &panel_cntl_regs[init_data->inst], 1096 &panel_cntl_shift, 1097 &panel_cntl_mask); 1098 1099 return &panel_cntl->base; 1100 } 1101 1102 1103 #define CTX ctx 1104 1105 #define REG(reg_name) \ 1106 (DCN_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name) 1107 1108 static uint32_t read_pipe_fuses(struct dc_context *ctx) 1109 { 1110 uint32_t value = REG_READ(CC_DC_PIPE_DIS); 1111 /* RV1 support max 4 pipes */ 1112 value = value & 0xf; 1113 return value; 1114 } 1115 1116 1117 static void read_dce_straps( 1118 struct dc_context *ctx, 1119 struct resource_straps *straps) 1120 { 1121 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX), 1122 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 1123 1124 } 1125 1126 static struct audio *dcn301_create_audio( 1127 struct dc_context *ctx, unsigned int inst) 1128 { 1129 return dce_audio_create(ctx, inst, 1130 &audio_regs[inst], &audio_shift, &audio_mask); 1131 } 1132 1133 static struct vpg *dcn301_vpg_create( 1134 struct dc_context *ctx, 1135 uint32_t inst) 1136 { 1137 struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL); 1138 1139 if (!vpg3) 1140 return NULL; 1141 1142 vpg3_construct(vpg3, ctx, inst, 1143 &vpg_regs[inst], 1144 &vpg_shift, 1145 &vpg_mask); 1146 1147 return &vpg3->base; 1148 } 1149 1150 static struct afmt *dcn301_afmt_create( 1151 struct dc_context *ctx, 1152 uint32_t inst) 1153 { 1154 struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL); 1155 1156 if (!afmt3) 1157 return NULL; 1158 1159 afmt3_construct(afmt3, ctx, inst, 1160 &afmt_regs[inst], 1161 &afmt_shift, 1162 &afmt_mask); 1163 1164 return &afmt3->base; 1165 } 1166 1167 struct stream_encoder *dcn301_stream_encoder_create( 1168 enum engine_id eng_id, 1169 struct dc_context *ctx) 1170 { 1171 struct dcn10_stream_encoder *enc1; 1172 struct vpg *vpg; 1173 struct afmt *afmt; 1174 int vpg_inst; 1175 int afmt_inst; 1176 1177 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */ 1178 if (eng_id <= ENGINE_ID_DIGF) { 1179 vpg_inst = eng_id; 1180 afmt_inst = eng_id; 1181 } else 1182 return NULL; 1183 1184 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 1185 vpg = dcn301_vpg_create(ctx, vpg_inst); 1186 afmt = dcn301_afmt_create(ctx, afmt_inst); 1187 1188 if (!enc1 || !vpg || !afmt) 1189 return NULL; 1190 1191 dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, 1192 eng_id, vpg, afmt, 1193 &stream_enc_regs[eng_id], 1194 &se_shift, &se_mask); 1195 1196 return &enc1->base; 1197 } 1198 1199 struct dce_hwseq *dcn301_hwseq_create( 1200 struct dc_context *ctx) 1201 { 1202 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 1203 1204 if (hws) { 1205 hws->ctx = ctx; 1206 hws->regs = &hwseq_reg; 1207 hws->shifts = &hwseq_shift; 1208 hws->masks = &hwseq_mask; 1209 } 1210 return hws; 1211 } 1212 static const struct resource_create_funcs res_create_funcs = { 1213 .read_dce_straps = read_dce_straps, 1214 .create_audio = dcn301_create_audio, 1215 .create_stream_encoder = dcn301_stream_encoder_create, 1216 .create_hwseq = dcn301_hwseq_create, 1217 }; 1218 1219 static const struct resource_create_funcs res_create_maximus_funcs = { 1220 .read_dce_straps = NULL, 1221 .create_audio = NULL, 1222 .create_stream_encoder = NULL, 1223 .create_hwseq = dcn301_hwseq_create, 1224 }; 1225 1226 static void dcn301_destruct(struct dcn301_resource_pool *pool) 1227 { 1228 unsigned int i; 1229 1230 for (i = 0; i < pool->base.stream_enc_count; i++) { 1231 if (pool->base.stream_enc[i] != NULL) { 1232 if (pool->base.stream_enc[i]->vpg != NULL) { 1233 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg)); 1234 pool->base.stream_enc[i]->vpg = NULL; 1235 } 1236 if (pool->base.stream_enc[i]->afmt != NULL) { 1237 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt)); 1238 pool->base.stream_enc[i]->afmt = NULL; 1239 } 1240 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); 1241 pool->base.stream_enc[i] = NULL; 1242 } 1243 } 1244 1245 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 1246 if (pool->base.dscs[i] != NULL) 1247 dcn20_dsc_destroy(&pool->base.dscs[i]); 1248 } 1249 1250 if (pool->base.mpc != NULL) { 1251 kfree(TO_DCN20_MPC(pool->base.mpc)); 1252 pool->base.mpc = NULL; 1253 } 1254 if (pool->base.hubbub != NULL) { 1255 kfree(pool->base.hubbub); 1256 pool->base.hubbub = NULL; 1257 } 1258 for (i = 0; i < pool->base.pipe_count; i++) { 1259 if (pool->base.dpps[i] != NULL) 1260 dcn301_dpp_destroy(&pool->base.dpps[i]); 1261 1262 if (pool->base.ipps[i] != NULL) 1263 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); 1264 1265 if (pool->base.hubps[i] != NULL) { 1266 kfree(TO_DCN20_HUBP(pool->base.hubps[i])); 1267 pool->base.hubps[i] = NULL; 1268 } 1269 1270 if (pool->base.irqs != NULL) { 1271 dal_irq_service_destroy(&pool->base.irqs); 1272 } 1273 } 1274 1275 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1276 if (pool->base.engines[i] != NULL) 1277 dce110_engine_destroy(&pool->base.engines[i]); 1278 if (pool->base.hw_i2cs[i] != NULL) { 1279 kfree(pool->base.hw_i2cs[i]); 1280 pool->base.hw_i2cs[i] = NULL; 1281 } 1282 if (pool->base.sw_i2cs[i] != NULL) { 1283 kfree(pool->base.sw_i2cs[i]); 1284 pool->base.sw_i2cs[i] = NULL; 1285 } 1286 } 1287 1288 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 1289 if (pool->base.opps[i] != NULL) 1290 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); 1291 } 1292 1293 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1294 if (pool->base.timing_generators[i] != NULL) { 1295 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); 1296 pool->base.timing_generators[i] = NULL; 1297 } 1298 } 1299 1300 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { 1301 if (pool->base.dwbc[i] != NULL) { 1302 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); 1303 pool->base.dwbc[i] = NULL; 1304 } 1305 if (pool->base.mcif_wb[i] != NULL) { 1306 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i])); 1307 pool->base.mcif_wb[i] = NULL; 1308 } 1309 } 1310 1311 for (i = 0; i < pool->base.audio_count; i++) { 1312 if (pool->base.audios[i]) 1313 dce_aud_destroy(&pool->base.audios[i]); 1314 } 1315 1316 for (i = 0; i < pool->base.clk_src_count; i++) { 1317 if (pool->base.clock_sources[i] != NULL) { 1318 dcn20_clock_source_destroy(&pool->base.clock_sources[i]); 1319 pool->base.clock_sources[i] = NULL; 1320 } 1321 } 1322 1323 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { 1324 if (pool->base.mpc_lut[i] != NULL) { 1325 dc_3dlut_func_release(pool->base.mpc_lut[i]); 1326 pool->base.mpc_lut[i] = NULL; 1327 } 1328 if (pool->base.mpc_shaper[i] != NULL) { 1329 dc_transfer_func_release(pool->base.mpc_shaper[i]); 1330 pool->base.mpc_shaper[i] = NULL; 1331 } 1332 } 1333 1334 if (pool->base.dp_clock_source != NULL) { 1335 dcn20_clock_source_destroy(&pool->base.dp_clock_source); 1336 pool->base.dp_clock_source = NULL; 1337 } 1338 1339 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1340 if (pool->base.multiple_abms[i] != NULL) 1341 dce_abm_destroy(&pool->base.multiple_abms[i]); 1342 } 1343 1344 if (pool->base.dccg != NULL) 1345 dcn_dccg_destroy(&pool->base.dccg); 1346 } 1347 1348 struct hubp *dcn301_hubp_create( 1349 struct dc_context *ctx, 1350 uint32_t inst) 1351 { 1352 struct dcn20_hubp *hubp2 = 1353 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL); 1354 1355 if (!hubp2) 1356 return NULL; 1357 1358 if (hubp3_construct(hubp2, ctx, inst, 1359 &hubp_regs[inst], &hubp_shift, &hubp_mask)) 1360 return &hubp2->base; 1361 1362 BREAK_TO_DEBUGGER(); 1363 kfree(hubp2); 1364 return NULL; 1365 } 1366 1367 bool dcn301_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) 1368 { 1369 int i; 1370 uint32_t pipe_count = pool->res_cap->num_dwb; 1371 1372 for (i = 0; i < pipe_count; i++) { 1373 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), 1374 GFP_KERNEL); 1375 1376 if (!dwbc30) { 1377 dm_error("DC: failed to create dwbc30!\n"); 1378 return false; 1379 } 1380 1381 dcn30_dwbc_construct(dwbc30, ctx, 1382 &dwbc30_regs[i], 1383 &dwbc30_shift, 1384 &dwbc30_mask, 1385 i); 1386 1387 pool->dwbc[i] = &dwbc30->base; 1388 } 1389 return true; 1390 } 1391 1392 bool dcn301_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) 1393 { 1394 int i; 1395 uint32_t pipe_count = pool->res_cap->num_dwb; 1396 1397 for (i = 0; i < pipe_count; i++) { 1398 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), 1399 GFP_KERNEL); 1400 1401 if (!mcif_wb30) { 1402 dm_error("DC: failed to create mcif_wb30!\n"); 1403 return false; 1404 } 1405 1406 dcn30_mmhubbub_construct(mcif_wb30, ctx, 1407 &mcif_wb30_regs[i], 1408 &mcif_wb30_shift, 1409 &mcif_wb30_mask, 1410 i); 1411 1412 pool->mcif_wb[i] = &mcif_wb30->base; 1413 } 1414 return true; 1415 } 1416 1417 static struct display_stream_compressor *dcn301_dsc_create( 1418 struct dc_context *ctx, uint32_t inst) 1419 { 1420 struct dcn20_dsc *dsc = 1421 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); 1422 1423 if (!dsc) { 1424 BREAK_TO_DEBUGGER(); 1425 return NULL; 1426 } 1427 1428 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 1429 return &dsc->base; 1430 } 1431 1432 1433 static void dcn301_destroy_resource_pool(struct resource_pool **pool) 1434 { 1435 struct dcn301_resource_pool *dcn301_pool = TO_DCN301_RES_POOL(*pool); 1436 1437 dcn301_destruct(dcn301_pool); 1438 kfree(dcn301_pool); 1439 *pool = NULL; 1440 } 1441 1442 static struct clock_source *dcn301_clock_source_create( 1443 struct dc_context *ctx, 1444 struct dc_bios *bios, 1445 enum clock_source_id id, 1446 const struct dce110_clk_src_regs *regs, 1447 bool dp_clk_src) 1448 { 1449 struct dce110_clk_src *clk_src = 1450 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 1451 1452 if (!clk_src) 1453 return NULL; 1454 1455 if (dcn301_clk_src_construct(clk_src, ctx, bios, id, 1456 regs, &cs_shift, &cs_mask)) { 1457 clk_src->base.dp_clk_src = dp_clk_src; 1458 return &clk_src->base; 1459 } 1460 1461 BREAK_TO_DEBUGGER(); 1462 return NULL; 1463 } 1464 1465 static struct dc_cap_funcs cap_funcs = { 1466 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap 1467 }; 1468 1469 #define fixed16_to_double(x) (((double) x) / ((double) (1 << 16))) 1470 #define fixed16_to_double_to_cpu(x) fixed16_to_double(le32_to_cpu(x)) 1471 1472 static bool is_soc_bounding_box_valid(struct dc *dc) 1473 { 1474 uint32_t hw_internal_rev = dc->ctx->asic_id.hw_internal_rev; 1475 1476 if (ASICREV_IS_VANGOGH(hw_internal_rev)) 1477 return true; 1478 1479 return false; 1480 } 1481 1482 static bool init_soc_bounding_box(struct dc *dc, 1483 struct dcn301_resource_pool *pool) 1484 { 1485 const struct gpu_info_soc_bounding_box_v1_0 *bb = dc->soc_bounding_box; 1486 struct _vcs_dpi_soc_bounding_box_st *loaded_bb = &dcn3_01_soc; 1487 struct _vcs_dpi_ip_params_st *loaded_ip = &dcn3_01_ip; 1488 1489 DC_LOGGER_INIT(dc->ctx->logger); 1490 1491 if (!bb && !is_soc_bounding_box_valid(dc)) { 1492 DC_LOG_ERROR("%s: not valid soc bounding box/n", __func__); 1493 return false; 1494 } 1495 1496 if (bb && !is_soc_bounding_box_valid(dc)) { 1497 int i; 1498 1499 dcn3_01_soc.sr_exit_time_us = 1500 fixed16_to_double_to_cpu(bb->sr_exit_time_us); 1501 dcn3_01_soc.sr_enter_plus_exit_time_us = 1502 fixed16_to_double_to_cpu(bb->sr_enter_plus_exit_time_us); 1503 dcn3_01_soc.urgent_latency_us = 1504 fixed16_to_double_to_cpu(bb->urgent_latency_us); 1505 dcn3_01_soc.urgent_latency_pixel_data_only_us = 1506 fixed16_to_double_to_cpu(bb->urgent_latency_pixel_data_only_us); 1507 dcn3_01_soc.urgent_latency_pixel_mixed_with_vm_data_us = 1508 fixed16_to_double_to_cpu(bb->urgent_latency_pixel_mixed_with_vm_data_us); 1509 dcn3_01_soc.urgent_latency_vm_data_only_us = 1510 fixed16_to_double_to_cpu(bb->urgent_latency_vm_data_only_us); 1511 dcn3_01_soc.urgent_out_of_order_return_per_channel_pixel_only_bytes = 1512 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_pixel_only_bytes); 1513 dcn3_01_soc.urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 1514 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_pixel_and_vm_bytes); 1515 dcn3_01_soc.urgent_out_of_order_return_per_channel_vm_only_bytes = 1516 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_vm_only_bytes); 1517 dcn3_01_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 1518 fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_pixel_only); 1519 dcn3_01_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 1520 fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm); 1521 dcn3_01_soc.pct_ideal_dram_sdp_bw_after_urgent_vm_only = 1522 fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_vm_only); 1523 dcn3_01_soc.max_avg_sdp_bw_use_normal_percent = 1524 fixed16_to_double_to_cpu(bb->max_avg_sdp_bw_use_normal_percent); 1525 dcn3_01_soc.max_avg_dram_bw_use_normal_percent = 1526 fixed16_to_double_to_cpu(bb->max_avg_dram_bw_use_normal_percent); 1527 dcn3_01_soc.writeback_latency_us = 1528 fixed16_to_double_to_cpu(bb->writeback_latency_us); 1529 dcn3_01_soc.ideal_dram_bw_after_urgent_percent = 1530 fixed16_to_double_to_cpu(bb->ideal_dram_bw_after_urgent_percent); 1531 dcn3_01_soc.max_request_size_bytes = 1532 le32_to_cpu(bb->max_request_size_bytes); 1533 dcn3_01_soc.dram_channel_width_bytes = 1534 le32_to_cpu(bb->dram_channel_width_bytes); 1535 dcn3_01_soc.fabric_datapath_to_dcn_data_return_bytes = 1536 le32_to_cpu(bb->fabric_datapath_to_dcn_data_return_bytes); 1537 dcn3_01_soc.dcn_downspread_percent = 1538 fixed16_to_double_to_cpu(bb->dcn_downspread_percent); 1539 dcn3_01_soc.downspread_percent = 1540 fixed16_to_double_to_cpu(bb->downspread_percent); 1541 dcn3_01_soc.dram_page_open_time_ns = 1542 fixed16_to_double_to_cpu(bb->dram_page_open_time_ns); 1543 dcn3_01_soc.dram_rw_turnaround_time_ns = 1544 fixed16_to_double_to_cpu(bb->dram_rw_turnaround_time_ns); 1545 dcn3_01_soc.dram_return_buffer_per_channel_bytes = 1546 le32_to_cpu(bb->dram_return_buffer_per_channel_bytes); 1547 dcn3_01_soc.round_trip_ping_latency_dcfclk_cycles = 1548 le32_to_cpu(bb->round_trip_ping_latency_dcfclk_cycles); 1549 dcn3_01_soc.urgent_out_of_order_return_per_channel_bytes = 1550 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_bytes); 1551 dcn3_01_soc.channel_interleave_bytes = 1552 le32_to_cpu(bb->channel_interleave_bytes); 1553 dcn3_01_soc.num_banks = 1554 le32_to_cpu(bb->num_banks); 1555 dcn3_01_soc.num_chans = 1556 le32_to_cpu(bb->num_chans); 1557 dcn3_01_soc.gpuvm_min_page_size_bytes = 1558 le32_to_cpu(bb->vmm_page_size_bytes); 1559 dcn3_01_soc.dram_clock_change_latency_us = 1560 fixed16_to_double_to_cpu(bb->dram_clock_change_latency_us); 1561 dcn3_01_soc.writeback_dram_clock_change_latency_us = 1562 fixed16_to_double_to_cpu(bb->writeback_dram_clock_change_latency_us); 1563 dcn3_01_soc.return_bus_width_bytes = 1564 le32_to_cpu(bb->return_bus_width_bytes); 1565 dcn3_01_soc.dispclk_dppclk_vco_speed_mhz = 1566 le32_to_cpu(bb->dispclk_dppclk_vco_speed_mhz); 1567 dcn3_01_soc.xfc_bus_transport_time_us = 1568 le32_to_cpu(bb->xfc_bus_transport_time_us); 1569 dcn3_01_soc.xfc_xbuf_latency_tolerance_us = 1570 le32_to_cpu(bb->xfc_xbuf_latency_tolerance_us); 1571 dcn3_01_soc.use_urgent_burst_bw = 1572 le32_to_cpu(bb->use_urgent_burst_bw); 1573 dcn3_01_soc.num_states = 1574 le32_to_cpu(bb->num_states); 1575 1576 for (i = 0; i < dcn3_01_soc.num_states; i++) { 1577 dcn3_01_soc.clock_limits[i].state = 1578 le32_to_cpu(bb->clock_limits[i].state); 1579 dcn3_01_soc.clock_limits[i].dcfclk_mhz = 1580 fixed16_to_double_to_cpu(bb->clock_limits[i].dcfclk_mhz); 1581 dcn3_01_soc.clock_limits[i].fabricclk_mhz = 1582 fixed16_to_double_to_cpu(bb->clock_limits[i].fabricclk_mhz); 1583 dcn3_01_soc.clock_limits[i].dispclk_mhz = 1584 fixed16_to_double_to_cpu(bb->clock_limits[i].dispclk_mhz); 1585 dcn3_01_soc.clock_limits[i].dppclk_mhz = 1586 fixed16_to_double_to_cpu(bb->clock_limits[i].dppclk_mhz); 1587 dcn3_01_soc.clock_limits[i].phyclk_mhz = 1588 fixed16_to_double_to_cpu(bb->clock_limits[i].phyclk_mhz); 1589 dcn3_01_soc.clock_limits[i].socclk_mhz = 1590 fixed16_to_double_to_cpu(bb->clock_limits[i].socclk_mhz); 1591 dcn3_01_soc.clock_limits[i].dscclk_mhz = 1592 fixed16_to_double_to_cpu(bb->clock_limits[i].dscclk_mhz); 1593 dcn3_01_soc.clock_limits[i].dram_speed_mts = 1594 fixed16_to_double_to_cpu(bb->clock_limits[i].dram_speed_mts); 1595 } 1596 } 1597 1598 loaded_ip->max_num_otg = pool->base.res_cap->num_timing_generator; 1599 loaded_ip->max_num_dpp = pool->base.pipe_count; 1600 dcn20_patch_bounding_box(dc, loaded_bb); 1601 1602 if (!bb && dc->ctx->dc_bios->funcs->get_soc_bb_info) { 1603 struct bp_soc_bb_info bb_info = {0}; 1604 1605 if (dc->ctx->dc_bios->funcs->get_soc_bb_info(dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) { 1606 if (bb_info.dram_clock_change_latency_100ns > 0) 1607 dcn3_01_soc.dram_clock_change_latency_us = bb_info.dram_clock_change_latency_100ns * 10; 1608 1609 if (bb_info.dram_sr_enter_exit_latency_100ns > 0) 1610 dcn3_01_soc.sr_enter_plus_exit_time_us = bb_info.dram_sr_enter_exit_latency_100ns * 10; 1611 1612 if (bb_info.dram_sr_exit_latency_100ns > 0) 1613 dcn3_01_soc.sr_exit_time_us = bb_info.dram_sr_exit_latency_100ns * 10; 1614 } 1615 } 1616 1617 return true; 1618 } 1619 1620 static void set_wm_ranges( 1621 struct pp_smu_funcs *pp_smu, 1622 struct _vcs_dpi_soc_bounding_box_st *loaded_bb) 1623 { 1624 struct pp_smu_wm_range_sets ranges = {0}; 1625 int i; 1626 1627 ranges.num_reader_wm_sets = 0; 1628 1629 if (loaded_bb->num_states == 1) { 1630 ranges.reader_wm_sets[0].wm_inst = 0; 1631 ranges.reader_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 1632 ranges.reader_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 1633 ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 1634 ranges.reader_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 1635 1636 ranges.num_reader_wm_sets = 1; 1637 } else if (loaded_bb->num_states > 1) { 1638 for (i = 0; i < 4 && i < loaded_bb->num_states; i++) { 1639 ranges.reader_wm_sets[i].wm_inst = i; 1640 ranges.reader_wm_sets[i].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 1641 ranges.reader_wm_sets[i].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 1642 ranges.reader_wm_sets[i].min_fill_clk_mhz = (i > 0) ? (loaded_bb->clock_limits[i - 1].dram_speed_mts / 16) + 1 : 0; 1643 ranges.reader_wm_sets[i].max_fill_clk_mhz = loaded_bb->clock_limits[i].dram_speed_mts / 16; 1644 1645 ranges.num_reader_wm_sets = i + 1; 1646 } 1647 1648 ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 1649 ranges.reader_wm_sets[ranges.num_reader_wm_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 1650 } 1651 1652 ranges.num_writer_wm_sets = 1; 1653 1654 ranges.writer_wm_sets[0].wm_inst = 0; 1655 ranges.writer_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 1656 ranges.writer_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 1657 ranges.writer_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 1658 ranges.writer_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 1659 1660 /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */ 1661 pp_smu->nv_funcs.set_wm_ranges(&pp_smu->nv_funcs.pp_smu, &ranges); 1662 } 1663 1664 static void dcn301_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) 1665 { 1666 struct dcn301_resource_pool *pool = TO_DCN301_RES_POOL(dc->res_pool); 1667 struct clk_limit_table *clk_table = &bw_params->clk_table; 1668 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES]; 1669 unsigned int i, closest_clk_lvl; 1670 int j; 1671 1672 // Default clock levels are used for diags, which may lead to overclocking. 1673 if (!IS_DIAG_DC(dc->ctx->dce_environment)) { 1674 dcn3_01_ip.max_num_otg = pool->base.res_cap->num_timing_generator; 1675 dcn3_01_ip.max_num_dpp = pool->base.pipe_count; 1676 dcn3_01_soc.num_chans = bw_params->num_channels; 1677 1678 ASSERT(clk_table->num_entries); 1679 for (i = 0; i < clk_table->num_entries; i++) { 1680 /* loop backwards*/ 1681 for (closest_clk_lvl = 0, j = dcn3_01_soc.num_states - 1; j >= 0; j--) { 1682 if ((unsigned int) dcn3_01_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) { 1683 closest_clk_lvl = j; 1684 break; 1685 } 1686 } 1687 1688 clock_limits[i].state = i; 1689 clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; 1690 clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz; 1691 clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz; 1692 clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2; 1693 1694 clock_limits[i].dispclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dispclk_mhz; 1695 clock_limits[i].dppclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dppclk_mhz; 1696 clock_limits[i].dram_bw_per_chan_gbps = dcn3_01_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps; 1697 clock_limits[i].dscclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dscclk_mhz; 1698 clock_limits[i].dtbclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dtbclk_mhz; 1699 clock_limits[i].phyclk_d18_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz; 1700 clock_limits[i].phyclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].phyclk_mhz; 1701 } 1702 for (i = 0; i < clk_table->num_entries; i++) 1703 dcn3_01_soc.clock_limits[i] = clock_limits[i]; 1704 if (clk_table->num_entries) { 1705 dcn3_01_soc.num_states = clk_table->num_entries; 1706 /* duplicate last level */ 1707 dcn3_01_soc.clock_limits[dcn3_01_soc.num_states] = dcn3_01_soc.clock_limits[dcn3_01_soc.num_states - 1]; 1708 dcn3_01_soc.clock_limits[dcn3_01_soc.num_states].state = dcn3_01_soc.num_states; 1709 } 1710 } 1711 1712 dcn3_01_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0; 1713 dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0; 1714 1715 dml_init_instance(&dc->dml, &dcn3_01_soc, &dcn3_01_ip, DML_PROJECT_DCN30); 1716 } 1717 1718 static struct resource_funcs dcn301_res_pool_funcs = { 1719 .destroy = dcn301_destroy_resource_pool, 1720 .link_enc_create = dcn301_link_encoder_create, 1721 .panel_cntl_create = dcn301_panel_cntl_create, 1722 .validate_bandwidth = dcn30_validate_bandwidth, 1723 .calculate_wm_and_dlg = dcn30_calculate_wm_and_dlg, 1724 .populate_dml_pipes = dcn30_populate_dml_pipes_from_context, 1725 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer, 1726 .add_stream_to_ctx = dcn30_add_stream_to_ctx, 1727 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 1728 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, 1729 .set_mcif_arb_params = dcn30_set_mcif_arb_params, 1730 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, 1731 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut, 1732 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut, 1733 .update_bw_bounding_box = dcn301_update_bw_bounding_box 1734 }; 1735 1736 static bool dcn301_resource_construct( 1737 uint8_t num_virtual_links, 1738 struct dc *dc, 1739 struct dcn301_resource_pool *pool) 1740 { 1741 int i, j; 1742 struct dc_context *ctx = dc->ctx; 1743 struct irq_service_init_data init_data; 1744 uint32_t pipe_fuses = read_pipe_fuses(ctx); 1745 uint32_t num_pipes = 0; 1746 1747 DC_LOGGER_INIT(dc->ctx->logger); 1748 1749 ctx->dc_bios->regs = &bios_regs; 1750 1751 pool->base.res_cap = &res_cap_dcn301; 1752 1753 pool->base.funcs = &dcn301_res_pool_funcs; 1754 1755 /************************************************* 1756 * Resource + asic cap harcoding * 1757 *************************************************/ 1758 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1759 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; 1760 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator; 1761 dc->caps.max_downscale_ratio = 600; 1762 dc->caps.i2c_speed_in_khz = 100; 1763 dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a enabled by default*/ 1764 dc->caps.max_cursor_size = 256; 1765 dc->caps.min_horizontal_blanking_period = 80; 1766 dc->caps.dmdata_alloc_size = 2048; 1767 dc->caps.max_slave_planes = 1; 1768 dc->caps.is_apu = true; 1769 dc->caps.post_blend_color_processing = true; 1770 dc->caps.force_dp_tps4_for_cp2520 = true; 1771 dc->caps.extended_aux_timeout_support = true; 1772 #ifdef CONFIG_DRM_AMD_DC_DMUB 1773 dc->caps.dmcub_support = true; 1774 #endif 1775 1776 /* Color pipeline capabilities */ 1777 dc->caps.color.dpp.dcn_arch = 1; 1778 dc->caps.color.dpp.input_lut_shared = 0; 1779 dc->caps.color.dpp.icsc = 1; 1780 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr 1781 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; 1782 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; 1783 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1; 1784 dc->caps.color.dpp.dgam_rom_caps.pq = 1; 1785 dc->caps.color.dpp.dgam_rom_caps.hlg = 1; 1786 dc->caps.color.dpp.post_csc = 1; 1787 dc->caps.color.dpp.gamma_corr = 1; 1788 dc->caps.color.dpp.dgam_rom_for_yuv = 0; 1789 1790 dc->caps.color.dpp.hw_3d_lut = 1; 1791 dc->caps.color.dpp.ogam_ram = 1; 1792 // no OGAM ROM on DCN301 1793 dc->caps.color.dpp.ogam_rom_caps.srgb = 0; 1794 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; 1795 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; 1796 dc->caps.color.dpp.ogam_rom_caps.pq = 0; 1797 dc->caps.color.dpp.ogam_rom_caps.hlg = 0; 1798 dc->caps.color.dpp.ocsc = 0; 1799 1800 dc->caps.color.mpc.gamut_remap = 1; 1801 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2 1802 dc->caps.color.mpc.ogam_ram = 1; 1803 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; 1804 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; 1805 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; 1806 dc->caps.color.mpc.ogam_rom_caps.pq = 0; 1807 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 1808 dc->caps.color.mpc.ocsc = 1; 1809 1810 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 1811 dc->debug = debug_defaults_drv; 1812 else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) { 1813 dc->debug = debug_defaults_diags; 1814 } else 1815 dc->debug = debug_defaults_diags; 1816 // Init the vm_helper 1817 if (dc->vm_helper) 1818 vm_helper_init(dc->vm_helper, 16); 1819 1820 /************************************************* 1821 * Create resources * 1822 *************************************************/ 1823 1824 /* Clock Sources for Pixel Clock*/ 1825 pool->base.clock_sources[DCN301_CLK_SRC_PLL0] = 1826 dcn301_clock_source_create(ctx, ctx->dc_bios, 1827 CLOCK_SOURCE_COMBO_PHY_PLL0, 1828 &clk_src_regs[0], false); 1829 pool->base.clock_sources[DCN301_CLK_SRC_PLL1] = 1830 dcn301_clock_source_create(ctx, ctx->dc_bios, 1831 CLOCK_SOURCE_COMBO_PHY_PLL1, 1832 &clk_src_regs[1], false); 1833 pool->base.clock_sources[DCN301_CLK_SRC_PLL2] = 1834 dcn301_clock_source_create(ctx, ctx->dc_bios, 1835 CLOCK_SOURCE_COMBO_PHY_PLL2, 1836 &clk_src_regs[2], false); 1837 pool->base.clock_sources[DCN301_CLK_SRC_PLL3] = 1838 dcn301_clock_source_create(ctx, ctx->dc_bios, 1839 CLOCK_SOURCE_COMBO_PHY_PLL3, 1840 &clk_src_regs[3], false); 1841 1842 pool->base.clk_src_count = DCN301_CLK_SRC_TOTAL; 1843 1844 /* todo: not reuse phy_pll registers */ 1845 pool->base.dp_clock_source = 1846 dcn301_clock_source_create(ctx, ctx->dc_bios, 1847 CLOCK_SOURCE_ID_DP_DTO, 1848 &clk_src_regs[0], true); 1849 1850 for (i = 0; i < pool->base.clk_src_count; i++) { 1851 if (pool->base.clock_sources[i] == NULL) { 1852 dm_error("DC: failed to create clock sources!\n"); 1853 BREAK_TO_DEBUGGER(); 1854 goto create_fail; 1855 } 1856 } 1857 1858 /* DCCG */ 1859 pool->base.dccg = dccg301_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 1860 if (pool->base.dccg == NULL) { 1861 dm_error("DC: failed to create dccg!\n"); 1862 BREAK_TO_DEBUGGER(); 1863 goto create_fail; 1864 } 1865 1866 init_soc_bounding_box(dc, pool); 1867 1868 if (!dc->debug.disable_pplib_wm_range && pool->base.pp_smu->nv_funcs.set_wm_ranges) 1869 set_wm_ranges(pool->base.pp_smu, &dcn3_01_soc); 1870 1871 num_pipes = dcn3_01_ip.max_num_dpp; 1872 1873 for (i = 0; i < dcn3_01_ip.max_num_dpp; i++) 1874 if (pipe_fuses & 1 << i) 1875 num_pipes--; 1876 dcn3_01_ip.max_num_dpp = num_pipes; 1877 dcn3_01_ip.max_num_otg = num_pipes; 1878 1879 1880 dml_init_instance(&dc->dml, &dcn3_01_soc, &dcn3_01_ip, DML_PROJECT_DCN30); 1881 1882 /* IRQ */ 1883 init_data.ctx = dc->ctx; 1884 pool->base.irqs = dal_irq_service_dcn30_create(&init_data); 1885 if (!pool->base.irqs) 1886 goto create_fail; 1887 1888 /* HUBBUB */ 1889 pool->base.hubbub = dcn301_hubbub_create(ctx); 1890 if (pool->base.hubbub == NULL) { 1891 BREAK_TO_DEBUGGER(); 1892 dm_error("DC: failed to create hubbub!\n"); 1893 goto create_fail; 1894 } 1895 1896 j = 0; 1897 /* HUBPs, DPPs, OPPs and TGs */ 1898 for (i = 0; i < pool->base.pipe_count; i++) { 1899 1900 /* if pipe is disabled, skip instance of HW pipe, 1901 * i.e, skip ASIC register instance 1902 */ 1903 if ((pipe_fuses & (1 << i)) != 0) { 1904 DC_LOG_DEBUG("%s: fusing pipe %d\n", __func__, i); 1905 continue; 1906 } 1907 1908 pool->base.hubps[j] = dcn301_hubp_create(ctx, i); 1909 if (pool->base.hubps[j] == NULL) { 1910 BREAK_TO_DEBUGGER(); 1911 dm_error( 1912 "DC: failed to create hubps!\n"); 1913 goto create_fail; 1914 } 1915 1916 pool->base.dpps[j] = dcn301_dpp_create(ctx, i); 1917 if (pool->base.dpps[j] == NULL) { 1918 BREAK_TO_DEBUGGER(); 1919 dm_error( 1920 "DC: failed to create dpps!\n"); 1921 goto create_fail; 1922 } 1923 1924 pool->base.opps[j] = dcn301_opp_create(ctx, i); 1925 if (pool->base.opps[j] == NULL) { 1926 BREAK_TO_DEBUGGER(); 1927 dm_error( 1928 "DC: failed to create output pixel processor!\n"); 1929 goto create_fail; 1930 } 1931 1932 pool->base.timing_generators[j] = dcn301_timing_generator_create(ctx, i); 1933 if (pool->base.timing_generators[j] == NULL) { 1934 BREAK_TO_DEBUGGER(); 1935 dm_error("DC: failed to create tg!\n"); 1936 goto create_fail; 1937 } 1938 j++; 1939 } 1940 pool->base.timing_generator_count = j; 1941 pool->base.pipe_count = j; 1942 pool->base.mpcc_count = j; 1943 1944 /* ABM (or ABMs for NV2x) */ 1945 /* TODO: */ 1946 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1947 pool->base.multiple_abms[i] = dmub_abm_create(ctx, 1948 &abm_regs[i], 1949 &abm_shift, 1950 &abm_mask); 1951 if (pool->base.multiple_abms[i] == NULL) { 1952 dm_error("DC: failed to create abm for pipe %d!\n", i); 1953 BREAK_TO_DEBUGGER(); 1954 goto create_fail; 1955 } 1956 } 1957 1958 /* MPC and DSC */ 1959 pool->base.mpc = dcn301_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut); 1960 if (pool->base.mpc == NULL) { 1961 BREAK_TO_DEBUGGER(); 1962 dm_error("DC: failed to create mpc!\n"); 1963 goto create_fail; 1964 } 1965 1966 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 1967 pool->base.dscs[i] = dcn301_dsc_create(ctx, i); 1968 if (pool->base.dscs[i] == NULL) { 1969 BREAK_TO_DEBUGGER(); 1970 dm_error("DC: failed to create display stream compressor %d!\n", i); 1971 goto create_fail; 1972 } 1973 } 1974 1975 /* DWB and MMHUBBUB */ 1976 if (!dcn301_dwbc_create(ctx, &pool->base)) { 1977 BREAK_TO_DEBUGGER(); 1978 dm_error("DC: failed to create dwbc!\n"); 1979 goto create_fail; 1980 } 1981 1982 if (!dcn301_mmhubbub_create(ctx, &pool->base)) { 1983 BREAK_TO_DEBUGGER(); 1984 dm_error("DC: failed to create mcif_wb!\n"); 1985 goto create_fail; 1986 } 1987 1988 /* AUX and I2C */ 1989 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1990 pool->base.engines[i] = dcn301_aux_engine_create(ctx, i); 1991 if (pool->base.engines[i] == NULL) { 1992 BREAK_TO_DEBUGGER(); 1993 dm_error( 1994 "DC:failed to create aux engine!!\n"); 1995 goto create_fail; 1996 } 1997 pool->base.hw_i2cs[i] = dcn301_i2c_hw_create(ctx, i); 1998 if (pool->base.hw_i2cs[i] == NULL) { 1999 BREAK_TO_DEBUGGER(); 2000 dm_error( 2001 "DC:failed to create hw i2c!!\n"); 2002 goto create_fail; 2003 } 2004 pool->base.sw_i2cs[i] = NULL; 2005 } 2006 2007 /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */ 2008 if (!resource_construct(num_virtual_links, dc, &pool->base, 2009 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? 2010 &res_create_funcs : &res_create_maximus_funcs))) 2011 goto create_fail; 2012 2013 /* HW Sequencer and Plane caps */ 2014 dcn301_hw_sequencer_construct(dc); 2015 2016 dc->caps.max_planes = pool->base.pipe_count; 2017 2018 for (i = 0; i < dc->caps.max_planes; ++i) 2019 dc->caps.planes[i] = plane_cap; 2020 2021 dc->cap_funcs = cap_funcs; 2022 2023 return true; 2024 2025 create_fail: 2026 2027 dcn301_destruct(pool); 2028 2029 return false; 2030 } 2031 2032 struct resource_pool *dcn301_create_resource_pool( 2033 const struct dc_init_data *init_data, 2034 struct dc *dc) 2035 { 2036 struct dcn301_resource_pool *pool = 2037 kzalloc(sizeof(struct dcn301_resource_pool), GFP_KERNEL); 2038 2039 if (!pool) 2040 return NULL; 2041 2042 if (dcn301_resource_construct(init_data->num_virtual_links, dc, pool)) 2043 return &pool->base; 2044 2045 BREAK_TO_DEBUGGER(); 2046 kfree(pool); 2047 return NULL; 2048 } 2049