1 /*
2  * Copyright 2019-2021 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 
27 #include "dm_services.h"
28 #include "dc.h"
29 
30 #include "dcn301_init.h"
31 
32 #include "resource.h"
33 #include "include/irq_service_interface.h"
34 #include "dcn30/dcn30_resource.h"
35 #include "dcn301_resource.h"
36 
37 #include "dcn20/dcn20_resource.h"
38 
39 #include "dcn10/dcn10_ipp.h"
40 #include "dcn301/dcn301_hubbub.h"
41 #include "dcn30/dcn30_mpc.h"
42 #include "dcn30/dcn30_hubp.h"
43 #include "irq/dcn30/irq_service_dcn30.h"
44 #include "dcn30/dcn30_dpp.h"
45 #include "dcn301/dcn301_optc.h"
46 #include "dcn20/dcn20_hwseq.h"
47 #include "dcn30/dcn30_hwseq.h"
48 #include "dce110/dce110_hw_sequencer.h"
49 #include "dcn30/dcn30_opp.h"
50 #include "dcn20/dcn20_dsc.h"
51 #include "dcn30/dcn30_vpg.h"
52 #include "dcn30/dcn30_afmt.h"
53 #include "dce/dce_clock_source.h"
54 #include "dce/dce_audio.h"
55 #include "dce/dce_hwseq.h"
56 #include "clk_mgr.h"
57 #include "virtual/virtual_stream_encoder.h"
58 #include "dce110/dce110_resource.h"
59 #include "dml/display_mode_vba.h"
60 #include "dcn301/dcn301_dccg.h"
61 #include "dcn10/dcn10_resource.h"
62 #include "dcn30/dcn30_dio_stream_encoder.h"
63 #include "dcn301/dcn301_dio_link_encoder.h"
64 #include "dcn301_panel_cntl.h"
65 
66 #include "vangogh_ip_offset.h"
67 
68 #include "dcn30/dcn30_dwb.h"
69 #include "dcn30/dcn30_mmhubbub.h"
70 
71 #include "dcn/dcn_3_0_1_offset.h"
72 #include "dcn/dcn_3_0_1_sh_mask.h"
73 
74 #include "nbio/nbio_7_2_0_offset.h"
75 
76 #include "dpcs/dpcs_3_0_0_offset.h"
77 #include "dpcs/dpcs_3_0_0_sh_mask.h"
78 
79 #include "reg_helper.h"
80 #include "dce/dmub_abm.h"
81 #include "dce/dce_aux.h"
82 #include "dce/dce_i2c.h"
83 
84 #include "dml/dcn30/dcn30_fpu.h"
85 
86 #include "dml/dcn30/display_mode_vba_30.h"
87 #include "dml/dcn301/dcn301_fpu.h"
88 #include "vm_helper.h"
89 #include "dcn20/dcn20_vmid.h"
90 #include "amdgpu_socbb.h"
91 
92 #define TO_DCN301_RES_POOL(pool)\
93 	container_of(pool, struct dcn301_resource_pool, base)
94 
95 #define DC_LOGGER_INIT(logger)
96 
97 enum dcn301_clk_src_array_id {
98 	DCN301_CLK_SRC_PLL0,
99 	DCN301_CLK_SRC_PLL1,
100 	DCN301_CLK_SRC_PLL2,
101 	DCN301_CLK_SRC_PLL3,
102 	DCN301_CLK_SRC_TOTAL
103 };
104 
105 /* begin *********************
106  * macros to expend register list macro defined in HW object header file
107  */
108 
109 /* DCN */
110 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
111 
112 #define BASE(seg) BASE_INNER(seg)
113 
114 #define SR(reg_name)\
115 		.reg_name = BASE(mm ## reg_name ## _BASE_IDX) +  \
116 					mm ## reg_name
117 
118 #define SRI(reg_name, block, id)\
119 	.reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
120 					mm ## block ## id ## _ ## reg_name
121 
122 #define SRI2(reg_name, block, id)\
123 	.reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
124 					mm ## reg_name
125 
126 #define SRIR(var_name, reg_name, block, id)\
127 	.var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
128 					mm ## block ## id ## _ ## reg_name
129 
130 #define SRII(reg_name, block, id)\
131 	.reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
132 					mm ## block ## id ## _ ## reg_name
133 
134 #define SRII2(reg_name_pre, reg_name_post, id)\
135 	.reg_name_pre ## _ ##  reg_name_post[id] = BASE(mm ## reg_name_pre \
136 			## id ## _ ## reg_name_post ## _BASE_IDX) + \
137 			mm ## reg_name_pre ## id ## _ ## reg_name_post
138 
139 #define SRII_MPC_RMU(reg_name, block, id)\
140 	.RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
141 					mm ## block ## id ## _ ## reg_name
142 
143 #define SRII_DWB(reg_name, temp_name, block, id)\
144 	.reg_name[id] = BASE(mm ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
145 					mm ## block ## id ## _ ## temp_name
146 
147 #define SF_DWB2(reg_name, block, id, field_name, post_fix)	\
148 	.field_name = reg_name ## __ ## field_name ## post_fix
149 
150 #define DCCG_SRII(reg_name, block, id)\
151 	.block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
152 					mm ## block ## id ## _ ## reg_name
153 
154 #define VUPDATE_SRII(reg_name, block, id)\
155 	.reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
156 					mm ## reg_name ## _ ## block ## id
157 
158 /* NBIO */
159 #define NBIO_BASE_INNER(seg) \
160 	NBIO_BASE__INST0_SEG ## seg
161 
162 #define NBIO_BASE(seg) \
163 	NBIO_BASE_INNER(seg)
164 
165 #define NBIO_SR(reg_name)\
166 		.reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \
167 					regBIF_BX0_ ## reg_name
168 
169 /* MMHUB */
170 #define MMHUB_BASE_INNER(seg) \
171 	MMHUB_BASE__INST0_SEG ## seg
172 
173 #define MMHUB_BASE(seg) \
174 	MMHUB_BASE_INNER(seg)
175 
176 #define MMHUB_SR(reg_name)\
177 		.reg_name = MMHUB_BASE(regMM ## reg_name ## _BASE_IDX) + \
178 					regMM ## reg_name
179 
180 /* CLOCK */
181 #define CLK_BASE_INNER(seg) \
182 	CLK_BASE__INST0_SEG ## seg
183 
184 #define CLK_BASE(seg) \
185 	CLK_BASE_INNER(seg)
186 
187 #define CLK_SRI(reg_name, block, inst)\
188 	.reg_name = CLK_BASE(mm ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \
189 					mm ## block ## _ ## inst ## _ ## reg_name
190 
191 static const struct bios_registers bios_regs = {
192 		NBIO_SR(BIOS_SCRATCH_3),
193 		NBIO_SR(BIOS_SCRATCH_6)
194 };
195 
196 #define clk_src_regs(index, pllid)\
197 [index] = {\
198 	CS_COMMON_REG_LIST_DCN3_01(index, pllid),\
199 }
200 
201 static const struct dce110_clk_src_regs clk_src_regs[] = {
202 	clk_src_regs(0, A),
203 	clk_src_regs(1, B),
204 	clk_src_regs(2, C),
205 	clk_src_regs(3, D)
206 };
207 
208 static const struct dce110_clk_src_shift cs_shift = {
209 		CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
210 };
211 
212 static const struct dce110_clk_src_mask cs_mask = {
213 		CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
214 };
215 
216 #define abm_regs(id)\
217 [id] = {\
218 		ABM_DCN301_REG_LIST(id)\
219 }
220 
221 static const struct dce_abm_registers abm_regs[] = {
222 		abm_regs(0),
223 		abm_regs(1),
224 		abm_regs(2),
225 		abm_regs(3),
226 };
227 
228 static const struct dce_abm_shift abm_shift = {
229 		ABM_MASK_SH_LIST_DCN30(__SHIFT)
230 };
231 
232 static const struct dce_abm_mask abm_mask = {
233 		ABM_MASK_SH_LIST_DCN30(_MASK)
234 };
235 
236 #define audio_regs(id)\
237 [id] = {\
238 		AUD_COMMON_REG_LIST(id)\
239 }
240 
241 static const struct dce_audio_registers audio_regs[] = {
242 	audio_regs(0),
243 	audio_regs(1),
244 	audio_regs(2),
245 	audio_regs(3),
246 	audio_regs(4),
247 	audio_regs(5),
248 	audio_regs(6)
249 };
250 
251 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
252 		SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
253 		SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
254 		AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
255 
256 static const struct dce_audio_shift audio_shift = {
257 		DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
258 };
259 
260 static const struct dce_audio_mask audio_mask = {
261 		DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
262 };
263 
264 #define vpg_regs(id)\
265 [id] = {\
266 	VPG_DCN3_REG_LIST(id)\
267 }
268 
269 static const struct dcn30_vpg_registers vpg_regs[] = {
270 	vpg_regs(0),
271 	vpg_regs(1),
272 	vpg_regs(2),
273 	vpg_regs(3),
274 };
275 
276 static const struct dcn30_vpg_shift vpg_shift = {
277 	DCN3_VPG_MASK_SH_LIST(__SHIFT)
278 };
279 
280 static const struct dcn30_vpg_mask vpg_mask = {
281 	DCN3_VPG_MASK_SH_LIST(_MASK)
282 };
283 
284 #define afmt_regs(id)\
285 [id] = {\
286 	AFMT_DCN3_REG_LIST(id)\
287 }
288 
289 static const struct dcn30_afmt_registers afmt_regs[] = {
290 	afmt_regs(0),
291 	afmt_regs(1),
292 	afmt_regs(2),
293 	afmt_regs(3),
294 };
295 
296 static const struct dcn30_afmt_shift afmt_shift = {
297 	DCN3_AFMT_MASK_SH_LIST(__SHIFT)
298 };
299 
300 static const struct dcn30_afmt_mask afmt_mask = {
301 	DCN3_AFMT_MASK_SH_LIST(_MASK)
302 };
303 
304 #define stream_enc_regs(id)\
305 [id] = {\
306 	SE_DCN3_REG_LIST(id)\
307 }
308 
309 static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
310 	stream_enc_regs(0),
311 	stream_enc_regs(1),
312 	stream_enc_regs(2),
313 	stream_enc_regs(3),
314 };
315 
316 static const struct dcn10_stream_encoder_shift se_shift = {
317 		SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
318 };
319 
320 static const struct dcn10_stream_encoder_mask se_mask = {
321 		SE_COMMON_MASK_SH_LIST_DCN30(_MASK)
322 };
323 
324 
325 #define aux_regs(id)\
326 [id] = {\
327 	DCN2_AUX_REG_LIST(id)\
328 }
329 
330 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
331 		aux_regs(0),
332 		aux_regs(1),
333 		aux_regs(2),
334 		aux_regs(3),
335 };
336 
337 #define hpd_regs(id)\
338 [id] = {\
339 	HPD_REG_LIST(id)\
340 }
341 
342 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
343 		hpd_regs(0),
344 		hpd_regs(1),
345 		hpd_regs(2),
346 		hpd_regs(3),
347 };
348 
349 
350 #define link_regs(id, phyid)\
351 [id] = {\
352 	LE_DCN301_REG_LIST(id), \
353 	UNIPHY_DCN2_REG_LIST(phyid), \
354 	DPCS_DCN2_REG_LIST(id), \
355 	SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
356 }
357 
358 static const struct dce110_aux_registers_shift aux_shift = {
359 	DCN_AUX_MASK_SH_LIST(__SHIFT)
360 };
361 
362 static const struct dce110_aux_registers_mask aux_mask = {
363 	DCN_AUX_MASK_SH_LIST(_MASK)
364 };
365 
366 static const struct dcn10_link_enc_registers link_enc_regs[] = {
367 	link_regs(0, A),
368 	link_regs(1, B),
369 	link_regs(2, C),
370 	link_regs(3, D),
371 };
372 
373 static const struct dcn10_link_enc_shift le_shift = {
374 	LINK_ENCODER_MASK_SH_LIST_DCN301(__SHIFT),\
375 	DPCS_DCN2_MASK_SH_LIST(__SHIFT)
376 };
377 
378 static const struct dcn10_link_enc_mask le_mask = {
379 	LINK_ENCODER_MASK_SH_LIST_DCN301(_MASK),\
380 	DPCS_DCN2_MASK_SH_LIST(_MASK)
381 };
382 
383 #define panel_cntl_regs(id)\
384 [id] = {\
385 	DCN301_PANEL_CNTL_REG_LIST(id),\
386 }
387 
388 static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
389 	panel_cntl_regs(0),
390 	panel_cntl_regs(1),
391 };
392 
393 static const struct dcn301_panel_cntl_shift panel_cntl_shift = {
394 	DCN301_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
395 };
396 
397 static const struct dcn301_panel_cntl_mask panel_cntl_mask = {
398 	DCN301_PANEL_CNTL_MASK_SH_LIST(_MASK)
399 };
400 
401 #define dpp_regs(id)\
402 [id] = {\
403 	DPP_REG_LIST_DCN30(id),\
404 }
405 
406 static const struct dcn3_dpp_registers dpp_regs[] = {
407 	dpp_regs(0),
408 	dpp_regs(1),
409 	dpp_regs(2),
410 	dpp_regs(3),
411 };
412 
413 static const struct dcn3_dpp_shift tf_shift = {
414 		DPP_REG_LIST_SH_MASK_DCN30(__SHIFT)
415 };
416 
417 static const struct dcn3_dpp_mask tf_mask = {
418 		DPP_REG_LIST_SH_MASK_DCN30(_MASK)
419 };
420 
421 #define opp_regs(id)\
422 [id] = {\
423 	OPP_REG_LIST_DCN30(id),\
424 }
425 
426 static const struct dcn20_opp_registers opp_regs[] = {
427 	opp_regs(0),
428 	opp_regs(1),
429 	opp_regs(2),
430 	opp_regs(3),
431 };
432 
433 static const struct dcn20_opp_shift opp_shift = {
434 	OPP_MASK_SH_LIST_DCN20(__SHIFT)
435 };
436 
437 static const struct dcn20_opp_mask opp_mask = {
438 	OPP_MASK_SH_LIST_DCN20(_MASK)
439 };
440 
441 #define aux_engine_regs(id)\
442 [id] = {\
443 	AUX_COMMON_REG_LIST0(id), \
444 	.AUXN_IMPCAL = 0, \
445 	.AUXP_IMPCAL = 0, \
446 	.AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
447 }
448 
449 static const struct dce110_aux_registers aux_engine_regs[] = {
450 		aux_engine_regs(0),
451 		aux_engine_regs(1),
452 		aux_engine_regs(2),
453 		aux_engine_regs(3),
454 };
455 
456 #define dwbc_regs_dcn3(id)\
457 [id] = {\
458 	DWBC_COMMON_REG_LIST_DCN30(id),\
459 }
460 
461 static const struct dcn30_dwbc_registers dwbc30_regs[] = {
462 	dwbc_regs_dcn3(0),
463 };
464 
465 static const struct dcn30_dwbc_shift dwbc30_shift = {
466 	DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
467 };
468 
469 static const struct dcn30_dwbc_mask dwbc30_mask = {
470 	DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
471 };
472 
473 #define mcif_wb_regs_dcn3(id)\
474 [id] = {\
475 	MCIF_WB_COMMON_REG_LIST_DCN30(id),\
476 }
477 
478 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = {
479 	mcif_wb_regs_dcn3(0)
480 };
481 
482 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
483 	MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
484 };
485 
486 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
487 	MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK)
488 };
489 
490 #define dsc_regsDCN20(id)\
491 [id] = {\
492 	DSC_REG_LIST_DCN20(id)\
493 }
494 
495 static const struct dcn20_dsc_registers dsc_regs[] = {
496 	dsc_regsDCN20(0),
497 	dsc_regsDCN20(1),
498 	dsc_regsDCN20(2),
499 };
500 
501 static const struct dcn20_dsc_shift dsc_shift = {
502 	DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
503 };
504 
505 static const struct dcn20_dsc_mask dsc_mask = {
506 	DSC_REG_LIST_SH_MASK_DCN20(_MASK)
507 };
508 
509 static const struct dcn30_mpc_registers mpc_regs = {
510 		MPC_REG_LIST_DCN3_0(0),
511 		MPC_REG_LIST_DCN3_0(1),
512 		MPC_REG_LIST_DCN3_0(2),
513 		MPC_REG_LIST_DCN3_0(3),
514 		MPC_OUT_MUX_REG_LIST_DCN3_0(0),
515 		MPC_OUT_MUX_REG_LIST_DCN3_0(1),
516 		MPC_OUT_MUX_REG_LIST_DCN3_0(2),
517 		MPC_OUT_MUX_REG_LIST_DCN3_0(3),
518 		MPC_RMU_GLOBAL_REG_LIST_DCN3AG,
519 		MPC_RMU_REG_LIST_DCN3AG(0),
520 		MPC_RMU_REG_LIST_DCN3AG(1),
521 		MPC_DWB_MUX_REG_LIST_DCN3_0(0),
522 };
523 
524 static const struct dcn30_mpc_shift mpc_shift = {
525 	MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
526 };
527 
528 static const struct dcn30_mpc_mask mpc_mask = {
529 	MPC_COMMON_MASK_SH_LIST_DCN30(_MASK)
530 };
531 
532 #define optc_regs(id)\
533 [id] = {OPTC_COMMON_REG_LIST_DCN3_0(id)}
534 
535 
536 static const struct dcn_optc_registers optc_regs[] = {
537 	optc_regs(0),
538 	optc_regs(1),
539 	optc_regs(2),
540 	optc_regs(3),
541 };
542 
543 static const struct dcn_optc_shift optc_shift = {
544 	OPTC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
545 };
546 
547 static const struct dcn_optc_mask optc_mask = {
548 	OPTC_COMMON_MASK_SH_LIST_DCN30(_MASK)
549 };
550 
551 #define hubp_regs(id)\
552 [id] = {\
553 	HUBP_REG_LIST_DCN30(id)\
554 }
555 
556 static const struct dcn_hubp2_registers hubp_regs[] = {
557 		hubp_regs(0),
558 		hubp_regs(1),
559 		hubp_regs(2),
560 		hubp_regs(3),
561 };
562 
563 static const struct dcn_hubp2_shift hubp_shift = {
564 		HUBP_MASK_SH_LIST_DCN30(__SHIFT)
565 };
566 
567 static const struct dcn_hubp2_mask hubp_mask = {
568 		HUBP_MASK_SH_LIST_DCN30(_MASK)
569 };
570 
571 static const struct dcn_hubbub_registers hubbub_reg = {
572 		HUBBUB_REG_LIST_DCN301(0)
573 };
574 
575 static const struct dcn_hubbub_shift hubbub_shift = {
576 		HUBBUB_MASK_SH_LIST_DCN301(__SHIFT)
577 };
578 
579 static const struct dcn_hubbub_mask hubbub_mask = {
580 		HUBBUB_MASK_SH_LIST_DCN301(_MASK)
581 };
582 
583 static const struct dccg_registers dccg_regs = {
584 		DCCG_REG_LIST_DCN301()
585 };
586 
587 static const struct dccg_shift dccg_shift = {
588 		DCCG_MASK_SH_LIST_DCN301(__SHIFT)
589 };
590 
591 static const struct dccg_mask dccg_mask = {
592 		DCCG_MASK_SH_LIST_DCN301(_MASK)
593 };
594 
595 static const struct dce_hwseq_registers hwseq_reg = {
596 		HWSEQ_DCN301_REG_LIST()
597 };
598 
599 static const struct dce_hwseq_shift hwseq_shift = {
600 		HWSEQ_DCN301_MASK_SH_LIST(__SHIFT)
601 };
602 
603 static const struct dce_hwseq_mask hwseq_mask = {
604 		HWSEQ_DCN301_MASK_SH_LIST(_MASK)
605 };
606 #define vmid_regs(id)\
607 [id] = {\
608 		DCN20_VMID_REG_LIST(id)\
609 }
610 
611 static const struct dcn_vmid_registers vmid_regs[] = {
612 	vmid_regs(0),
613 	vmid_regs(1),
614 	vmid_regs(2),
615 	vmid_regs(3),
616 	vmid_regs(4),
617 	vmid_regs(5),
618 	vmid_regs(6),
619 	vmid_regs(7),
620 	vmid_regs(8),
621 	vmid_regs(9),
622 	vmid_regs(10),
623 	vmid_regs(11),
624 	vmid_regs(12),
625 	vmid_regs(13),
626 	vmid_regs(14),
627 	vmid_regs(15)
628 };
629 
630 static const struct dcn20_vmid_shift vmid_shifts = {
631 		DCN20_VMID_MASK_SH_LIST(__SHIFT)
632 };
633 
634 static const struct dcn20_vmid_mask vmid_masks = {
635 		DCN20_VMID_MASK_SH_LIST(_MASK)
636 };
637 
638 static struct resource_caps res_cap_dcn301 = {
639 	.num_timing_generator = 4,
640 	.num_opp = 4,
641 	.num_video_plane = 4,
642 	.num_audio = 4,
643 	.num_stream_encoder = 4,
644 	.num_pll = 4,
645 	.num_dwb = 1,
646 	.num_ddc = 4,
647 	.num_vmid = 16,
648 	.num_mpc_3dlut = 2,
649 	.num_dsc = 3,
650 };
651 
652 static const struct dc_plane_cap plane_cap = {
653 	.type = DC_PLANE_TYPE_DCN_UNIVERSAL,
654 	.per_pixel_alpha = true,
655 
656 	.pixel_format_support = {
657 			.argb8888 = true,
658 			.nv12 = true,
659 			.fp16 = true,
660 			.p010 = true,
661 			.ayuv = false,
662 	},
663 
664 	.max_upscale_factor = {
665 			.argb8888 = 16000,
666 			.nv12 = 16000,
667 			.fp16 = 16000
668 	},
669 
670 	/* 6:1 downscaling ratio: 1000/6 = 166.666 */
671 	.max_downscale_factor = {
672 			.argb8888 = 167,
673 			.nv12 = 167,
674 			.fp16 = 167
675 	},
676 	64,
677 	64
678 };
679 
680 static const struct dc_debug_options debug_defaults_drv = {
681 	.disable_dmcu = true,
682 	.force_abm_enable = false,
683 	.timing_trace = false,
684 	.clock_trace = true,
685 	.disable_dpp_power_gate = false,
686 	.disable_hubp_power_gate = false,
687 	.disable_clock_gate = true,
688 	.disable_pplib_clock_request = true,
689 	.disable_pplib_wm_range = true,
690 	.pipe_split_policy = MPC_SPLIT_DYNAMIC,
691 	.force_single_disp_pipe_split = false,
692 	.disable_dcc = DCC_ENABLE,
693 	.vsr_support = true,
694 	.performance_trace = false,
695 	.max_downscale_src_width = 7680,/*upto 8K*/
696 	.scl_reset_length10 = true,
697 	.sanity_checks = false,
698 	.underflow_assert_delay_us = 0xFFFFFFFF,
699 	.dwb_fi_phase = -1, // -1 = disable
700 	.dmub_command_table = true,
701 	.use_max_lb = false,
702 	.exit_idle_opt_for_cursor_updates = true
703 };
704 
705 static void dcn301_dpp_destroy(struct dpp **dpp)
706 {
707 	kfree(TO_DCN20_DPP(*dpp));
708 	*dpp = NULL;
709 }
710 
711 static struct dpp *dcn301_dpp_create(struct dc_context *ctx, uint32_t inst)
712 {
713 	struct dcn3_dpp *dpp =
714 		kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);
715 
716 	if (!dpp)
717 		return NULL;
718 
719 	if (dpp3_construct(dpp, ctx, inst,
720 			&dpp_regs[inst], &tf_shift, &tf_mask))
721 		return &dpp->base;
722 
723 	BREAK_TO_DEBUGGER();
724 	kfree(dpp);
725 	return NULL;
726 }
727 static struct output_pixel_processor *dcn301_opp_create(struct dc_context *ctx,
728 							uint32_t inst)
729 {
730 	struct dcn20_opp *opp =
731 		kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
732 
733 	if (!opp) {
734 		BREAK_TO_DEBUGGER();
735 		return NULL;
736 	}
737 
738 	dcn20_opp_construct(opp, ctx, inst,
739 			&opp_regs[inst], &opp_shift, &opp_mask);
740 	return &opp->base;
741 }
742 
743 static struct dce_aux *dcn301_aux_engine_create(struct dc_context *ctx, uint32_t inst)
744 {
745 	struct aux_engine_dce110 *aux_engine =
746 		kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
747 
748 	if (!aux_engine)
749 		return NULL;
750 
751 	dce110_aux_engine_construct(aux_engine, ctx, inst,
752 				    SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
753 				    &aux_engine_regs[inst],
754 					&aux_mask,
755 					&aux_shift,
756 					ctx->dc->caps.extended_aux_timeout_support);
757 
758 	return &aux_engine->base;
759 }
760 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
761 
762 static const struct dce_i2c_registers i2c_hw_regs[] = {
763 		i2c_inst_regs(1),
764 		i2c_inst_regs(2),
765 		i2c_inst_regs(3),
766 		i2c_inst_regs(4),
767 };
768 
769 static const struct dce_i2c_shift i2c_shifts = {
770 		I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT)
771 };
772 
773 static const struct dce_i2c_mask i2c_masks = {
774 		I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)
775 };
776 
777 static struct dce_i2c_hw *dcn301_i2c_hw_create(struct dc_context *ctx, uint32_t inst)
778 {
779 	struct dce_i2c_hw *dce_i2c_hw =
780 		kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
781 
782 	if (!dce_i2c_hw)
783 		return NULL;
784 
785 	dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
786 				    &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
787 
788 	return dce_i2c_hw;
789 }
790 static struct mpc *dcn301_mpc_create(
791 		struct dc_context *ctx,
792 		int num_mpcc,
793 		int num_rmu)
794 {
795 	struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc),
796 					  GFP_KERNEL);
797 
798 	if (!mpc30)
799 		return NULL;
800 
801 	dcn30_mpc_construct(mpc30, ctx,
802 			&mpc_regs,
803 			&mpc_shift,
804 			&mpc_mask,
805 			num_mpcc,
806 			num_rmu);
807 
808 	return &mpc30->base;
809 }
810 
811 static struct hubbub *dcn301_hubbub_create(struct dc_context *ctx)
812 {
813 	int i;
814 
815 	struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub),
816 					  GFP_KERNEL);
817 
818 	if (!hubbub3)
819 		return NULL;
820 
821 	hubbub301_construct(hubbub3, ctx,
822 			&hubbub_reg,
823 			&hubbub_shift,
824 			&hubbub_mask);
825 
826 
827 	for (i = 0; i < res_cap_dcn301.num_vmid; i++) {
828 		struct dcn20_vmid *vmid = &hubbub3->vmid[i];
829 
830 		vmid->ctx = ctx;
831 
832 		vmid->regs = &vmid_regs[i];
833 		vmid->shifts = &vmid_shifts;
834 		vmid->masks = &vmid_masks;
835 	}
836 
837 	hubbub3->num_vmid = res_cap_dcn301.num_vmid;
838 
839 	return &hubbub3->base;
840 }
841 
842 static struct timing_generator *dcn301_timing_generator_create(
843 	struct dc_context *ctx, uint32_t instance)
844 {
845 	struct optc *tgn10 =
846 		kzalloc(sizeof(struct optc), GFP_KERNEL);
847 
848 	if (!tgn10)
849 		return NULL;
850 
851 	tgn10->base.inst = instance;
852 	tgn10->base.ctx = ctx;
853 
854 	tgn10->tg_regs = &optc_regs[instance];
855 	tgn10->tg_shift = &optc_shift;
856 	tgn10->tg_mask = &optc_mask;
857 
858 	dcn301_timing_generator_init(tgn10);
859 
860 	return &tgn10->base;
861 }
862 
863 static const struct encoder_feature_support link_enc_feature = {
864 		.max_hdmi_deep_color = COLOR_DEPTH_121212,
865 		.max_hdmi_pixel_clock = 600000,
866 		.hdmi_ycbcr420_supported = true,
867 		.dp_ycbcr420_supported = true,
868 		.fec_supported = true,
869 		.flags.bits.IS_HBR2_CAPABLE = true,
870 		.flags.bits.IS_HBR3_CAPABLE = true,
871 		.flags.bits.IS_TPS3_CAPABLE = true,
872 		.flags.bits.IS_TPS4_CAPABLE = true
873 };
874 
875 static struct link_encoder *dcn301_link_encoder_create(
876 	struct dc_context *ctx,
877 	const struct encoder_init_data *enc_init_data)
878 {
879 	struct dcn20_link_encoder *enc20 =
880 		kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
881 
882 	if (!enc20)
883 		return NULL;
884 
885 	dcn301_link_encoder_construct(enc20,
886 			enc_init_data,
887 			&link_enc_feature,
888 			&link_enc_regs[enc_init_data->transmitter],
889 			&link_enc_aux_regs[enc_init_data->channel - 1],
890 			&link_enc_hpd_regs[enc_init_data->hpd_source],
891 			&le_shift,
892 			&le_mask);
893 
894 	return &enc20->enc10.base;
895 }
896 
897 static struct panel_cntl *dcn301_panel_cntl_create(const struct panel_cntl_init_data *init_data)
898 {
899 	struct dcn301_panel_cntl *panel_cntl =
900 		kzalloc(sizeof(struct dcn301_panel_cntl), GFP_KERNEL);
901 
902 	if (!panel_cntl)
903 		return NULL;
904 
905 	dcn301_panel_cntl_construct(panel_cntl,
906 			init_data,
907 			&panel_cntl_regs[init_data->inst],
908 			&panel_cntl_shift,
909 			&panel_cntl_mask);
910 
911 	return &panel_cntl->base;
912 }
913 
914 
915 #define CTX ctx
916 
917 #define REG(reg_name) \
918 	(DCN_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
919 
920 static uint32_t read_pipe_fuses(struct dc_context *ctx)
921 {
922 	uint32_t value = REG_READ(CC_DC_PIPE_DIS);
923 	/* RV1 support max 4 pipes */
924 	value = value & 0xf;
925 	return value;
926 }
927 
928 
929 static void read_dce_straps(
930 	struct dc_context *ctx,
931 	struct resource_straps *straps)
932 {
933 	generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
934 		FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
935 
936 }
937 
938 static struct audio *dcn301_create_audio(
939 		struct dc_context *ctx, unsigned int inst)
940 {
941 	return dce_audio_create(ctx, inst,
942 			&audio_regs[inst], &audio_shift, &audio_mask);
943 }
944 
945 static struct vpg *dcn301_vpg_create(
946 	struct dc_context *ctx,
947 	uint32_t inst)
948 {
949 	struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL);
950 
951 	if (!vpg3)
952 		return NULL;
953 
954 	vpg3_construct(vpg3, ctx, inst,
955 			&vpg_regs[inst],
956 			&vpg_shift,
957 			&vpg_mask);
958 
959 	return &vpg3->base;
960 }
961 
962 static struct afmt *dcn301_afmt_create(
963 	struct dc_context *ctx,
964 	uint32_t inst)
965 {
966 	struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL);
967 
968 	if (!afmt3)
969 		return NULL;
970 
971 	afmt3_construct(afmt3, ctx, inst,
972 			&afmt_regs[inst],
973 			&afmt_shift,
974 			&afmt_mask);
975 
976 	return &afmt3->base;
977 }
978 
979 static struct stream_encoder *dcn301_stream_encoder_create(enum engine_id eng_id,
980 							   struct dc_context *ctx)
981 {
982 	struct dcn10_stream_encoder *enc1;
983 	struct vpg *vpg;
984 	struct afmt *afmt;
985 	int vpg_inst;
986 	int afmt_inst;
987 
988 	/* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
989 	if (eng_id <= ENGINE_ID_DIGF) {
990 		vpg_inst = eng_id;
991 		afmt_inst = eng_id;
992 	} else
993 		return NULL;
994 
995 	enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
996 	vpg = dcn301_vpg_create(ctx, vpg_inst);
997 	afmt = dcn301_afmt_create(ctx, afmt_inst);
998 
999 	if (!enc1 || !vpg || !afmt) {
1000 		kfree(enc1);
1001 		kfree(vpg);
1002 		kfree(afmt);
1003 		return NULL;
1004 	}
1005 
1006 	dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
1007 					eng_id, vpg, afmt,
1008 					&stream_enc_regs[eng_id],
1009 					&se_shift, &se_mask);
1010 
1011 	return &enc1->base;
1012 }
1013 
1014 static struct dce_hwseq *dcn301_hwseq_create(struct dc_context *ctx)
1015 {
1016 	struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1017 
1018 	if (hws) {
1019 		hws->ctx = ctx;
1020 		hws->regs = &hwseq_reg;
1021 		hws->shifts = &hwseq_shift;
1022 		hws->masks = &hwseq_mask;
1023 	}
1024 	return hws;
1025 }
1026 static const struct resource_create_funcs res_create_funcs = {
1027 	.read_dce_straps = read_dce_straps,
1028 	.create_audio = dcn301_create_audio,
1029 	.create_stream_encoder = dcn301_stream_encoder_create,
1030 	.create_hwseq = dcn301_hwseq_create,
1031 };
1032 
1033 static void dcn301_destruct(struct dcn301_resource_pool *pool)
1034 {
1035 	unsigned int i;
1036 
1037 	for (i = 0; i < pool->base.stream_enc_count; i++) {
1038 		if (pool->base.stream_enc[i] != NULL) {
1039 			if (pool->base.stream_enc[i]->vpg != NULL) {
1040 				kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
1041 				pool->base.stream_enc[i]->vpg = NULL;
1042 			}
1043 			if (pool->base.stream_enc[i]->afmt != NULL) {
1044 				kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));
1045 				pool->base.stream_enc[i]->afmt = NULL;
1046 			}
1047 			kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1048 			pool->base.stream_enc[i] = NULL;
1049 		}
1050 	}
1051 
1052 	for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1053 		if (pool->base.dscs[i] != NULL)
1054 			dcn20_dsc_destroy(&pool->base.dscs[i]);
1055 	}
1056 
1057 	if (pool->base.mpc != NULL) {
1058 		kfree(TO_DCN20_MPC(pool->base.mpc));
1059 		pool->base.mpc = NULL;
1060 	}
1061 	if (pool->base.hubbub != NULL) {
1062 		kfree(pool->base.hubbub);
1063 		pool->base.hubbub = NULL;
1064 	}
1065 	for (i = 0; i < pool->base.pipe_count; i++) {
1066 		if (pool->base.dpps[i] != NULL)
1067 			dcn301_dpp_destroy(&pool->base.dpps[i]);
1068 
1069 		if (pool->base.ipps[i] != NULL)
1070 			pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1071 
1072 		if (pool->base.hubps[i] != NULL) {
1073 			kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1074 			pool->base.hubps[i] = NULL;
1075 		}
1076 
1077 		if (pool->base.irqs != NULL) {
1078 			dal_irq_service_destroy(&pool->base.irqs);
1079 		}
1080 	}
1081 
1082 	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1083 		if (pool->base.engines[i] != NULL)
1084 			dce110_engine_destroy(&pool->base.engines[i]);
1085 		if (pool->base.hw_i2cs[i] != NULL) {
1086 			kfree(pool->base.hw_i2cs[i]);
1087 			pool->base.hw_i2cs[i] = NULL;
1088 		}
1089 		if (pool->base.sw_i2cs[i] != NULL) {
1090 			kfree(pool->base.sw_i2cs[i]);
1091 			pool->base.sw_i2cs[i] = NULL;
1092 		}
1093 	}
1094 
1095 	for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1096 		if (pool->base.opps[i] != NULL)
1097 			pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1098 	}
1099 
1100 	for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1101 		if (pool->base.timing_generators[i] != NULL)	{
1102 			kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1103 			pool->base.timing_generators[i] = NULL;
1104 		}
1105 	}
1106 
1107 	for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1108 		if (pool->base.dwbc[i] != NULL) {
1109 			kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
1110 			pool->base.dwbc[i] = NULL;
1111 		}
1112 		if (pool->base.mcif_wb[i] != NULL) {
1113 			kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));
1114 			pool->base.mcif_wb[i] = NULL;
1115 		}
1116 	}
1117 
1118 	for (i = 0; i < pool->base.audio_count; i++) {
1119 		if (pool->base.audios[i])
1120 			dce_aud_destroy(&pool->base.audios[i]);
1121 	}
1122 
1123 	for (i = 0; i < pool->base.clk_src_count; i++) {
1124 		if (pool->base.clock_sources[i] != NULL) {
1125 			dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1126 			pool->base.clock_sources[i] = NULL;
1127 		}
1128 	}
1129 
1130 	for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
1131 		if (pool->base.mpc_lut[i] != NULL) {
1132 			dc_3dlut_func_release(pool->base.mpc_lut[i]);
1133 			pool->base.mpc_lut[i] = NULL;
1134 		}
1135 		if (pool->base.mpc_shaper[i] != NULL) {
1136 			dc_transfer_func_release(pool->base.mpc_shaper[i]);
1137 			pool->base.mpc_shaper[i] = NULL;
1138 		}
1139 	}
1140 
1141 	if (pool->base.dp_clock_source != NULL) {
1142 		dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1143 		pool->base.dp_clock_source = NULL;
1144 	}
1145 
1146 	for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1147 		if (pool->base.multiple_abms[i] != NULL)
1148 			dce_abm_destroy(&pool->base.multiple_abms[i]);
1149 	}
1150 
1151 	if (pool->base.dccg != NULL)
1152 		dcn_dccg_destroy(&pool->base.dccg);
1153 }
1154 
1155 static struct hubp *dcn301_hubp_create(struct dc_context *ctx, uint32_t inst)
1156 {
1157 	struct dcn20_hubp *hubp2 =
1158 		kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
1159 
1160 	if (!hubp2)
1161 		return NULL;
1162 
1163 	if (hubp3_construct(hubp2, ctx, inst,
1164 			&hubp_regs[inst], &hubp_shift, &hubp_mask))
1165 		return &hubp2->base;
1166 
1167 	BREAK_TO_DEBUGGER();
1168 	kfree(hubp2);
1169 	return NULL;
1170 }
1171 
1172 static bool dcn301_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
1173 {
1174 	int i;
1175 	uint32_t pipe_count = pool->res_cap->num_dwb;
1176 
1177 	for (i = 0; i < pipe_count; i++) {
1178 		struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc),
1179 						    GFP_KERNEL);
1180 
1181 		if (!dwbc30) {
1182 			dm_error("DC: failed to create dwbc30!\n");
1183 			return false;
1184 		}
1185 
1186 		dcn30_dwbc_construct(dwbc30, ctx,
1187 				&dwbc30_regs[i],
1188 				&dwbc30_shift,
1189 				&dwbc30_mask,
1190 				i);
1191 
1192 		pool->dwbc[i] = &dwbc30->base;
1193 	}
1194 	return true;
1195 }
1196 
1197 static bool dcn301_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
1198 {
1199 	int i;
1200 	uint32_t pipe_count = pool->res_cap->num_dwb;
1201 
1202 	for (i = 0; i < pipe_count; i++) {
1203 		struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub),
1204 						    GFP_KERNEL);
1205 
1206 		if (!mcif_wb30) {
1207 			dm_error("DC: failed to create mcif_wb30!\n");
1208 			return false;
1209 		}
1210 
1211 		dcn30_mmhubbub_construct(mcif_wb30, ctx,
1212 				&mcif_wb30_regs[i],
1213 				&mcif_wb30_shift,
1214 				&mcif_wb30_mask,
1215 				i);
1216 
1217 		pool->mcif_wb[i] = &mcif_wb30->base;
1218 	}
1219 	return true;
1220 }
1221 
1222 static struct display_stream_compressor *dcn301_dsc_create(
1223 	struct dc_context *ctx, uint32_t inst)
1224 {
1225 	struct dcn20_dsc *dsc =
1226 		kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1227 
1228 	if (!dsc) {
1229 		BREAK_TO_DEBUGGER();
1230 		return NULL;
1231 	}
1232 
1233 	dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1234 	return &dsc->base;
1235 }
1236 
1237 
1238 static void dcn301_destroy_resource_pool(struct resource_pool **pool)
1239 {
1240 	struct dcn301_resource_pool *dcn301_pool = TO_DCN301_RES_POOL(*pool);
1241 
1242 	dcn301_destruct(dcn301_pool);
1243 	kfree(dcn301_pool);
1244 	*pool = NULL;
1245 }
1246 
1247 static struct clock_source *dcn301_clock_source_create(
1248 		struct dc_context *ctx,
1249 		struct dc_bios *bios,
1250 		enum clock_source_id id,
1251 		const struct dce110_clk_src_regs *regs,
1252 		bool dp_clk_src)
1253 {
1254 	struct dce110_clk_src *clk_src =
1255 		kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1256 
1257 	if (!clk_src)
1258 		return NULL;
1259 
1260 	if (dcn301_clk_src_construct(clk_src, ctx, bios, id,
1261 			regs, &cs_shift, &cs_mask)) {
1262 		clk_src->base.dp_clk_src = dp_clk_src;
1263 		return &clk_src->base;
1264 	}
1265 
1266 	kfree(clk_src);
1267 	BREAK_TO_DEBUGGER();
1268 	return NULL;
1269 }
1270 
1271 static struct dc_cap_funcs cap_funcs = {
1272 	.get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1273 };
1274 
1275 
1276 static bool is_soc_bounding_box_valid(struct dc *dc)
1277 {
1278 	uint32_t hw_internal_rev = dc->ctx->asic_id.hw_internal_rev;
1279 
1280 	if (ASICREV_IS_VANGOGH(hw_internal_rev))
1281 		return true;
1282 
1283 	return false;
1284 }
1285 
1286 static bool init_soc_bounding_box(struct dc *dc,
1287 				  struct dcn301_resource_pool *pool)
1288 {
1289 	struct _vcs_dpi_soc_bounding_box_st *loaded_bb = &dcn3_01_soc;
1290 	struct _vcs_dpi_ip_params_st *loaded_ip = &dcn3_01_ip;
1291 
1292 	DC_LOGGER_INIT(dc->ctx->logger);
1293 
1294 	if (!is_soc_bounding_box_valid(dc)) {
1295 		DC_LOG_ERROR("%s: not valid soc bounding box\n", __func__);
1296 		return false;
1297 	}
1298 
1299 	loaded_ip->max_num_otg = pool->base.res_cap->num_timing_generator;
1300 	loaded_ip->max_num_dpp = pool->base.pipe_count;
1301 	DC_FP_START();
1302 	dcn20_patch_bounding_box(dc, loaded_bb);
1303 	DC_FP_END();
1304 
1305 	if (dc->ctx->dc_bios->funcs->get_soc_bb_info) {
1306 		struct bp_soc_bb_info bb_info = {0};
1307 
1308 		if (dc->ctx->dc_bios->funcs->get_soc_bb_info(dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) {
1309 			DC_FP_START();
1310 			dcn301_fpu_init_soc_bounding_box(bb_info);
1311 			DC_FP_END();
1312 		}
1313 	}
1314 
1315 	return true;
1316 }
1317 
1318 
1319 static void set_wm_ranges(
1320 		struct pp_smu_funcs *pp_smu,
1321 		struct _vcs_dpi_soc_bounding_box_st *loaded_bb)
1322 {
1323 	struct pp_smu_wm_range_sets ranges = {0};
1324 	int i;
1325 
1326 	ranges.num_reader_wm_sets = 0;
1327 
1328 	if (loaded_bb->num_states == 1) {
1329 		ranges.reader_wm_sets[0].wm_inst = 0;
1330 		ranges.reader_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
1331 		ranges.reader_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
1332 		ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
1333 		ranges.reader_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
1334 
1335 		ranges.num_reader_wm_sets = 1;
1336 	} else if (loaded_bb->num_states > 1) {
1337 		for (i = 0; i < 4 && i < loaded_bb->num_states; i++) {
1338 			ranges.reader_wm_sets[i].wm_inst = i;
1339 			ranges.reader_wm_sets[i].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
1340 			ranges.reader_wm_sets[i].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
1341 			DC_FP_START();
1342 			dcn301_fpu_set_wm_ranges(i, &ranges, loaded_bb);
1343 			DC_FP_END();
1344 			ranges.num_reader_wm_sets = i + 1;
1345 		}
1346 
1347 		ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
1348 		ranges.reader_wm_sets[ranges.num_reader_wm_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
1349 	}
1350 
1351 	ranges.num_writer_wm_sets = 1;
1352 
1353 	ranges.writer_wm_sets[0].wm_inst = 0;
1354 	ranges.writer_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
1355 	ranges.writer_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
1356 	ranges.writer_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
1357 	ranges.writer_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
1358 
1359 	/* Notify PP Lib/SMU which Watermarks to use for which clock ranges */
1360 	pp_smu->nv_funcs.set_wm_ranges(&pp_smu->nv_funcs.pp_smu, &ranges);
1361 }
1362 
1363 static void dcn301_calculate_wm_and_dlg(
1364 		struct dc *dc, struct dc_state *context,
1365 		display_e2e_pipe_params_st *pipes,
1366 		int pipe_cnt,
1367 		int vlevel)
1368 {
1369 	DC_FP_START();
1370 	dcn301_calculate_wm_and_dlg_fp(dc, context, pipes, pipe_cnt, vlevel);
1371 	DC_FP_END();
1372 }
1373 
1374 static struct resource_funcs dcn301_res_pool_funcs = {
1375 	.destroy = dcn301_destroy_resource_pool,
1376 	.link_enc_create = dcn301_link_encoder_create,
1377 	.panel_cntl_create = dcn301_panel_cntl_create,
1378 	.validate_bandwidth = dcn30_validate_bandwidth,
1379 	.calculate_wm_and_dlg = dcn301_calculate_wm_and_dlg,
1380 	.update_soc_for_wm_a = dcn30_update_soc_for_wm_a,
1381 	.populate_dml_pipes = dcn30_populate_dml_pipes_from_context,
1382 	.acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer,
1383 	.add_stream_to_ctx = dcn30_add_stream_to_ctx,
1384 	.add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
1385 	.remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1386 	.populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
1387 	.set_mcif_arb_params = dcn30_set_mcif_arb_params,
1388 	.find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1389 	.acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
1390 	.release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
1391 	.update_bw_bounding_box = dcn301_update_bw_bounding_box,
1392 	.patch_unknown_plane_state = dcn20_patch_unknown_plane_state
1393 };
1394 
1395 static bool dcn301_resource_construct(
1396 	uint8_t num_virtual_links,
1397 	struct dc *dc,
1398 	struct dcn301_resource_pool *pool)
1399 {
1400 	int i, j;
1401 	struct dc_context *ctx = dc->ctx;
1402 	struct irq_service_init_data init_data;
1403 	uint32_t pipe_fuses = read_pipe_fuses(ctx);
1404 	uint32_t num_pipes = 0;
1405 
1406 	DC_LOGGER_INIT(dc->ctx->logger);
1407 
1408 	ctx->dc_bios->regs = &bios_regs;
1409 
1410 	if (dc->ctx->asic_id.chip_id == DEVICE_ID_VGH_1435)
1411 		res_cap_dcn301.num_pll = 2;
1412 	pool->base.res_cap = &res_cap_dcn301;
1413 
1414 	pool->base.funcs = &dcn301_res_pool_funcs;
1415 
1416 	/*************************************************
1417 	 *  Resource + asic cap harcoding                *
1418 	 *************************************************/
1419 	pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1420 	pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1421 	pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;
1422 	dc->caps.max_downscale_ratio = 600;
1423 	dc->caps.i2c_speed_in_khz = 100;
1424 	dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a enabled by default*/
1425 	dc->caps.max_cursor_size = 256;
1426 	dc->caps.min_horizontal_blanking_period = 80;
1427 	dc->caps.dmdata_alloc_size = 2048;
1428 	dc->caps.max_slave_planes = 2;
1429 	dc->caps.max_slave_yuv_planes = 2;
1430 	dc->caps.max_slave_rgb_planes = 2;
1431 	dc->caps.is_apu = true;
1432 	dc->caps.post_blend_color_processing = true;
1433 	dc->caps.force_dp_tps4_for_cp2520 = true;
1434 	dc->caps.extended_aux_timeout_support = true;
1435 	dc->caps.dmcub_support = true;
1436 
1437 	/* Color pipeline capabilities */
1438 	dc->caps.color.dpp.dcn_arch = 1;
1439 	dc->caps.color.dpp.input_lut_shared = 0;
1440 	dc->caps.color.dpp.icsc = 1;
1441 	dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
1442 	dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1443 	dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1444 	dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
1445 	dc->caps.color.dpp.dgam_rom_caps.pq = 1;
1446 	dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
1447 	dc->caps.color.dpp.post_csc = 1;
1448 	dc->caps.color.dpp.gamma_corr = 1;
1449 	dc->caps.color.dpp.dgam_rom_for_yuv = 0;
1450 
1451 	dc->caps.color.dpp.hw_3d_lut = 1;
1452 	dc->caps.color.dpp.ogam_ram = 1;
1453 	// no OGAM ROM on DCN301
1454 	dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
1455 	dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
1456 	dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
1457 	dc->caps.color.dpp.ogam_rom_caps.pq = 0;
1458 	dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
1459 	dc->caps.color.dpp.ocsc = 0;
1460 
1461 	dc->caps.color.mpc.gamut_remap = 1;
1462 	dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2
1463 	dc->caps.color.mpc.ogam_ram = 1;
1464 	dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
1465 	dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
1466 	dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
1467 	dc->caps.color.mpc.ogam_rom_caps.pq = 0;
1468 	dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1469 	dc->caps.color.mpc.ocsc = 1;
1470 
1471 	dc->caps.dp_hdmi21_pcon_support = true;
1472 
1473 	/* read VBIOS LTTPR caps */
1474 	if (ctx->dc_bios->funcs->get_lttpr_caps) {
1475 		enum bp_result bp_query_result;
1476 		uint8_t is_vbios_lttpr_enable = 0;
1477 
1478 		bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
1479 		dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
1480 	}
1481 
1482 	if (ctx->dc_bios->funcs->get_lttpr_interop) {
1483 		enum bp_result bp_query_result;
1484 		uint8_t is_vbios_interop_enabled = 0;
1485 
1486 		bp_query_result = ctx->dc_bios->funcs->get_lttpr_interop(ctx->dc_bios, &is_vbios_interop_enabled);
1487 		dc->caps.vbios_lttpr_aware = (bp_query_result == BP_RESULT_OK) && !!is_vbios_interop_enabled;
1488 	}
1489 
1490 	if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1491 		dc->debug = debug_defaults_drv;
1492 
1493 	// Init the vm_helper
1494 	if (dc->vm_helper)
1495 		vm_helper_init(dc->vm_helper, 16);
1496 
1497 	/*************************************************
1498 	 *  Create resources                             *
1499 	 *************************************************/
1500 
1501 	/* Clock Sources for Pixel Clock*/
1502 	pool->base.clock_sources[DCN301_CLK_SRC_PLL0] =
1503 			dcn301_clock_source_create(ctx, ctx->dc_bios,
1504 				CLOCK_SOURCE_COMBO_PHY_PLL0,
1505 				&clk_src_regs[0], false);
1506 	pool->base.clock_sources[DCN301_CLK_SRC_PLL1] =
1507 			dcn301_clock_source_create(ctx, ctx->dc_bios,
1508 				CLOCK_SOURCE_COMBO_PHY_PLL1,
1509 				&clk_src_regs[1], false);
1510 	pool->base.clock_sources[DCN301_CLK_SRC_PLL2] =
1511 			dcn301_clock_source_create(ctx, ctx->dc_bios,
1512 				CLOCK_SOURCE_COMBO_PHY_PLL2,
1513 				&clk_src_regs[2], false);
1514 	pool->base.clock_sources[DCN301_CLK_SRC_PLL3] =
1515 			dcn301_clock_source_create(ctx, ctx->dc_bios,
1516 				CLOCK_SOURCE_COMBO_PHY_PLL3,
1517 				&clk_src_regs[3], false);
1518 
1519 	pool->base.clk_src_count = DCN301_CLK_SRC_TOTAL;
1520 
1521 	/* todo: not reuse phy_pll registers */
1522 	pool->base.dp_clock_source =
1523 			dcn301_clock_source_create(ctx, ctx->dc_bios,
1524 				CLOCK_SOURCE_ID_DP_DTO,
1525 				&clk_src_regs[0], true);
1526 
1527 	for (i = 0; i < pool->base.clk_src_count; i++) {
1528 		if (pool->base.clock_sources[i] == NULL) {
1529 			dm_error("DC: failed to create clock sources!\n");
1530 			BREAK_TO_DEBUGGER();
1531 			goto create_fail;
1532 		}
1533 	}
1534 
1535 	/* DCCG */
1536 	pool->base.dccg = dccg301_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
1537 	if (pool->base.dccg == NULL) {
1538 		dm_error("DC: failed to create dccg!\n");
1539 		BREAK_TO_DEBUGGER();
1540 		goto create_fail;
1541 	}
1542 
1543 	init_soc_bounding_box(dc, pool);
1544 
1545 	if (!dc->debug.disable_pplib_wm_range && pool->base.pp_smu->nv_funcs.set_wm_ranges)
1546 		set_wm_ranges(pool->base.pp_smu, &dcn3_01_soc);
1547 
1548 	num_pipes = dcn3_01_ip.max_num_dpp;
1549 
1550 	for (i = 0; i < dcn3_01_ip.max_num_dpp; i++)
1551 		if (pipe_fuses & 1 << i)
1552 			num_pipes--;
1553 	dcn3_01_ip.max_num_dpp = num_pipes;
1554 	dcn3_01_ip.max_num_otg = num_pipes;
1555 
1556 
1557 	dml_init_instance(&dc->dml, &dcn3_01_soc, &dcn3_01_ip, DML_PROJECT_DCN30);
1558 
1559 	/* IRQ */
1560 	init_data.ctx = dc->ctx;
1561 	pool->base.irqs = dal_irq_service_dcn30_create(&init_data);
1562 	if (!pool->base.irqs)
1563 		goto create_fail;
1564 
1565 	/* HUBBUB */
1566 	pool->base.hubbub = dcn301_hubbub_create(ctx);
1567 	if (pool->base.hubbub == NULL) {
1568 		BREAK_TO_DEBUGGER();
1569 		dm_error("DC: failed to create hubbub!\n");
1570 		goto create_fail;
1571 	}
1572 
1573 	j = 0;
1574 	/* HUBPs, DPPs, OPPs and TGs */
1575 	for (i = 0; i < pool->base.pipe_count; i++) {
1576 
1577 		/* if pipe is disabled, skip instance of HW pipe,
1578 		 * i.e, skip ASIC register instance
1579 		 */
1580 		if ((pipe_fuses & (1 << i)) != 0) {
1581 			DC_LOG_DEBUG("%s: fusing pipe %d\n", __func__, i);
1582 			continue;
1583 		}
1584 
1585 		pool->base.hubps[j] = dcn301_hubp_create(ctx, i);
1586 		if (pool->base.hubps[j] == NULL) {
1587 			BREAK_TO_DEBUGGER();
1588 			dm_error(
1589 				"DC: failed to create hubps!\n");
1590 			goto create_fail;
1591 		}
1592 
1593 		pool->base.dpps[j] = dcn301_dpp_create(ctx, i);
1594 		if (pool->base.dpps[j] == NULL) {
1595 			BREAK_TO_DEBUGGER();
1596 			dm_error(
1597 				"DC: failed to create dpps!\n");
1598 			goto create_fail;
1599 		}
1600 
1601 		pool->base.opps[j] = dcn301_opp_create(ctx, i);
1602 		if (pool->base.opps[j] == NULL) {
1603 			BREAK_TO_DEBUGGER();
1604 			dm_error(
1605 				"DC: failed to create output pixel processor!\n");
1606 			goto create_fail;
1607 		}
1608 
1609 		pool->base.timing_generators[j] = dcn301_timing_generator_create(ctx, i);
1610 		if (pool->base.timing_generators[j] == NULL) {
1611 			BREAK_TO_DEBUGGER();
1612 			dm_error("DC: failed to create tg!\n");
1613 			goto create_fail;
1614 		}
1615 		j++;
1616 	}
1617 	pool->base.timing_generator_count = j;
1618 	pool->base.pipe_count = j;
1619 	pool->base.mpcc_count = j;
1620 
1621 	/* ABM (or ABMs for NV2x) */
1622 	/* TODO: */
1623 	for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1624 		pool->base.multiple_abms[i] = dmub_abm_create(ctx,
1625 				&abm_regs[i],
1626 				&abm_shift,
1627 				&abm_mask);
1628 		if (pool->base.multiple_abms[i] == NULL) {
1629 			dm_error("DC: failed to create abm for pipe %d!\n", i);
1630 			BREAK_TO_DEBUGGER();
1631 			goto create_fail;
1632 		}
1633 	}
1634 
1635 	/* MPC and DSC */
1636 	pool->base.mpc = dcn301_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);
1637 	if (pool->base.mpc == NULL) {
1638 		BREAK_TO_DEBUGGER();
1639 		dm_error("DC: failed to create mpc!\n");
1640 		goto create_fail;
1641 	}
1642 
1643 	for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1644 		pool->base.dscs[i] = dcn301_dsc_create(ctx, i);
1645 		if (pool->base.dscs[i] == NULL) {
1646 			BREAK_TO_DEBUGGER();
1647 			dm_error("DC: failed to create display stream compressor %d!\n", i);
1648 			goto create_fail;
1649 		}
1650 	}
1651 
1652 	/* DWB and MMHUBBUB */
1653 	if (!dcn301_dwbc_create(ctx, &pool->base)) {
1654 		BREAK_TO_DEBUGGER();
1655 		dm_error("DC: failed to create dwbc!\n");
1656 		goto create_fail;
1657 	}
1658 
1659 	if (!dcn301_mmhubbub_create(ctx, &pool->base)) {
1660 		BREAK_TO_DEBUGGER();
1661 		dm_error("DC: failed to create mcif_wb!\n");
1662 		goto create_fail;
1663 	}
1664 
1665 	/* AUX and I2C */
1666 	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1667 		pool->base.engines[i] = dcn301_aux_engine_create(ctx, i);
1668 		if (pool->base.engines[i] == NULL) {
1669 			BREAK_TO_DEBUGGER();
1670 			dm_error(
1671 				"DC:failed to create aux engine!!\n");
1672 			goto create_fail;
1673 		}
1674 		pool->base.hw_i2cs[i] = dcn301_i2c_hw_create(ctx, i);
1675 		if (pool->base.hw_i2cs[i] == NULL) {
1676 			BREAK_TO_DEBUGGER();
1677 			dm_error(
1678 				"DC:failed to create hw i2c!!\n");
1679 			goto create_fail;
1680 		}
1681 		pool->base.sw_i2cs[i] = NULL;
1682 	}
1683 
1684 	/* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */
1685 	if (!resource_construct(num_virtual_links, dc, &pool->base,
1686 			&res_create_funcs))
1687 		goto create_fail;
1688 
1689 	/* HW Sequencer and Plane caps */
1690 	dcn301_hw_sequencer_construct(dc);
1691 
1692 	dc->caps.max_planes =  pool->base.pipe_count;
1693 
1694 	for (i = 0; i < dc->caps.max_planes; ++i)
1695 		dc->caps.planes[i] = plane_cap;
1696 
1697 	dc->cap_funcs = cap_funcs;
1698 
1699 	return true;
1700 
1701 create_fail:
1702 
1703 	dcn301_destruct(pool);
1704 
1705 	return false;
1706 }
1707 
1708 struct resource_pool *dcn301_create_resource_pool(
1709 		const struct dc_init_data *init_data,
1710 		struct dc *dc)
1711 {
1712 	struct dcn301_resource_pool *pool =
1713 		kzalloc(sizeof(struct dcn301_resource_pool), GFP_KERNEL);
1714 
1715 	if (!pool)
1716 		return NULL;
1717 
1718 	if (dcn301_resource_construct(init_data->num_virtual_links, dc, pool))
1719 		return &pool->base;
1720 
1721 	BREAK_TO_DEBUGGER();
1722 	kfree(pool);
1723 	return NULL;
1724 }
1725