1 /* 2 * Copyright 2019-2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 27 #include "dm_services.h" 28 #include "dc.h" 29 30 #include "dcn301_init.h" 31 32 #include "resource.h" 33 #include "include/irq_service_interface.h" 34 #include "dcn30/dcn30_resource.h" 35 #include "dcn301_resource.h" 36 37 #include "dcn20/dcn20_resource.h" 38 39 #include "dcn10/dcn10_ipp.h" 40 #include "dcn301/dcn301_hubbub.h" 41 #include "dcn30/dcn30_mpc.h" 42 #include "dcn30/dcn30_hubp.h" 43 #include "irq/dcn30/irq_service_dcn30.h" 44 #include "dcn30/dcn30_dpp.h" 45 #include "dcn30/dcn30_optc.h" 46 #include "dcn20/dcn20_hwseq.h" 47 #include "dcn30/dcn30_hwseq.h" 48 #include "dce110/dce110_hw_sequencer.h" 49 #include "dcn30/dcn30_opp.h" 50 #include "dcn20/dcn20_dsc.h" 51 #include "dcn30/dcn30_vpg.h" 52 #include "dcn30/dcn30_afmt.h" 53 #include "dce/dce_clock_source.h" 54 #include "dce/dce_audio.h" 55 #include "dce/dce_hwseq.h" 56 #include "clk_mgr.h" 57 #include "virtual/virtual_stream_encoder.h" 58 #include "dce110/dce110_resource.h" 59 #include "dml/display_mode_vba.h" 60 #include "dcn301/dcn301_dccg.h" 61 #include "dcn10/dcn10_resource.h" 62 #include "dcn30/dcn30_dio_stream_encoder.h" 63 #include "dcn301/dcn301_dio_link_encoder.h" 64 #include "dcn301_panel_cntl.h" 65 66 #include "vangogh_ip_offset.h" 67 68 #include "dcn30/dcn30_dwb.h" 69 #include "dcn30/dcn30_mmhubbub.h" 70 71 #include "dcn/dcn_3_0_1_offset.h" 72 #include "dcn/dcn_3_0_1_sh_mask.h" 73 74 #include "nbio/nbio_7_2_0_offset.h" 75 76 #include "dpcs/dpcs_3_0_0_offset.h" 77 #include "dpcs/dpcs_3_0_0_sh_mask.h" 78 79 #include "reg_helper.h" 80 #include "dce/dmub_abm.h" 81 #include "dce/dce_aux.h" 82 #include "dce/dce_i2c.h" 83 84 #include "dml/dcn30/dcn30_fpu.h" 85 86 #include "dml/dcn30/display_mode_vba_30.h" 87 #include "dml/dcn301/dcn301_fpu.h" 88 #include "vm_helper.h" 89 #include "dcn20/dcn20_vmid.h" 90 #include "amdgpu_socbb.h" 91 92 #define TO_DCN301_RES_POOL(pool)\ 93 container_of(pool, struct dcn301_resource_pool, base) 94 95 #define DC_LOGGER_INIT(logger) 96 97 enum dcn301_clk_src_array_id { 98 DCN301_CLK_SRC_PLL0, 99 DCN301_CLK_SRC_PLL1, 100 DCN301_CLK_SRC_PLL2, 101 DCN301_CLK_SRC_PLL3, 102 DCN301_CLK_SRC_TOTAL 103 }; 104 105 /* begin ********************* 106 * macros to expend register list macro defined in HW object header file 107 */ 108 109 /* DCN */ 110 /* TODO awful hack. fixup dcn20_dwb.h */ 111 #undef BASE_INNER 112 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg 113 114 #define BASE(seg) BASE_INNER(seg) 115 116 #define SR(reg_name)\ 117 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ 118 mm ## reg_name 119 120 #define SRI(reg_name, block, id)\ 121 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 122 mm ## block ## id ## _ ## reg_name 123 124 #define SRI2(reg_name, block, id)\ 125 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ 126 mm ## reg_name 127 128 #define SRIR(var_name, reg_name, block, id)\ 129 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 130 mm ## block ## id ## _ ## reg_name 131 132 #define SRII(reg_name, block, id)\ 133 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 134 mm ## block ## id ## _ ## reg_name 135 136 #define SRII2(reg_name_pre, reg_name_post, id)\ 137 .reg_name_pre ## _ ## reg_name_post[id] = BASE(mm ## reg_name_pre \ 138 ## id ## _ ## reg_name_post ## _BASE_IDX) + \ 139 mm ## reg_name_pre ## id ## _ ## reg_name_post 140 141 #define SRII_MPC_RMU(reg_name, block, id)\ 142 .RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 143 mm ## block ## id ## _ ## reg_name 144 145 #define SRII_DWB(reg_name, temp_name, block, id)\ 146 .reg_name[id] = BASE(mm ## block ## id ## _ ## temp_name ## _BASE_IDX) + \ 147 mm ## block ## id ## _ ## temp_name 148 149 #define DCCG_SRII(reg_name, block, id)\ 150 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 151 mm ## block ## id ## _ ## reg_name 152 153 #define VUPDATE_SRII(reg_name, block, id)\ 154 .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \ 155 mm ## reg_name ## _ ## block ## id 156 157 /* NBIO */ 158 #define NBIO_BASE_INNER(seg) \ 159 NBIO_BASE__INST0_SEG ## seg 160 161 #define NBIO_BASE(seg) \ 162 NBIO_BASE_INNER(seg) 163 164 #define NBIO_SR(reg_name)\ 165 .reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \ 166 regBIF_BX0_ ## reg_name 167 168 /* MMHUB */ 169 #define MMHUB_BASE_INNER(seg) \ 170 MMHUB_BASE__INST0_SEG ## seg 171 172 #define MMHUB_BASE(seg) \ 173 MMHUB_BASE_INNER(seg) 174 175 #define MMHUB_SR(reg_name)\ 176 .reg_name = MMHUB_BASE(regMM ## reg_name ## _BASE_IDX) + \ 177 regMM ## reg_name 178 179 /* CLOCK */ 180 #define CLK_BASE_INNER(seg) \ 181 CLK_BASE__INST0_SEG ## seg 182 183 #define CLK_BASE(seg) \ 184 CLK_BASE_INNER(seg) 185 186 #define CLK_SRI(reg_name, block, inst)\ 187 .reg_name = CLK_BASE(mm ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \ 188 mm ## block ## _ ## inst ## _ ## reg_name 189 190 static const struct bios_registers bios_regs = { 191 NBIO_SR(BIOS_SCRATCH_3), 192 NBIO_SR(BIOS_SCRATCH_6) 193 }; 194 195 #define clk_src_regs(index, pllid)\ 196 [index] = {\ 197 CS_COMMON_REG_LIST_DCN3_01(index, pllid),\ 198 } 199 200 static const struct dce110_clk_src_regs clk_src_regs[] = { 201 clk_src_regs(0, A), 202 clk_src_regs(1, B), 203 clk_src_regs(2, C), 204 clk_src_regs(3, D) 205 }; 206 207 static const struct dce110_clk_src_shift cs_shift = { 208 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 209 }; 210 211 static const struct dce110_clk_src_mask cs_mask = { 212 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 213 }; 214 215 #define abm_regs(id)\ 216 [id] = {\ 217 ABM_DCN301_REG_LIST(id)\ 218 } 219 220 static const struct dce_abm_registers abm_regs[] = { 221 abm_regs(0), 222 abm_regs(1), 223 abm_regs(2), 224 abm_regs(3), 225 }; 226 227 static const struct dce_abm_shift abm_shift = { 228 ABM_MASK_SH_LIST_DCN30(__SHIFT) 229 }; 230 231 static const struct dce_abm_mask abm_mask = { 232 ABM_MASK_SH_LIST_DCN30(_MASK) 233 }; 234 235 #define audio_regs(id)\ 236 [id] = {\ 237 AUD_COMMON_REG_LIST(id)\ 238 } 239 240 static const struct dce_audio_registers audio_regs[] = { 241 audio_regs(0), 242 audio_regs(1), 243 audio_regs(2), 244 audio_regs(3), 245 audio_regs(4), 246 audio_regs(5), 247 audio_regs(6) 248 }; 249 250 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 251 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 252 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 253 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 254 255 static const struct dce_audio_shift audio_shift = { 256 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 257 }; 258 259 static const struct dce_audio_mask audio_mask = { 260 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 261 }; 262 263 #define vpg_regs(id)\ 264 [id] = {\ 265 VPG_DCN3_REG_LIST(id)\ 266 } 267 268 static const struct dcn30_vpg_registers vpg_regs[] = { 269 vpg_regs(0), 270 vpg_regs(1), 271 vpg_regs(2), 272 vpg_regs(3), 273 }; 274 275 static const struct dcn30_vpg_shift vpg_shift = { 276 DCN3_VPG_MASK_SH_LIST(__SHIFT) 277 }; 278 279 static const struct dcn30_vpg_mask vpg_mask = { 280 DCN3_VPG_MASK_SH_LIST(_MASK) 281 }; 282 283 #define afmt_regs(id)\ 284 [id] = {\ 285 AFMT_DCN3_REG_LIST(id)\ 286 } 287 288 static const struct dcn30_afmt_registers afmt_regs[] = { 289 afmt_regs(0), 290 afmt_regs(1), 291 afmt_regs(2), 292 afmt_regs(3), 293 }; 294 295 static const struct dcn30_afmt_shift afmt_shift = { 296 DCN3_AFMT_MASK_SH_LIST(__SHIFT) 297 }; 298 299 static const struct dcn30_afmt_mask afmt_mask = { 300 DCN3_AFMT_MASK_SH_LIST(_MASK) 301 }; 302 303 #define stream_enc_regs(id)\ 304 [id] = {\ 305 SE_DCN3_REG_LIST(id)\ 306 } 307 308 static const struct dcn10_stream_enc_registers stream_enc_regs[] = { 309 stream_enc_regs(0), 310 stream_enc_regs(1), 311 stream_enc_regs(2), 312 stream_enc_regs(3), 313 }; 314 315 static const struct dcn10_stream_encoder_shift se_shift = { 316 SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 317 }; 318 319 static const struct dcn10_stream_encoder_mask se_mask = { 320 SE_COMMON_MASK_SH_LIST_DCN30(_MASK) 321 }; 322 323 324 #define aux_regs(id)\ 325 [id] = {\ 326 DCN2_AUX_REG_LIST(id)\ 327 } 328 329 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { 330 aux_regs(0), 331 aux_regs(1), 332 aux_regs(2), 333 aux_regs(3), 334 }; 335 336 #define hpd_regs(id)\ 337 [id] = {\ 338 HPD_REG_LIST(id)\ 339 } 340 341 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { 342 hpd_regs(0), 343 hpd_regs(1), 344 hpd_regs(2), 345 hpd_regs(3), 346 }; 347 348 349 #define link_regs(id, phyid)\ 350 [id] = {\ 351 LE_DCN301_REG_LIST(id), \ 352 UNIPHY_DCN2_REG_LIST(phyid), \ 353 DPCS_DCN2_REG_LIST(id), \ 354 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \ 355 } 356 357 static const struct dce110_aux_registers_shift aux_shift = { 358 DCN_AUX_MASK_SH_LIST(__SHIFT) 359 }; 360 361 static const struct dce110_aux_registers_mask aux_mask = { 362 DCN_AUX_MASK_SH_LIST(_MASK) 363 }; 364 365 static const struct dcn10_link_enc_registers link_enc_regs[] = { 366 link_regs(0, A), 367 link_regs(1, B), 368 link_regs(2, C), 369 link_regs(3, D), 370 }; 371 372 static const struct dcn10_link_enc_shift le_shift = { 373 LINK_ENCODER_MASK_SH_LIST_DCN301(__SHIFT),\ 374 DPCS_DCN2_MASK_SH_LIST(__SHIFT) 375 }; 376 377 static const struct dcn10_link_enc_mask le_mask = { 378 LINK_ENCODER_MASK_SH_LIST_DCN301(_MASK),\ 379 DPCS_DCN2_MASK_SH_LIST(_MASK) 380 }; 381 382 #define panel_cntl_regs(id)\ 383 [id] = {\ 384 DCN301_PANEL_CNTL_REG_LIST(id),\ 385 } 386 387 static const struct dce_panel_cntl_registers panel_cntl_regs[] = { 388 panel_cntl_regs(0), 389 panel_cntl_regs(1), 390 }; 391 392 static const struct dcn301_panel_cntl_shift panel_cntl_shift = { 393 DCN301_PANEL_CNTL_MASK_SH_LIST(__SHIFT) 394 }; 395 396 static const struct dcn301_panel_cntl_mask panel_cntl_mask = { 397 DCN301_PANEL_CNTL_MASK_SH_LIST(_MASK) 398 }; 399 400 #define dpp_regs(id)\ 401 [id] = {\ 402 DPP_REG_LIST_DCN30(id),\ 403 } 404 405 static const struct dcn3_dpp_registers dpp_regs[] = { 406 dpp_regs(0), 407 dpp_regs(1), 408 dpp_regs(2), 409 dpp_regs(3), 410 }; 411 412 static const struct dcn3_dpp_shift tf_shift = { 413 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT) 414 }; 415 416 static const struct dcn3_dpp_mask tf_mask = { 417 DPP_REG_LIST_SH_MASK_DCN30(_MASK) 418 }; 419 420 #define opp_regs(id)\ 421 [id] = {\ 422 OPP_REG_LIST_DCN30(id),\ 423 } 424 425 static const struct dcn20_opp_registers opp_regs[] = { 426 opp_regs(0), 427 opp_regs(1), 428 opp_regs(2), 429 opp_regs(3), 430 }; 431 432 static const struct dcn20_opp_shift opp_shift = { 433 OPP_MASK_SH_LIST_DCN20(__SHIFT) 434 }; 435 436 static const struct dcn20_opp_mask opp_mask = { 437 OPP_MASK_SH_LIST_DCN20(_MASK) 438 }; 439 440 #define aux_engine_regs(id)\ 441 [id] = {\ 442 AUX_COMMON_REG_LIST0(id), \ 443 .AUXN_IMPCAL = 0, \ 444 .AUXP_IMPCAL = 0, \ 445 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \ 446 } 447 448 static const struct dce110_aux_registers aux_engine_regs[] = { 449 aux_engine_regs(0), 450 aux_engine_regs(1), 451 aux_engine_regs(2), 452 aux_engine_regs(3), 453 }; 454 455 #define dwbc_regs_dcn3(id)\ 456 [id] = {\ 457 DWBC_COMMON_REG_LIST_DCN30(id),\ 458 } 459 460 static const struct dcn30_dwbc_registers dwbc30_regs[] = { 461 dwbc_regs_dcn3(0), 462 }; 463 464 static const struct dcn30_dwbc_shift dwbc30_shift = { 465 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 466 }; 467 468 static const struct dcn30_dwbc_mask dwbc30_mask = { 469 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK) 470 }; 471 472 #define mcif_wb_regs_dcn3(id)\ 473 [id] = {\ 474 MCIF_WB_COMMON_REG_LIST_DCN30(id),\ 475 } 476 477 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = { 478 mcif_wb_regs_dcn3(0) 479 }; 480 481 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = { 482 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 483 }; 484 485 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { 486 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK) 487 }; 488 489 #define dsc_regsDCN20(id)\ 490 [id] = {\ 491 DSC_REG_LIST_DCN20(id)\ 492 } 493 494 static const struct dcn20_dsc_registers dsc_regs[] = { 495 dsc_regsDCN20(0), 496 dsc_regsDCN20(1), 497 dsc_regsDCN20(2), 498 }; 499 500 static const struct dcn20_dsc_shift dsc_shift = { 501 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) 502 }; 503 504 static const struct dcn20_dsc_mask dsc_mask = { 505 DSC_REG_LIST_SH_MASK_DCN20(_MASK) 506 }; 507 508 static const struct dcn30_mpc_registers mpc_regs = { 509 MPC_REG_LIST_DCN3_0(0), 510 MPC_REG_LIST_DCN3_0(1), 511 MPC_REG_LIST_DCN3_0(2), 512 MPC_REG_LIST_DCN3_0(3), 513 MPC_OUT_MUX_REG_LIST_DCN3_0(0), 514 MPC_OUT_MUX_REG_LIST_DCN3_0(1), 515 MPC_OUT_MUX_REG_LIST_DCN3_0(2), 516 MPC_OUT_MUX_REG_LIST_DCN3_0(3), 517 MPC_RMU_GLOBAL_REG_LIST_DCN3AG, 518 MPC_RMU_REG_LIST_DCN3AG(0), 519 MPC_RMU_REG_LIST_DCN3AG(1), 520 MPC_DWB_MUX_REG_LIST_DCN3_0(0), 521 }; 522 523 static const struct dcn30_mpc_shift mpc_shift = { 524 MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 525 }; 526 527 static const struct dcn30_mpc_mask mpc_mask = { 528 MPC_COMMON_MASK_SH_LIST_DCN30(_MASK) 529 }; 530 531 #define optc_regs(id)\ 532 [id] = {OPTC_COMMON_REG_LIST_DCN3_0(id)} 533 534 535 static const struct dcn_optc_registers optc_regs[] = { 536 optc_regs(0), 537 optc_regs(1), 538 optc_regs(2), 539 optc_regs(3), 540 }; 541 542 static const struct dcn_optc_shift optc_shift = { 543 OPTC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 544 }; 545 546 static const struct dcn_optc_mask optc_mask = { 547 OPTC_COMMON_MASK_SH_LIST_DCN30(_MASK) 548 }; 549 550 #define hubp_regs(id)\ 551 [id] = {\ 552 HUBP_REG_LIST_DCN30(id)\ 553 } 554 555 static const struct dcn_hubp2_registers hubp_regs[] = { 556 hubp_regs(0), 557 hubp_regs(1), 558 hubp_regs(2), 559 hubp_regs(3), 560 }; 561 562 static const struct dcn_hubp2_shift hubp_shift = { 563 HUBP_MASK_SH_LIST_DCN30(__SHIFT) 564 }; 565 566 static const struct dcn_hubp2_mask hubp_mask = { 567 HUBP_MASK_SH_LIST_DCN30(_MASK) 568 }; 569 570 static const struct dcn_hubbub_registers hubbub_reg = { 571 HUBBUB_REG_LIST_DCN301(0) 572 }; 573 574 static const struct dcn_hubbub_shift hubbub_shift = { 575 HUBBUB_MASK_SH_LIST_DCN301(__SHIFT) 576 }; 577 578 static const struct dcn_hubbub_mask hubbub_mask = { 579 HUBBUB_MASK_SH_LIST_DCN301(_MASK) 580 }; 581 582 static const struct dccg_registers dccg_regs = { 583 DCCG_REG_LIST_DCN301() 584 }; 585 586 static const struct dccg_shift dccg_shift = { 587 DCCG_MASK_SH_LIST_DCN301(__SHIFT) 588 }; 589 590 static const struct dccg_mask dccg_mask = { 591 DCCG_MASK_SH_LIST_DCN301(_MASK) 592 }; 593 594 static const struct dce_hwseq_registers hwseq_reg = { 595 HWSEQ_DCN301_REG_LIST() 596 }; 597 598 static const struct dce_hwseq_shift hwseq_shift = { 599 HWSEQ_DCN301_MASK_SH_LIST(__SHIFT) 600 }; 601 602 static const struct dce_hwseq_mask hwseq_mask = { 603 HWSEQ_DCN301_MASK_SH_LIST(_MASK) 604 }; 605 #define vmid_regs(id)\ 606 [id] = {\ 607 DCN20_VMID_REG_LIST(id)\ 608 } 609 610 static const struct dcn_vmid_registers vmid_regs[] = { 611 vmid_regs(0), 612 vmid_regs(1), 613 vmid_regs(2), 614 vmid_regs(3), 615 vmid_regs(4), 616 vmid_regs(5), 617 vmid_regs(6), 618 vmid_regs(7), 619 vmid_regs(8), 620 vmid_regs(9), 621 vmid_regs(10), 622 vmid_regs(11), 623 vmid_regs(12), 624 vmid_regs(13), 625 vmid_regs(14), 626 vmid_regs(15) 627 }; 628 629 static const struct dcn20_vmid_shift vmid_shifts = { 630 DCN20_VMID_MASK_SH_LIST(__SHIFT) 631 }; 632 633 static const struct dcn20_vmid_mask vmid_masks = { 634 DCN20_VMID_MASK_SH_LIST(_MASK) 635 }; 636 637 static struct resource_caps res_cap_dcn301 = { 638 .num_timing_generator = 4, 639 .num_opp = 4, 640 .num_video_plane = 4, 641 .num_audio = 4, 642 .num_stream_encoder = 4, 643 .num_pll = 4, 644 .num_dwb = 1, 645 .num_ddc = 4, 646 .num_vmid = 16, 647 .num_mpc_3dlut = 2, 648 .num_dsc = 3, 649 }; 650 651 static const struct dc_plane_cap plane_cap = { 652 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 653 .blends_with_above = true, 654 .blends_with_below = true, 655 .per_pixel_alpha = true, 656 657 .pixel_format_support = { 658 .argb8888 = true, 659 .nv12 = true, 660 .fp16 = true, 661 .p010 = true, 662 .ayuv = false, 663 }, 664 665 .max_upscale_factor = { 666 .argb8888 = 16000, 667 .nv12 = 16000, 668 .fp16 = 16000 669 }, 670 671 /* 6:1 downscaling ratio: 1000/6 = 166.666 */ 672 .max_downscale_factor = { 673 .argb8888 = 167, 674 .nv12 = 167, 675 .fp16 = 167 676 }, 677 64, 678 64 679 }; 680 681 static const struct dc_debug_options debug_defaults_drv = { 682 .disable_dmcu = true, 683 .force_abm_enable = false, 684 .timing_trace = false, 685 .clock_trace = true, 686 .disable_dpp_power_gate = false, 687 .disable_hubp_power_gate = false, 688 .disable_clock_gate = true, 689 .disable_pplib_clock_request = true, 690 .disable_pplib_wm_range = true, 691 .pipe_split_policy = MPC_SPLIT_AVOID, 692 .force_single_disp_pipe_split = false, 693 .disable_dcc = DCC_ENABLE, 694 .vsr_support = true, 695 .performance_trace = false, 696 .max_downscale_src_width = 7680,/*upto 8K*/ 697 .scl_reset_length10 = true, 698 .sanity_checks = false, 699 .underflow_assert_delay_us = 0xFFFFFFFF, 700 .dwb_fi_phase = -1, // -1 = disable 701 .dmub_command_table = true, 702 .use_max_lb = false, 703 .exit_idle_opt_for_cursor_updates = true 704 }; 705 706 static const struct dc_debug_options debug_defaults_diags = { 707 .disable_dmcu = true, 708 .force_abm_enable = false, 709 .timing_trace = true, 710 .clock_trace = true, 711 .disable_dpp_power_gate = false, 712 .disable_hubp_power_gate = false, 713 .disable_clock_gate = true, 714 .disable_pplib_clock_request = true, 715 .disable_pplib_wm_range = true, 716 .disable_stutter = true, 717 .scl_reset_length10 = true, 718 .dwb_fi_phase = -1, // -1 = disable 719 .dmub_command_table = true, 720 .use_max_lb = false, 721 }; 722 723 static void dcn301_dpp_destroy(struct dpp **dpp) 724 { 725 kfree(TO_DCN20_DPP(*dpp)); 726 *dpp = NULL; 727 } 728 729 static struct dpp *dcn301_dpp_create(struct dc_context *ctx, uint32_t inst) 730 { 731 struct dcn3_dpp *dpp = 732 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL); 733 734 if (!dpp) 735 return NULL; 736 737 if (dpp3_construct(dpp, ctx, inst, 738 &dpp_regs[inst], &tf_shift, &tf_mask)) 739 return &dpp->base; 740 741 BREAK_TO_DEBUGGER(); 742 kfree(dpp); 743 return NULL; 744 } 745 static struct output_pixel_processor *dcn301_opp_create(struct dc_context *ctx, 746 uint32_t inst) 747 { 748 struct dcn20_opp *opp = 749 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); 750 751 if (!opp) { 752 BREAK_TO_DEBUGGER(); 753 return NULL; 754 } 755 756 dcn20_opp_construct(opp, ctx, inst, 757 &opp_regs[inst], &opp_shift, &opp_mask); 758 return &opp->base; 759 } 760 761 static struct dce_aux *dcn301_aux_engine_create(struct dc_context *ctx, uint32_t inst) 762 { 763 struct aux_engine_dce110 *aux_engine = 764 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 765 766 if (!aux_engine) 767 return NULL; 768 769 dce110_aux_engine_construct(aux_engine, ctx, inst, 770 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 771 &aux_engine_regs[inst], 772 &aux_mask, 773 &aux_shift, 774 ctx->dc->caps.extended_aux_timeout_support); 775 776 return &aux_engine->base; 777 } 778 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 779 780 static const struct dce_i2c_registers i2c_hw_regs[] = { 781 i2c_inst_regs(1), 782 i2c_inst_regs(2), 783 i2c_inst_regs(3), 784 i2c_inst_regs(4), 785 }; 786 787 static const struct dce_i2c_shift i2c_shifts = { 788 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT) 789 }; 790 791 static const struct dce_i2c_mask i2c_masks = { 792 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK) 793 }; 794 795 static struct dce_i2c_hw *dcn301_i2c_hw_create(struct dc_context *ctx, uint32_t inst) 796 { 797 struct dce_i2c_hw *dce_i2c_hw = 798 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 799 800 if (!dce_i2c_hw) 801 return NULL; 802 803 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, 804 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 805 806 return dce_i2c_hw; 807 } 808 static struct mpc *dcn301_mpc_create( 809 struct dc_context *ctx, 810 int num_mpcc, 811 int num_rmu) 812 { 813 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), 814 GFP_KERNEL); 815 816 if (!mpc30) 817 return NULL; 818 819 dcn30_mpc_construct(mpc30, ctx, 820 &mpc_regs, 821 &mpc_shift, 822 &mpc_mask, 823 num_mpcc, 824 num_rmu); 825 826 return &mpc30->base; 827 } 828 829 static struct hubbub *dcn301_hubbub_create(struct dc_context *ctx) 830 { 831 int i; 832 833 struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub), 834 GFP_KERNEL); 835 836 if (!hubbub3) 837 return NULL; 838 839 hubbub301_construct(hubbub3, ctx, 840 &hubbub_reg, 841 &hubbub_shift, 842 &hubbub_mask); 843 844 845 for (i = 0; i < res_cap_dcn301.num_vmid; i++) { 846 struct dcn20_vmid *vmid = &hubbub3->vmid[i]; 847 848 vmid->ctx = ctx; 849 850 vmid->regs = &vmid_regs[i]; 851 vmid->shifts = &vmid_shifts; 852 vmid->masks = &vmid_masks; 853 } 854 855 hubbub3->num_vmid = res_cap_dcn301.num_vmid; 856 857 return &hubbub3->base; 858 } 859 860 static struct timing_generator *dcn301_timing_generator_create( 861 struct dc_context *ctx, uint32_t instance) 862 { 863 struct optc *tgn10 = 864 kzalloc(sizeof(struct optc), GFP_KERNEL); 865 866 if (!tgn10) 867 return NULL; 868 869 tgn10->base.inst = instance; 870 tgn10->base.ctx = ctx; 871 872 tgn10->tg_regs = &optc_regs[instance]; 873 tgn10->tg_shift = &optc_shift; 874 tgn10->tg_mask = &optc_mask; 875 876 dcn30_timing_generator_init(tgn10); 877 878 return &tgn10->base; 879 } 880 881 static const struct encoder_feature_support link_enc_feature = { 882 .max_hdmi_deep_color = COLOR_DEPTH_121212, 883 .max_hdmi_pixel_clock = 600000, 884 .hdmi_ycbcr420_supported = true, 885 .dp_ycbcr420_supported = true, 886 .fec_supported = true, 887 .flags.bits.IS_HBR2_CAPABLE = true, 888 .flags.bits.IS_HBR3_CAPABLE = true, 889 .flags.bits.IS_TPS3_CAPABLE = true, 890 .flags.bits.IS_TPS4_CAPABLE = true 891 }; 892 893 static struct link_encoder *dcn301_link_encoder_create( 894 struct dc_context *ctx, 895 const struct encoder_init_data *enc_init_data) 896 { 897 struct dcn20_link_encoder *enc20 = 898 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 899 900 if (!enc20) 901 return NULL; 902 903 dcn301_link_encoder_construct(enc20, 904 enc_init_data, 905 &link_enc_feature, 906 &link_enc_regs[enc_init_data->transmitter], 907 &link_enc_aux_regs[enc_init_data->channel - 1], 908 &link_enc_hpd_regs[enc_init_data->hpd_source], 909 &le_shift, 910 &le_mask); 911 912 return &enc20->enc10.base; 913 } 914 915 static struct panel_cntl *dcn301_panel_cntl_create(const struct panel_cntl_init_data *init_data) 916 { 917 struct dcn301_panel_cntl *panel_cntl = 918 kzalloc(sizeof(struct dcn301_panel_cntl), GFP_KERNEL); 919 920 if (!panel_cntl) 921 return NULL; 922 923 dcn301_panel_cntl_construct(panel_cntl, 924 init_data, 925 &panel_cntl_regs[init_data->inst], 926 &panel_cntl_shift, 927 &panel_cntl_mask); 928 929 return &panel_cntl->base; 930 } 931 932 933 #define CTX ctx 934 935 #define REG(reg_name) \ 936 (DCN_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name) 937 938 static uint32_t read_pipe_fuses(struct dc_context *ctx) 939 { 940 uint32_t value = REG_READ(CC_DC_PIPE_DIS); 941 /* RV1 support max 4 pipes */ 942 value = value & 0xf; 943 return value; 944 } 945 946 947 static void read_dce_straps( 948 struct dc_context *ctx, 949 struct resource_straps *straps) 950 { 951 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX), 952 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 953 954 } 955 956 static struct audio *dcn301_create_audio( 957 struct dc_context *ctx, unsigned int inst) 958 { 959 return dce_audio_create(ctx, inst, 960 &audio_regs[inst], &audio_shift, &audio_mask); 961 } 962 963 static struct vpg *dcn301_vpg_create( 964 struct dc_context *ctx, 965 uint32_t inst) 966 { 967 struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL); 968 969 if (!vpg3) 970 return NULL; 971 972 vpg3_construct(vpg3, ctx, inst, 973 &vpg_regs[inst], 974 &vpg_shift, 975 &vpg_mask); 976 977 return &vpg3->base; 978 } 979 980 static struct afmt *dcn301_afmt_create( 981 struct dc_context *ctx, 982 uint32_t inst) 983 { 984 struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL); 985 986 if (!afmt3) 987 return NULL; 988 989 afmt3_construct(afmt3, ctx, inst, 990 &afmt_regs[inst], 991 &afmt_shift, 992 &afmt_mask); 993 994 return &afmt3->base; 995 } 996 997 static struct stream_encoder *dcn301_stream_encoder_create(enum engine_id eng_id, 998 struct dc_context *ctx) 999 { 1000 struct dcn10_stream_encoder *enc1; 1001 struct vpg *vpg; 1002 struct afmt *afmt; 1003 int vpg_inst; 1004 int afmt_inst; 1005 1006 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */ 1007 if (eng_id <= ENGINE_ID_DIGF) { 1008 vpg_inst = eng_id; 1009 afmt_inst = eng_id; 1010 } else 1011 return NULL; 1012 1013 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 1014 vpg = dcn301_vpg_create(ctx, vpg_inst); 1015 afmt = dcn301_afmt_create(ctx, afmt_inst); 1016 1017 if (!enc1 || !vpg || !afmt) { 1018 kfree(enc1); 1019 kfree(vpg); 1020 kfree(afmt); 1021 return NULL; 1022 } 1023 1024 dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, 1025 eng_id, vpg, afmt, 1026 &stream_enc_regs[eng_id], 1027 &se_shift, &se_mask); 1028 1029 return &enc1->base; 1030 } 1031 1032 static struct dce_hwseq *dcn301_hwseq_create(struct dc_context *ctx) 1033 { 1034 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 1035 1036 if (hws) { 1037 hws->ctx = ctx; 1038 hws->regs = &hwseq_reg; 1039 hws->shifts = &hwseq_shift; 1040 hws->masks = &hwseq_mask; 1041 } 1042 return hws; 1043 } 1044 static const struct resource_create_funcs res_create_funcs = { 1045 .read_dce_straps = read_dce_straps, 1046 .create_audio = dcn301_create_audio, 1047 .create_stream_encoder = dcn301_stream_encoder_create, 1048 .create_hwseq = dcn301_hwseq_create, 1049 }; 1050 1051 static const struct resource_create_funcs res_create_maximus_funcs = { 1052 .read_dce_straps = NULL, 1053 .create_audio = NULL, 1054 .create_stream_encoder = NULL, 1055 .create_hwseq = dcn301_hwseq_create, 1056 }; 1057 1058 static void dcn301_destruct(struct dcn301_resource_pool *pool) 1059 { 1060 unsigned int i; 1061 1062 for (i = 0; i < pool->base.stream_enc_count; i++) { 1063 if (pool->base.stream_enc[i] != NULL) { 1064 if (pool->base.stream_enc[i]->vpg != NULL) { 1065 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg)); 1066 pool->base.stream_enc[i]->vpg = NULL; 1067 } 1068 if (pool->base.stream_enc[i]->afmt != NULL) { 1069 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt)); 1070 pool->base.stream_enc[i]->afmt = NULL; 1071 } 1072 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); 1073 pool->base.stream_enc[i] = NULL; 1074 } 1075 } 1076 1077 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 1078 if (pool->base.dscs[i] != NULL) 1079 dcn20_dsc_destroy(&pool->base.dscs[i]); 1080 } 1081 1082 if (pool->base.mpc != NULL) { 1083 kfree(TO_DCN20_MPC(pool->base.mpc)); 1084 pool->base.mpc = NULL; 1085 } 1086 if (pool->base.hubbub != NULL) { 1087 kfree(pool->base.hubbub); 1088 pool->base.hubbub = NULL; 1089 } 1090 for (i = 0; i < pool->base.pipe_count; i++) { 1091 if (pool->base.dpps[i] != NULL) 1092 dcn301_dpp_destroy(&pool->base.dpps[i]); 1093 1094 if (pool->base.ipps[i] != NULL) 1095 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); 1096 1097 if (pool->base.hubps[i] != NULL) { 1098 kfree(TO_DCN20_HUBP(pool->base.hubps[i])); 1099 pool->base.hubps[i] = NULL; 1100 } 1101 1102 if (pool->base.irqs != NULL) { 1103 dal_irq_service_destroy(&pool->base.irqs); 1104 } 1105 } 1106 1107 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1108 if (pool->base.engines[i] != NULL) 1109 dce110_engine_destroy(&pool->base.engines[i]); 1110 if (pool->base.hw_i2cs[i] != NULL) { 1111 kfree(pool->base.hw_i2cs[i]); 1112 pool->base.hw_i2cs[i] = NULL; 1113 } 1114 if (pool->base.sw_i2cs[i] != NULL) { 1115 kfree(pool->base.sw_i2cs[i]); 1116 pool->base.sw_i2cs[i] = NULL; 1117 } 1118 } 1119 1120 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 1121 if (pool->base.opps[i] != NULL) 1122 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); 1123 } 1124 1125 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1126 if (pool->base.timing_generators[i] != NULL) { 1127 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); 1128 pool->base.timing_generators[i] = NULL; 1129 } 1130 } 1131 1132 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { 1133 if (pool->base.dwbc[i] != NULL) { 1134 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); 1135 pool->base.dwbc[i] = NULL; 1136 } 1137 if (pool->base.mcif_wb[i] != NULL) { 1138 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i])); 1139 pool->base.mcif_wb[i] = NULL; 1140 } 1141 } 1142 1143 for (i = 0; i < pool->base.audio_count; i++) { 1144 if (pool->base.audios[i]) 1145 dce_aud_destroy(&pool->base.audios[i]); 1146 } 1147 1148 for (i = 0; i < pool->base.clk_src_count; i++) { 1149 if (pool->base.clock_sources[i] != NULL) { 1150 dcn20_clock_source_destroy(&pool->base.clock_sources[i]); 1151 pool->base.clock_sources[i] = NULL; 1152 } 1153 } 1154 1155 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { 1156 if (pool->base.mpc_lut[i] != NULL) { 1157 dc_3dlut_func_release(pool->base.mpc_lut[i]); 1158 pool->base.mpc_lut[i] = NULL; 1159 } 1160 if (pool->base.mpc_shaper[i] != NULL) { 1161 dc_transfer_func_release(pool->base.mpc_shaper[i]); 1162 pool->base.mpc_shaper[i] = NULL; 1163 } 1164 } 1165 1166 if (pool->base.dp_clock_source != NULL) { 1167 dcn20_clock_source_destroy(&pool->base.dp_clock_source); 1168 pool->base.dp_clock_source = NULL; 1169 } 1170 1171 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1172 if (pool->base.multiple_abms[i] != NULL) 1173 dce_abm_destroy(&pool->base.multiple_abms[i]); 1174 } 1175 1176 if (pool->base.dccg != NULL) 1177 dcn_dccg_destroy(&pool->base.dccg); 1178 } 1179 1180 static struct hubp *dcn301_hubp_create(struct dc_context *ctx, uint32_t inst) 1181 { 1182 struct dcn20_hubp *hubp2 = 1183 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL); 1184 1185 if (!hubp2) 1186 return NULL; 1187 1188 if (hubp3_construct(hubp2, ctx, inst, 1189 &hubp_regs[inst], &hubp_shift, &hubp_mask)) 1190 return &hubp2->base; 1191 1192 BREAK_TO_DEBUGGER(); 1193 kfree(hubp2); 1194 return NULL; 1195 } 1196 1197 static bool dcn301_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) 1198 { 1199 int i; 1200 uint32_t pipe_count = pool->res_cap->num_dwb; 1201 1202 for (i = 0; i < pipe_count; i++) { 1203 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), 1204 GFP_KERNEL); 1205 1206 if (!dwbc30) { 1207 dm_error("DC: failed to create dwbc30!\n"); 1208 return false; 1209 } 1210 1211 dcn30_dwbc_construct(dwbc30, ctx, 1212 &dwbc30_regs[i], 1213 &dwbc30_shift, 1214 &dwbc30_mask, 1215 i); 1216 1217 pool->dwbc[i] = &dwbc30->base; 1218 } 1219 return true; 1220 } 1221 1222 static bool dcn301_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) 1223 { 1224 int i; 1225 uint32_t pipe_count = pool->res_cap->num_dwb; 1226 1227 for (i = 0; i < pipe_count; i++) { 1228 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), 1229 GFP_KERNEL); 1230 1231 if (!mcif_wb30) { 1232 dm_error("DC: failed to create mcif_wb30!\n"); 1233 return false; 1234 } 1235 1236 dcn30_mmhubbub_construct(mcif_wb30, ctx, 1237 &mcif_wb30_regs[i], 1238 &mcif_wb30_shift, 1239 &mcif_wb30_mask, 1240 i); 1241 1242 pool->mcif_wb[i] = &mcif_wb30->base; 1243 } 1244 return true; 1245 } 1246 1247 static struct display_stream_compressor *dcn301_dsc_create( 1248 struct dc_context *ctx, uint32_t inst) 1249 { 1250 struct dcn20_dsc *dsc = 1251 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); 1252 1253 if (!dsc) { 1254 BREAK_TO_DEBUGGER(); 1255 return NULL; 1256 } 1257 1258 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 1259 return &dsc->base; 1260 } 1261 1262 1263 static void dcn301_destroy_resource_pool(struct resource_pool **pool) 1264 { 1265 struct dcn301_resource_pool *dcn301_pool = TO_DCN301_RES_POOL(*pool); 1266 1267 dcn301_destruct(dcn301_pool); 1268 kfree(dcn301_pool); 1269 *pool = NULL; 1270 } 1271 1272 static struct clock_source *dcn301_clock_source_create( 1273 struct dc_context *ctx, 1274 struct dc_bios *bios, 1275 enum clock_source_id id, 1276 const struct dce110_clk_src_regs *regs, 1277 bool dp_clk_src) 1278 { 1279 struct dce110_clk_src *clk_src = 1280 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 1281 1282 if (!clk_src) 1283 return NULL; 1284 1285 if (dcn301_clk_src_construct(clk_src, ctx, bios, id, 1286 regs, &cs_shift, &cs_mask)) { 1287 clk_src->base.dp_clk_src = dp_clk_src; 1288 return &clk_src->base; 1289 } 1290 1291 BREAK_TO_DEBUGGER(); 1292 return NULL; 1293 } 1294 1295 static struct dc_cap_funcs cap_funcs = { 1296 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap 1297 }; 1298 1299 1300 static bool is_soc_bounding_box_valid(struct dc *dc) 1301 { 1302 uint32_t hw_internal_rev = dc->ctx->asic_id.hw_internal_rev; 1303 1304 if (ASICREV_IS_VANGOGH(hw_internal_rev)) 1305 return true; 1306 1307 return false; 1308 } 1309 1310 static bool init_soc_bounding_box(struct dc *dc, 1311 struct dcn301_resource_pool *pool) 1312 { 1313 struct _vcs_dpi_soc_bounding_box_st *loaded_bb = &dcn3_01_soc; 1314 struct _vcs_dpi_ip_params_st *loaded_ip = &dcn3_01_ip; 1315 1316 DC_LOGGER_INIT(dc->ctx->logger); 1317 1318 if (!is_soc_bounding_box_valid(dc)) { 1319 DC_LOG_ERROR("%s: not valid soc bounding box\n", __func__); 1320 return false; 1321 } 1322 1323 loaded_ip->max_num_otg = pool->base.res_cap->num_timing_generator; 1324 loaded_ip->max_num_dpp = pool->base.pipe_count; 1325 DC_FP_START(); 1326 dcn20_patch_bounding_box(dc, loaded_bb); 1327 DC_FP_END(); 1328 1329 if (dc->ctx->dc_bios->funcs->get_soc_bb_info) { 1330 struct bp_soc_bb_info bb_info = {0}; 1331 1332 if (dc->ctx->dc_bios->funcs->get_soc_bb_info(dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) { 1333 DC_FP_START(); 1334 dcn301_fpu_init_soc_bounding_box(bb_info); 1335 DC_FP_END(); 1336 } 1337 } 1338 1339 return true; 1340 } 1341 1342 1343 static void set_wm_ranges( 1344 struct pp_smu_funcs *pp_smu, 1345 struct _vcs_dpi_soc_bounding_box_st *loaded_bb) 1346 { 1347 struct pp_smu_wm_range_sets ranges = {0}; 1348 int i; 1349 1350 ranges.num_reader_wm_sets = 0; 1351 1352 if (loaded_bb->num_states == 1) { 1353 ranges.reader_wm_sets[0].wm_inst = 0; 1354 ranges.reader_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 1355 ranges.reader_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 1356 ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 1357 ranges.reader_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 1358 1359 ranges.num_reader_wm_sets = 1; 1360 } else if (loaded_bb->num_states > 1) { 1361 for (i = 0; i < 4 && i < loaded_bb->num_states; i++) { 1362 ranges.reader_wm_sets[i].wm_inst = i; 1363 ranges.reader_wm_sets[i].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 1364 ranges.reader_wm_sets[i].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 1365 DC_FP_START(); 1366 dcn301_fpu_set_wm_ranges(i, &ranges, loaded_bb); 1367 DC_FP_END(); 1368 ranges.num_reader_wm_sets = i + 1; 1369 } 1370 1371 ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 1372 ranges.reader_wm_sets[ranges.num_reader_wm_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 1373 } 1374 1375 ranges.num_writer_wm_sets = 1; 1376 1377 ranges.writer_wm_sets[0].wm_inst = 0; 1378 ranges.writer_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 1379 ranges.writer_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 1380 ranges.writer_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 1381 ranges.writer_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 1382 1383 /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */ 1384 pp_smu->nv_funcs.set_wm_ranges(&pp_smu->nv_funcs.pp_smu, &ranges); 1385 } 1386 1387 static void dcn301_calculate_wm_and_dlg( 1388 struct dc *dc, struct dc_state *context, 1389 display_e2e_pipe_params_st *pipes, 1390 int pipe_cnt, 1391 int vlevel) 1392 { 1393 DC_FP_START(); 1394 dcn301_calculate_wm_and_dlg_fp(dc, context, pipes, pipe_cnt, vlevel); 1395 DC_FP_END(); 1396 } 1397 1398 static struct resource_funcs dcn301_res_pool_funcs = { 1399 .destroy = dcn301_destroy_resource_pool, 1400 .link_enc_create = dcn301_link_encoder_create, 1401 .panel_cntl_create = dcn301_panel_cntl_create, 1402 .validate_bandwidth = dcn30_validate_bandwidth, 1403 .calculate_wm_and_dlg = dcn301_calculate_wm_and_dlg, 1404 .update_soc_for_wm_a = dcn30_update_soc_for_wm_a, 1405 .populate_dml_pipes = dcn30_populate_dml_pipes_from_context, 1406 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer, 1407 .add_stream_to_ctx = dcn30_add_stream_to_ctx, 1408 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, 1409 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 1410 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, 1411 .set_mcif_arb_params = dcn30_set_mcif_arb_params, 1412 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, 1413 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut, 1414 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut, 1415 .update_bw_bounding_box = dcn301_update_bw_bounding_box 1416 }; 1417 1418 static bool dcn301_resource_construct( 1419 uint8_t num_virtual_links, 1420 struct dc *dc, 1421 struct dcn301_resource_pool *pool) 1422 { 1423 int i, j; 1424 struct dc_context *ctx = dc->ctx; 1425 struct irq_service_init_data init_data; 1426 uint32_t pipe_fuses = read_pipe_fuses(ctx); 1427 uint32_t num_pipes = 0; 1428 1429 DC_LOGGER_INIT(dc->ctx->logger); 1430 1431 ctx->dc_bios->regs = &bios_regs; 1432 1433 if (dc->ctx->asic_id.chip_id == DEVICE_ID_VGH_1435) 1434 res_cap_dcn301.num_pll = 2; 1435 pool->base.res_cap = &res_cap_dcn301; 1436 1437 pool->base.funcs = &dcn301_res_pool_funcs; 1438 1439 /************************************************* 1440 * Resource + asic cap harcoding * 1441 *************************************************/ 1442 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1443 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; 1444 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator; 1445 dc->caps.max_downscale_ratio = 600; 1446 dc->caps.i2c_speed_in_khz = 100; 1447 dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a enabled by default*/ 1448 dc->caps.max_cursor_size = 256; 1449 dc->caps.min_horizontal_blanking_period = 80; 1450 dc->caps.dmdata_alloc_size = 2048; 1451 dc->caps.max_slave_planes = 1; 1452 dc->caps.max_slave_yuv_planes = 1; 1453 dc->caps.max_slave_rgb_planes = 1; 1454 dc->caps.is_apu = true; 1455 dc->caps.post_blend_color_processing = true; 1456 dc->caps.force_dp_tps4_for_cp2520 = true; 1457 dc->caps.extended_aux_timeout_support = true; 1458 dc->caps.dmcub_support = true; 1459 1460 /* Color pipeline capabilities */ 1461 dc->caps.color.dpp.dcn_arch = 1; 1462 dc->caps.color.dpp.input_lut_shared = 0; 1463 dc->caps.color.dpp.icsc = 1; 1464 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr 1465 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; 1466 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; 1467 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1; 1468 dc->caps.color.dpp.dgam_rom_caps.pq = 1; 1469 dc->caps.color.dpp.dgam_rom_caps.hlg = 1; 1470 dc->caps.color.dpp.post_csc = 1; 1471 dc->caps.color.dpp.gamma_corr = 1; 1472 dc->caps.color.dpp.dgam_rom_for_yuv = 0; 1473 1474 dc->caps.color.dpp.hw_3d_lut = 1; 1475 dc->caps.color.dpp.ogam_ram = 1; 1476 // no OGAM ROM on DCN301 1477 dc->caps.color.dpp.ogam_rom_caps.srgb = 0; 1478 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; 1479 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; 1480 dc->caps.color.dpp.ogam_rom_caps.pq = 0; 1481 dc->caps.color.dpp.ogam_rom_caps.hlg = 0; 1482 dc->caps.color.dpp.ocsc = 0; 1483 1484 dc->caps.color.mpc.gamut_remap = 1; 1485 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2 1486 dc->caps.color.mpc.ogam_ram = 1; 1487 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; 1488 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; 1489 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; 1490 dc->caps.color.mpc.ogam_rom_caps.pq = 0; 1491 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 1492 dc->caps.color.mpc.ocsc = 1; 1493 1494 /* read VBIOS LTTPR caps */ 1495 if (ctx->dc_bios->funcs->get_lttpr_caps) { 1496 enum bp_result bp_query_result; 1497 uint8_t is_vbios_lttpr_enable = 0; 1498 1499 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable); 1500 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable; 1501 } 1502 1503 if (ctx->dc_bios->funcs->get_lttpr_interop) { 1504 enum bp_result bp_query_result; 1505 uint8_t is_vbios_interop_enabled = 0; 1506 1507 bp_query_result = ctx->dc_bios->funcs->get_lttpr_interop(ctx->dc_bios, &is_vbios_interop_enabled); 1508 dc->caps.vbios_lttpr_aware = (bp_query_result == BP_RESULT_OK) && !!is_vbios_interop_enabled; 1509 } 1510 1511 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 1512 dc->debug = debug_defaults_drv; 1513 else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) { 1514 dc->debug = debug_defaults_diags; 1515 } else 1516 dc->debug = debug_defaults_diags; 1517 // Init the vm_helper 1518 if (dc->vm_helper) 1519 vm_helper_init(dc->vm_helper, 16); 1520 1521 /************************************************* 1522 * Create resources * 1523 *************************************************/ 1524 1525 /* Clock Sources for Pixel Clock*/ 1526 pool->base.clock_sources[DCN301_CLK_SRC_PLL0] = 1527 dcn301_clock_source_create(ctx, ctx->dc_bios, 1528 CLOCK_SOURCE_COMBO_PHY_PLL0, 1529 &clk_src_regs[0], false); 1530 pool->base.clock_sources[DCN301_CLK_SRC_PLL1] = 1531 dcn301_clock_source_create(ctx, ctx->dc_bios, 1532 CLOCK_SOURCE_COMBO_PHY_PLL1, 1533 &clk_src_regs[1], false); 1534 pool->base.clock_sources[DCN301_CLK_SRC_PLL2] = 1535 dcn301_clock_source_create(ctx, ctx->dc_bios, 1536 CLOCK_SOURCE_COMBO_PHY_PLL2, 1537 &clk_src_regs[2], false); 1538 pool->base.clock_sources[DCN301_CLK_SRC_PLL3] = 1539 dcn301_clock_source_create(ctx, ctx->dc_bios, 1540 CLOCK_SOURCE_COMBO_PHY_PLL3, 1541 &clk_src_regs[3], false); 1542 1543 pool->base.clk_src_count = DCN301_CLK_SRC_TOTAL; 1544 1545 /* todo: not reuse phy_pll registers */ 1546 pool->base.dp_clock_source = 1547 dcn301_clock_source_create(ctx, ctx->dc_bios, 1548 CLOCK_SOURCE_ID_DP_DTO, 1549 &clk_src_regs[0], true); 1550 1551 for (i = 0; i < pool->base.clk_src_count; i++) { 1552 if (pool->base.clock_sources[i] == NULL) { 1553 dm_error("DC: failed to create clock sources!\n"); 1554 BREAK_TO_DEBUGGER(); 1555 goto create_fail; 1556 } 1557 } 1558 1559 /* DCCG */ 1560 pool->base.dccg = dccg301_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 1561 if (pool->base.dccg == NULL) { 1562 dm_error("DC: failed to create dccg!\n"); 1563 BREAK_TO_DEBUGGER(); 1564 goto create_fail; 1565 } 1566 1567 init_soc_bounding_box(dc, pool); 1568 1569 if (!dc->debug.disable_pplib_wm_range && pool->base.pp_smu->nv_funcs.set_wm_ranges) 1570 set_wm_ranges(pool->base.pp_smu, &dcn3_01_soc); 1571 1572 num_pipes = dcn3_01_ip.max_num_dpp; 1573 1574 for (i = 0; i < dcn3_01_ip.max_num_dpp; i++) 1575 if (pipe_fuses & 1 << i) 1576 num_pipes--; 1577 dcn3_01_ip.max_num_dpp = num_pipes; 1578 dcn3_01_ip.max_num_otg = num_pipes; 1579 1580 1581 dml_init_instance(&dc->dml, &dcn3_01_soc, &dcn3_01_ip, DML_PROJECT_DCN30); 1582 1583 /* IRQ */ 1584 init_data.ctx = dc->ctx; 1585 pool->base.irqs = dal_irq_service_dcn30_create(&init_data); 1586 if (!pool->base.irqs) 1587 goto create_fail; 1588 1589 /* HUBBUB */ 1590 pool->base.hubbub = dcn301_hubbub_create(ctx); 1591 if (pool->base.hubbub == NULL) { 1592 BREAK_TO_DEBUGGER(); 1593 dm_error("DC: failed to create hubbub!\n"); 1594 goto create_fail; 1595 } 1596 1597 j = 0; 1598 /* HUBPs, DPPs, OPPs and TGs */ 1599 for (i = 0; i < pool->base.pipe_count; i++) { 1600 1601 /* if pipe is disabled, skip instance of HW pipe, 1602 * i.e, skip ASIC register instance 1603 */ 1604 if ((pipe_fuses & (1 << i)) != 0) { 1605 DC_LOG_DEBUG("%s: fusing pipe %d\n", __func__, i); 1606 continue; 1607 } 1608 1609 pool->base.hubps[j] = dcn301_hubp_create(ctx, i); 1610 if (pool->base.hubps[j] == NULL) { 1611 BREAK_TO_DEBUGGER(); 1612 dm_error( 1613 "DC: failed to create hubps!\n"); 1614 goto create_fail; 1615 } 1616 1617 pool->base.dpps[j] = dcn301_dpp_create(ctx, i); 1618 if (pool->base.dpps[j] == NULL) { 1619 BREAK_TO_DEBUGGER(); 1620 dm_error( 1621 "DC: failed to create dpps!\n"); 1622 goto create_fail; 1623 } 1624 1625 pool->base.opps[j] = dcn301_opp_create(ctx, i); 1626 if (pool->base.opps[j] == NULL) { 1627 BREAK_TO_DEBUGGER(); 1628 dm_error( 1629 "DC: failed to create output pixel processor!\n"); 1630 goto create_fail; 1631 } 1632 1633 pool->base.timing_generators[j] = dcn301_timing_generator_create(ctx, i); 1634 if (pool->base.timing_generators[j] == NULL) { 1635 BREAK_TO_DEBUGGER(); 1636 dm_error("DC: failed to create tg!\n"); 1637 goto create_fail; 1638 } 1639 j++; 1640 } 1641 pool->base.timing_generator_count = j; 1642 pool->base.pipe_count = j; 1643 pool->base.mpcc_count = j; 1644 1645 /* ABM (or ABMs for NV2x) */ 1646 /* TODO: */ 1647 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1648 pool->base.multiple_abms[i] = dmub_abm_create(ctx, 1649 &abm_regs[i], 1650 &abm_shift, 1651 &abm_mask); 1652 if (pool->base.multiple_abms[i] == NULL) { 1653 dm_error("DC: failed to create abm for pipe %d!\n", i); 1654 BREAK_TO_DEBUGGER(); 1655 goto create_fail; 1656 } 1657 } 1658 1659 /* MPC and DSC */ 1660 pool->base.mpc = dcn301_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut); 1661 if (pool->base.mpc == NULL) { 1662 BREAK_TO_DEBUGGER(); 1663 dm_error("DC: failed to create mpc!\n"); 1664 goto create_fail; 1665 } 1666 1667 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 1668 pool->base.dscs[i] = dcn301_dsc_create(ctx, i); 1669 if (pool->base.dscs[i] == NULL) { 1670 BREAK_TO_DEBUGGER(); 1671 dm_error("DC: failed to create display stream compressor %d!\n", i); 1672 goto create_fail; 1673 } 1674 } 1675 1676 /* DWB and MMHUBBUB */ 1677 if (!dcn301_dwbc_create(ctx, &pool->base)) { 1678 BREAK_TO_DEBUGGER(); 1679 dm_error("DC: failed to create dwbc!\n"); 1680 goto create_fail; 1681 } 1682 1683 if (!dcn301_mmhubbub_create(ctx, &pool->base)) { 1684 BREAK_TO_DEBUGGER(); 1685 dm_error("DC: failed to create mcif_wb!\n"); 1686 goto create_fail; 1687 } 1688 1689 /* AUX and I2C */ 1690 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1691 pool->base.engines[i] = dcn301_aux_engine_create(ctx, i); 1692 if (pool->base.engines[i] == NULL) { 1693 BREAK_TO_DEBUGGER(); 1694 dm_error( 1695 "DC:failed to create aux engine!!\n"); 1696 goto create_fail; 1697 } 1698 pool->base.hw_i2cs[i] = dcn301_i2c_hw_create(ctx, i); 1699 if (pool->base.hw_i2cs[i] == NULL) { 1700 BREAK_TO_DEBUGGER(); 1701 dm_error( 1702 "DC:failed to create hw i2c!!\n"); 1703 goto create_fail; 1704 } 1705 pool->base.sw_i2cs[i] = NULL; 1706 } 1707 1708 /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */ 1709 if (!resource_construct(num_virtual_links, dc, &pool->base, 1710 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? 1711 &res_create_funcs : &res_create_maximus_funcs))) 1712 goto create_fail; 1713 1714 /* HW Sequencer and Plane caps */ 1715 dcn301_hw_sequencer_construct(dc); 1716 1717 dc->caps.max_planes = pool->base.pipe_count; 1718 1719 for (i = 0; i < dc->caps.max_planes; ++i) 1720 dc->caps.planes[i] = plane_cap; 1721 1722 dc->cap_funcs = cap_funcs; 1723 1724 return true; 1725 1726 create_fail: 1727 1728 dcn301_destruct(pool); 1729 1730 return false; 1731 } 1732 1733 struct resource_pool *dcn301_create_resource_pool( 1734 const struct dc_init_data *init_data, 1735 struct dc *dc) 1736 { 1737 struct dcn301_resource_pool *pool = 1738 kzalloc(sizeof(struct dcn301_resource_pool), GFP_KERNEL); 1739 1740 if (!pool) 1741 return NULL; 1742 1743 if (dcn301_resource_construct(init_data->num_virtual_links, dc, pool)) 1744 return &pool->base; 1745 1746 BREAK_TO_DEBUGGER(); 1747 kfree(pool); 1748 return NULL; 1749 } 1750