1 /*
2  * Copyright 2019-2021 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 
27 #include "dm_services.h"
28 #include "dc.h"
29 
30 #include "dcn301_init.h"
31 
32 #include "resource.h"
33 #include "include/irq_service_interface.h"
34 #include "dcn30/dcn30_resource.h"
35 #include "dcn301_resource.h"
36 
37 #include "dcn20/dcn20_resource.h"
38 
39 #include "dcn10/dcn10_ipp.h"
40 #include "dcn301/dcn301_hubbub.h"
41 #include "dcn30/dcn30_mpc.h"
42 #include "dcn30/dcn30_hubp.h"
43 #include "irq/dcn30/irq_service_dcn30.h"
44 #include "dcn30/dcn30_dpp.h"
45 #include "dcn30/dcn30_optc.h"
46 #include "dcn20/dcn20_hwseq.h"
47 #include "dcn30/dcn30_hwseq.h"
48 #include "dce110/dce110_hw_sequencer.h"
49 #include "dcn30/dcn30_opp.h"
50 #include "dcn20/dcn20_dsc.h"
51 #include "dcn30/dcn30_vpg.h"
52 #include "dcn30/dcn30_afmt.h"
53 #include "dce/dce_clock_source.h"
54 #include "dce/dce_audio.h"
55 #include "dce/dce_hwseq.h"
56 #include "clk_mgr.h"
57 #include "virtual/virtual_stream_encoder.h"
58 #include "dce110/dce110_resource.h"
59 #include "dml/display_mode_vba.h"
60 #include "dcn301/dcn301_dccg.h"
61 #include "dcn10/dcn10_resource.h"
62 #include "dcn30/dcn30_dio_stream_encoder.h"
63 #include "dcn301/dcn301_dio_link_encoder.h"
64 #include "dcn301_panel_cntl.h"
65 
66 #include "vangogh_ip_offset.h"
67 
68 #include "dcn30/dcn30_dwb.h"
69 #include "dcn30/dcn30_mmhubbub.h"
70 
71 #include "dcn/dcn_3_0_1_offset.h"
72 #include "dcn/dcn_3_0_1_sh_mask.h"
73 
74 #include "nbio/nbio_7_2_0_offset.h"
75 
76 #include "dcn/dpcs_3_0_0_offset.h"
77 #include "dcn/dpcs_3_0_0_sh_mask.h"
78 
79 #include "reg_helper.h"
80 #include "dce/dmub_abm.h"
81 #include "dce/dce_aux.h"
82 #include "dce/dce_i2c.h"
83 
84 #include "dml/dcn30/display_mode_vba_30.h"
85 #include "dml/dcn301/dcn301_fpu.h"
86 #include "vm_helper.h"
87 #include "dcn20/dcn20_vmid.h"
88 #include "amdgpu_socbb.h"
89 
90 #define TO_DCN301_RES_POOL(pool)\
91 	container_of(pool, struct dcn301_resource_pool, base)
92 
93 #define DC_LOGGER_INIT(logger)
94 
95 enum dcn301_clk_src_array_id {
96 	DCN301_CLK_SRC_PLL0,
97 	DCN301_CLK_SRC_PLL1,
98 	DCN301_CLK_SRC_PLL2,
99 	DCN301_CLK_SRC_PLL3,
100 	DCN301_CLK_SRC_TOTAL
101 };
102 
103 /* begin *********************
104  * macros to expend register list macro defined in HW object header file
105  */
106 
107 /* DCN */
108 /* TODO awful hack. fixup dcn20_dwb.h */
109 #undef BASE_INNER
110 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
111 
112 #define BASE(seg) BASE_INNER(seg)
113 
114 #define SR(reg_name)\
115 		.reg_name = BASE(mm ## reg_name ## _BASE_IDX) +  \
116 					mm ## reg_name
117 
118 #define SRI(reg_name, block, id)\
119 	.reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
120 					mm ## block ## id ## _ ## reg_name
121 
122 #define SRI2(reg_name, block, id)\
123 	.reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
124 					mm ## reg_name
125 
126 #define SRIR(var_name, reg_name, block, id)\
127 	.var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
128 					mm ## block ## id ## _ ## reg_name
129 
130 #define SRII(reg_name, block, id)\
131 	.reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
132 					mm ## block ## id ## _ ## reg_name
133 
134 #define SRII2(reg_name_pre, reg_name_post, id)\
135 	.reg_name_pre ## _ ##  reg_name_post[id] = BASE(mm ## reg_name_pre \
136 			## id ## _ ## reg_name_post ## _BASE_IDX) + \
137 			mm ## reg_name_pre ## id ## _ ## reg_name_post
138 
139 #define SRII_MPC_RMU(reg_name, block, id)\
140 	.RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
141 					mm ## block ## id ## _ ## reg_name
142 
143 #define SRII_DWB(reg_name, temp_name, block, id)\
144 	.reg_name[id] = BASE(mm ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
145 					mm ## block ## id ## _ ## temp_name
146 
147 #define DCCG_SRII(reg_name, block, id)\
148 	.block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
149 					mm ## block ## id ## _ ## reg_name
150 
151 #define VUPDATE_SRII(reg_name, block, id)\
152 	.reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
153 					mm ## reg_name ## _ ## block ## id
154 
155 /* NBIO */
156 #define NBIO_BASE_INNER(seg) \
157 	NBIO_BASE__INST0_SEG ## seg
158 
159 #define NBIO_BASE(seg) \
160 	NBIO_BASE_INNER(seg)
161 
162 #define NBIO_SR(reg_name)\
163 		.reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \
164 					regBIF_BX0_ ## reg_name
165 
166 /* MMHUB */
167 #define MMHUB_BASE_INNER(seg) \
168 	MMHUB_BASE__INST0_SEG ## seg
169 
170 #define MMHUB_BASE(seg) \
171 	MMHUB_BASE_INNER(seg)
172 
173 #define MMHUB_SR(reg_name)\
174 		.reg_name = MMHUB_BASE(regMM ## reg_name ## _BASE_IDX) + \
175 					regMM ## reg_name
176 
177 /* CLOCK */
178 #define CLK_BASE_INNER(seg) \
179 	CLK_BASE__INST0_SEG ## seg
180 
181 #define CLK_BASE(seg) \
182 	CLK_BASE_INNER(seg)
183 
184 #define CLK_SRI(reg_name, block, inst)\
185 	.reg_name = CLK_BASE(mm ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \
186 					mm ## block ## _ ## inst ## _ ## reg_name
187 
188 static const struct bios_registers bios_regs = {
189 		NBIO_SR(BIOS_SCRATCH_3),
190 		NBIO_SR(BIOS_SCRATCH_6)
191 };
192 
193 #define clk_src_regs(index, pllid)\
194 [index] = {\
195 	CS_COMMON_REG_LIST_DCN3_01(index, pllid),\
196 }
197 
198 static const struct dce110_clk_src_regs clk_src_regs[] = {
199 	clk_src_regs(0, A),
200 	clk_src_regs(1, B),
201 	clk_src_regs(2, C),
202 	clk_src_regs(3, D)
203 };
204 
205 static const struct dce110_clk_src_shift cs_shift = {
206 		CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
207 };
208 
209 static const struct dce110_clk_src_mask cs_mask = {
210 		CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
211 };
212 
213 #define abm_regs(id)\
214 [id] = {\
215 		ABM_DCN301_REG_LIST(id)\
216 }
217 
218 static const struct dce_abm_registers abm_regs[] = {
219 		abm_regs(0),
220 		abm_regs(1),
221 		abm_regs(2),
222 		abm_regs(3),
223 };
224 
225 static const struct dce_abm_shift abm_shift = {
226 		ABM_MASK_SH_LIST_DCN30(__SHIFT)
227 };
228 
229 static const struct dce_abm_mask abm_mask = {
230 		ABM_MASK_SH_LIST_DCN30(_MASK)
231 };
232 
233 #define audio_regs(id)\
234 [id] = {\
235 		AUD_COMMON_REG_LIST(id)\
236 }
237 
238 static const struct dce_audio_registers audio_regs[] = {
239 	audio_regs(0),
240 	audio_regs(1),
241 	audio_regs(2),
242 	audio_regs(3),
243 	audio_regs(4),
244 	audio_regs(5),
245 	audio_regs(6)
246 };
247 
248 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
249 		SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
250 		SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
251 		AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
252 
253 static const struct dce_audio_shift audio_shift = {
254 		DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
255 };
256 
257 static const struct dce_audio_mask audio_mask = {
258 		DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
259 };
260 
261 #define vpg_regs(id)\
262 [id] = {\
263 	VPG_DCN3_REG_LIST(id)\
264 }
265 
266 static const struct dcn30_vpg_registers vpg_regs[] = {
267 	vpg_regs(0),
268 	vpg_regs(1),
269 	vpg_regs(2),
270 	vpg_regs(3),
271 };
272 
273 static const struct dcn30_vpg_shift vpg_shift = {
274 	DCN3_VPG_MASK_SH_LIST(__SHIFT)
275 };
276 
277 static const struct dcn30_vpg_mask vpg_mask = {
278 	DCN3_VPG_MASK_SH_LIST(_MASK)
279 };
280 
281 #define afmt_regs(id)\
282 [id] = {\
283 	AFMT_DCN3_REG_LIST(id)\
284 }
285 
286 static const struct dcn30_afmt_registers afmt_regs[] = {
287 	afmt_regs(0),
288 	afmt_regs(1),
289 	afmt_regs(2),
290 	afmt_regs(3),
291 };
292 
293 static const struct dcn30_afmt_shift afmt_shift = {
294 	DCN3_AFMT_MASK_SH_LIST(__SHIFT)
295 };
296 
297 static const struct dcn30_afmt_mask afmt_mask = {
298 	DCN3_AFMT_MASK_SH_LIST(_MASK)
299 };
300 
301 #define stream_enc_regs(id)\
302 [id] = {\
303 	SE_DCN3_REG_LIST(id)\
304 }
305 
306 static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
307 	stream_enc_regs(0),
308 	stream_enc_regs(1),
309 	stream_enc_regs(2),
310 	stream_enc_regs(3),
311 };
312 
313 static const struct dcn10_stream_encoder_shift se_shift = {
314 		SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
315 };
316 
317 static const struct dcn10_stream_encoder_mask se_mask = {
318 		SE_COMMON_MASK_SH_LIST_DCN30(_MASK)
319 };
320 
321 
322 #define aux_regs(id)\
323 [id] = {\
324 	DCN2_AUX_REG_LIST(id)\
325 }
326 
327 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
328 		aux_regs(0),
329 		aux_regs(1),
330 		aux_regs(2),
331 		aux_regs(3),
332 };
333 
334 #define hpd_regs(id)\
335 [id] = {\
336 	HPD_REG_LIST(id)\
337 }
338 
339 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
340 		hpd_regs(0),
341 		hpd_regs(1),
342 		hpd_regs(2),
343 		hpd_regs(3),
344 };
345 
346 
347 #define link_regs(id, phyid)\
348 [id] = {\
349 	LE_DCN301_REG_LIST(id), \
350 	UNIPHY_DCN2_REG_LIST(phyid), \
351 	DPCS_DCN2_REG_LIST(id), \
352 	SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
353 }
354 
355 static const struct dce110_aux_registers_shift aux_shift = {
356 	DCN_AUX_MASK_SH_LIST(__SHIFT)
357 };
358 
359 static const struct dce110_aux_registers_mask aux_mask = {
360 	DCN_AUX_MASK_SH_LIST(_MASK)
361 };
362 
363 static const struct dcn10_link_enc_registers link_enc_regs[] = {
364 	link_regs(0, A),
365 	link_regs(1, B),
366 	link_regs(2, C),
367 	link_regs(3, D),
368 };
369 
370 static const struct dcn10_link_enc_shift le_shift = {
371 	LINK_ENCODER_MASK_SH_LIST_DCN301(__SHIFT),\
372 	DPCS_DCN2_MASK_SH_LIST(__SHIFT)
373 };
374 
375 static const struct dcn10_link_enc_mask le_mask = {
376 	LINK_ENCODER_MASK_SH_LIST_DCN301(_MASK),\
377 	DPCS_DCN2_MASK_SH_LIST(_MASK)
378 };
379 
380 #define panel_cntl_regs(id)\
381 [id] = {\
382 	DCN301_PANEL_CNTL_REG_LIST(id),\
383 }
384 
385 static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
386 	panel_cntl_regs(0),
387 	panel_cntl_regs(1),
388 };
389 
390 static const struct dcn301_panel_cntl_shift panel_cntl_shift = {
391 	DCN301_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
392 };
393 
394 static const struct dcn301_panel_cntl_mask panel_cntl_mask = {
395 	DCN301_PANEL_CNTL_MASK_SH_LIST(_MASK)
396 };
397 
398 #define dpp_regs(id)\
399 [id] = {\
400 	DPP_REG_LIST_DCN30(id),\
401 }
402 
403 static const struct dcn3_dpp_registers dpp_regs[] = {
404 	dpp_regs(0),
405 	dpp_regs(1),
406 	dpp_regs(2),
407 	dpp_regs(3),
408 };
409 
410 static const struct dcn3_dpp_shift tf_shift = {
411 		DPP_REG_LIST_SH_MASK_DCN30(__SHIFT)
412 };
413 
414 static const struct dcn3_dpp_mask tf_mask = {
415 		DPP_REG_LIST_SH_MASK_DCN30(_MASK)
416 };
417 
418 #define opp_regs(id)\
419 [id] = {\
420 	OPP_REG_LIST_DCN30(id),\
421 }
422 
423 static const struct dcn20_opp_registers opp_regs[] = {
424 	opp_regs(0),
425 	opp_regs(1),
426 	opp_regs(2),
427 	opp_regs(3),
428 };
429 
430 static const struct dcn20_opp_shift opp_shift = {
431 	OPP_MASK_SH_LIST_DCN20(__SHIFT)
432 };
433 
434 static const struct dcn20_opp_mask opp_mask = {
435 	OPP_MASK_SH_LIST_DCN20(_MASK)
436 };
437 
438 #define aux_engine_regs(id)\
439 [id] = {\
440 	AUX_COMMON_REG_LIST0(id), \
441 	.AUXN_IMPCAL = 0, \
442 	.AUXP_IMPCAL = 0, \
443 	.AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
444 }
445 
446 static const struct dce110_aux_registers aux_engine_regs[] = {
447 		aux_engine_regs(0),
448 		aux_engine_regs(1),
449 		aux_engine_regs(2),
450 		aux_engine_regs(3),
451 };
452 
453 #define dwbc_regs_dcn3(id)\
454 [id] = {\
455 	DWBC_COMMON_REG_LIST_DCN30(id),\
456 }
457 
458 static const struct dcn30_dwbc_registers dwbc30_regs[] = {
459 	dwbc_regs_dcn3(0),
460 };
461 
462 static const struct dcn30_dwbc_shift dwbc30_shift = {
463 	DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
464 };
465 
466 static const struct dcn30_dwbc_mask dwbc30_mask = {
467 	DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
468 };
469 
470 #define mcif_wb_regs_dcn3(id)\
471 [id] = {\
472 	MCIF_WB_COMMON_REG_LIST_DCN30(id),\
473 }
474 
475 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = {
476 	mcif_wb_regs_dcn3(0)
477 };
478 
479 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
480 	MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
481 };
482 
483 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
484 	MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK)
485 };
486 
487 #define dsc_regsDCN20(id)\
488 [id] = {\
489 	DSC_REG_LIST_DCN20(id)\
490 }
491 
492 static const struct dcn20_dsc_registers dsc_regs[] = {
493 	dsc_regsDCN20(0),
494 	dsc_regsDCN20(1),
495 	dsc_regsDCN20(2),
496 };
497 
498 static const struct dcn20_dsc_shift dsc_shift = {
499 	DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
500 };
501 
502 static const struct dcn20_dsc_mask dsc_mask = {
503 	DSC_REG_LIST_SH_MASK_DCN20(_MASK)
504 };
505 
506 static const struct dcn30_mpc_registers mpc_regs = {
507 		MPC_REG_LIST_DCN3_0(0),
508 		MPC_REG_LIST_DCN3_0(1),
509 		MPC_REG_LIST_DCN3_0(2),
510 		MPC_REG_LIST_DCN3_0(3),
511 		MPC_OUT_MUX_REG_LIST_DCN3_0(0),
512 		MPC_OUT_MUX_REG_LIST_DCN3_0(1),
513 		MPC_OUT_MUX_REG_LIST_DCN3_0(2),
514 		MPC_OUT_MUX_REG_LIST_DCN3_0(3),
515 		MPC_RMU_GLOBAL_REG_LIST_DCN3AG,
516 		MPC_RMU_REG_LIST_DCN3AG(0),
517 		MPC_RMU_REG_LIST_DCN3AG(1),
518 		MPC_DWB_MUX_REG_LIST_DCN3_0(0),
519 };
520 
521 static const struct dcn30_mpc_shift mpc_shift = {
522 	MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
523 };
524 
525 static const struct dcn30_mpc_mask mpc_mask = {
526 	MPC_COMMON_MASK_SH_LIST_DCN30(_MASK)
527 };
528 
529 #define optc_regs(id)\
530 [id] = {OPTC_COMMON_REG_LIST_DCN3_0(id)}
531 
532 
533 static const struct dcn_optc_registers optc_regs[] = {
534 	optc_regs(0),
535 	optc_regs(1),
536 	optc_regs(2),
537 	optc_regs(3),
538 };
539 
540 static const struct dcn_optc_shift optc_shift = {
541 	OPTC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
542 };
543 
544 static const struct dcn_optc_mask optc_mask = {
545 	OPTC_COMMON_MASK_SH_LIST_DCN30(_MASK)
546 };
547 
548 #define hubp_regs(id)\
549 [id] = {\
550 	HUBP_REG_LIST_DCN30(id)\
551 }
552 
553 static const struct dcn_hubp2_registers hubp_regs[] = {
554 		hubp_regs(0),
555 		hubp_regs(1),
556 		hubp_regs(2),
557 		hubp_regs(3),
558 };
559 
560 static const struct dcn_hubp2_shift hubp_shift = {
561 		HUBP_MASK_SH_LIST_DCN30(__SHIFT)
562 };
563 
564 static const struct dcn_hubp2_mask hubp_mask = {
565 		HUBP_MASK_SH_LIST_DCN30(_MASK)
566 };
567 
568 static const struct dcn_hubbub_registers hubbub_reg = {
569 		HUBBUB_REG_LIST_DCN301(0)
570 };
571 
572 static const struct dcn_hubbub_shift hubbub_shift = {
573 		HUBBUB_MASK_SH_LIST_DCN301(__SHIFT)
574 };
575 
576 static const struct dcn_hubbub_mask hubbub_mask = {
577 		HUBBUB_MASK_SH_LIST_DCN301(_MASK)
578 };
579 
580 static const struct dccg_registers dccg_regs = {
581 		DCCG_REG_LIST_DCN301()
582 };
583 
584 static const struct dccg_shift dccg_shift = {
585 		DCCG_MASK_SH_LIST_DCN301(__SHIFT)
586 };
587 
588 static const struct dccg_mask dccg_mask = {
589 		DCCG_MASK_SH_LIST_DCN301(_MASK)
590 };
591 
592 static const struct dce_hwseq_registers hwseq_reg = {
593 		HWSEQ_DCN301_REG_LIST()
594 };
595 
596 static const struct dce_hwseq_shift hwseq_shift = {
597 		HWSEQ_DCN301_MASK_SH_LIST(__SHIFT)
598 };
599 
600 static const struct dce_hwseq_mask hwseq_mask = {
601 		HWSEQ_DCN301_MASK_SH_LIST(_MASK)
602 };
603 #define vmid_regs(id)\
604 [id] = {\
605 		DCN20_VMID_REG_LIST(id)\
606 }
607 
608 static const struct dcn_vmid_registers vmid_regs[] = {
609 	vmid_regs(0),
610 	vmid_regs(1),
611 	vmid_regs(2),
612 	vmid_regs(3),
613 	vmid_regs(4),
614 	vmid_regs(5),
615 	vmid_regs(6),
616 	vmid_regs(7),
617 	vmid_regs(8),
618 	vmid_regs(9),
619 	vmid_regs(10),
620 	vmid_regs(11),
621 	vmid_regs(12),
622 	vmid_regs(13),
623 	vmid_regs(14),
624 	vmid_regs(15)
625 };
626 
627 static const struct dcn20_vmid_shift vmid_shifts = {
628 		DCN20_VMID_MASK_SH_LIST(__SHIFT)
629 };
630 
631 static const struct dcn20_vmid_mask vmid_masks = {
632 		DCN20_VMID_MASK_SH_LIST(_MASK)
633 };
634 
635 static const struct resource_caps res_cap_dcn301 = {
636 	.num_timing_generator = 4,
637 	.num_opp = 4,
638 	.num_video_plane = 4,
639 	.num_audio = 4,
640 	.num_stream_encoder = 4,
641 	.num_pll = 4,
642 	.num_dwb = 1,
643 	.num_ddc = 4,
644 	.num_vmid = 16,
645 	.num_mpc_3dlut = 2,
646 	.num_dsc = 3,
647 };
648 
649 static const struct dc_plane_cap plane_cap = {
650 	.type = DC_PLANE_TYPE_DCN_UNIVERSAL,
651 	.blends_with_above = true,
652 	.blends_with_below = true,
653 	.per_pixel_alpha = true,
654 
655 	.pixel_format_support = {
656 			.argb8888 = true,
657 			.nv12 = true,
658 			.fp16 = true,
659 			.p010 = true,
660 			.ayuv = false,
661 	},
662 
663 	.max_upscale_factor = {
664 			.argb8888 = 16000,
665 			.nv12 = 16000,
666 			.fp16 = 16000
667 	},
668 
669 	/* 6:1 downscaling ratio: 1000/6 = 166.666 */
670 	.max_downscale_factor = {
671 			.argb8888 = 167,
672 			.nv12 = 167,
673 			.fp16 = 167
674 	},
675 	64,
676 	64
677 };
678 
679 static const struct dc_debug_options debug_defaults_drv = {
680 	.disable_dmcu = true,
681 	.force_abm_enable = false,
682 	.timing_trace = false,
683 	.clock_trace = true,
684 	.disable_dpp_power_gate = false,
685 	.disable_hubp_power_gate = false,
686 	.disable_clock_gate = true,
687 	.disable_pplib_clock_request = true,
688 	.disable_pplib_wm_range = true,
689 	.pipe_split_policy = MPC_SPLIT_AVOID,
690 	.force_single_disp_pipe_split = false,
691 	.disable_dcc = DCC_ENABLE,
692 	.vsr_support = true,
693 	.performance_trace = false,
694 	.max_downscale_src_width = 7680,/*upto 8K*/
695 	.scl_reset_length10 = true,
696 	.sanity_checks = false,
697 	.underflow_assert_delay_us = 0xFFFFFFFF,
698 	.dwb_fi_phase = -1, // -1 = disable
699 	.dmub_command_table = true,
700 	.use_max_lb = false,
701 };
702 
703 static const struct dc_debug_options debug_defaults_diags = {
704 	.disable_dmcu = true,
705 	.force_abm_enable = false,
706 	.timing_trace = true,
707 	.clock_trace = true,
708 	.disable_dpp_power_gate = false,
709 	.disable_hubp_power_gate = false,
710 	.disable_clock_gate = true,
711 	.disable_pplib_clock_request = true,
712 	.disable_pplib_wm_range = true,
713 	.disable_stutter = true,
714 	.scl_reset_length10 = true,
715 	.dwb_fi_phase = -1, // -1 = disable
716 	.dmub_command_table = true,
717 	.use_max_lb = false,
718 };
719 
720 static void dcn301_dpp_destroy(struct dpp **dpp)
721 {
722 	kfree(TO_DCN20_DPP(*dpp));
723 	*dpp = NULL;
724 }
725 
726 static struct dpp *dcn301_dpp_create(struct dc_context *ctx, uint32_t inst)
727 {
728 	struct dcn3_dpp *dpp =
729 		kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);
730 
731 	if (!dpp)
732 		return NULL;
733 
734 	if (dpp3_construct(dpp, ctx, inst,
735 			&dpp_regs[inst], &tf_shift, &tf_mask))
736 		return &dpp->base;
737 
738 	BREAK_TO_DEBUGGER();
739 	kfree(dpp);
740 	return NULL;
741 }
742 static struct output_pixel_processor *dcn301_opp_create(struct dc_context *ctx,
743 							uint32_t inst)
744 {
745 	struct dcn20_opp *opp =
746 		kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
747 
748 	if (!opp) {
749 		BREAK_TO_DEBUGGER();
750 		return NULL;
751 	}
752 
753 	dcn20_opp_construct(opp, ctx, inst,
754 			&opp_regs[inst], &opp_shift, &opp_mask);
755 	return &opp->base;
756 }
757 
758 static struct dce_aux *dcn301_aux_engine_create(struct dc_context *ctx, uint32_t inst)
759 {
760 	struct aux_engine_dce110 *aux_engine =
761 		kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
762 
763 	if (!aux_engine)
764 		return NULL;
765 
766 	dce110_aux_engine_construct(aux_engine, ctx, inst,
767 				    SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
768 				    &aux_engine_regs[inst],
769 					&aux_mask,
770 					&aux_shift,
771 					ctx->dc->caps.extended_aux_timeout_support);
772 
773 	return &aux_engine->base;
774 }
775 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
776 
777 static const struct dce_i2c_registers i2c_hw_regs[] = {
778 		i2c_inst_regs(1),
779 		i2c_inst_regs(2),
780 		i2c_inst_regs(3),
781 		i2c_inst_regs(4),
782 };
783 
784 static const struct dce_i2c_shift i2c_shifts = {
785 		I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT)
786 };
787 
788 static const struct dce_i2c_mask i2c_masks = {
789 		I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)
790 };
791 
792 static struct dce_i2c_hw *dcn301_i2c_hw_create(struct dc_context *ctx, uint32_t inst)
793 {
794 	struct dce_i2c_hw *dce_i2c_hw =
795 		kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
796 
797 	if (!dce_i2c_hw)
798 		return NULL;
799 
800 	dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
801 				    &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
802 
803 	return dce_i2c_hw;
804 }
805 static struct mpc *dcn301_mpc_create(
806 		struct dc_context *ctx,
807 		int num_mpcc,
808 		int num_rmu)
809 {
810 	struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc),
811 					  GFP_KERNEL);
812 
813 	if (!mpc30)
814 		return NULL;
815 
816 	dcn30_mpc_construct(mpc30, ctx,
817 			&mpc_regs,
818 			&mpc_shift,
819 			&mpc_mask,
820 			num_mpcc,
821 			num_rmu);
822 
823 	return &mpc30->base;
824 }
825 
826 static struct hubbub *dcn301_hubbub_create(struct dc_context *ctx)
827 {
828 	int i;
829 
830 	struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub),
831 					  GFP_KERNEL);
832 
833 	if (!hubbub3)
834 		return NULL;
835 
836 	hubbub301_construct(hubbub3, ctx,
837 			&hubbub_reg,
838 			&hubbub_shift,
839 			&hubbub_mask);
840 
841 
842 	for (i = 0; i < res_cap_dcn301.num_vmid; i++) {
843 		struct dcn20_vmid *vmid = &hubbub3->vmid[i];
844 
845 		vmid->ctx = ctx;
846 
847 		vmid->regs = &vmid_regs[i];
848 		vmid->shifts = &vmid_shifts;
849 		vmid->masks = &vmid_masks;
850 	}
851 
852 	 hubbub3->num_vmid = res_cap_dcn301.num_vmid;
853 
854 	return &hubbub3->base;
855 }
856 
857 static struct timing_generator *dcn301_timing_generator_create(
858 	struct dc_context *ctx, uint32_t instance)
859 {
860 	struct optc *tgn10 =
861 		kzalloc(sizeof(struct optc), GFP_KERNEL);
862 
863 	if (!tgn10)
864 		return NULL;
865 
866 	tgn10->base.inst = instance;
867 	tgn10->base.ctx = ctx;
868 
869 	tgn10->tg_regs = &optc_regs[instance];
870 	tgn10->tg_shift = &optc_shift;
871 	tgn10->tg_mask = &optc_mask;
872 
873 	dcn30_timing_generator_init(tgn10);
874 
875 	return &tgn10->base;
876 }
877 
878 static const struct encoder_feature_support link_enc_feature = {
879 		.max_hdmi_deep_color = COLOR_DEPTH_121212,
880 		.max_hdmi_pixel_clock = 600000,
881 		.hdmi_ycbcr420_supported = true,
882 		.dp_ycbcr420_supported = true,
883 		.fec_supported = true,
884 		.flags.bits.IS_HBR2_CAPABLE = true,
885 		.flags.bits.IS_HBR3_CAPABLE = true,
886 		.flags.bits.IS_TPS3_CAPABLE = true,
887 		.flags.bits.IS_TPS4_CAPABLE = true
888 };
889 
890 static struct link_encoder *dcn301_link_encoder_create(
891 	const struct encoder_init_data *enc_init_data)
892 {
893 	struct dcn20_link_encoder *enc20 =
894 		kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
895 
896 	if (!enc20)
897 		return NULL;
898 
899 	dcn301_link_encoder_construct(enc20,
900 			enc_init_data,
901 			&link_enc_feature,
902 			&link_enc_regs[enc_init_data->transmitter],
903 			&link_enc_aux_regs[enc_init_data->channel - 1],
904 			&link_enc_hpd_regs[enc_init_data->hpd_source],
905 			&le_shift,
906 			&le_mask);
907 
908 	return &enc20->enc10.base;
909 }
910 
911 static struct panel_cntl *dcn301_panel_cntl_create(const struct panel_cntl_init_data *init_data)
912 {
913 	struct dcn301_panel_cntl *panel_cntl =
914 		kzalloc(sizeof(struct dcn301_panel_cntl), GFP_KERNEL);
915 
916 	if (!panel_cntl)
917 		return NULL;
918 
919 	dcn301_panel_cntl_construct(panel_cntl,
920 			init_data,
921 			&panel_cntl_regs[init_data->inst],
922 			&panel_cntl_shift,
923 			&panel_cntl_mask);
924 
925 	return &panel_cntl->base;
926 }
927 
928 
929 #define CTX ctx
930 
931 #define REG(reg_name) \
932 	(DCN_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
933 
934 static uint32_t read_pipe_fuses(struct dc_context *ctx)
935 {
936 	uint32_t value = REG_READ(CC_DC_PIPE_DIS);
937 	/* RV1 support max 4 pipes */
938 	value = value & 0xf;
939 	return value;
940 }
941 
942 
943 static void read_dce_straps(
944 	struct dc_context *ctx,
945 	struct resource_straps *straps)
946 {
947 	generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
948 		FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
949 
950 }
951 
952 static struct audio *dcn301_create_audio(
953 		struct dc_context *ctx, unsigned int inst)
954 {
955 	return dce_audio_create(ctx, inst,
956 			&audio_regs[inst], &audio_shift, &audio_mask);
957 }
958 
959 static struct vpg *dcn301_vpg_create(
960 	struct dc_context *ctx,
961 	uint32_t inst)
962 {
963 	struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL);
964 
965 	if (!vpg3)
966 		return NULL;
967 
968 	vpg3_construct(vpg3, ctx, inst,
969 			&vpg_regs[inst],
970 			&vpg_shift,
971 			&vpg_mask);
972 
973 	return &vpg3->base;
974 }
975 
976 static struct afmt *dcn301_afmt_create(
977 	struct dc_context *ctx,
978 	uint32_t inst)
979 {
980 	struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL);
981 
982 	if (!afmt3)
983 		return NULL;
984 
985 	afmt3_construct(afmt3, ctx, inst,
986 			&afmt_regs[inst],
987 			&afmt_shift,
988 			&afmt_mask);
989 
990 	return &afmt3->base;
991 }
992 
993 static struct stream_encoder *dcn301_stream_encoder_create(enum engine_id eng_id,
994 							   struct dc_context *ctx)
995 {
996 	struct dcn10_stream_encoder *enc1;
997 	struct vpg *vpg;
998 	struct afmt *afmt;
999 	int vpg_inst;
1000 	int afmt_inst;
1001 
1002 	/* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
1003 	if (eng_id <= ENGINE_ID_DIGF) {
1004 		vpg_inst = eng_id;
1005 		afmt_inst = eng_id;
1006 	} else
1007 		return NULL;
1008 
1009 	enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1010 	vpg = dcn301_vpg_create(ctx, vpg_inst);
1011 	afmt = dcn301_afmt_create(ctx, afmt_inst);
1012 
1013 	if (!enc1 || !vpg || !afmt) {
1014 		kfree(enc1);
1015 		kfree(vpg);
1016 		kfree(afmt);
1017 		return NULL;
1018 	}
1019 
1020 	dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
1021 					eng_id, vpg, afmt,
1022 					&stream_enc_regs[eng_id],
1023 					&se_shift, &se_mask);
1024 
1025 	return &enc1->base;
1026 }
1027 
1028 static struct dce_hwseq *dcn301_hwseq_create(struct dc_context *ctx)
1029 {
1030 	struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1031 
1032 	if (hws) {
1033 		hws->ctx = ctx;
1034 		hws->regs = &hwseq_reg;
1035 		hws->shifts = &hwseq_shift;
1036 		hws->masks = &hwseq_mask;
1037 	}
1038 	return hws;
1039 }
1040 static const struct resource_create_funcs res_create_funcs = {
1041 	.read_dce_straps = read_dce_straps,
1042 	.create_audio = dcn301_create_audio,
1043 	.create_stream_encoder = dcn301_stream_encoder_create,
1044 	.create_hwseq = dcn301_hwseq_create,
1045 };
1046 
1047 static const struct resource_create_funcs res_create_maximus_funcs = {
1048 	.read_dce_straps = NULL,
1049 	.create_audio = NULL,
1050 	.create_stream_encoder = NULL,
1051 	.create_hwseq = dcn301_hwseq_create,
1052 };
1053 
1054 static void dcn301_destruct(struct dcn301_resource_pool *pool)
1055 {
1056 	unsigned int i;
1057 
1058 	for (i = 0; i < pool->base.stream_enc_count; i++) {
1059 		if (pool->base.stream_enc[i] != NULL) {
1060 			if (pool->base.stream_enc[i]->vpg != NULL) {
1061 				kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
1062 				pool->base.stream_enc[i]->vpg = NULL;
1063 			}
1064 			if (pool->base.stream_enc[i]->afmt != NULL) {
1065 				kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));
1066 				pool->base.stream_enc[i]->afmt = NULL;
1067 			}
1068 			kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1069 			pool->base.stream_enc[i] = NULL;
1070 		}
1071 	}
1072 
1073 	for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1074 		if (pool->base.dscs[i] != NULL)
1075 			dcn20_dsc_destroy(&pool->base.dscs[i]);
1076 	}
1077 
1078 	if (pool->base.mpc != NULL) {
1079 		kfree(TO_DCN20_MPC(pool->base.mpc));
1080 		pool->base.mpc = NULL;
1081 	}
1082 	if (pool->base.hubbub != NULL) {
1083 		kfree(pool->base.hubbub);
1084 		pool->base.hubbub = NULL;
1085 	}
1086 	for (i = 0; i < pool->base.pipe_count; i++) {
1087 		if (pool->base.dpps[i] != NULL)
1088 			dcn301_dpp_destroy(&pool->base.dpps[i]);
1089 
1090 		if (pool->base.ipps[i] != NULL)
1091 			pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1092 
1093 		if (pool->base.hubps[i] != NULL) {
1094 			kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1095 			pool->base.hubps[i] = NULL;
1096 		}
1097 
1098 		if (pool->base.irqs != NULL) {
1099 			dal_irq_service_destroy(&pool->base.irqs);
1100 		}
1101 	}
1102 
1103 	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1104 		if (pool->base.engines[i] != NULL)
1105 			dce110_engine_destroy(&pool->base.engines[i]);
1106 		if (pool->base.hw_i2cs[i] != NULL) {
1107 			kfree(pool->base.hw_i2cs[i]);
1108 			pool->base.hw_i2cs[i] = NULL;
1109 		}
1110 		if (pool->base.sw_i2cs[i] != NULL) {
1111 			kfree(pool->base.sw_i2cs[i]);
1112 			pool->base.sw_i2cs[i] = NULL;
1113 		}
1114 	}
1115 
1116 	for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1117 		if (pool->base.opps[i] != NULL)
1118 			pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1119 	}
1120 
1121 	for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1122 		if (pool->base.timing_generators[i] != NULL)	{
1123 			kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1124 			pool->base.timing_generators[i] = NULL;
1125 		}
1126 	}
1127 
1128 	for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1129 		if (pool->base.dwbc[i] != NULL) {
1130 			kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
1131 			pool->base.dwbc[i] = NULL;
1132 		}
1133 		if (pool->base.mcif_wb[i] != NULL) {
1134 			kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));
1135 			pool->base.mcif_wb[i] = NULL;
1136 		}
1137 	}
1138 
1139 	for (i = 0; i < pool->base.audio_count; i++) {
1140 		if (pool->base.audios[i])
1141 			dce_aud_destroy(&pool->base.audios[i]);
1142 	}
1143 
1144 	for (i = 0; i < pool->base.clk_src_count; i++) {
1145 		if (pool->base.clock_sources[i] != NULL) {
1146 			dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1147 			pool->base.clock_sources[i] = NULL;
1148 		}
1149 	}
1150 
1151 	for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
1152 		if (pool->base.mpc_lut[i] != NULL) {
1153 			dc_3dlut_func_release(pool->base.mpc_lut[i]);
1154 			pool->base.mpc_lut[i] = NULL;
1155 		}
1156 		if (pool->base.mpc_shaper[i] != NULL) {
1157 			dc_transfer_func_release(pool->base.mpc_shaper[i]);
1158 			pool->base.mpc_shaper[i] = NULL;
1159 		}
1160 	}
1161 
1162 	if (pool->base.dp_clock_source != NULL) {
1163 		dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1164 		pool->base.dp_clock_source = NULL;
1165 	}
1166 
1167 	for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1168 		if (pool->base.multiple_abms[i] != NULL)
1169 			dce_abm_destroy(&pool->base.multiple_abms[i]);
1170 	}
1171 
1172 	if (pool->base.dccg != NULL)
1173 		dcn_dccg_destroy(&pool->base.dccg);
1174 }
1175 
1176 static struct hubp *dcn301_hubp_create(struct dc_context *ctx, uint32_t inst)
1177 {
1178 	struct dcn20_hubp *hubp2 =
1179 		kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
1180 
1181 	if (!hubp2)
1182 		return NULL;
1183 
1184 	if (hubp3_construct(hubp2, ctx, inst,
1185 			&hubp_regs[inst], &hubp_shift, &hubp_mask))
1186 		return &hubp2->base;
1187 
1188 	BREAK_TO_DEBUGGER();
1189 	kfree(hubp2);
1190 	return NULL;
1191 }
1192 
1193 static bool dcn301_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
1194 {
1195 	int i;
1196 	uint32_t pipe_count = pool->res_cap->num_dwb;
1197 
1198 	for (i = 0; i < pipe_count; i++) {
1199 		struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc),
1200 						    GFP_KERNEL);
1201 
1202 		if (!dwbc30) {
1203 			dm_error("DC: failed to create dwbc30!\n");
1204 			return false;
1205 		}
1206 
1207 		dcn30_dwbc_construct(dwbc30, ctx,
1208 				&dwbc30_regs[i],
1209 				&dwbc30_shift,
1210 				&dwbc30_mask,
1211 				i);
1212 
1213 		pool->dwbc[i] = &dwbc30->base;
1214 	}
1215 	return true;
1216 }
1217 
1218 static bool dcn301_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
1219 {
1220 	int i;
1221 	uint32_t pipe_count = pool->res_cap->num_dwb;
1222 
1223 	for (i = 0; i < pipe_count; i++) {
1224 		struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub),
1225 						    GFP_KERNEL);
1226 
1227 		if (!mcif_wb30) {
1228 			dm_error("DC: failed to create mcif_wb30!\n");
1229 			return false;
1230 		}
1231 
1232 		dcn30_mmhubbub_construct(mcif_wb30, ctx,
1233 				&mcif_wb30_regs[i],
1234 				&mcif_wb30_shift,
1235 				&mcif_wb30_mask,
1236 				i);
1237 
1238 		pool->mcif_wb[i] = &mcif_wb30->base;
1239 	}
1240 	return true;
1241 }
1242 
1243 static struct display_stream_compressor *dcn301_dsc_create(
1244 	struct dc_context *ctx, uint32_t inst)
1245 {
1246 	struct dcn20_dsc *dsc =
1247 		kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1248 
1249 	if (!dsc) {
1250 		BREAK_TO_DEBUGGER();
1251 		return NULL;
1252 	}
1253 
1254 	dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1255 	return &dsc->base;
1256 }
1257 
1258 
1259 static void dcn301_destroy_resource_pool(struct resource_pool **pool)
1260 {
1261 	struct dcn301_resource_pool *dcn301_pool = TO_DCN301_RES_POOL(*pool);
1262 
1263 	dcn301_destruct(dcn301_pool);
1264 	kfree(dcn301_pool);
1265 	*pool = NULL;
1266 }
1267 
1268 static struct clock_source *dcn301_clock_source_create(
1269 		struct dc_context *ctx,
1270 		struct dc_bios *bios,
1271 		enum clock_source_id id,
1272 		const struct dce110_clk_src_regs *regs,
1273 		bool dp_clk_src)
1274 {
1275 	struct dce110_clk_src *clk_src =
1276 		kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1277 
1278 	if (!clk_src)
1279 		return NULL;
1280 
1281 	if (dcn301_clk_src_construct(clk_src, ctx, bios, id,
1282 			regs, &cs_shift, &cs_mask)) {
1283 		clk_src->base.dp_clk_src = dp_clk_src;
1284 		return &clk_src->base;
1285 	}
1286 
1287 	BREAK_TO_DEBUGGER();
1288 	return NULL;
1289 }
1290 
1291 static struct dc_cap_funcs cap_funcs = {
1292 	.get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1293 };
1294 
1295 
1296 static bool is_soc_bounding_box_valid(struct dc *dc)
1297 {
1298 	uint32_t hw_internal_rev = dc->ctx->asic_id.hw_internal_rev;
1299 
1300 	if (ASICREV_IS_VANGOGH(hw_internal_rev))
1301 		return true;
1302 
1303 	return false;
1304 }
1305 
1306 static bool init_soc_bounding_box(struct dc *dc,
1307 				  struct dcn301_resource_pool *pool)
1308 {
1309 	struct _vcs_dpi_soc_bounding_box_st *loaded_bb = &dcn3_01_soc;
1310 	struct _vcs_dpi_ip_params_st *loaded_ip = &dcn3_01_ip;
1311 
1312 	DC_LOGGER_INIT(dc->ctx->logger);
1313 
1314 	if (!is_soc_bounding_box_valid(dc)) {
1315 		DC_LOG_ERROR("%s: not valid soc bounding box\n", __func__);
1316 		return false;
1317 	}
1318 
1319 	loaded_ip->max_num_otg = pool->base.res_cap->num_timing_generator;
1320 	loaded_ip->max_num_dpp = pool->base.pipe_count;
1321 	DC_FP_START();
1322 	dcn20_patch_bounding_box(dc, loaded_bb);
1323 	DC_FP_END();
1324 
1325 	if (dc->ctx->dc_bios->funcs->get_soc_bb_info) {
1326 		struct bp_soc_bb_info bb_info = {0};
1327 
1328 		if (dc->ctx->dc_bios->funcs->get_soc_bb_info(dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) {
1329 			DC_FP_START();
1330 			dcn301_fpu_init_soc_bounding_box(bb_info);
1331 			DC_FP_END();
1332 		}
1333 	}
1334 
1335 	return true;
1336 }
1337 
1338 
1339 static void set_wm_ranges(
1340 		struct pp_smu_funcs *pp_smu,
1341 		struct _vcs_dpi_soc_bounding_box_st *loaded_bb)
1342 {
1343 	struct pp_smu_wm_range_sets ranges = {0};
1344 	int i;
1345 
1346 	ranges.num_reader_wm_sets = 0;
1347 
1348 	if (loaded_bb->num_states == 1) {
1349 		ranges.reader_wm_sets[0].wm_inst = 0;
1350 		ranges.reader_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
1351 		ranges.reader_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
1352 		ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
1353 		ranges.reader_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
1354 
1355 		ranges.num_reader_wm_sets = 1;
1356 	} else if (loaded_bb->num_states > 1) {
1357 		for (i = 0; i < 4 && i < loaded_bb->num_states; i++) {
1358 			ranges.reader_wm_sets[i].wm_inst = i;
1359 			ranges.reader_wm_sets[i].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
1360 			ranges.reader_wm_sets[i].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
1361 			DC_FP_START();
1362 			dcn301_fpu_set_wm_ranges(i, &ranges, loaded_bb);
1363 			DC_FP_END();
1364 			ranges.num_reader_wm_sets = i + 1;
1365 		}
1366 
1367 		ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
1368 		ranges.reader_wm_sets[ranges.num_reader_wm_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
1369 	}
1370 
1371 	ranges.num_writer_wm_sets = 1;
1372 
1373 	ranges.writer_wm_sets[0].wm_inst = 0;
1374 	ranges.writer_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
1375 	ranges.writer_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
1376 	ranges.writer_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
1377 	ranges.writer_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
1378 
1379 	/* Notify PP Lib/SMU which Watermarks to use for which clock ranges */
1380 	pp_smu->nv_funcs.set_wm_ranges(&pp_smu->nv_funcs.pp_smu, &ranges);
1381 }
1382 
1383 static void dcn301_calculate_wm_and_dlg(
1384 		struct dc *dc, struct dc_state *context,
1385 		display_e2e_pipe_params_st *pipes,
1386 		int pipe_cnt,
1387 		int vlevel)
1388 {
1389 	DC_FP_START();
1390 	dcn301_calculate_wm_and_dlg_fp(dc, context, pipes, pipe_cnt, vlevel);
1391 	DC_FP_END();
1392 }
1393 
1394 static struct resource_funcs dcn301_res_pool_funcs = {
1395 	.destroy = dcn301_destroy_resource_pool,
1396 	.link_enc_create = dcn301_link_encoder_create,
1397 	.panel_cntl_create = dcn301_panel_cntl_create,
1398 	.validate_bandwidth = dcn30_validate_bandwidth,
1399 	.calculate_wm_and_dlg = dcn301_calculate_wm_and_dlg,
1400 	.update_soc_for_wm_a = dcn30_update_soc_for_wm_a,
1401 	.populate_dml_pipes = dcn30_populate_dml_pipes_from_context,
1402 	.acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
1403 	.add_stream_to_ctx = dcn30_add_stream_to_ctx,
1404 	.add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
1405 	.remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1406 	.populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
1407 	.set_mcif_arb_params = dcn30_set_mcif_arb_params,
1408 	.find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1409 	.acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
1410 	.release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
1411 	.update_bw_bounding_box = dcn301_update_bw_bounding_box
1412 };
1413 
1414 static bool dcn301_resource_construct(
1415 	uint8_t num_virtual_links,
1416 	struct dc *dc,
1417 	struct dcn301_resource_pool *pool)
1418 {
1419 	int i, j;
1420 	struct dc_context *ctx = dc->ctx;
1421 	struct irq_service_init_data init_data;
1422 	uint32_t pipe_fuses = read_pipe_fuses(ctx);
1423 	uint32_t num_pipes = 0;
1424 
1425 	DC_LOGGER_INIT(dc->ctx->logger);
1426 
1427 	ctx->dc_bios->regs = &bios_regs;
1428 
1429 	pool->base.res_cap = &res_cap_dcn301;
1430 
1431 	pool->base.funcs = &dcn301_res_pool_funcs;
1432 
1433 	/*************************************************
1434 	 *  Resource + asic cap harcoding                *
1435 	 *************************************************/
1436 	pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1437 	pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1438 	pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;
1439 	dc->caps.max_downscale_ratio = 600;
1440 	dc->caps.i2c_speed_in_khz = 100;
1441 	dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a enabled by default*/
1442 	dc->caps.max_cursor_size = 256;
1443 	dc->caps.min_horizontal_blanking_period = 80;
1444 	dc->caps.dmdata_alloc_size = 2048;
1445 	dc->caps.max_slave_planes = 1;
1446 	dc->caps.max_slave_yuv_planes = 1;
1447 	dc->caps.max_slave_rgb_planes = 1;
1448 	dc->caps.is_apu = true;
1449 	dc->caps.post_blend_color_processing = true;
1450 	dc->caps.force_dp_tps4_for_cp2520 = true;
1451 	dc->caps.extended_aux_timeout_support = true;
1452 	dc->caps.dmcub_support = true;
1453 
1454 	/* Color pipeline capabilities */
1455 	dc->caps.color.dpp.dcn_arch = 1;
1456 	dc->caps.color.dpp.input_lut_shared = 0;
1457 	dc->caps.color.dpp.icsc = 1;
1458 	dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
1459 	dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1460 	dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1461 	dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
1462 	dc->caps.color.dpp.dgam_rom_caps.pq = 1;
1463 	dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
1464 	dc->caps.color.dpp.post_csc = 1;
1465 	dc->caps.color.dpp.gamma_corr = 1;
1466 	dc->caps.color.dpp.dgam_rom_for_yuv = 0;
1467 
1468 	dc->caps.color.dpp.hw_3d_lut = 1;
1469 	dc->caps.color.dpp.ogam_ram = 1;
1470 	// no OGAM ROM on DCN301
1471 	dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
1472 	dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
1473 	dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
1474 	dc->caps.color.dpp.ogam_rom_caps.pq = 0;
1475 	dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
1476 	dc->caps.color.dpp.ocsc = 0;
1477 
1478 	dc->caps.color.mpc.gamut_remap = 1;
1479 	dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2
1480 	dc->caps.color.mpc.ogam_ram = 1;
1481 	dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
1482 	dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
1483 	dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
1484 	dc->caps.color.mpc.ogam_rom_caps.pq = 0;
1485 	dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1486 	dc->caps.color.mpc.ocsc = 1;
1487 
1488 	/* read VBIOS LTTPR caps */
1489 	if (ctx->dc_bios->funcs->get_lttpr_caps) {
1490 		enum bp_result bp_query_result;
1491 		uint8_t is_vbios_lttpr_enable = 0;
1492 
1493 		bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
1494 		dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
1495 	}
1496 
1497 	if (ctx->dc_bios->funcs->get_lttpr_interop) {
1498 		enum bp_result bp_query_result;
1499 		uint8_t is_vbios_interop_enabled = 0;
1500 
1501 		bp_query_result = ctx->dc_bios->funcs->get_lttpr_interop(ctx->dc_bios, &is_vbios_interop_enabled);
1502 		dc->caps.vbios_lttpr_aware = (bp_query_result == BP_RESULT_OK) && !!is_vbios_interop_enabled;
1503 	}
1504 
1505 	if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1506 		dc->debug = debug_defaults_drv;
1507 	else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) {
1508 		dc->debug = debug_defaults_diags;
1509 	} else
1510 		dc->debug = debug_defaults_diags;
1511 	// Init the vm_helper
1512 	if (dc->vm_helper)
1513 		vm_helper_init(dc->vm_helper, 16);
1514 
1515 	/*************************************************
1516 	 *  Create resources                             *
1517 	 *************************************************/
1518 
1519 	/* Clock Sources for Pixel Clock*/
1520 	pool->base.clock_sources[DCN301_CLK_SRC_PLL0] =
1521 			dcn301_clock_source_create(ctx, ctx->dc_bios,
1522 				CLOCK_SOURCE_COMBO_PHY_PLL0,
1523 				&clk_src_regs[0], false);
1524 	pool->base.clock_sources[DCN301_CLK_SRC_PLL1] =
1525 			dcn301_clock_source_create(ctx, ctx->dc_bios,
1526 				CLOCK_SOURCE_COMBO_PHY_PLL1,
1527 				&clk_src_regs[1], false);
1528 	pool->base.clock_sources[DCN301_CLK_SRC_PLL2] =
1529 			dcn301_clock_source_create(ctx, ctx->dc_bios,
1530 				CLOCK_SOURCE_COMBO_PHY_PLL2,
1531 				&clk_src_regs[2], false);
1532 	pool->base.clock_sources[DCN301_CLK_SRC_PLL3] =
1533 			dcn301_clock_source_create(ctx, ctx->dc_bios,
1534 				CLOCK_SOURCE_COMBO_PHY_PLL3,
1535 				&clk_src_regs[3], false);
1536 
1537 	pool->base.clk_src_count = DCN301_CLK_SRC_TOTAL;
1538 
1539 	/* todo: not reuse phy_pll registers */
1540 	pool->base.dp_clock_source =
1541 			dcn301_clock_source_create(ctx, ctx->dc_bios,
1542 				CLOCK_SOURCE_ID_DP_DTO,
1543 				&clk_src_regs[0], true);
1544 
1545 	for (i = 0; i < pool->base.clk_src_count; i++) {
1546 		if (pool->base.clock_sources[i] == NULL) {
1547 			dm_error("DC: failed to create clock sources!\n");
1548 			BREAK_TO_DEBUGGER();
1549 			goto create_fail;
1550 		}
1551 	}
1552 
1553 	/* DCCG */
1554 	pool->base.dccg = dccg301_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
1555 	if (pool->base.dccg == NULL) {
1556 		dm_error("DC: failed to create dccg!\n");
1557 		BREAK_TO_DEBUGGER();
1558 		goto create_fail;
1559 	}
1560 
1561 	init_soc_bounding_box(dc, pool);
1562 
1563 	if (!dc->debug.disable_pplib_wm_range && pool->base.pp_smu->nv_funcs.set_wm_ranges)
1564 		set_wm_ranges(pool->base.pp_smu, &dcn3_01_soc);
1565 
1566 	num_pipes = dcn3_01_ip.max_num_dpp;
1567 
1568 	for (i = 0; i < dcn3_01_ip.max_num_dpp; i++)
1569 		if (pipe_fuses & 1 << i)
1570 			num_pipes--;
1571 	dcn3_01_ip.max_num_dpp = num_pipes;
1572 	dcn3_01_ip.max_num_otg = num_pipes;
1573 
1574 
1575 	dml_init_instance(&dc->dml, &dcn3_01_soc, &dcn3_01_ip, DML_PROJECT_DCN30);
1576 
1577 	/* IRQ */
1578 	init_data.ctx = dc->ctx;
1579 	pool->base.irqs = dal_irq_service_dcn30_create(&init_data);
1580 	if (!pool->base.irqs)
1581 		goto create_fail;
1582 
1583 	/* HUBBUB */
1584 	pool->base.hubbub = dcn301_hubbub_create(ctx);
1585 	if (pool->base.hubbub == NULL) {
1586 		BREAK_TO_DEBUGGER();
1587 		dm_error("DC: failed to create hubbub!\n");
1588 		goto create_fail;
1589 	}
1590 
1591 	j = 0;
1592 	/* HUBPs, DPPs, OPPs and TGs */
1593 	for (i = 0; i < pool->base.pipe_count; i++) {
1594 
1595 		/* if pipe is disabled, skip instance of HW pipe,
1596 		 * i.e, skip ASIC register instance
1597 		 */
1598 		if ((pipe_fuses & (1 << i)) != 0) {
1599 			DC_LOG_DEBUG("%s: fusing pipe %d\n", __func__, i);
1600 			continue;
1601 		}
1602 
1603 		pool->base.hubps[j] = dcn301_hubp_create(ctx, i);
1604 		if (pool->base.hubps[j] == NULL) {
1605 			BREAK_TO_DEBUGGER();
1606 			dm_error(
1607 				"DC: failed to create hubps!\n");
1608 			goto create_fail;
1609 		}
1610 
1611 		pool->base.dpps[j] = dcn301_dpp_create(ctx, i);
1612 		if (pool->base.dpps[j] == NULL) {
1613 			BREAK_TO_DEBUGGER();
1614 			dm_error(
1615 				"DC: failed to create dpps!\n");
1616 			goto create_fail;
1617 		}
1618 
1619 		pool->base.opps[j] = dcn301_opp_create(ctx, i);
1620 		if (pool->base.opps[j] == NULL) {
1621 			BREAK_TO_DEBUGGER();
1622 			dm_error(
1623 				"DC: failed to create output pixel processor!\n");
1624 			goto create_fail;
1625 		}
1626 
1627 		pool->base.timing_generators[j] = dcn301_timing_generator_create(ctx, i);
1628 		if (pool->base.timing_generators[j] == NULL) {
1629 			BREAK_TO_DEBUGGER();
1630 			dm_error("DC: failed to create tg!\n");
1631 			goto create_fail;
1632 		}
1633 		j++;
1634 	}
1635 	pool->base.timing_generator_count = j;
1636 	pool->base.pipe_count = j;
1637 	pool->base.mpcc_count = j;
1638 
1639 	/* ABM (or ABMs for NV2x) */
1640 	/* TODO: */
1641 	for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1642 		pool->base.multiple_abms[i] = dmub_abm_create(ctx,
1643 				&abm_regs[i],
1644 				&abm_shift,
1645 				&abm_mask);
1646 		if (pool->base.multiple_abms[i] == NULL) {
1647 			dm_error("DC: failed to create abm for pipe %d!\n", i);
1648 			BREAK_TO_DEBUGGER();
1649 			goto create_fail;
1650 		}
1651 	}
1652 
1653 	/* MPC and DSC */
1654 	pool->base.mpc = dcn301_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);
1655 	if (pool->base.mpc == NULL) {
1656 		BREAK_TO_DEBUGGER();
1657 		dm_error("DC: failed to create mpc!\n");
1658 		goto create_fail;
1659 	}
1660 
1661 	for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1662 		pool->base.dscs[i] = dcn301_dsc_create(ctx, i);
1663 		if (pool->base.dscs[i] == NULL) {
1664 			BREAK_TO_DEBUGGER();
1665 			dm_error("DC: failed to create display stream compressor %d!\n", i);
1666 			goto create_fail;
1667 		}
1668 	}
1669 
1670 	/* DWB and MMHUBBUB */
1671 	if (!dcn301_dwbc_create(ctx, &pool->base)) {
1672 		BREAK_TO_DEBUGGER();
1673 		dm_error("DC: failed to create dwbc!\n");
1674 		goto create_fail;
1675 	}
1676 
1677 	if (!dcn301_mmhubbub_create(ctx, &pool->base)) {
1678 		BREAK_TO_DEBUGGER();
1679 		dm_error("DC: failed to create mcif_wb!\n");
1680 		goto create_fail;
1681 	}
1682 
1683 	/* AUX and I2C */
1684 	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1685 		pool->base.engines[i] = dcn301_aux_engine_create(ctx, i);
1686 		if (pool->base.engines[i] == NULL) {
1687 			BREAK_TO_DEBUGGER();
1688 			dm_error(
1689 				"DC:failed to create aux engine!!\n");
1690 			goto create_fail;
1691 		}
1692 		pool->base.hw_i2cs[i] = dcn301_i2c_hw_create(ctx, i);
1693 		if (pool->base.hw_i2cs[i] == NULL) {
1694 			BREAK_TO_DEBUGGER();
1695 			dm_error(
1696 				"DC:failed to create hw i2c!!\n");
1697 			goto create_fail;
1698 		}
1699 		pool->base.sw_i2cs[i] = NULL;
1700 	}
1701 
1702 	/* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */
1703 	if (!resource_construct(num_virtual_links, dc, &pool->base,
1704 			(!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
1705 			&res_create_funcs : &res_create_maximus_funcs)))
1706 			goto create_fail;
1707 
1708 	/* HW Sequencer and Plane caps */
1709 	dcn301_hw_sequencer_construct(dc);
1710 
1711 	dc->caps.max_planes =  pool->base.pipe_count;
1712 
1713 	for (i = 0; i < dc->caps.max_planes; ++i)
1714 		dc->caps.planes[i] = plane_cap;
1715 
1716 	dc->cap_funcs = cap_funcs;
1717 
1718 	return true;
1719 
1720 create_fail:
1721 
1722 	dcn301_destruct(pool);
1723 
1724 	return false;
1725 }
1726 
1727 struct resource_pool *dcn301_create_resource_pool(
1728 		const struct dc_init_data *init_data,
1729 		struct dc *dc)
1730 {
1731 	struct dcn301_resource_pool *pool =
1732 		kzalloc(sizeof(struct dcn301_resource_pool), GFP_KERNEL);
1733 
1734 	if (!pool)
1735 		return NULL;
1736 
1737 	if (dcn301_resource_construct(init_data->num_virtual_links, dc, pool))
1738 		return &pool->base;
1739 
1740 	BREAK_TO_DEBUGGER();
1741 	kfree(pool);
1742 	return NULL;
1743 }
1744