1 /* 2 * Copyright 2019-2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 27 #include "dm_services.h" 28 #include "dc.h" 29 30 #include "dcn301_init.h" 31 32 #include "resource.h" 33 #include "include/irq_service_interface.h" 34 #include "dcn30/dcn30_resource.h" 35 #include "dcn301_resource.h" 36 37 #include "dcn20/dcn20_resource.h" 38 39 #include "dcn10/dcn10_ipp.h" 40 #include "dcn301/dcn301_hubbub.h" 41 #include "dcn30/dcn30_mpc.h" 42 #include "dcn30/dcn30_hubp.h" 43 #include "irq/dcn30/irq_service_dcn30.h" 44 #include "dcn30/dcn30_dpp.h" 45 #include "dcn30/dcn30_optc.h" 46 #include "dcn20/dcn20_hwseq.h" 47 #include "dcn30/dcn30_hwseq.h" 48 #include "dce110/dce110_hw_sequencer.h" 49 #include "dcn30/dcn30_opp.h" 50 #include "dcn20/dcn20_dsc.h" 51 #include "dcn30/dcn30_vpg.h" 52 #include "dcn30/dcn30_afmt.h" 53 #include "dce/dce_clock_source.h" 54 #include "dce/dce_audio.h" 55 #include "dce/dce_hwseq.h" 56 #include "clk_mgr.h" 57 #include "virtual/virtual_stream_encoder.h" 58 #include "dce110/dce110_resource.h" 59 #include "dml/display_mode_vba.h" 60 #include "dcn301/dcn301_dccg.h" 61 #include "dcn10/dcn10_resource.h" 62 #include "dcn30/dcn30_dio_stream_encoder.h" 63 #include "dcn301/dcn301_dio_link_encoder.h" 64 #include "dcn301_panel_cntl.h" 65 66 #include "vangogh_ip_offset.h" 67 68 #include "dcn30/dcn30_dwb.h" 69 #include "dcn30/dcn30_mmhubbub.h" 70 71 #include "dcn/dcn_3_0_1_offset.h" 72 #include "dcn/dcn_3_0_1_sh_mask.h" 73 74 #include "nbio/nbio_7_2_0_offset.h" 75 76 #include "dcn/dpcs_3_0_0_offset.h" 77 #include "dcn/dpcs_3_0_0_sh_mask.h" 78 79 #include "reg_helper.h" 80 #include "dce/dmub_abm.h" 81 #include "dce/dce_aux.h" 82 #include "dce/dce_i2c.h" 83 84 #include "dml/dcn30/display_mode_vba_30.h" 85 #include "dml/dcn301/dcn301_fpu.h" 86 #include "vm_helper.h" 87 #include "dcn20/dcn20_vmid.h" 88 #include "amdgpu_socbb.h" 89 90 #define TO_DCN301_RES_POOL(pool)\ 91 container_of(pool, struct dcn301_resource_pool, base) 92 93 #define DC_LOGGER_INIT(logger) 94 95 enum dcn301_clk_src_array_id { 96 DCN301_CLK_SRC_PLL0, 97 DCN301_CLK_SRC_PLL1, 98 DCN301_CLK_SRC_PLL2, 99 DCN301_CLK_SRC_PLL3, 100 DCN301_CLK_SRC_TOTAL 101 }; 102 103 /* begin ********************* 104 * macros to expend register list macro defined in HW object header file 105 */ 106 107 /* DCN */ 108 /* TODO awful hack. fixup dcn20_dwb.h */ 109 #undef BASE_INNER 110 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg 111 112 #define BASE(seg) BASE_INNER(seg) 113 114 #define SR(reg_name)\ 115 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ 116 mm ## reg_name 117 118 #define SRI(reg_name, block, id)\ 119 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 120 mm ## block ## id ## _ ## reg_name 121 122 #define SRI2(reg_name, block, id)\ 123 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ 124 mm ## reg_name 125 126 #define SRIR(var_name, reg_name, block, id)\ 127 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 128 mm ## block ## id ## _ ## reg_name 129 130 #define SRII(reg_name, block, id)\ 131 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 132 mm ## block ## id ## _ ## reg_name 133 134 #define SRII2(reg_name_pre, reg_name_post, id)\ 135 .reg_name_pre ## _ ## reg_name_post[id] = BASE(mm ## reg_name_pre \ 136 ## id ## _ ## reg_name_post ## _BASE_IDX) + \ 137 mm ## reg_name_pre ## id ## _ ## reg_name_post 138 139 #define SRII_MPC_RMU(reg_name, block, id)\ 140 .RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 141 mm ## block ## id ## _ ## reg_name 142 143 #define SRII_DWB(reg_name, temp_name, block, id)\ 144 .reg_name[id] = BASE(mm ## block ## id ## _ ## temp_name ## _BASE_IDX) + \ 145 mm ## block ## id ## _ ## temp_name 146 147 #define DCCG_SRII(reg_name, block, id)\ 148 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 149 mm ## block ## id ## _ ## reg_name 150 151 #define VUPDATE_SRII(reg_name, block, id)\ 152 .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \ 153 mm ## reg_name ## _ ## block ## id 154 155 /* NBIO */ 156 #define NBIO_BASE_INNER(seg) \ 157 NBIO_BASE__INST0_SEG ## seg 158 159 #define NBIO_BASE(seg) \ 160 NBIO_BASE_INNER(seg) 161 162 #define NBIO_SR(reg_name)\ 163 .reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \ 164 regBIF_BX0_ ## reg_name 165 166 /* MMHUB */ 167 #define MMHUB_BASE_INNER(seg) \ 168 MMHUB_BASE__INST0_SEG ## seg 169 170 #define MMHUB_BASE(seg) \ 171 MMHUB_BASE_INNER(seg) 172 173 #define MMHUB_SR(reg_name)\ 174 .reg_name = MMHUB_BASE(regMM ## reg_name ## _BASE_IDX) + \ 175 regMM ## reg_name 176 177 /* CLOCK */ 178 #define CLK_BASE_INNER(seg) \ 179 CLK_BASE__INST0_SEG ## seg 180 181 #define CLK_BASE(seg) \ 182 CLK_BASE_INNER(seg) 183 184 #define CLK_SRI(reg_name, block, inst)\ 185 .reg_name = CLK_BASE(mm ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \ 186 mm ## block ## _ ## inst ## _ ## reg_name 187 188 static const struct bios_registers bios_regs = { 189 NBIO_SR(BIOS_SCRATCH_3), 190 NBIO_SR(BIOS_SCRATCH_6) 191 }; 192 193 #define clk_src_regs(index, pllid)\ 194 [index] = {\ 195 CS_COMMON_REG_LIST_DCN3_01(index, pllid),\ 196 } 197 198 static const struct dce110_clk_src_regs clk_src_regs[] = { 199 clk_src_regs(0, A), 200 clk_src_regs(1, B), 201 clk_src_regs(2, C), 202 clk_src_regs(3, D) 203 }; 204 205 static const struct dce110_clk_src_shift cs_shift = { 206 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 207 }; 208 209 static const struct dce110_clk_src_mask cs_mask = { 210 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 211 }; 212 213 #define abm_regs(id)\ 214 [id] = {\ 215 ABM_DCN301_REG_LIST(id)\ 216 } 217 218 static const struct dce_abm_registers abm_regs[] = { 219 abm_regs(0), 220 abm_regs(1), 221 abm_regs(2), 222 abm_regs(3), 223 }; 224 225 static const struct dce_abm_shift abm_shift = { 226 ABM_MASK_SH_LIST_DCN30(__SHIFT) 227 }; 228 229 static const struct dce_abm_mask abm_mask = { 230 ABM_MASK_SH_LIST_DCN30(_MASK) 231 }; 232 233 #define audio_regs(id)\ 234 [id] = {\ 235 AUD_COMMON_REG_LIST(id)\ 236 } 237 238 static const struct dce_audio_registers audio_regs[] = { 239 audio_regs(0), 240 audio_regs(1), 241 audio_regs(2), 242 audio_regs(3), 243 audio_regs(4), 244 audio_regs(5), 245 audio_regs(6) 246 }; 247 248 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 249 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 250 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 251 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 252 253 static const struct dce_audio_shift audio_shift = { 254 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 255 }; 256 257 static const struct dce_audio_mask audio_mask = { 258 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 259 }; 260 261 #define vpg_regs(id)\ 262 [id] = {\ 263 VPG_DCN3_REG_LIST(id)\ 264 } 265 266 static const struct dcn30_vpg_registers vpg_regs[] = { 267 vpg_regs(0), 268 vpg_regs(1), 269 vpg_regs(2), 270 vpg_regs(3), 271 }; 272 273 static const struct dcn30_vpg_shift vpg_shift = { 274 DCN3_VPG_MASK_SH_LIST(__SHIFT) 275 }; 276 277 static const struct dcn30_vpg_mask vpg_mask = { 278 DCN3_VPG_MASK_SH_LIST(_MASK) 279 }; 280 281 #define afmt_regs(id)\ 282 [id] = {\ 283 AFMT_DCN3_REG_LIST(id)\ 284 } 285 286 static const struct dcn30_afmt_registers afmt_regs[] = { 287 afmt_regs(0), 288 afmt_regs(1), 289 afmt_regs(2), 290 afmt_regs(3), 291 }; 292 293 static const struct dcn30_afmt_shift afmt_shift = { 294 DCN3_AFMT_MASK_SH_LIST(__SHIFT) 295 }; 296 297 static const struct dcn30_afmt_mask afmt_mask = { 298 DCN3_AFMT_MASK_SH_LIST(_MASK) 299 }; 300 301 #define stream_enc_regs(id)\ 302 [id] = {\ 303 SE_DCN3_REG_LIST(id)\ 304 } 305 306 static const struct dcn10_stream_enc_registers stream_enc_regs[] = { 307 stream_enc_regs(0), 308 stream_enc_regs(1), 309 stream_enc_regs(2), 310 stream_enc_regs(3), 311 }; 312 313 static const struct dcn10_stream_encoder_shift se_shift = { 314 SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 315 }; 316 317 static const struct dcn10_stream_encoder_mask se_mask = { 318 SE_COMMON_MASK_SH_LIST_DCN30(_MASK) 319 }; 320 321 322 #define aux_regs(id)\ 323 [id] = {\ 324 DCN2_AUX_REG_LIST(id)\ 325 } 326 327 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { 328 aux_regs(0), 329 aux_regs(1), 330 aux_regs(2), 331 aux_regs(3), 332 }; 333 334 #define hpd_regs(id)\ 335 [id] = {\ 336 HPD_REG_LIST(id)\ 337 } 338 339 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { 340 hpd_regs(0), 341 hpd_regs(1), 342 hpd_regs(2), 343 hpd_regs(3), 344 }; 345 346 347 #define link_regs(id, phyid)\ 348 [id] = {\ 349 LE_DCN301_REG_LIST(id), \ 350 UNIPHY_DCN2_REG_LIST(phyid), \ 351 DPCS_DCN2_REG_LIST(id), \ 352 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \ 353 } 354 355 static const struct dce110_aux_registers_shift aux_shift = { 356 DCN_AUX_MASK_SH_LIST(__SHIFT) 357 }; 358 359 static const struct dce110_aux_registers_mask aux_mask = { 360 DCN_AUX_MASK_SH_LIST(_MASK) 361 }; 362 363 static const struct dcn10_link_enc_registers link_enc_regs[] = { 364 link_regs(0, A), 365 link_regs(1, B), 366 link_regs(2, C), 367 link_regs(3, D), 368 }; 369 370 static const struct dcn10_link_enc_shift le_shift = { 371 LINK_ENCODER_MASK_SH_LIST_DCN301(__SHIFT),\ 372 DPCS_DCN2_MASK_SH_LIST(__SHIFT) 373 }; 374 375 static const struct dcn10_link_enc_mask le_mask = { 376 LINK_ENCODER_MASK_SH_LIST_DCN301(_MASK),\ 377 DPCS_DCN2_MASK_SH_LIST(_MASK) 378 }; 379 380 #define panel_cntl_regs(id)\ 381 [id] = {\ 382 DCN301_PANEL_CNTL_REG_LIST(id),\ 383 } 384 385 static const struct dce_panel_cntl_registers panel_cntl_regs[] = { 386 panel_cntl_regs(0), 387 panel_cntl_regs(1), 388 }; 389 390 static const struct dcn301_panel_cntl_shift panel_cntl_shift = { 391 DCN301_PANEL_CNTL_MASK_SH_LIST(__SHIFT) 392 }; 393 394 static const struct dcn301_panel_cntl_mask panel_cntl_mask = { 395 DCN301_PANEL_CNTL_MASK_SH_LIST(_MASK) 396 }; 397 398 #define dpp_regs(id)\ 399 [id] = {\ 400 DPP_REG_LIST_DCN30(id),\ 401 } 402 403 static const struct dcn3_dpp_registers dpp_regs[] = { 404 dpp_regs(0), 405 dpp_regs(1), 406 dpp_regs(2), 407 dpp_regs(3), 408 }; 409 410 static const struct dcn3_dpp_shift tf_shift = { 411 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT) 412 }; 413 414 static const struct dcn3_dpp_mask tf_mask = { 415 DPP_REG_LIST_SH_MASK_DCN30(_MASK) 416 }; 417 418 #define opp_regs(id)\ 419 [id] = {\ 420 OPP_REG_LIST_DCN30(id),\ 421 } 422 423 static const struct dcn20_opp_registers opp_regs[] = { 424 opp_regs(0), 425 opp_regs(1), 426 opp_regs(2), 427 opp_regs(3), 428 }; 429 430 static const struct dcn20_opp_shift opp_shift = { 431 OPP_MASK_SH_LIST_DCN20(__SHIFT) 432 }; 433 434 static const struct dcn20_opp_mask opp_mask = { 435 OPP_MASK_SH_LIST_DCN20(_MASK) 436 }; 437 438 #define aux_engine_regs(id)\ 439 [id] = {\ 440 AUX_COMMON_REG_LIST0(id), \ 441 .AUXN_IMPCAL = 0, \ 442 .AUXP_IMPCAL = 0, \ 443 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \ 444 } 445 446 static const struct dce110_aux_registers aux_engine_regs[] = { 447 aux_engine_regs(0), 448 aux_engine_regs(1), 449 aux_engine_regs(2), 450 aux_engine_regs(3), 451 }; 452 453 #define dwbc_regs_dcn3(id)\ 454 [id] = {\ 455 DWBC_COMMON_REG_LIST_DCN30(id),\ 456 } 457 458 static const struct dcn30_dwbc_registers dwbc30_regs[] = { 459 dwbc_regs_dcn3(0), 460 }; 461 462 static const struct dcn30_dwbc_shift dwbc30_shift = { 463 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 464 }; 465 466 static const struct dcn30_dwbc_mask dwbc30_mask = { 467 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK) 468 }; 469 470 #define mcif_wb_regs_dcn3(id)\ 471 [id] = {\ 472 MCIF_WB_COMMON_REG_LIST_DCN30(id),\ 473 } 474 475 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = { 476 mcif_wb_regs_dcn3(0) 477 }; 478 479 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = { 480 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 481 }; 482 483 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { 484 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK) 485 }; 486 487 #define dsc_regsDCN20(id)\ 488 [id] = {\ 489 DSC_REG_LIST_DCN20(id)\ 490 } 491 492 static const struct dcn20_dsc_registers dsc_regs[] = { 493 dsc_regsDCN20(0), 494 dsc_regsDCN20(1), 495 dsc_regsDCN20(2), 496 }; 497 498 static const struct dcn20_dsc_shift dsc_shift = { 499 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) 500 }; 501 502 static const struct dcn20_dsc_mask dsc_mask = { 503 DSC_REG_LIST_SH_MASK_DCN20(_MASK) 504 }; 505 506 static const struct dcn30_mpc_registers mpc_regs = { 507 MPC_REG_LIST_DCN3_0(0), 508 MPC_REG_LIST_DCN3_0(1), 509 MPC_REG_LIST_DCN3_0(2), 510 MPC_REG_LIST_DCN3_0(3), 511 MPC_OUT_MUX_REG_LIST_DCN3_0(0), 512 MPC_OUT_MUX_REG_LIST_DCN3_0(1), 513 MPC_OUT_MUX_REG_LIST_DCN3_0(2), 514 MPC_OUT_MUX_REG_LIST_DCN3_0(3), 515 MPC_RMU_GLOBAL_REG_LIST_DCN3AG, 516 MPC_RMU_REG_LIST_DCN3AG(0), 517 MPC_RMU_REG_LIST_DCN3AG(1), 518 MPC_DWB_MUX_REG_LIST_DCN3_0(0), 519 }; 520 521 static const struct dcn30_mpc_shift mpc_shift = { 522 MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 523 }; 524 525 static const struct dcn30_mpc_mask mpc_mask = { 526 MPC_COMMON_MASK_SH_LIST_DCN30(_MASK) 527 }; 528 529 #define optc_regs(id)\ 530 [id] = {OPTC_COMMON_REG_LIST_DCN3_0(id)} 531 532 533 static const struct dcn_optc_registers optc_regs[] = { 534 optc_regs(0), 535 optc_regs(1), 536 optc_regs(2), 537 optc_regs(3), 538 }; 539 540 static const struct dcn_optc_shift optc_shift = { 541 OPTC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 542 }; 543 544 static const struct dcn_optc_mask optc_mask = { 545 OPTC_COMMON_MASK_SH_LIST_DCN30(_MASK) 546 }; 547 548 #define hubp_regs(id)\ 549 [id] = {\ 550 HUBP_REG_LIST_DCN30(id)\ 551 } 552 553 static const struct dcn_hubp2_registers hubp_regs[] = { 554 hubp_regs(0), 555 hubp_regs(1), 556 hubp_regs(2), 557 hubp_regs(3), 558 }; 559 560 static const struct dcn_hubp2_shift hubp_shift = { 561 HUBP_MASK_SH_LIST_DCN30(__SHIFT) 562 }; 563 564 static const struct dcn_hubp2_mask hubp_mask = { 565 HUBP_MASK_SH_LIST_DCN30(_MASK) 566 }; 567 568 static const struct dcn_hubbub_registers hubbub_reg = { 569 HUBBUB_REG_LIST_DCN301(0) 570 }; 571 572 static const struct dcn_hubbub_shift hubbub_shift = { 573 HUBBUB_MASK_SH_LIST_DCN301(__SHIFT) 574 }; 575 576 static const struct dcn_hubbub_mask hubbub_mask = { 577 HUBBUB_MASK_SH_LIST_DCN301(_MASK) 578 }; 579 580 static const struct dccg_registers dccg_regs = { 581 DCCG_REG_LIST_DCN301() 582 }; 583 584 static const struct dccg_shift dccg_shift = { 585 DCCG_MASK_SH_LIST_DCN301(__SHIFT) 586 }; 587 588 static const struct dccg_mask dccg_mask = { 589 DCCG_MASK_SH_LIST_DCN301(_MASK) 590 }; 591 592 static const struct dce_hwseq_registers hwseq_reg = { 593 HWSEQ_DCN301_REG_LIST() 594 }; 595 596 static const struct dce_hwseq_shift hwseq_shift = { 597 HWSEQ_DCN301_MASK_SH_LIST(__SHIFT) 598 }; 599 600 static const struct dce_hwseq_mask hwseq_mask = { 601 HWSEQ_DCN301_MASK_SH_LIST(_MASK) 602 }; 603 #define vmid_regs(id)\ 604 [id] = {\ 605 DCN20_VMID_REG_LIST(id)\ 606 } 607 608 static const struct dcn_vmid_registers vmid_regs[] = { 609 vmid_regs(0), 610 vmid_regs(1), 611 vmid_regs(2), 612 vmid_regs(3), 613 vmid_regs(4), 614 vmid_regs(5), 615 vmid_regs(6), 616 vmid_regs(7), 617 vmid_regs(8), 618 vmid_regs(9), 619 vmid_regs(10), 620 vmid_regs(11), 621 vmid_regs(12), 622 vmid_regs(13), 623 vmid_regs(14), 624 vmid_regs(15) 625 }; 626 627 static const struct dcn20_vmid_shift vmid_shifts = { 628 DCN20_VMID_MASK_SH_LIST(__SHIFT) 629 }; 630 631 static const struct dcn20_vmid_mask vmid_masks = { 632 DCN20_VMID_MASK_SH_LIST(_MASK) 633 }; 634 635 static const struct resource_caps res_cap_dcn301 = { 636 .num_timing_generator = 4, 637 .num_opp = 4, 638 .num_video_plane = 4, 639 .num_audio = 4, 640 .num_stream_encoder = 4, 641 .num_pll = 4, 642 .num_dwb = 1, 643 .num_ddc = 4, 644 .num_vmid = 16, 645 .num_mpc_3dlut = 2, 646 .num_dsc = 3, 647 }; 648 649 static const struct dc_plane_cap plane_cap = { 650 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 651 .blends_with_above = true, 652 .blends_with_below = true, 653 .per_pixel_alpha = true, 654 655 .pixel_format_support = { 656 .argb8888 = true, 657 .nv12 = true, 658 .fp16 = true, 659 .p010 = false, 660 .ayuv = false, 661 }, 662 663 .max_upscale_factor = { 664 .argb8888 = 16000, 665 .nv12 = 16000, 666 .fp16 = 16000 667 }, 668 669 /* 6:1 downscaling ratio: 1000/6 = 166.666 */ 670 .max_downscale_factor = { 671 .argb8888 = 167, 672 .nv12 = 167, 673 .fp16 = 167 674 }, 675 64, 676 64 677 }; 678 679 static const struct dc_debug_options debug_defaults_drv = { 680 .disable_dmcu = true, 681 .force_abm_enable = false, 682 .timing_trace = false, 683 .clock_trace = true, 684 .disable_dpp_power_gate = false, 685 .disable_hubp_power_gate = false, 686 .disable_clock_gate = true, 687 .disable_pplib_clock_request = true, 688 .disable_pplib_wm_range = true, 689 .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP, 690 .force_single_disp_pipe_split = false, 691 .disable_dcc = DCC_ENABLE, 692 .vsr_support = true, 693 .performance_trace = false, 694 .max_downscale_src_width = 7680,/*upto 8K*/ 695 .scl_reset_length10 = true, 696 .sanity_checks = false, 697 .underflow_assert_delay_us = 0xFFFFFFFF, 698 .dwb_fi_phase = -1, // -1 = disable 699 .dmub_command_table = true, 700 .use_max_lb = false, 701 }; 702 703 static const struct dc_debug_options debug_defaults_diags = { 704 .disable_dmcu = true, 705 .force_abm_enable = false, 706 .timing_trace = true, 707 .clock_trace = true, 708 .disable_dpp_power_gate = false, 709 .disable_hubp_power_gate = false, 710 .disable_clock_gate = true, 711 .disable_pplib_clock_request = true, 712 .disable_pplib_wm_range = true, 713 .disable_stutter = true, 714 .scl_reset_length10 = true, 715 .dwb_fi_phase = -1, // -1 = disable 716 .dmub_command_table = true, 717 .use_max_lb = false, 718 }; 719 720 void dcn301_dpp_destroy(struct dpp **dpp) 721 { 722 kfree(TO_DCN20_DPP(*dpp)); 723 *dpp = NULL; 724 } 725 726 struct dpp *dcn301_dpp_create( 727 struct dc_context *ctx, 728 uint32_t inst) 729 { 730 struct dcn3_dpp *dpp = 731 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL); 732 733 if (!dpp) 734 return NULL; 735 736 if (dpp3_construct(dpp, ctx, inst, 737 &dpp_regs[inst], &tf_shift, &tf_mask)) 738 return &dpp->base; 739 740 BREAK_TO_DEBUGGER(); 741 kfree(dpp); 742 return NULL; 743 } 744 struct output_pixel_processor *dcn301_opp_create( 745 struct dc_context *ctx, uint32_t inst) 746 { 747 struct dcn20_opp *opp = 748 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); 749 750 if (!opp) { 751 BREAK_TO_DEBUGGER(); 752 return NULL; 753 } 754 755 dcn20_opp_construct(opp, ctx, inst, 756 &opp_regs[inst], &opp_shift, &opp_mask); 757 return &opp->base; 758 } 759 760 struct dce_aux *dcn301_aux_engine_create( 761 struct dc_context *ctx, 762 uint32_t inst) 763 { 764 struct aux_engine_dce110 *aux_engine = 765 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 766 767 if (!aux_engine) 768 return NULL; 769 770 dce110_aux_engine_construct(aux_engine, ctx, inst, 771 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 772 &aux_engine_regs[inst], 773 &aux_mask, 774 &aux_shift, 775 ctx->dc->caps.extended_aux_timeout_support); 776 777 return &aux_engine->base; 778 } 779 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 780 781 static const struct dce_i2c_registers i2c_hw_regs[] = { 782 i2c_inst_regs(1), 783 i2c_inst_regs(2), 784 i2c_inst_regs(3), 785 i2c_inst_regs(4), 786 }; 787 788 static const struct dce_i2c_shift i2c_shifts = { 789 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT) 790 }; 791 792 static const struct dce_i2c_mask i2c_masks = { 793 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK) 794 }; 795 796 struct dce_i2c_hw *dcn301_i2c_hw_create( 797 struct dc_context *ctx, 798 uint32_t inst) 799 { 800 struct dce_i2c_hw *dce_i2c_hw = 801 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 802 803 if (!dce_i2c_hw) 804 return NULL; 805 806 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, 807 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 808 809 return dce_i2c_hw; 810 } 811 static struct mpc *dcn301_mpc_create( 812 struct dc_context *ctx, 813 int num_mpcc, 814 int num_rmu) 815 { 816 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), 817 GFP_KERNEL); 818 819 if (!mpc30) 820 return NULL; 821 822 dcn30_mpc_construct(mpc30, ctx, 823 &mpc_regs, 824 &mpc_shift, 825 &mpc_mask, 826 num_mpcc, 827 num_rmu); 828 829 return &mpc30->base; 830 } 831 832 struct hubbub *dcn301_hubbub_create(struct dc_context *ctx) 833 { 834 int i; 835 836 struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub), 837 GFP_KERNEL); 838 839 if (!hubbub3) 840 return NULL; 841 842 hubbub301_construct(hubbub3, ctx, 843 &hubbub_reg, 844 &hubbub_shift, 845 &hubbub_mask); 846 847 848 for (i = 0; i < res_cap_dcn301.num_vmid; i++) { 849 struct dcn20_vmid *vmid = &hubbub3->vmid[i]; 850 851 vmid->ctx = ctx; 852 853 vmid->regs = &vmid_regs[i]; 854 vmid->shifts = &vmid_shifts; 855 vmid->masks = &vmid_masks; 856 } 857 858 hubbub3->num_vmid = res_cap_dcn301.num_vmid; 859 860 return &hubbub3->base; 861 } 862 863 struct timing_generator *dcn301_timing_generator_create( 864 struct dc_context *ctx, 865 uint32_t instance) 866 { 867 struct optc *tgn10 = 868 kzalloc(sizeof(struct optc), GFP_KERNEL); 869 870 if (!tgn10) 871 return NULL; 872 873 tgn10->base.inst = instance; 874 tgn10->base.ctx = ctx; 875 876 tgn10->tg_regs = &optc_regs[instance]; 877 tgn10->tg_shift = &optc_shift; 878 tgn10->tg_mask = &optc_mask; 879 880 dcn30_timing_generator_init(tgn10); 881 882 return &tgn10->base; 883 } 884 885 static const struct encoder_feature_support link_enc_feature = { 886 .max_hdmi_deep_color = COLOR_DEPTH_121212, 887 .max_hdmi_pixel_clock = 600000, 888 .hdmi_ycbcr420_supported = true, 889 .dp_ycbcr420_supported = true, 890 .fec_supported = true, 891 .flags.bits.IS_HBR2_CAPABLE = true, 892 .flags.bits.IS_HBR3_CAPABLE = true, 893 .flags.bits.IS_TPS3_CAPABLE = true, 894 .flags.bits.IS_TPS4_CAPABLE = true 895 }; 896 897 struct link_encoder *dcn301_link_encoder_create( 898 const struct encoder_init_data *enc_init_data) 899 { 900 struct dcn20_link_encoder *enc20 = 901 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 902 903 if (!enc20) 904 return NULL; 905 906 dcn301_link_encoder_construct(enc20, 907 enc_init_data, 908 &link_enc_feature, 909 &link_enc_regs[enc_init_data->transmitter], 910 &link_enc_aux_regs[enc_init_data->channel - 1], 911 &link_enc_hpd_regs[enc_init_data->hpd_source], 912 &le_shift, 913 &le_mask); 914 915 return &enc20->enc10.base; 916 } 917 918 struct panel_cntl *dcn301_panel_cntl_create(const struct panel_cntl_init_data *init_data) 919 { 920 struct dcn301_panel_cntl *panel_cntl = 921 kzalloc(sizeof(struct dcn301_panel_cntl), GFP_KERNEL); 922 923 if (!panel_cntl) 924 return NULL; 925 926 dcn301_panel_cntl_construct(panel_cntl, 927 init_data, 928 &panel_cntl_regs[init_data->inst], 929 &panel_cntl_shift, 930 &panel_cntl_mask); 931 932 return &panel_cntl->base; 933 } 934 935 936 #define CTX ctx 937 938 #define REG(reg_name) \ 939 (DCN_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name) 940 941 static uint32_t read_pipe_fuses(struct dc_context *ctx) 942 { 943 uint32_t value = REG_READ(CC_DC_PIPE_DIS); 944 /* RV1 support max 4 pipes */ 945 value = value & 0xf; 946 return value; 947 } 948 949 950 static void read_dce_straps( 951 struct dc_context *ctx, 952 struct resource_straps *straps) 953 { 954 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX), 955 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 956 957 } 958 959 static struct audio *dcn301_create_audio( 960 struct dc_context *ctx, unsigned int inst) 961 { 962 return dce_audio_create(ctx, inst, 963 &audio_regs[inst], &audio_shift, &audio_mask); 964 } 965 966 static struct vpg *dcn301_vpg_create( 967 struct dc_context *ctx, 968 uint32_t inst) 969 { 970 struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL); 971 972 if (!vpg3) 973 return NULL; 974 975 vpg3_construct(vpg3, ctx, inst, 976 &vpg_regs[inst], 977 &vpg_shift, 978 &vpg_mask); 979 980 return &vpg3->base; 981 } 982 983 static struct afmt *dcn301_afmt_create( 984 struct dc_context *ctx, 985 uint32_t inst) 986 { 987 struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL); 988 989 if (!afmt3) 990 return NULL; 991 992 afmt3_construct(afmt3, ctx, inst, 993 &afmt_regs[inst], 994 &afmt_shift, 995 &afmt_mask); 996 997 return &afmt3->base; 998 } 999 1000 struct stream_encoder *dcn301_stream_encoder_create( 1001 enum engine_id eng_id, 1002 struct dc_context *ctx) 1003 { 1004 struct dcn10_stream_encoder *enc1; 1005 struct vpg *vpg; 1006 struct afmt *afmt; 1007 int vpg_inst; 1008 int afmt_inst; 1009 1010 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */ 1011 if (eng_id <= ENGINE_ID_DIGF) { 1012 vpg_inst = eng_id; 1013 afmt_inst = eng_id; 1014 } else 1015 return NULL; 1016 1017 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 1018 vpg = dcn301_vpg_create(ctx, vpg_inst); 1019 afmt = dcn301_afmt_create(ctx, afmt_inst); 1020 1021 if (!enc1 || !vpg || !afmt) { 1022 kfree(enc1); 1023 kfree(vpg); 1024 kfree(afmt); 1025 return NULL; 1026 } 1027 1028 dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, 1029 eng_id, vpg, afmt, 1030 &stream_enc_regs[eng_id], 1031 &se_shift, &se_mask); 1032 1033 return &enc1->base; 1034 } 1035 1036 struct dce_hwseq *dcn301_hwseq_create( 1037 struct dc_context *ctx) 1038 { 1039 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 1040 1041 if (hws) { 1042 hws->ctx = ctx; 1043 hws->regs = &hwseq_reg; 1044 hws->shifts = &hwseq_shift; 1045 hws->masks = &hwseq_mask; 1046 } 1047 return hws; 1048 } 1049 static const struct resource_create_funcs res_create_funcs = { 1050 .read_dce_straps = read_dce_straps, 1051 .create_audio = dcn301_create_audio, 1052 .create_stream_encoder = dcn301_stream_encoder_create, 1053 .create_hwseq = dcn301_hwseq_create, 1054 }; 1055 1056 static const struct resource_create_funcs res_create_maximus_funcs = { 1057 .read_dce_straps = NULL, 1058 .create_audio = NULL, 1059 .create_stream_encoder = NULL, 1060 .create_hwseq = dcn301_hwseq_create, 1061 }; 1062 1063 static void dcn301_destruct(struct dcn301_resource_pool *pool) 1064 { 1065 unsigned int i; 1066 1067 for (i = 0; i < pool->base.stream_enc_count; i++) { 1068 if (pool->base.stream_enc[i] != NULL) { 1069 if (pool->base.stream_enc[i]->vpg != NULL) { 1070 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg)); 1071 pool->base.stream_enc[i]->vpg = NULL; 1072 } 1073 if (pool->base.stream_enc[i]->afmt != NULL) { 1074 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt)); 1075 pool->base.stream_enc[i]->afmt = NULL; 1076 } 1077 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); 1078 pool->base.stream_enc[i] = NULL; 1079 } 1080 } 1081 1082 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 1083 if (pool->base.dscs[i] != NULL) 1084 dcn20_dsc_destroy(&pool->base.dscs[i]); 1085 } 1086 1087 if (pool->base.mpc != NULL) { 1088 kfree(TO_DCN20_MPC(pool->base.mpc)); 1089 pool->base.mpc = NULL; 1090 } 1091 if (pool->base.hubbub != NULL) { 1092 kfree(pool->base.hubbub); 1093 pool->base.hubbub = NULL; 1094 } 1095 for (i = 0; i < pool->base.pipe_count; i++) { 1096 if (pool->base.dpps[i] != NULL) 1097 dcn301_dpp_destroy(&pool->base.dpps[i]); 1098 1099 if (pool->base.ipps[i] != NULL) 1100 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); 1101 1102 if (pool->base.hubps[i] != NULL) { 1103 kfree(TO_DCN20_HUBP(pool->base.hubps[i])); 1104 pool->base.hubps[i] = NULL; 1105 } 1106 1107 if (pool->base.irqs != NULL) { 1108 dal_irq_service_destroy(&pool->base.irqs); 1109 } 1110 } 1111 1112 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1113 if (pool->base.engines[i] != NULL) 1114 dce110_engine_destroy(&pool->base.engines[i]); 1115 if (pool->base.hw_i2cs[i] != NULL) { 1116 kfree(pool->base.hw_i2cs[i]); 1117 pool->base.hw_i2cs[i] = NULL; 1118 } 1119 if (pool->base.sw_i2cs[i] != NULL) { 1120 kfree(pool->base.sw_i2cs[i]); 1121 pool->base.sw_i2cs[i] = NULL; 1122 } 1123 } 1124 1125 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 1126 if (pool->base.opps[i] != NULL) 1127 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); 1128 } 1129 1130 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1131 if (pool->base.timing_generators[i] != NULL) { 1132 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); 1133 pool->base.timing_generators[i] = NULL; 1134 } 1135 } 1136 1137 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { 1138 if (pool->base.dwbc[i] != NULL) { 1139 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); 1140 pool->base.dwbc[i] = NULL; 1141 } 1142 if (pool->base.mcif_wb[i] != NULL) { 1143 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i])); 1144 pool->base.mcif_wb[i] = NULL; 1145 } 1146 } 1147 1148 for (i = 0; i < pool->base.audio_count; i++) { 1149 if (pool->base.audios[i]) 1150 dce_aud_destroy(&pool->base.audios[i]); 1151 } 1152 1153 for (i = 0; i < pool->base.clk_src_count; i++) { 1154 if (pool->base.clock_sources[i] != NULL) { 1155 dcn20_clock_source_destroy(&pool->base.clock_sources[i]); 1156 pool->base.clock_sources[i] = NULL; 1157 } 1158 } 1159 1160 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { 1161 if (pool->base.mpc_lut[i] != NULL) { 1162 dc_3dlut_func_release(pool->base.mpc_lut[i]); 1163 pool->base.mpc_lut[i] = NULL; 1164 } 1165 if (pool->base.mpc_shaper[i] != NULL) { 1166 dc_transfer_func_release(pool->base.mpc_shaper[i]); 1167 pool->base.mpc_shaper[i] = NULL; 1168 } 1169 } 1170 1171 if (pool->base.dp_clock_source != NULL) { 1172 dcn20_clock_source_destroy(&pool->base.dp_clock_source); 1173 pool->base.dp_clock_source = NULL; 1174 } 1175 1176 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1177 if (pool->base.multiple_abms[i] != NULL) 1178 dce_abm_destroy(&pool->base.multiple_abms[i]); 1179 } 1180 1181 if (pool->base.dccg != NULL) 1182 dcn_dccg_destroy(&pool->base.dccg); 1183 } 1184 1185 struct hubp *dcn301_hubp_create( 1186 struct dc_context *ctx, 1187 uint32_t inst) 1188 { 1189 struct dcn20_hubp *hubp2 = 1190 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL); 1191 1192 if (!hubp2) 1193 return NULL; 1194 1195 if (hubp3_construct(hubp2, ctx, inst, 1196 &hubp_regs[inst], &hubp_shift, &hubp_mask)) 1197 return &hubp2->base; 1198 1199 BREAK_TO_DEBUGGER(); 1200 kfree(hubp2); 1201 return NULL; 1202 } 1203 1204 bool dcn301_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) 1205 { 1206 int i; 1207 uint32_t pipe_count = pool->res_cap->num_dwb; 1208 1209 for (i = 0; i < pipe_count; i++) { 1210 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), 1211 GFP_KERNEL); 1212 1213 if (!dwbc30) { 1214 dm_error("DC: failed to create dwbc30!\n"); 1215 return false; 1216 } 1217 1218 dcn30_dwbc_construct(dwbc30, ctx, 1219 &dwbc30_regs[i], 1220 &dwbc30_shift, 1221 &dwbc30_mask, 1222 i); 1223 1224 pool->dwbc[i] = &dwbc30->base; 1225 } 1226 return true; 1227 } 1228 1229 bool dcn301_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) 1230 { 1231 int i; 1232 uint32_t pipe_count = pool->res_cap->num_dwb; 1233 1234 for (i = 0; i < pipe_count; i++) { 1235 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), 1236 GFP_KERNEL); 1237 1238 if (!mcif_wb30) { 1239 dm_error("DC: failed to create mcif_wb30!\n"); 1240 return false; 1241 } 1242 1243 dcn30_mmhubbub_construct(mcif_wb30, ctx, 1244 &mcif_wb30_regs[i], 1245 &mcif_wb30_shift, 1246 &mcif_wb30_mask, 1247 i); 1248 1249 pool->mcif_wb[i] = &mcif_wb30->base; 1250 } 1251 return true; 1252 } 1253 1254 static struct display_stream_compressor *dcn301_dsc_create( 1255 struct dc_context *ctx, uint32_t inst) 1256 { 1257 struct dcn20_dsc *dsc = 1258 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); 1259 1260 if (!dsc) { 1261 BREAK_TO_DEBUGGER(); 1262 return NULL; 1263 } 1264 1265 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 1266 return &dsc->base; 1267 } 1268 1269 1270 static void dcn301_destroy_resource_pool(struct resource_pool **pool) 1271 { 1272 struct dcn301_resource_pool *dcn301_pool = TO_DCN301_RES_POOL(*pool); 1273 1274 dcn301_destruct(dcn301_pool); 1275 kfree(dcn301_pool); 1276 *pool = NULL; 1277 } 1278 1279 static struct clock_source *dcn301_clock_source_create( 1280 struct dc_context *ctx, 1281 struct dc_bios *bios, 1282 enum clock_source_id id, 1283 const struct dce110_clk_src_regs *regs, 1284 bool dp_clk_src) 1285 { 1286 struct dce110_clk_src *clk_src = 1287 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 1288 1289 if (!clk_src) 1290 return NULL; 1291 1292 if (dcn301_clk_src_construct(clk_src, ctx, bios, id, 1293 regs, &cs_shift, &cs_mask)) { 1294 clk_src->base.dp_clk_src = dp_clk_src; 1295 return &clk_src->base; 1296 } 1297 1298 BREAK_TO_DEBUGGER(); 1299 return NULL; 1300 } 1301 1302 static struct dc_cap_funcs cap_funcs = { 1303 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap 1304 }; 1305 1306 1307 static bool is_soc_bounding_box_valid(struct dc *dc) 1308 { 1309 uint32_t hw_internal_rev = dc->ctx->asic_id.hw_internal_rev; 1310 1311 if (ASICREV_IS_VANGOGH(hw_internal_rev)) 1312 return true; 1313 1314 return false; 1315 } 1316 1317 static bool init_soc_bounding_box(struct dc *dc, 1318 struct dcn301_resource_pool *pool) 1319 { 1320 struct _vcs_dpi_soc_bounding_box_st *loaded_bb = &dcn3_01_soc; 1321 struct _vcs_dpi_ip_params_st *loaded_ip = &dcn3_01_ip; 1322 1323 DC_LOGGER_INIT(dc->ctx->logger); 1324 1325 if (!is_soc_bounding_box_valid(dc)) { 1326 DC_LOG_ERROR("%s: not valid soc bounding box\n", __func__); 1327 return false; 1328 } 1329 1330 loaded_ip->max_num_otg = pool->base.res_cap->num_timing_generator; 1331 loaded_ip->max_num_dpp = pool->base.pipe_count; 1332 DC_FP_START(); 1333 dcn20_patch_bounding_box(dc, loaded_bb); 1334 DC_FP_END(); 1335 1336 if (dc->ctx->dc_bios->funcs->get_soc_bb_info) { 1337 struct bp_soc_bb_info bb_info = {0}; 1338 1339 if (dc->ctx->dc_bios->funcs->get_soc_bb_info(dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) { 1340 DC_FP_START(); 1341 dcn301_fpu_init_soc_bounding_box(bb_info); 1342 DC_FP_END(); 1343 } 1344 } 1345 1346 return true; 1347 } 1348 1349 1350 static void set_wm_ranges( 1351 struct pp_smu_funcs *pp_smu, 1352 struct _vcs_dpi_soc_bounding_box_st *loaded_bb) 1353 { 1354 struct pp_smu_wm_range_sets ranges = {0}; 1355 int i; 1356 1357 ranges.num_reader_wm_sets = 0; 1358 1359 if (loaded_bb->num_states == 1) { 1360 ranges.reader_wm_sets[0].wm_inst = 0; 1361 ranges.reader_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 1362 ranges.reader_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 1363 ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 1364 ranges.reader_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 1365 1366 ranges.num_reader_wm_sets = 1; 1367 } else if (loaded_bb->num_states > 1) { 1368 for (i = 0; i < 4 && i < loaded_bb->num_states; i++) { 1369 ranges.reader_wm_sets[i].wm_inst = i; 1370 ranges.reader_wm_sets[i].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 1371 ranges.reader_wm_sets[i].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 1372 DC_FP_START(); 1373 dcn301_fpu_set_wm_ranges(i, &ranges, loaded_bb); 1374 DC_FP_END(); 1375 ranges.num_reader_wm_sets = i + 1; 1376 } 1377 1378 ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 1379 ranges.reader_wm_sets[ranges.num_reader_wm_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 1380 } 1381 1382 ranges.num_writer_wm_sets = 1; 1383 1384 ranges.writer_wm_sets[0].wm_inst = 0; 1385 ranges.writer_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 1386 ranges.writer_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 1387 ranges.writer_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 1388 ranges.writer_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 1389 1390 /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */ 1391 pp_smu->nv_funcs.set_wm_ranges(&pp_smu->nv_funcs.pp_smu, &ranges); 1392 } 1393 1394 static struct resource_funcs dcn301_res_pool_funcs = { 1395 .destroy = dcn301_destroy_resource_pool, 1396 .link_enc_create = dcn301_link_encoder_create, 1397 .panel_cntl_create = dcn301_panel_cntl_create, 1398 .validate_bandwidth = dcn30_validate_bandwidth, 1399 .calculate_wm_and_dlg = dcn301_calculate_wm_and_dlg, 1400 .update_soc_for_wm_a = dcn30_update_soc_for_wm_a, 1401 .populate_dml_pipes = dcn30_populate_dml_pipes_from_context, 1402 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer, 1403 .add_stream_to_ctx = dcn30_add_stream_to_ctx, 1404 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, 1405 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 1406 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, 1407 .set_mcif_arb_params = dcn30_set_mcif_arb_params, 1408 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, 1409 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut, 1410 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut, 1411 .update_bw_bounding_box = dcn301_update_bw_bounding_box 1412 }; 1413 1414 static bool dcn301_resource_construct( 1415 uint8_t num_virtual_links, 1416 struct dc *dc, 1417 struct dcn301_resource_pool *pool) 1418 { 1419 int i, j; 1420 struct dc_context *ctx = dc->ctx; 1421 struct irq_service_init_data init_data; 1422 uint32_t pipe_fuses = read_pipe_fuses(ctx); 1423 uint32_t num_pipes = 0; 1424 1425 DC_LOGGER_INIT(dc->ctx->logger); 1426 1427 ctx->dc_bios->regs = &bios_regs; 1428 1429 pool->base.res_cap = &res_cap_dcn301; 1430 1431 pool->base.funcs = &dcn301_res_pool_funcs; 1432 1433 /************************************************* 1434 * Resource + asic cap harcoding * 1435 *************************************************/ 1436 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1437 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; 1438 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator; 1439 dc->caps.max_downscale_ratio = 600; 1440 dc->caps.i2c_speed_in_khz = 100; 1441 dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a enabled by default*/ 1442 dc->caps.max_cursor_size = 256; 1443 dc->caps.min_horizontal_blanking_period = 80; 1444 dc->caps.dmdata_alloc_size = 2048; 1445 dc->caps.max_slave_planes = 1; 1446 dc->caps.max_slave_yuv_planes = 1; 1447 dc->caps.max_slave_rgb_planes = 1; 1448 dc->caps.is_apu = true; 1449 dc->caps.post_blend_color_processing = true; 1450 dc->caps.force_dp_tps4_for_cp2520 = true; 1451 dc->caps.extended_aux_timeout_support = true; 1452 #ifdef CONFIG_DRM_AMD_DC_DMUB 1453 dc->caps.dmcub_support = true; 1454 #endif 1455 1456 /* Color pipeline capabilities */ 1457 dc->caps.color.dpp.dcn_arch = 1; 1458 dc->caps.color.dpp.input_lut_shared = 0; 1459 dc->caps.color.dpp.icsc = 1; 1460 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr 1461 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; 1462 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; 1463 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1; 1464 dc->caps.color.dpp.dgam_rom_caps.pq = 1; 1465 dc->caps.color.dpp.dgam_rom_caps.hlg = 1; 1466 dc->caps.color.dpp.post_csc = 1; 1467 dc->caps.color.dpp.gamma_corr = 1; 1468 dc->caps.color.dpp.dgam_rom_for_yuv = 0; 1469 1470 dc->caps.color.dpp.hw_3d_lut = 1; 1471 dc->caps.color.dpp.ogam_ram = 1; 1472 // no OGAM ROM on DCN301 1473 dc->caps.color.dpp.ogam_rom_caps.srgb = 0; 1474 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; 1475 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; 1476 dc->caps.color.dpp.ogam_rom_caps.pq = 0; 1477 dc->caps.color.dpp.ogam_rom_caps.hlg = 0; 1478 dc->caps.color.dpp.ocsc = 0; 1479 1480 dc->caps.color.mpc.gamut_remap = 1; 1481 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2 1482 dc->caps.color.mpc.ogam_ram = 1; 1483 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; 1484 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; 1485 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; 1486 dc->caps.color.mpc.ogam_rom_caps.pq = 0; 1487 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 1488 dc->caps.color.mpc.ocsc = 1; 1489 1490 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 1491 dc->debug = debug_defaults_drv; 1492 else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) { 1493 dc->debug = debug_defaults_diags; 1494 } else 1495 dc->debug = debug_defaults_diags; 1496 // Init the vm_helper 1497 if (dc->vm_helper) 1498 vm_helper_init(dc->vm_helper, 16); 1499 1500 /************************************************* 1501 * Create resources * 1502 *************************************************/ 1503 1504 /* Clock Sources for Pixel Clock*/ 1505 pool->base.clock_sources[DCN301_CLK_SRC_PLL0] = 1506 dcn301_clock_source_create(ctx, ctx->dc_bios, 1507 CLOCK_SOURCE_COMBO_PHY_PLL0, 1508 &clk_src_regs[0], false); 1509 pool->base.clock_sources[DCN301_CLK_SRC_PLL1] = 1510 dcn301_clock_source_create(ctx, ctx->dc_bios, 1511 CLOCK_SOURCE_COMBO_PHY_PLL1, 1512 &clk_src_regs[1], false); 1513 pool->base.clock_sources[DCN301_CLK_SRC_PLL2] = 1514 dcn301_clock_source_create(ctx, ctx->dc_bios, 1515 CLOCK_SOURCE_COMBO_PHY_PLL2, 1516 &clk_src_regs[2], false); 1517 pool->base.clock_sources[DCN301_CLK_SRC_PLL3] = 1518 dcn301_clock_source_create(ctx, ctx->dc_bios, 1519 CLOCK_SOURCE_COMBO_PHY_PLL3, 1520 &clk_src_regs[3], false); 1521 1522 pool->base.clk_src_count = DCN301_CLK_SRC_TOTAL; 1523 1524 /* todo: not reuse phy_pll registers */ 1525 pool->base.dp_clock_source = 1526 dcn301_clock_source_create(ctx, ctx->dc_bios, 1527 CLOCK_SOURCE_ID_DP_DTO, 1528 &clk_src_regs[0], true); 1529 1530 for (i = 0; i < pool->base.clk_src_count; i++) { 1531 if (pool->base.clock_sources[i] == NULL) { 1532 dm_error("DC: failed to create clock sources!\n"); 1533 BREAK_TO_DEBUGGER(); 1534 goto create_fail; 1535 } 1536 } 1537 1538 /* DCCG */ 1539 pool->base.dccg = dccg301_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 1540 if (pool->base.dccg == NULL) { 1541 dm_error("DC: failed to create dccg!\n"); 1542 BREAK_TO_DEBUGGER(); 1543 goto create_fail; 1544 } 1545 1546 init_soc_bounding_box(dc, pool); 1547 1548 if (!dc->debug.disable_pplib_wm_range && pool->base.pp_smu->nv_funcs.set_wm_ranges) 1549 set_wm_ranges(pool->base.pp_smu, &dcn3_01_soc); 1550 1551 num_pipes = dcn3_01_ip.max_num_dpp; 1552 1553 for (i = 0; i < dcn3_01_ip.max_num_dpp; i++) 1554 if (pipe_fuses & 1 << i) 1555 num_pipes--; 1556 dcn3_01_ip.max_num_dpp = num_pipes; 1557 dcn3_01_ip.max_num_otg = num_pipes; 1558 1559 1560 dml_init_instance(&dc->dml, &dcn3_01_soc, &dcn3_01_ip, DML_PROJECT_DCN30); 1561 1562 /* IRQ */ 1563 init_data.ctx = dc->ctx; 1564 pool->base.irqs = dal_irq_service_dcn30_create(&init_data); 1565 if (!pool->base.irqs) 1566 goto create_fail; 1567 1568 /* HUBBUB */ 1569 pool->base.hubbub = dcn301_hubbub_create(ctx); 1570 if (pool->base.hubbub == NULL) { 1571 BREAK_TO_DEBUGGER(); 1572 dm_error("DC: failed to create hubbub!\n"); 1573 goto create_fail; 1574 } 1575 1576 j = 0; 1577 /* HUBPs, DPPs, OPPs and TGs */ 1578 for (i = 0; i < pool->base.pipe_count; i++) { 1579 1580 /* if pipe is disabled, skip instance of HW pipe, 1581 * i.e, skip ASIC register instance 1582 */ 1583 if ((pipe_fuses & (1 << i)) != 0) { 1584 DC_LOG_DEBUG("%s: fusing pipe %d\n", __func__, i); 1585 continue; 1586 } 1587 1588 pool->base.hubps[j] = dcn301_hubp_create(ctx, i); 1589 if (pool->base.hubps[j] == NULL) { 1590 BREAK_TO_DEBUGGER(); 1591 dm_error( 1592 "DC: failed to create hubps!\n"); 1593 goto create_fail; 1594 } 1595 1596 pool->base.dpps[j] = dcn301_dpp_create(ctx, i); 1597 if (pool->base.dpps[j] == NULL) { 1598 BREAK_TO_DEBUGGER(); 1599 dm_error( 1600 "DC: failed to create dpps!\n"); 1601 goto create_fail; 1602 } 1603 1604 pool->base.opps[j] = dcn301_opp_create(ctx, i); 1605 if (pool->base.opps[j] == NULL) { 1606 BREAK_TO_DEBUGGER(); 1607 dm_error( 1608 "DC: failed to create output pixel processor!\n"); 1609 goto create_fail; 1610 } 1611 1612 pool->base.timing_generators[j] = dcn301_timing_generator_create(ctx, i); 1613 if (pool->base.timing_generators[j] == NULL) { 1614 BREAK_TO_DEBUGGER(); 1615 dm_error("DC: failed to create tg!\n"); 1616 goto create_fail; 1617 } 1618 j++; 1619 } 1620 pool->base.timing_generator_count = j; 1621 pool->base.pipe_count = j; 1622 pool->base.mpcc_count = j; 1623 1624 /* ABM (or ABMs for NV2x) */ 1625 /* TODO: */ 1626 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1627 pool->base.multiple_abms[i] = dmub_abm_create(ctx, 1628 &abm_regs[i], 1629 &abm_shift, 1630 &abm_mask); 1631 if (pool->base.multiple_abms[i] == NULL) { 1632 dm_error("DC: failed to create abm for pipe %d!\n", i); 1633 BREAK_TO_DEBUGGER(); 1634 goto create_fail; 1635 } 1636 } 1637 1638 /* MPC and DSC */ 1639 pool->base.mpc = dcn301_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut); 1640 if (pool->base.mpc == NULL) { 1641 BREAK_TO_DEBUGGER(); 1642 dm_error("DC: failed to create mpc!\n"); 1643 goto create_fail; 1644 } 1645 1646 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 1647 pool->base.dscs[i] = dcn301_dsc_create(ctx, i); 1648 if (pool->base.dscs[i] == NULL) { 1649 BREAK_TO_DEBUGGER(); 1650 dm_error("DC: failed to create display stream compressor %d!\n", i); 1651 goto create_fail; 1652 } 1653 } 1654 1655 /* DWB and MMHUBBUB */ 1656 if (!dcn301_dwbc_create(ctx, &pool->base)) { 1657 BREAK_TO_DEBUGGER(); 1658 dm_error("DC: failed to create dwbc!\n"); 1659 goto create_fail; 1660 } 1661 1662 if (!dcn301_mmhubbub_create(ctx, &pool->base)) { 1663 BREAK_TO_DEBUGGER(); 1664 dm_error("DC: failed to create mcif_wb!\n"); 1665 goto create_fail; 1666 } 1667 1668 /* AUX and I2C */ 1669 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1670 pool->base.engines[i] = dcn301_aux_engine_create(ctx, i); 1671 if (pool->base.engines[i] == NULL) { 1672 BREAK_TO_DEBUGGER(); 1673 dm_error( 1674 "DC:failed to create aux engine!!\n"); 1675 goto create_fail; 1676 } 1677 pool->base.hw_i2cs[i] = dcn301_i2c_hw_create(ctx, i); 1678 if (pool->base.hw_i2cs[i] == NULL) { 1679 BREAK_TO_DEBUGGER(); 1680 dm_error( 1681 "DC:failed to create hw i2c!!\n"); 1682 goto create_fail; 1683 } 1684 pool->base.sw_i2cs[i] = NULL; 1685 } 1686 1687 /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */ 1688 if (!resource_construct(num_virtual_links, dc, &pool->base, 1689 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? 1690 &res_create_funcs : &res_create_maximus_funcs))) 1691 goto create_fail; 1692 1693 /* HW Sequencer and Plane caps */ 1694 dcn301_hw_sequencer_construct(dc); 1695 1696 dc->caps.max_planes = pool->base.pipe_count; 1697 1698 for (i = 0; i < dc->caps.max_planes; ++i) 1699 dc->caps.planes[i] = plane_cap; 1700 1701 dc->cap_funcs = cap_funcs; 1702 1703 return true; 1704 1705 create_fail: 1706 1707 dcn301_destruct(pool); 1708 1709 return false; 1710 } 1711 1712 struct resource_pool *dcn301_create_resource_pool( 1713 const struct dc_init_data *init_data, 1714 struct dc *dc) 1715 { 1716 struct dcn301_resource_pool *pool = 1717 kzalloc(sizeof(struct dcn301_resource_pool), GFP_KERNEL); 1718 1719 if (!pool) 1720 return NULL; 1721 1722 if (dcn301_resource_construct(init_data->num_virtual_links, dc, pool)) 1723 return &pool->base; 1724 1725 BREAK_TO_DEBUGGER(); 1726 kfree(pool); 1727 return NULL; 1728 } 1729