13c10f4fbSBhawanpreet Lakha /* 23c10f4fbSBhawanpreet Lakha * Copyright 2020 Advanced Micro Devices, Inc. 33c10f4fbSBhawanpreet Lakha * 43c10f4fbSBhawanpreet Lakha * Permission is hereby granted, free of charge, to any person obtaining a 53c10f4fbSBhawanpreet Lakha * copy of this software and associated documentation files (the "Software"), 63c10f4fbSBhawanpreet Lakha * to deal in the Software without restriction, including without limitation 73c10f4fbSBhawanpreet Lakha * the rights to use, copy, modify, merge, publish, distribute, sublicense, 83c10f4fbSBhawanpreet Lakha * and/or sell copies of the Software, and to permit persons to whom the 93c10f4fbSBhawanpreet Lakha * Software is furnished to do so, subject to the following conditions: 103c10f4fbSBhawanpreet Lakha * 113c10f4fbSBhawanpreet Lakha * The above copyright notice and this permission notice shall be included in 123c10f4fbSBhawanpreet Lakha * all copies or substantial portions of the Software. 133c10f4fbSBhawanpreet Lakha * 143c10f4fbSBhawanpreet Lakha * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 153c10f4fbSBhawanpreet Lakha * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 163c10f4fbSBhawanpreet Lakha * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 173c10f4fbSBhawanpreet Lakha * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 183c10f4fbSBhawanpreet Lakha * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 193c10f4fbSBhawanpreet Lakha * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 203c10f4fbSBhawanpreet Lakha * OTHER DEALINGS IN THE SOFTWARE. 213c10f4fbSBhawanpreet Lakha * 223c10f4fbSBhawanpreet Lakha * Authors: AMD 233c10f4fbSBhawanpreet Lakha * 243c10f4fbSBhawanpreet Lakha */ 253c10f4fbSBhawanpreet Lakha 263c10f4fbSBhawanpreet Lakha 273c10f4fbSBhawanpreet Lakha #include "dc_bios_types.h" 283c10f4fbSBhawanpreet Lakha #include "dcn30_vpg.h" 293c10f4fbSBhawanpreet Lakha #include "reg_helper.h" 303c10f4fbSBhawanpreet Lakha 313c10f4fbSBhawanpreet Lakha #define DC_LOGGER \ 323c10f4fbSBhawanpreet Lakha vpg3->base.ctx->logger 333c10f4fbSBhawanpreet Lakha 343c10f4fbSBhawanpreet Lakha #define REG(reg)\ 353c10f4fbSBhawanpreet Lakha (vpg3->regs->reg) 363c10f4fbSBhawanpreet Lakha 373c10f4fbSBhawanpreet Lakha #undef FN 383c10f4fbSBhawanpreet Lakha #define FN(reg_name, field_name) \ 393c10f4fbSBhawanpreet Lakha vpg3->vpg_shift->field_name, vpg3->vpg_mask->field_name 403c10f4fbSBhawanpreet Lakha 413c10f4fbSBhawanpreet Lakha 423c10f4fbSBhawanpreet Lakha #define CTX \ 433c10f4fbSBhawanpreet Lakha vpg3->base.ctx 443c10f4fbSBhawanpreet Lakha 453c10f4fbSBhawanpreet Lakha 463c10f4fbSBhawanpreet Lakha static void vpg3_update_generic_info_packet( 473c10f4fbSBhawanpreet Lakha struct vpg *vpg, 483c10f4fbSBhawanpreet Lakha uint32_t packet_index, 493c10f4fbSBhawanpreet Lakha const struct dc_info_packet *info_packet) 503c10f4fbSBhawanpreet Lakha { 513c10f4fbSBhawanpreet Lakha struct dcn30_vpg *vpg3 = DCN30_VPG_FROM_VPG(vpg); 523c10f4fbSBhawanpreet Lakha uint32_t i; 533c10f4fbSBhawanpreet Lakha 543c10f4fbSBhawanpreet Lakha /* TODOFPGA Figure out a proper number for max_retries polling for lock 553c10f4fbSBhawanpreet Lakha * use 50 for now. 563c10f4fbSBhawanpreet Lakha */ 573c10f4fbSBhawanpreet Lakha uint32_t max_retries = 50; 583c10f4fbSBhawanpreet Lakha 593c10f4fbSBhawanpreet Lakha if (packet_index > 14) 603c10f4fbSBhawanpreet Lakha ASSERT(0); 613c10f4fbSBhawanpreet Lakha 623c10f4fbSBhawanpreet Lakha /* poll dig_update_lock is not locked -> asic internal signal 633c10f4fbSBhawanpreet Lakha * assume otg master lock will unlock it 643c10f4fbSBhawanpreet Lakha */ 653c10f4fbSBhawanpreet Lakha /* REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_LOCK_STATUS, 663c10f4fbSBhawanpreet Lakha * 0, 10, max_retries); 673c10f4fbSBhawanpreet Lakha */ 683c10f4fbSBhawanpreet Lakha 693c10f4fbSBhawanpreet Lakha /* TODO: Check if this is required */ 703c10f4fbSBhawanpreet Lakha /* check if HW reading GSP memory */ 713c10f4fbSBhawanpreet Lakha REG_WAIT(VPG_GENERIC_STATUS, VPG_GENERIC_CONFLICT_OCCURED, 723c10f4fbSBhawanpreet Lakha 0, 10, max_retries); 733c10f4fbSBhawanpreet Lakha 743c10f4fbSBhawanpreet Lakha /* HW does is not reading GSP memory not reading too long -> 753c10f4fbSBhawanpreet Lakha * something wrong. clear GPS memory access and notify? 763c10f4fbSBhawanpreet Lakha * hw SW is writing to GSP memory 773c10f4fbSBhawanpreet Lakha */ 783c10f4fbSBhawanpreet Lakha REG_UPDATE(VPG_GENERIC_STATUS, VPG_GENERIC_CONFLICT_CLR, 1); 793c10f4fbSBhawanpreet Lakha 803c10f4fbSBhawanpreet Lakha /* choose which generic packet to use */ 813c10f4fbSBhawanpreet Lakha REG_UPDATE(VPG_GENERIC_PACKET_ACCESS_CTRL, 823c10f4fbSBhawanpreet Lakha VPG_GENERIC_DATA_INDEX, packet_index*9); 833c10f4fbSBhawanpreet Lakha 843c10f4fbSBhawanpreet Lakha /* write generic packet header 853c10f4fbSBhawanpreet Lakha * (4th byte is for GENERIC0 only) 863c10f4fbSBhawanpreet Lakha */ 873c10f4fbSBhawanpreet Lakha REG_SET_4(VPG_GENERIC_PACKET_DATA, 0, 883c10f4fbSBhawanpreet Lakha VPG_GENERIC_DATA_BYTE0, info_packet->hb0, 893c10f4fbSBhawanpreet Lakha VPG_GENERIC_DATA_BYTE1, info_packet->hb1, 903c10f4fbSBhawanpreet Lakha VPG_GENERIC_DATA_BYTE2, info_packet->hb2, 913c10f4fbSBhawanpreet Lakha VPG_GENERIC_DATA_BYTE3, info_packet->hb3); 923c10f4fbSBhawanpreet Lakha 933c10f4fbSBhawanpreet Lakha /* write generic packet contents 943c10f4fbSBhawanpreet Lakha * (we never use last 4 bytes) 953c10f4fbSBhawanpreet Lakha * there are 8 (0-7) mmDIG0_AFMT_GENERIC0_x registers 963c10f4fbSBhawanpreet Lakha */ 973c10f4fbSBhawanpreet Lakha { 983c10f4fbSBhawanpreet Lakha const uint32_t *content = 993c10f4fbSBhawanpreet Lakha (const uint32_t *) &info_packet->sb[0]; 1003c10f4fbSBhawanpreet Lakha 1013c10f4fbSBhawanpreet Lakha for (i = 0; i < 8; i++) { 1023c10f4fbSBhawanpreet Lakha REG_WRITE(VPG_GENERIC_PACKET_DATA, *content++); 1033c10f4fbSBhawanpreet Lakha } 1043c10f4fbSBhawanpreet Lakha } 1053c10f4fbSBhawanpreet Lakha 106*a013dd15SJudy Cai /* atomically update double-buffered GENERIC0 registers in immediate mode 1073c10f4fbSBhawanpreet Lakha * (update at next block_update when block_update_lock == 0). 1083c10f4fbSBhawanpreet Lakha */ 1093c10f4fbSBhawanpreet Lakha switch (packet_index) { 1103c10f4fbSBhawanpreet Lakha case 0: 111*a013dd15SJudy Cai REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL, 112*a013dd15SJudy Cai VPG_GENERIC0_IMMEDIATE_UPDATE, 1); 1133c10f4fbSBhawanpreet Lakha break; 1143c10f4fbSBhawanpreet Lakha case 1: 115*a013dd15SJudy Cai REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL, 116*a013dd15SJudy Cai VPG_GENERIC1_IMMEDIATE_UPDATE, 1); 1173c10f4fbSBhawanpreet Lakha break; 1183c10f4fbSBhawanpreet Lakha case 2: 119*a013dd15SJudy Cai REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL, 120*a013dd15SJudy Cai VPG_GENERIC2_IMMEDIATE_UPDATE, 1); 1213c10f4fbSBhawanpreet Lakha break; 1223c10f4fbSBhawanpreet Lakha case 3: 123*a013dd15SJudy Cai REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL, 124*a013dd15SJudy Cai VPG_GENERIC3_IMMEDIATE_UPDATE, 1); 1253c10f4fbSBhawanpreet Lakha break; 1263c10f4fbSBhawanpreet Lakha case 4: 127*a013dd15SJudy Cai REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL, 128*a013dd15SJudy Cai VPG_GENERIC4_IMMEDIATE_UPDATE, 1); 1293c10f4fbSBhawanpreet Lakha break; 1303c10f4fbSBhawanpreet Lakha case 5: 131*a013dd15SJudy Cai REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL, 132*a013dd15SJudy Cai VPG_GENERIC5_IMMEDIATE_UPDATE, 1); 1333c10f4fbSBhawanpreet Lakha break; 1343c10f4fbSBhawanpreet Lakha case 6: 135*a013dd15SJudy Cai REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL, 136*a013dd15SJudy Cai VPG_GENERIC6_IMMEDIATE_UPDATE, 1); 1373c10f4fbSBhawanpreet Lakha break; 1383c10f4fbSBhawanpreet Lakha case 7: 139*a013dd15SJudy Cai REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL, 140*a013dd15SJudy Cai VPG_GENERIC7_IMMEDIATE_UPDATE, 1); 1413c10f4fbSBhawanpreet Lakha break; 1423c10f4fbSBhawanpreet Lakha case 8: 143*a013dd15SJudy Cai REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL, 144*a013dd15SJudy Cai VPG_GENERIC8_IMMEDIATE_UPDATE, 1); 1453c10f4fbSBhawanpreet Lakha break; 1463c10f4fbSBhawanpreet Lakha case 9: 147*a013dd15SJudy Cai REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL, 148*a013dd15SJudy Cai VPG_GENERIC9_IMMEDIATE_UPDATE, 1); 1493c10f4fbSBhawanpreet Lakha break; 1503c10f4fbSBhawanpreet Lakha case 10: 151*a013dd15SJudy Cai REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL, 152*a013dd15SJudy Cai VPG_GENERIC10_IMMEDIATE_UPDATE, 1); 1533c10f4fbSBhawanpreet Lakha break; 1543c10f4fbSBhawanpreet Lakha case 11: 155*a013dd15SJudy Cai REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL, 156*a013dd15SJudy Cai VPG_GENERIC11_IMMEDIATE_UPDATE, 1); 1573c10f4fbSBhawanpreet Lakha break; 1583c10f4fbSBhawanpreet Lakha case 12: 159*a013dd15SJudy Cai REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL, 160*a013dd15SJudy Cai VPG_GENERIC12_IMMEDIATE_UPDATE, 1); 1613c10f4fbSBhawanpreet Lakha break; 1623c10f4fbSBhawanpreet Lakha case 13: 163*a013dd15SJudy Cai REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL, 164*a013dd15SJudy Cai VPG_GENERIC13_IMMEDIATE_UPDATE, 1); 1653c10f4fbSBhawanpreet Lakha break; 1663c10f4fbSBhawanpreet Lakha case 14: 167*a013dd15SJudy Cai REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL, 168*a013dd15SJudy Cai VPG_GENERIC14_IMMEDIATE_UPDATE, 1); 1693c10f4fbSBhawanpreet Lakha break; 1703c10f4fbSBhawanpreet Lakha default: 1713c10f4fbSBhawanpreet Lakha break; 1723c10f4fbSBhawanpreet Lakha } 1733c10f4fbSBhawanpreet Lakha } 1743c10f4fbSBhawanpreet Lakha 1753c10f4fbSBhawanpreet Lakha static struct vpg_funcs dcn30_vpg_funcs = { 1763c10f4fbSBhawanpreet Lakha .update_generic_info_packet = vpg3_update_generic_info_packet, 1773c10f4fbSBhawanpreet Lakha }; 1783c10f4fbSBhawanpreet Lakha 1793c10f4fbSBhawanpreet Lakha void vpg3_construct(struct dcn30_vpg *vpg3, 1803c10f4fbSBhawanpreet Lakha struct dc_context *ctx, 1813c10f4fbSBhawanpreet Lakha uint32_t inst, 1823c10f4fbSBhawanpreet Lakha const struct dcn30_vpg_registers *vpg_regs, 1833c10f4fbSBhawanpreet Lakha const struct dcn30_vpg_shift *vpg_shift, 1843c10f4fbSBhawanpreet Lakha const struct dcn30_vpg_mask *vpg_mask) 1853c10f4fbSBhawanpreet Lakha { 1863c10f4fbSBhawanpreet Lakha vpg3->base.ctx = ctx; 1873c10f4fbSBhawanpreet Lakha 1883c10f4fbSBhawanpreet Lakha vpg3->base.inst = inst; 1893c10f4fbSBhawanpreet Lakha vpg3->base.funcs = &dcn30_vpg_funcs; 1903c10f4fbSBhawanpreet Lakha 1913c10f4fbSBhawanpreet Lakha vpg3->regs = vpg_regs; 1923c10f4fbSBhawanpreet Lakha vpg3->vpg_shift = vpg_shift; 1933c10f4fbSBhawanpreet Lakha vpg3->vpg_mask = vpg_mask; 1943c10f4fbSBhawanpreet Lakha } 195