1 /*
2  * Copyright 2020 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 
27 #include "dm_services.h"
28 #include "dc.h"
29 
30 #include "dcn30_init.h"
31 
32 #include "resource.h"
33 #include "include/irq_service_interface.h"
34 #include "dcn20/dcn20_resource.h"
35 
36 #include "dcn30_resource.h"
37 
38 #include "dcn10/dcn10_ipp.h"
39 #include "dcn30/dcn30_hubbub.h"
40 #include "dcn30/dcn30_mpc.h"
41 #include "dcn30/dcn30_hubp.h"
42 #include "irq/dcn30/irq_service_dcn30.h"
43 #include "dcn30/dcn30_dpp.h"
44 #include "dcn30/dcn30_optc.h"
45 #include "dcn20/dcn20_hwseq.h"
46 #include "dcn30/dcn30_hwseq.h"
47 #include "dce110/dce110_hw_sequencer.h"
48 #include "dcn30/dcn30_opp.h"
49 #include "dcn20/dcn20_dsc.h"
50 #include "dcn30/dcn30_vpg.h"
51 #include "dcn30/dcn30_afmt.h"
52 #include "dcn30/dcn30_dio_stream_encoder.h"
53 #include "dcn30/dcn30_dio_link_encoder.h"
54 #include "dce/dce_clock_source.h"
55 #include "dce/dce_audio.h"
56 #include "dce/dce_hwseq.h"
57 #include "clk_mgr.h"
58 #include "virtual/virtual_stream_encoder.h"
59 #include "dce110/dce110_resource.h"
60 #include "dml/display_mode_vba.h"
61 #include "dcn30/dcn30_dccg.h"
62 #include "dcn10/dcn10_resource.h"
63 #include "link.h"
64 #include "dce/dce_panel_cntl.h"
65 
66 #include "dcn30/dcn30_dwb.h"
67 #include "dcn30/dcn30_mmhubbub.h"
68 
69 #include "sienna_cichlid_ip_offset.h"
70 #include "dcn/dcn_3_0_0_offset.h"
71 #include "dcn/dcn_3_0_0_sh_mask.h"
72 
73 #include "nbio/nbio_7_4_offset.h"
74 
75 #include "dpcs/dpcs_3_0_0_offset.h"
76 #include "dpcs/dpcs_3_0_0_sh_mask.h"
77 
78 #include "mmhub/mmhub_2_0_0_offset.h"
79 #include "mmhub/mmhub_2_0_0_sh_mask.h"
80 
81 #include "reg_helper.h"
82 #include "dce/dmub_abm.h"
83 #include "dce/dmub_psr.h"
84 #include "dce/dce_aux.h"
85 #include "dce/dce_i2c.h"
86 
87 #include "dml/dcn30/dcn30_fpu.h"
88 #include "dml/dcn30/display_mode_vba_30.h"
89 #include "vm_helper.h"
90 #include "dcn20/dcn20_vmid.h"
91 #include "amdgpu_socbb.h"
92 #include "dc_dmub_srv.h"
93 
94 #define DC_LOGGER_INIT(logger)
95 
96 enum dcn30_clk_src_array_id {
97 	DCN30_CLK_SRC_PLL0,
98 	DCN30_CLK_SRC_PLL1,
99 	DCN30_CLK_SRC_PLL2,
100 	DCN30_CLK_SRC_PLL3,
101 	DCN30_CLK_SRC_PLL4,
102 	DCN30_CLK_SRC_PLL5,
103 	DCN30_CLK_SRC_TOTAL
104 };
105 
106 /* begin *********************
107  * macros to expend register list macro defined in HW object header file
108  */
109 
110 /* DCN */
111 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
112 
113 #define BASE(seg) BASE_INNER(seg)
114 
115 #define SR(reg_name)\
116 		.reg_name = BASE(mm ## reg_name ## _BASE_IDX) +  \
117 					mm ## reg_name
118 
119 #define SRI(reg_name, block, id)\
120 	.reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
121 					mm ## block ## id ## _ ## reg_name
122 
123 #define SRI2(reg_name, block, id)\
124 	.reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
125 					mm ## reg_name
126 
127 #define SRIR(var_name, reg_name, block, id)\
128 	.var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
129 					mm ## block ## id ## _ ## reg_name
130 
131 #define SRII(reg_name, block, id)\
132 	.reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
133 					mm ## block ## id ## _ ## reg_name
134 
135 #define SRII_MPC_RMU(reg_name, block, id)\
136 	.RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
137 					mm ## block ## id ## _ ## reg_name
138 
139 #define SRII_DWB(reg_name, temp_name, block, id)\
140 	.reg_name[id] = BASE(mm ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
141 					mm ## block ## id ## _ ## temp_name
142 
143 #define SF_DWB2(reg_name, block, id, field_name, post_fix)	\
144 	.field_name = reg_name ## __ ## field_name ## post_fix
145 
146 #define DCCG_SRII(reg_name, block, id)\
147 	.block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
148 					mm ## block ## id ## _ ## reg_name
149 
150 #define VUPDATE_SRII(reg_name, block, id)\
151 	.reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
152 					mm ## reg_name ## _ ## block ## id
153 
154 /* NBIO */
155 #define NBIO_BASE_INNER(seg) \
156 	NBIO_BASE__INST0_SEG ## seg
157 
158 #define NBIO_BASE(seg) \
159 	NBIO_BASE_INNER(seg)
160 
161 #define NBIO_SR(reg_name)\
162 		.reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
163 					mm ## reg_name
164 
165 /* MMHUB */
166 #define MMHUB_BASE_INNER(seg) \
167 	MMHUB_BASE__INST0_SEG ## seg
168 
169 #define MMHUB_BASE(seg) \
170 	MMHUB_BASE_INNER(seg)
171 
172 #define MMHUB_SR(reg_name)\
173 		.reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \
174 					mmMM ## reg_name
175 
176 /* CLOCK */
177 #define CLK_BASE_INNER(seg) \
178 	CLK_BASE__INST0_SEG ## seg
179 
180 #define CLK_BASE(seg) \
181 	CLK_BASE_INNER(seg)
182 
183 #define CLK_SRI(reg_name, block, inst)\
184 	.reg_name = CLK_BASE(mm ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \
185 					mm ## block ## _ ## inst ## _ ## reg_name
186 
187 
188 static const struct bios_registers bios_regs = {
189 		NBIO_SR(BIOS_SCRATCH_3),
190 		NBIO_SR(BIOS_SCRATCH_6)
191 };
192 
193 #define clk_src_regs(index, pllid)\
194 [index] = {\
195 	CS_COMMON_REG_LIST_DCN2_0(index, pllid),\
196 }
197 
198 static const struct dce110_clk_src_regs clk_src_regs[] = {
199 	clk_src_regs(0, A),
200 	clk_src_regs(1, B),
201 	clk_src_regs(2, C),
202 	clk_src_regs(3, D),
203 	clk_src_regs(4, E),
204 	clk_src_regs(5, F)
205 };
206 
207 static const struct dce110_clk_src_shift cs_shift = {
208 		CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
209 };
210 
211 static const struct dce110_clk_src_mask cs_mask = {
212 		CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
213 };
214 
215 #define abm_regs(id)\
216 [id] = {\
217 		ABM_DCN30_REG_LIST(id)\
218 }
219 
220 static const struct dce_abm_registers abm_regs[] = {
221 		abm_regs(0),
222 		abm_regs(1),
223 		abm_regs(2),
224 		abm_regs(3),
225 		abm_regs(4),
226 		abm_regs(5),
227 };
228 
229 static const struct dce_abm_shift abm_shift = {
230 		ABM_MASK_SH_LIST_DCN30(__SHIFT)
231 };
232 
233 static const struct dce_abm_mask abm_mask = {
234 		ABM_MASK_SH_LIST_DCN30(_MASK)
235 };
236 
237 
238 
239 #define audio_regs(id)\
240 [id] = {\
241 		AUD_COMMON_REG_LIST(id)\
242 }
243 
244 static const struct dce_audio_registers audio_regs[] = {
245 	audio_regs(0),
246 	audio_regs(1),
247 	audio_regs(2),
248 	audio_regs(3),
249 	audio_regs(4),
250 	audio_regs(5),
251 	audio_regs(6)
252 };
253 
254 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
255 		SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
256 		SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
257 		AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
258 
259 static const struct dce_audio_shift audio_shift = {
260 		DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
261 };
262 
263 static const struct dce_audio_mask audio_mask = {
264 		DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
265 };
266 
267 #define vpg_regs(id)\
268 [id] = {\
269 	VPG_DCN3_REG_LIST(id)\
270 }
271 
272 static const struct dcn30_vpg_registers vpg_regs[] = {
273 	vpg_regs(0),
274 	vpg_regs(1),
275 	vpg_regs(2),
276 	vpg_regs(3),
277 	vpg_regs(4),
278 	vpg_regs(5),
279 	vpg_regs(6),
280 };
281 
282 static const struct dcn30_vpg_shift vpg_shift = {
283 	DCN3_VPG_MASK_SH_LIST(__SHIFT)
284 };
285 
286 static const struct dcn30_vpg_mask vpg_mask = {
287 	DCN3_VPG_MASK_SH_LIST(_MASK)
288 };
289 
290 #define afmt_regs(id)\
291 [id] = {\
292 	AFMT_DCN3_REG_LIST(id)\
293 }
294 
295 static const struct dcn30_afmt_registers afmt_regs[] = {
296 	afmt_regs(0),
297 	afmt_regs(1),
298 	afmt_regs(2),
299 	afmt_regs(3),
300 	afmt_regs(4),
301 	afmt_regs(5),
302 	afmt_regs(6),
303 };
304 
305 static const struct dcn30_afmt_shift afmt_shift = {
306 	DCN3_AFMT_MASK_SH_LIST(__SHIFT)
307 };
308 
309 static const struct dcn30_afmt_mask afmt_mask = {
310 	DCN3_AFMT_MASK_SH_LIST(_MASK)
311 };
312 
313 #define stream_enc_regs(id)\
314 [id] = {\
315 	SE_DCN3_REG_LIST(id)\
316 }
317 
318 static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
319 	stream_enc_regs(0),
320 	stream_enc_regs(1),
321 	stream_enc_regs(2),
322 	stream_enc_regs(3),
323 	stream_enc_regs(4),
324 	stream_enc_regs(5)
325 };
326 
327 static const struct dcn10_stream_encoder_shift se_shift = {
328 		SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
329 };
330 
331 static const struct dcn10_stream_encoder_mask se_mask = {
332 		SE_COMMON_MASK_SH_LIST_DCN30(_MASK)
333 };
334 
335 
336 #define aux_regs(id)\
337 [id] = {\
338 	DCN2_AUX_REG_LIST(id)\
339 }
340 
341 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
342 		aux_regs(0),
343 		aux_regs(1),
344 		aux_regs(2),
345 		aux_regs(3),
346 		aux_regs(4),
347 		aux_regs(5)
348 };
349 
350 #define hpd_regs(id)\
351 [id] = {\
352 	HPD_REG_LIST(id)\
353 }
354 
355 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
356 		hpd_regs(0),
357 		hpd_regs(1),
358 		hpd_regs(2),
359 		hpd_regs(3),
360 		hpd_regs(4),
361 		hpd_regs(5)
362 };
363 
364 #define link_regs(id, phyid)\
365 [id] = {\
366 	LE_DCN3_REG_LIST(id), \
367 	UNIPHY_DCN2_REG_LIST(phyid), \
368 	DPCS_DCN2_REG_LIST(id), \
369 	SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
370 }
371 
372 static const struct dce110_aux_registers_shift aux_shift = {
373 	DCN_AUX_MASK_SH_LIST(__SHIFT)
374 };
375 
376 static const struct dce110_aux_registers_mask aux_mask = {
377 	DCN_AUX_MASK_SH_LIST(_MASK)
378 };
379 
380 static const struct dcn10_link_enc_registers link_enc_regs[] = {
381 	link_regs(0, A),
382 	link_regs(1, B),
383 	link_regs(2, C),
384 	link_regs(3, D),
385 	link_regs(4, E),
386 	link_regs(5, F)
387 };
388 
389 static const struct dcn10_link_enc_shift le_shift = {
390 	LINK_ENCODER_MASK_SH_LIST_DCN30(__SHIFT),\
391 	DPCS_DCN2_MASK_SH_LIST(__SHIFT)
392 };
393 
394 static const struct dcn10_link_enc_mask le_mask = {
395 	LINK_ENCODER_MASK_SH_LIST_DCN30(_MASK),\
396 	DPCS_DCN2_MASK_SH_LIST(_MASK)
397 };
398 
399 
400 static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
401 	{ DCN_PANEL_CNTL_REG_LIST() }
402 };
403 
404 static const struct dce_panel_cntl_shift panel_cntl_shift = {
405 	DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
406 };
407 
408 static const struct dce_panel_cntl_mask panel_cntl_mask = {
409 	DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
410 };
411 
412 #define dpp_regs(id)\
413 [id] = {\
414 	DPP_REG_LIST_DCN30(id),\
415 }
416 
417 static const struct dcn3_dpp_registers dpp_regs[] = {
418 	dpp_regs(0),
419 	dpp_regs(1),
420 	dpp_regs(2),
421 	dpp_regs(3),
422 	dpp_regs(4),
423 	dpp_regs(5),
424 };
425 
426 static const struct dcn3_dpp_shift tf_shift = {
427 		DPP_REG_LIST_SH_MASK_DCN30(__SHIFT)
428 };
429 
430 static const struct dcn3_dpp_mask tf_mask = {
431 		DPP_REG_LIST_SH_MASK_DCN30(_MASK)
432 };
433 
434 #define opp_regs(id)\
435 [id] = {\
436 	OPP_REG_LIST_DCN30(id),\
437 }
438 
439 static const struct dcn20_opp_registers opp_regs[] = {
440 	opp_regs(0),
441 	opp_regs(1),
442 	opp_regs(2),
443 	opp_regs(3),
444 	opp_regs(4),
445 	opp_regs(5)
446 };
447 
448 static const struct dcn20_opp_shift opp_shift = {
449 	OPP_MASK_SH_LIST_DCN20(__SHIFT)
450 };
451 
452 static const struct dcn20_opp_mask opp_mask = {
453 	OPP_MASK_SH_LIST_DCN20(_MASK)
454 };
455 
456 #define aux_engine_regs(id)\
457 [id] = {\
458 	AUX_COMMON_REG_LIST0(id), \
459 	.AUXN_IMPCAL = 0, \
460 	.AUXP_IMPCAL = 0, \
461 	.AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
462 }
463 
464 static const struct dce110_aux_registers aux_engine_regs[] = {
465 		aux_engine_regs(0),
466 		aux_engine_regs(1),
467 		aux_engine_regs(2),
468 		aux_engine_regs(3),
469 		aux_engine_regs(4),
470 		aux_engine_regs(5)
471 };
472 
473 #define dwbc_regs_dcn3(id)\
474 [id] = {\
475 	DWBC_COMMON_REG_LIST_DCN30(id),\
476 }
477 
478 static const struct dcn30_dwbc_registers dwbc30_regs[] = {
479 	dwbc_regs_dcn3(0),
480 };
481 
482 static const struct dcn30_dwbc_shift dwbc30_shift = {
483 	DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
484 };
485 
486 static const struct dcn30_dwbc_mask dwbc30_mask = {
487 	DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
488 };
489 
490 #define mcif_wb_regs_dcn3(id)\
491 [id] = {\
492 	MCIF_WB_COMMON_REG_LIST_DCN30(id),\
493 }
494 
495 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = {
496 	mcif_wb_regs_dcn3(0)
497 };
498 
499 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
500 	MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
501 };
502 
503 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
504 	MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK)
505 };
506 
507 #define dsc_regsDCN20(id)\
508 [id] = {\
509 	DSC_REG_LIST_DCN20(id)\
510 }
511 
512 static const struct dcn20_dsc_registers dsc_regs[] = {
513 	dsc_regsDCN20(0),
514 	dsc_regsDCN20(1),
515 	dsc_regsDCN20(2),
516 	dsc_regsDCN20(3),
517 	dsc_regsDCN20(4),
518 	dsc_regsDCN20(5)
519 };
520 
521 static const struct dcn20_dsc_shift dsc_shift = {
522 	DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
523 };
524 
525 static const struct dcn20_dsc_mask dsc_mask = {
526 	DSC_REG_LIST_SH_MASK_DCN20(_MASK)
527 };
528 
529 static const struct dcn30_mpc_registers mpc_regs = {
530 		MPC_REG_LIST_DCN3_0(0),
531 		MPC_REG_LIST_DCN3_0(1),
532 		MPC_REG_LIST_DCN3_0(2),
533 		MPC_REG_LIST_DCN3_0(3),
534 		MPC_REG_LIST_DCN3_0(4),
535 		MPC_REG_LIST_DCN3_0(5),
536 		MPC_OUT_MUX_REG_LIST_DCN3_0(0),
537 		MPC_OUT_MUX_REG_LIST_DCN3_0(1),
538 		MPC_OUT_MUX_REG_LIST_DCN3_0(2),
539 		MPC_OUT_MUX_REG_LIST_DCN3_0(3),
540 		MPC_OUT_MUX_REG_LIST_DCN3_0(4),
541 		MPC_OUT_MUX_REG_LIST_DCN3_0(5),
542 		MPC_RMU_GLOBAL_REG_LIST_DCN3AG,
543 		MPC_RMU_REG_LIST_DCN3AG(0),
544 		MPC_RMU_REG_LIST_DCN3AG(1),
545 		MPC_RMU_REG_LIST_DCN3AG(2),
546 		MPC_DWB_MUX_REG_LIST_DCN3_0(0),
547 };
548 
549 static const struct dcn30_mpc_shift mpc_shift = {
550 	MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
551 };
552 
553 static const struct dcn30_mpc_mask mpc_mask = {
554 	MPC_COMMON_MASK_SH_LIST_DCN30(_MASK)
555 };
556 
557 #define optc_regs(id)\
558 [id] = {OPTC_COMMON_REG_LIST_DCN3_0(id)}
559 
560 
561 static const struct dcn_optc_registers optc_regs[] = {
562 	optc_regs(0),
563 	optc_regs(1),
564 	optc_regs(2),
565 	optc_regs(3),
566 	optc_regs(4),
567 	optc_regs(5)
568 };
569 
570 static const struct dcn_optc_shift optc_shift = {
571 	OPTC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
572 };
573 
574 static const struct dcn_optc_mask optc_mask = {
575 	OPTC_COMMON_MASK_SH_LIST_DCN30(_MASK)
576 };
577 
578 #define hubp_regs(id)\
579 [id] = {\
580 	HUBP_REG_LIST_DCN30(id)\
581 }
582 
583 static const struct dcn_hubp2_registers hubp_regs[] = {
584 		hubp_regs(0),
585 		hubp_regs(1),
586 		hubp_regs(2),
587 		hubp_regs(3),
588 		hubp_regs(4),
589 		hubp_regs(5)
590 };
591 
592 static const struct dcn_hubp2_shift hubp_shift = {
593 		HUBP_MASK_SH_LIST_DCN30(__SHIFT)
594 };
595 
596 static const struct dcn_hubp2_mask hubp_mask = {
597 		HUBP_MASK_SH_LIST_DCN30(_MASK)
598 };
599 
600 static const struct dcn_hubbub_registers hubbub_reg = {
601 		HUBBUB_REG_LIST_DCN30(0)
602 };
603 
604 static const struct dcn_hubbub_shift hubbub_shift = {
605 		HUBBUB_MASK_SH_LIST_DCN30(__SHIFT)
606 };
607 
608 static const struct dcn_hubbub_mask hubbub_mask = {
609 		HUBBUB_MASK_SH_LIST_DCN30(_MASK)
610 };
611 
612 static const struct dccg_registers dccg_regs = {
613 		DCCG_REG_LIST_DCN30()
614 };
615 
616 static const struct dccg_shift dccg_shift = {
617 		DCCG_MASK_SH_LIST_DCN3(__SHIFT)
618 };
619 
620 static const struct dccg_mask dccg_mask = {
621 		DCCG_MASK_SH_LIST_DCN3(_MASK)
622 };
623 
624 static const struct dce_hwseq_registers hwseq_reg = {
625 		HWSEQ_DCN30_REG_LIST()
626 };
627 
628 static const struct dce_hwseq_shift hwseq_shift = {
629 		HWSEQ_DCN30_MASK_SH_LIST(__SHIFT)
630 };
631 
632 static const struct dce_hwseq_mask hwseq_mask = {
633 		HWSEQ_DCN30_MASK_SH_LIST(_MASK)
634 };
635 #define vmid_regs(id)\
636 [id] = {\
637 		DCN20_VMID_REG_LIST(id)\
638 }
639 
640 static const struct dcn_vmid_registers vmid_regs[] = {
641 	vmid_regs(0),
642 	vmid_regs(1),
643 	vmid_regs(2),
644 	vmid_regs(3),
645 	vmid_regs(4),
646 	vmid_regs(5),
647 	vmid_regs(6),
648 	vmid_regs(7),
649 	vmid_regs(8),
650 	vmid_regs(9),
651 	vmid_regs(10),
652 	vmid_regs(11),
653 	vmid_regs(12),
654 	vmid_regs(13),
655 	vmid_regs(14),
656 	vmid_regs(15)
657 };
658 
659 static const struct dcn20_vmid_shift vmid_shifts = {
660 		DCN20_VMID_MASK_SH_LIST(__SHIFT)
661 };
662 
663 static const struct dcn20_vmid_mask vmid_masks = {
664 		DCN20_VMID_MASK_SH_LIST(_MASK)
665 };
666 
667 static const struct resource_caps res_cap_dcn3 = {
668 	.num_timing_generator = 6,
669 	.num_opp = 6,
670 	.num_video_plane = 6,
671 	.num_audio = 6,
672 	.num_stream_encoder = 6,
673 	.num_pll = 6,
674 	.num_dwb = 1,
675 	.num_ddc = 6,
676 	.num_vmid = 16,
677 	.num_mpc_3dlut = 3,
678 	.num_dsc = 6,
679 };
680 
681 static const struct dc_plane_cap plane_cap = {
682 	.type = DC_PLANE_TYPE_DCN_UNIVERSAL,
683 	.per_pixel_alpha = true,
684 
685 	.pixel_format_support = {
686 			.argb8888 = true,
687 			.nv12 = true,
688 			.fp16 = true,
689 			.p010 = true,
690 			.ayuv = false,
691 	},
692 
693 	.max_upscale_factor = {
694 			.argb8888 = 16000,
695 			.nv12 = 16000,
696 			.fp16 = 16000
697 	},
698 
699 	/* 6:1 downscaling ratio: 1000/6 = 166.666 */
700 	.max_downscale_factor = {
701 			.argb8888 = 167,
702 			.nv12 = 167,
703 			.fp16 = 167
704 	},
705 	16,
706 	16
707 };
708 
709 static const struct dc_debug_options debug_defaults_drv = {
710 	.disable_dmcu = true, //No DMCU on DCN30
711 	.force_abm_enable = false,
712 	.timing_trace = false,
713 	.clock_trace = true,
714 	.disable_pplib_clock_request = true,
715 	.pipe_split_policy = MPC_SPLIT_DYNAMIC,
716 	.force_single_disp_pipe_split = false,
717 	.disable_dcc = DCC_ENABLE,
718 	.vsr_support = true,
719 	.performance_trace = false,
720 	.max_downscale_src_width = 7680,/*upto 8K*/
721 	.disable_pplib_wm_range = false,
722 	.scl_reset_length10 = true,
723 	.sanity_checks = false,
724 	.underflow_assert_delay_us = 0xFFFFFFFF,
725 	.dwb_fi_phase = -1, // -1 = disable,
726 	.dmub_command_table = true,
727 	.use_max_lb = true,
728 	.exit_idle_opt_for_cursor_updates = true,
729 	.enable_legacy_fast_update = false,
730 };
731 
732 static const struct dc_panel_config panel_config_defaults = {
733 	.psr = {
734 		.disable_psr = false,
735 		.disallow_psrsu = false,
736 		.disallow_replay = false,
737 	},
738 };
739 
740 static void dcn30_dpp_destroy(struct dpp **dpp)
741 {
742 	kfree(TO_DCN20_DPP(*dpp));
743 	*dpp = NULL;
744 }
745 
746 static struct dpp *dcn30_dpp_create(
747 	struct dc_context *ctx,
748 	uint32_t inst)
749 {
750 	struct dcn3_dpp *dpp =
751 		kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);
752 
753 	if (!dpp)
754 		return NULL;
755 
756 	if (dpp3_construct(dpp, ctx, inst,
757 			&dpp_regs[inst], &tf_shift, &tf_mask))
758 		return &dpp->base;
759 
760 	BREAK_TO_DEBUGGER();
761 	kfree(dpp);
762 	return NULL;
763 }
764 
765 static struct output_pixel_processor *dcn30_opp_create(
766 	struct dc_context *ctx, uint32_t inst)
767 {
768 	struct dcn20_opp *opp =
769 		kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
770 
771 	if (!opp) {
772 		BREAK_TO_DEBUGGER();
773 		return NULL;
774 	}
775 
776 	dcn20_opp_construct(opp, ctx, inst,
777 			&opp_regs[inst], &opp_shift, &opp_mask);
778 	return &opp->base;
779 }
780 
781 static struct dce_aux *dcn30_aux_engine_create(
782 	struct dc_context *ctx,
783 	uint32_t inst)
784 {
785 	struct aux_engine_dce110 *aux_engine =
786 		kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
787 
788 	if (!aux_engine)
789 		return NULL;
790 
791 	dce110_aux_engine_construct(aux_engine, ctx, inst,
792 				    SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
793 				    &aux_engine_regs[inst],
794 					&aux_mask,
795 					&aux_shift,
796 					ctx->dc->caps.extended_aux_timeout_support);
797 
798 	return &aux_engine->base;
799 }
800 
801 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) }
802 
803 static const struct dce_i2c_registers i2c_hw_regs[] = {
804 		i2c_inst_regs(1),
805 		i2c_inst_regs(2),
806 		i2c_inst_regs(3),
807 		i2c_inst_regs(4),
808 		i2c_inst_regs(5),
809 		i2c_inst_regs(6),
810 };
811 
812 static const struct dce_i2c_shift i2c_shifts = {
813 		I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
814 };
815 
816 static const struct dce_i2c_mask i2c_masks = {
817 		I2C_COMMON_MASK_SH_LIST_DCN30(_MASK)
818 };
819 
820 static struct dce_i2c_hw *dcn30_i2c_hw_create(
821 	struct dc_context *ctx,
822 	uint32_t inst)
823 {
824 	struct dce_i2c_hw *dce_i2c_hw =
825 		kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
826 
827 	if (!dce_i2c_hw)
828 		return NULL;
829 
830 	dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
831 				    &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
832 
833 	return dce_i2c_hw;
834 }
835 
836 static struct mpc *dcn30_mpc_create(
837 		struct dc_context *ctx,
838 		int num_mpcc,
839 		int num_rmu)
840 {
841 	struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc),
842 					  GFP_KERNEL);
843 
844 	if (!mpc30)
845 		return NULL;
846 
847 	dcn30_mpc_construct(mpc30, ctx,
848 			&mpc_regs,
849 			&mpc_shift,
850 			&mpc_mask,
851 			num_mpcc,
852 			num_rmu);
853 
854 	return &mpc30->base;
855 }
856 
857 static struct hubbub *dcn30_hubbub_create(struct dc_context *ctx)
858 {
859 	int i;
860 
861 	struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub),
862 					  GFP_KERNEL);
863 
864 	if (!hubbub3)
865 		return NULL;
866 
867 	hubbub3_construct(hubbub3, ctx,
868 			&hubbub_reg,
869 			&hubbub_shift,
870 			&hubbub_mask);
871 
872 
873 	for (i = 0; i < res_cap_dcn3.num_vmid; i++) {
874 		struct dcn20_vmid *vmid = &hubbub3->vmid[i];
875 
876 		vmid->ctx = ctx;
877 
878 		vmid->regs = &vmid_regs[i];
879 		vmid->shifts = &vmid_shifts;
880 		vmid->masks = &vmid_masks;
881 	}
882 
883 	return &hubbub3->base;
884 }
885 
886 static struct timing_generator *dcn30_timing_generator_create(
887 		struct dc_context *ctx,
888 		uint32_t instance)
889 {
890 	struct optc *tgn10 =
891 		kzalloc(sizeof(struct optc), GFP_KERNEL);
892 
893 	if (!tgn10)
894 		return NULL;
895 
896 	tgn10->base.inst = instance;
897 	tgn10->base.ctx = ctx;
898 
899 	tgn10->tg_regs = &optc_regs[instance];
900 	tgn10->tg_shift = &optc_shift;
901 	tgn10->tg_mask = &optc_mask;
902 
903 	dcn30_timing_generator_init(tgn10);
904 
905 	return &tgn10->base;
906 }
907 
908 static const struct encoder_feature_support link_enc_feature = {
909 		.max_hdmi_deep_color = COLOR_DEPTH_121212,
910 		.max_hdmi_pixel_clock = 600000,
911 		.hdmi_ycbcr420_supported = true,
912 		.dp_ycbcr420_supported = true,
913 		.fec_supported = true,
914 		.flags.bits.IS_HBR2_CAPABLE = true,
915 		.flags.bits.IS_HBR3_CAPABLE = true,
916 		.flags.bits.IS_TPS3_CAPABLE = true,
917 		.flags.bits.IS_TPS4_CAPABLE = true
918 };
919 
920 static struct link_encoder *dcn30_link_encoder_create(
921 	struct dc_context *ctx,
922 	const struct encoder_init_data *enc_init_data)
923 {
924 	struct dcn20_link_encoder *enc20 =
925 		kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
926 
927 	if (!enc20)
928 		return NULL;
929 
930 	dcn30_link_encoder_construct(enc20,
931 			enc_init_data,
932 			&link_enc_feature,
933 			&link_enc_regs[enc_init_data->transmitter],
934 			&link_enc_aux_regs[enc_init_data->channel - 1],
935 			&link_enc_hpd_regs[enc_init_data->hpd_source],
936 			&le_shift,
937 			&le_mask);
938 
939 	return &enc20->enc10.base;
940 }
941 
942 static struct panel_cntl *dcn30_panel_cntl_create(const struct panel_cntl_init_data *init_data)
943 {
944 	struct dce_panel_cntl *panel_cntl =
945 		kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
946 
947 	if (!panel_cntl)
948 		return NULL;
949 
950 	dce_panel_cntl_construct(panel_cntl,
951 			init_data,
952 			&panel_cntl_regs[init_data->inst],
953 			&panel_cntl_shift,
954 			&panel_cntl_mask);
955 
956 	return &panel_cntl->base;
957 }
958 
959 static void read_dce_straps(
960 	struct dc_context *ctx,
961 	struct resource_straps *straps)
962 {
963 	generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
964 		FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
965 
966 }
967 
968 static struct audio *dcn30_create_audio(
969 		struct dc_context *ctx, unsigned int inst)
970 {
971 	return dce_audio_create(ctx, inst,
972 			&audio_regs[inst], &audio_shift, &audio_mask);
973 }
974 
975 static struct vpg *dcn30_vpg_create(
976 	struct dc_context *ctx,
977 	uint32_t inst)
978 {
979 	struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL);
980 
981 	if (!vpg3)
982 		return NULL;
983 
984 	vpg3_construct(vpg3, ctx, inst,
985 			&vpg_regs[inst],
986 			&vpg_shift,
987 			&vpg_mask);
988 
989 	return &vpg3->base;
990 }
991 
992 static struct afmt *dcn30_afmt_create(
993 	struct dc_context *ctx,
994 	uint32_t inst)
995 {
996 	struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL);
997 
998 	if (!afmt3)
999 		return NULL;
1000 
1001 	afmt3_construct(afmt3, ctx, inst,
1002 			&afmt_regs[inst],
1003 			&afmt_shift,
1004 			&afmt_mask);
1005 
1006 	return &afmt3->base;
1007 }
1008 
1009 static struct stream_encoder *dcn30_stream_encoder_create(enum engine_id eng_id,
1010 							  struct dc_context *ctx)
1011 {
1012 	struct dcn10_stream_encoder *enc1;
1013 	struct vpg *vpg;
1014 	struct afmt *afmt;
1015 	int vpg_inst;
1016 	int afmt_inst;
1017 
1018 	/* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
1019 	if (eng_id <= ENGINE_ID_DIGF) {
1020 		vpg_inst = eng_id;
1021 		afmt_inst = eng_id;
1022 	} else
1023 		return NULL;
1024 
1025 	enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1026 	vpg = dcn30_vpg_create(ctx, vpg_inst);
1027 	afmt = dcn30_afmt_create(ctx, afmt_inst);
1028 
1029 	if (!enc1 || !vpg || !afmt) {
1030 		kfree(enc1);
1031 		kfree(vpg);
1032 		kfree(afmt);
1033 		return NULL;
1034 	}
1035 
1036 	dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
1037 					eng_id, vpg, afmt,
1038 					&stream_enc_regs[eng_id],
1039 					&se_shift, &se_mask);
1040 
1041 	return &enc1->base;
1042 }
1043 
1044 static struct dce_hwseq *dcn30_hwseq_create(struct dc_context *ctx)
1045 {
1046 	struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1047 
1048 	if (hws) {
1049 		hws->ctx = ctx;
1050 		hws->regs = &hwseq_reg;
1051 		hws->shifts = &hwseq_shift;
1052 		hws->masks = &hwseq_mask;
1053 	}
1054 	return hws;
1055 }
1056 static const struct resource_create_funcs res_create_funcs = {
1057 	.read_dce_straps = read_dce_straps,
1058 	.create_audio = dcn30_create_audio,
1059 	.create_stream_encoder = dcn30_stream_encoder_create,
1060 	.create_hwseq = dcn30_hwseq_create,
1061 };
1062 
1063 static void dcn30_resource_destruct(struct dcn30_resource_pool *pool)
1064 {
1065 	unsigned int i;
1066 
1067 	for (i = 0; i < pool->base.stream_enc_count; i++) {
1068 		if (pool->base.stream_enc[i] != NULL) {
1069 			if (pool->base.stream_enc[i]->vpg != NULL) {
1070 				kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
1071 				pool->base.stream_enc[i]->vpg = NULL;
1072 			}
1073 			if (pool->base.stream_enc[i]->afmt != NULL) {
1074 				kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));
1075 				pool->base.stream_enc[i]->afmt = NULL;
1076 			}
1077 			kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1078 			pool->base.stream_enc[i] = NULL;
1079 		}
1080 	}
1081 
1082 	for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1083 		if (pool->base.dscs[i] != NULL)
1084 			dcn20_dsc_destroy(&pool->base.dscs[i]);
1085 	}
1086 
1087 	if (pool->base.mpc != NULL) {
1088 		kfree(TO_DCN20_MPC(pool->base.mpc));
1089 		pool->base.mpc = NULL;
1090 	}
1091 	if (pool->base.hubbub != NULL) {
1092 		kfree(pool->base.hubbub);
1093 		pool->base.hubbub = NULL;
1094 	}
1095 	for (i = 0; i < pool->base.pipe_count; i++) {
1096 		if (pool->base.dpps[i] != NULL)
1097 			dcn30_dpp_destroy(&pool->base.dpps[i]);
1098 
1099 		if (pool->base.ipps[i] != NULL)
1100 			pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1101 
1102 		if (pool->base.hubps[i] != NULL) {
1103 			kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1104 			pool->base.hubps[i] = NULL;
1105 		}
1106 
1107 		if (pool->base.irqs != NULL) {
1108 			dal_irq_service_destroy(&pool->base.irqs);
1109 		}
1110 	}
1111 
1112 	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1113 		if (pool->base.engines[i] != NULL)
1114 			dce110_engine_destroy(&pool->base.engines[i]);
1115 		if (pool->base.hw_i2cs[i] != NULL) {
1116 			kfree(pool->base.hw_i2cs[i]);
1117 			pool->base.hw_i2cs[i] = NULL;
1118 		}
1119 		if (pool->base.sw_i2cs[i] != NULL) {
1120 			kfree(pool->base.sw_i2cs[i]);
1121 			pool->base.sw_i2cs[i] = NULL;
1122 		}
1123 	}
1124 
1125 	for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1126 		if (pool->base.opps[i] != NULL)
1127 			pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1128 	}
1129 
1130 	for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1131 		if (pool->base.timing_generators[i] != NULL)	{
1132 			kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1133 			pool->base.timing_generators[i] = NULL;
1134 		}
1135 	}
1136 
1137 	for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1138 		if (pool->base.dwbc[i] != NULL) {
1139 			kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
1140 			pool->base.dwbc[i] = NULL;
1141 		}
1142 		if (pool->base.mcif_wb[i] != NULL) {
1143 			kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));
1144 			pool->base.mcif_wb[i] = NULL;
1145 		}
1146 	}
1147 
1148 	for (i = 0; i < pool->base.audio_count; i++) {
1149 		if (pool->base.audios[i])
1150 			dce_aud_destroy(&pool->base.audios[i]);
1151 	}
1152 
1153 	for (i = 0; i < pool->base.clk_src_count; i++) {
1154 		if (pool->base.clock_sources[i] != NULL) {
1155 			dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1156 			pool->base.clock_sources[i] = NULL;
1157 		}
1158 	}
1159 
1160 	for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
1161 		if (pool->base.mpc_lut[i] != NULL) {
1162 			dc_3dlut_func_release(pool->base.mpc_lut[i]);
1163 			pool->base.mpc_lut[i] = NULL;
1164 		}
1165 		if (pool->base.mpc_shaper[i] != NULL) {
1166 			dc_transfer_func_release(pool->base.mpc_shaper[i]);
1167 			pool->base.mpc_shaper[i] = NULL;
1168 		}
1169 	}
1170 
1171 	if (pool->base.dp_clock_source != NULL) {
1172 		dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1173 		pool->base.dp_clock_source = NULL;
1174 	}
1175 
1176 	for (i = 0; i < pool->base.pipe_count; i++) {
1177 		if (pool->base.multiple_abms[i] != NULL)
1178 			dce_abm_destroy(&pool->base.multiple_abms[i]);
1179 	}
1180 
1181 	if (pool->base.psr != NULL)
1182 		dmub_psr_destroy(&pool->base.psr);
1183 
1184 	if (pool->base.dccg != NULL)
1185 		dcn_dccg_destroy(&pool->base.dccg);
1186 
1187 	if (pool->base.oem_device != NULL) {
1188 		struct dc *dc = pool->base.oem_device->ctx->dc;
1189 
1190 		dc->link_srv->destroy_ddc_service(&pool->base.oem_device);
1191 	}
1192 }
1193 
1194 static struct hubp *dcn30_hubp_create(
1195 	struct dc_context *ctx,
1196 	uint32_t inst)
1197 {
1198 	struct dcn20_hubp *hubp2 =
1199 		kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
1200 
1201 	if (!hubp2)
1202 		return NULL;
1203 
1204 	if (hubp3_construct(hubp2, ctx, inst,
1205 			&hubp_regs[inst], &hubp_shift, &hubp_mask))
1206 		return &hubp2->base;
1207 
1208 	BREAK_TO_DEBUGGER();
1209 	kfree(hubp2);
1210 	return NULL;
1211 }
1212 
1213 static bool dcn30_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
1214 {
1215 	int i;
1216 	uint32_t pipe_count = pool->res_cap->num_dwb;
1217 
1218 	for (i = 0; i < pipe_count; i++) {
1219 		struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc),
1220 						    GFP_KERNEL);
1221 
1222 		if (!dwbc30) {
1223 			dm_error("DC: failed to create dwbc30!\n");
1224 			return false;
1225 		}
1226 
1227 		dcn30_dwbc_construct(dwbc30, ctx,
1228 				&dwbc30_regs[i],
1229 				&dwbc30_shift,
1230 				&dwbc30_mask,
1231 				i);
1232 
1233 		pool->dwbc[i] = &dwbc30->base;
1234 	}
1235 	return true;
1236 }
1237 
1238 static bool dcn30_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
1239 {
1240 	int i;
1241 	uint32_t pipe_count = pool->res_cap->num_dwb;
1242 
1243 	for (i = 0; i < pipe_count; i++) {
1244 		struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub),
1245 						    GFP_KERNEL);
1246 
1247 		if (!mcif_wb30) {
1248 			dm_error("DC: failed to create mcif_wb30!\n");
1249 			return false;
1250 		}
1251 
1252 		dcn30_mmhubbub_construct(mcif_wb30, ctx,
1253 				&mcif_wb30_regs[i],
1254 				&mcif_wb30_shift,
1255 				&mcif_wb30_mask,
1256 				i);
1257 
1258 		pool->mcif_wb[i] = &mcif_wb30->base;
1259 	}
1260 	return true;
1261 }
1262 
1263 static struct display_stream_compressor *dcn30_dsc_create(
1264 	struct dc_context *ctx, uint32_t inst)
1265 {
1266 	struct dcn20_dsc *dsc =
1267 		kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1268 
1269 	if (!dsc) {
1270 		BREAK_TO_DEBUGGER();
1271 		return NULL;
1272 	}
1273 
1274 	dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1275 	return &dsc->base;
1276 }
1277 
1278 enum dc_status dcn30_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream)
1279 {
1280 
1281 	return dcn20_add_stream_to_ctx(dc, new_ctx, dc_stream);
1282 }
1283 
1284 static void dcn30_destroy_resource_pool(struct resource_pool **pool)
1285 {
1286 	struct dcn30_resource_pool *dcn30_pool = TO_DCN30_RES_POOL(*pool);
1287 
1288 	dcn30_resource_destruct(dcn30_pool);
1289 	kfree(dcn30_pool);
1290 	*pool = NULL;
1291 }
1292 
1293 static struct clock_source *dcn30_clock_source_create(
1294 		struct dc_context *ctx,
1295 		struct dc_bios *bios,
1296 		enum clock_source_id id,
1297 		const struct dce110_clk_src_regs *regs,
1298 		bool dp_clk_src)
1299 {
1300 	struct dce110_clk_src *clk_src =
1301 		kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1302 
1303 	if (!clk_src)
1304 		return NULL;
1305 
1306 	if (dcn3_clk_src_construct(clk_src, ctx, bios, id,
1307 			regs, &cs_shift, &cs_mask)) {
1308 		clk_src->base.dp_clk_src = dp_clk_src;
1309 		return &clk_src->base;
1310 	}
1311 
1312 	kfree(clk_src);
1313 	BREAK_TO_DEBUGGER();
1314 	return NULL;
1315 }
1316 
1317 int dcn30_populate_dml_pipes_from_context(
1318 	struct dc *dc, struct dc_state *context,
1319 	display_e2e_pipe_params_st *pipes,
1320 	bool fast_validate)
1321 {
1322 	int i, pipe_cnt;
1323 	struct resource_context *res_ctx = &context->res_ctx;
1324 
1325 	DC_FP_START();
1326 	dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);
1327 	DC_FP_END();
1328 
1329 	for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1330 		if (!res_ctx->pipe_ctx[i].stream)
1331 			continue;
1332 
1333 		pipes[pipe_cnt++].pipe.scale_ratio_depth.lb_depth =
1334 			dm_lb_16;
1335 	}
1336 
1337 	return pipe_cnt;
1338 }
1339 
1340 void dcn30_populate_dml_writeback_from_context(
1341 	struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes)
1342 {
1343 	DC_FP_START();
1344 	dcn30_fpu_populate_dml_writeback_from_context(dc, res_ctx, pipes);
1345 	DC_FP_END();
1346 }
1347 
1348 unsigned int dcn30_calc_max_scaled_time(
1349 		unsigned int time_per_pixel,
1350 		enum mmhubbub_wbif_mode mode,
1351 		unsigned int urgent_watermark)
1352 {
1353 	unsigned int time_per_byte = 0;
1354 	unsigned int total_free_entry = 0xb40;
1355 	unsigned int buf_lh_capability;
1356 	unsigned int max_scaled_time;
1357 
1358 	if (mode == PACKED_444) /* packed mode 32 bpp */
1359 		time_per_byte = time_per_pixel/4;
1360 	else if (mode == PACKED_444_FP16) /* packed mode 64 bpp */
1361 		time_per_byte = time_per_pixel/8;
1362 
1363 	if (time_per_byte == 0)
1364 		time_per_byte = 1;
1365 
1366 	buf_lh_capability = (total_free_entry*time_per_byte*32) >> 6; /* time_per_byte is in u6.6*/
1367 	max_scaled_time   = buf_lh_capability - urgent_watermark;
1368 	return max_scaled_time;
1369 }
1370 
1371 void dcn30_set_mcif_arb_params(
1372 		struct dc *dc,
1373 		struct dc_state *context,
1374 		display_e2e_pipe_params_st *pipes,
1375 		int pipe_cnt)
1376 {
1377 	enum mmhubbub_wbif_mode wbif_mode;
1378 	struct display_mode_lib *dml = &context->bw_ctx.dml;
1379 	struct mcif_arb_params *wb_arb_params;
1380 	int i, j, dwb_pipe;
1381 
1382 	/* Writeback MCIF_WB arbitration parameters */
1383 	dwb_pipe = 0;
1384 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
1385 
1386 		if (!context->res_ctx.pipe_ctx[i].stream)
1387 			continue;
1388 
1389 		for (j = 0; j < MAX_DWB_PIPES; j++) {
1390 			struct dc_writeback_info *writeback_info = &context->res_ctx.pipe_ctx[i].stream->writeback_info[j];
1391 
1392 			if (writeback_info->wb_enabled == false)
1393 				continue;
1394 
1395 			//wb_arb_params = &context->res_ctx.pipe_ctx[i].stream->writeback_info[j].mcif_arb_params;
1396 			wb_arb_params = &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[dwb_pipe];
1397 
1398 			if (writeback_info->dwb_params.cnv_params.fc_out_format == DWB_OUT_FORMAT_64BPP_ARGB ||
1399 				writeback_info->dwb_params.cnv_params.fc_out_format == DWB_OUT_FORMAT_64BPP_RGBA)
1400 				wbif_mode = PACKED_444_FP16;
1401 			else
1402 				wbif_mode = PACKED_444;
1403 
1404 			DC_FP_START();
1405 			dcn30_fpu_set_mcif_arb_params(wb_arb_params, dml, pipes, pipe_cnt, j);
1406 			DC_FP_END();
1407 			wb_arb_params->time_per_pixel = (1000000 << 6) / context->res_ctx.pipe_ctx[i].stream->phy_pix_clk; /* time_per_pixel should be in u6.6 format */
1408 			wb_arb_params->slice_lines = 32;
1409 			wb_arb_params->arbitration_slice = 2; /* irrelevant since there is no YUV output */
1410 			wb_arb_params->max_scaled_time = dcn30_calc_max_scaled_time(wb_arb_params->time_per_pixel,
1411 					wbif_mode,
1412 					wb_arb_params->cli_watermark[0]); /* assume 4 watermark sets have the same value */
1413 
1414 			dwb_pipe++;
1415 
1416 			if (dwb_pipe >= MAX_DWB_PIPES)
1417 				return;
1418 		}
1419 		if (dwb_pipe >= MAX_DWB_PIPES)
1420 			return;
1421 	}
1422 
1423 }
1424 
1425 static struct dc_cap_funcs cap_funcs = {
1426 	.get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1427 };
1428 
1429 bool dcn30_acquire_post_bldn_3dlut(
1430 		struct resource_context *res_ctx,
1431 		const struct resource_pool *pool,
1432 		int mpcc_id,
1433 		struct dc_3dlut **lut,
1434 		struct dc_transfer_func **shaper)
1435 {
1436 	int i;
1437 	bool ret = false;
1438 	union dc_3dlut_state *state;
1439 
1440 	ASSERT(*lut == NULL && *shaper == NULL);
1441 	*lut = NULL;
1442 	*shaper = NULL;
1443 
1444 	for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) {
1445 		if (!res_ctx->is_mpc_3dlut_acquired[i]) {
1446 			*lut = pool->mpc_lut[i];
1447 			*shaper = pool->mpc_shaper[i];
1448 			state = &pool->mpc_lut[i]->state;
1449 			res_ctx->is_mpc_3dlut_acquired[i] = true;
1450 			state->bits.rmu_idx_valid = 1;
1451 			state->bits.rmu_mux_num = i;
1452 			if (state->bits.rmu_mux_num == 0)
1453 				state->bits.mpc_rmu0_mux = mpcc_id;
1454 			else if (state->bits.rmu_mux_num == 1)
1455 				state->bits.mpc_rmu1_mux = mpcc_id;
1456 			else if (state->bits.rmu_mux_num == 2)
1457 				state->bits.mpc_rmu2_mux = mpcc_id;
1458 			ret = true;
1459 			break;
1460 		}
1461 	}
1462 	return ret;
1463 }
1464 
1465 bool dcn30_release_post_bldn_3dlut(
1466 		struct resource_context *res_ctx,
1467 		const struct resource_pool *pool,
1468 		struct dc_3dlut **lut,
1469 		struct dc_transfer_func **shaper)
1470 {
1471 	int i;
1472 	bool ret = false;
1473 
1474 	for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) {
1475 		if (pool->mpc_lut[i] == *lut && pool->mpc_shaper[i] == *shaper) {
1476 			res_ctx->is_mpc_3dlut_acquired[i] = false;
1477 			pool->mpc_lut[i]->state.raw = 0;
1478 			*lut = NULL;
1479 			*shaper = NULL;
1480 			ret = true;
1481 			break;
1482 		}
1483 	}
1484 	return ret;
1485 }
1486 
1487 static bool is_soc_bounding_box_valid(struct dc *dc)
1488 {
1489 	uint32_t hw_internal_rev = dc->ctx->asic_id.hw_internal_rev;
1490 
1491 	if (ASICREV_IS_SIENNA_CICHLID_P(hw_internal_rev))
1492 		return true;
1493 
1494 	return false;
1495 }
1496 
1497 static bool init_soc_bounding_box(struct dc *dc,
1498 				  struct dcn30_resource_pool *pool)
1499 {
1500 	struct _vcs_dpi_soc_bounding_box_st *loaded_bb = &dcn3_0_soc;
1501 	struct _vcs_dpi_ip_params_st *loaded_ip = &dcn3_0_ip;
1502 
1503 	DC_LOGGER_INIT(dc->ctx->logger);
1504 
1505 	if (!is_soc_bounding_box_valid(dc)) {
1506 		DC_LOG_ERROR("%s: not valid soc bounding box\n", __func__);
1507 		return false;
1508 	}
1509 
1510 	loaded_ip->max_num_otg = pool->base.res_cap->num_timing_generator;
1511 	loaded_ip->max_num_dpp = pool->base.pipe_count;
1512 	loaded_ip->clamp_min_dcfclk = dc->config.clamp_min_dcfclk;
1513 	dcn20_patch_bounding_box(dc, loaded_bb);
1514 	DC_FP_START();
1515 	patch_dcn30_soc_bounding_box(dc, &dcn3_0_soc);
1516 	DC_FP_END();
1517 
1518 	return true;
1519 }
1520 
1521 static bool dcn30_split_stream_for_mpc_or_odm(
1522 		const struct dc *dc,
1523 		struct resource_context *res_ctx,
1524 		struct pipe_ctx *pri_pipe,
1525 		struct pipe_ctx *sec_pipe,
1526 		bool odm)
1527 {
1528 	int pipe_idx = sec_pipe->pipe_idx;
1529 	const struct resource_pool *pool = dc->res_pool;
1530 
1531 	*sec_pipe = *pri_pipe;
1532 
1533 	sec_pipe->pipe_idx = pipe_idx;
1534 	sec_pipe->plane_res.mi = pool->mis[pipe_idx];
1535 	sec_pipe->plane_res.hubp = pool->hubps[pipe_idx];
1536 	sec_pipe->plane_res.ipp = pool->ipps[pipe_idx];
1537 	sec_pipe->plane_res.xfm = pool->transforms[pipe_idx];
1538 	sec_pipe->plane_res.dpp = pool->dpps[pipe_idx];
1539 	sec_pipe->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst;
1540 	sec_pipe->stream_res.dsc = NULL;
1541 	if (odm) {
1542 		if (pri_pipe->next_odm_pipe) {
1543 			ASSERT(pri_pipe->next_odm_pipe != sec_pipe);
1544 			sec_pipe->next_odm_pipe = pri_pipe->next_odm_pipe;
1545 			sec_pipe->next_odm_pipe->prev_odm_pipe = sec_pipe;
1546 		}
1547 		if (pri_pipe->top_pipe && pri_pipe->top_pipe->next_odm_pipe) {
1548 			pri_pipe->top_pipe->next_odm_pipe->bottom_pipe = sec_pipe;
1549 			sec_pipe->top_pipe = pri_pipe->top_pipe->next_odm_pipe;
1550 		}
1551 		if (pri_pipe->bottom_pipe && pri_pipe->bottom_pipe->next_odm_pipe) {
1552 			pri_pipe->bottom_pipe->next_odm_pipe->top_pipe = sec_pipe;
1553 			sec_pipe->bottom_pipe = pri_pipe->bottom_pipe->next_odm_pipe;
1554 		}
1555 		pri_pipe->next_odm_pipe = sec_pipe;
1556 		sec_pipe->prev_odm_pipe = pri_pipe;
1557 
1558 		if (!sec_pipe->top_pipe)
1559 			sec_pipe->stream_res.opp = pool->opps[pipe_idx];
1560 		else
1561 			sec_pipe->stream_res.opp = sec_pipe->top_pipe->stream_res.opp;
1562 		if (sec_pipe->stream->timing.flags.DSC == 1) {
1563 			dcn20_acquire_dsc(dc, res_ctx, &sec_pipe->stream_res.dsc, pipe_idx);
1564 			ASSERT(sec_pipe->stream_res.dsc);
1565 			if (sec_pipe->stream_res.dsc == NULL)
1566 				return false;
1567 		}
1568 	} else {
1569 		if (pri_pipe->bottom_pipe) {
1570 			ASSERT(pri_pipe->bottom_pipe != sec_pipe);
1571 			sec_pipe->bottom_pipe = pri_pipe->bottom_pipe;
1572 			sec_pipe->bottom_pipe->top_pipe = sec_pipe;
1573 		}
1574 		pri_pipe->bottom_pipe = sec_pipe;
1575 		sec_pipe->top_pipe = pri_pipe;
1576 
1577 		ASSERT(pri_pipe->plane_state);
1578 	}
1579 
1580 	return true;
1581 }
1582 
1583 static struct pipe_ctx *dcn30_find_split_pipe(
1584 		struct dc *dc,
1585 		struct dc_state *context,
1586 		int old_index)
1587 {
1588 	struct pipe_ctx *pipe = NULL;
1589 	int i;
1590 
1591 	if (old_index >= 0 && context->res_ctx.pipe_ctx[old_index].stream == NULL) {
1592 		pipe = &context->res_ctx.pipe_ctx[old_index];
1593 		pipe->pipe_idx = old_index;
1594 	}
1595 
1596 	if (!pipe)
1597 		for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) {
1598 			if (dc->current_state->res_ctx.pipe_ctx[i].top_pipe == NULL
1599 					&& dc->current_state->res_ctx.pipe_ctx[i].prev_odm_pipe == NULL) {
1600 				if (context->res_ctx.pipe_ctx[i].stream == NULL) {
1601 					pipe = &context->res_ctx.pipe_ctx[i];
1602 					pipe->pipe_idx = i;
1603 					break;
1604 				}
1605 			}
1606 		}
1607 
1608 	/*
1609 	 * May need to fix pipes getting tossed from 1 opp to another on flip
1610 	 * Add for debugging transient underflow during topology updates:
1611 	 * ASSERT(pipe);
1612 	 */
1613 	if (!pipe)
1614 		for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) {
1615 			if (context->res_ctx.pipe_ctx[i].stream == NULL) {
1616 				pipe = &context->res_ctx.pipe_ctx[i];
1617 				pipe->pipe_idx = i;
1618 				break;
1619 			}
1620 		}
1621 
1622 	return pipe;
1623 }
1624 
1625 noinline bool dcn30_internal_validate_bw(
1626 		struct dc *dc,
1627 		struct dc_state *context,
1628 		display_e2e_pipe_params_st *pipes,
1629 		int *pipe_cnt_out,
1630 		int *vlevel_out,
1631 		bool fast_validate,
1632 		bool allow_self_refresh_only)
1633 {
1634 	bool out = false;
1635 	bool repopulate_pipes = false;
1636 	int split[MAX_PIPES] = { 0 };
1637 	bool merge[MAX_PIPES] = { false };
1638 	bool newly_split[MAX_PIPES] = { false };
1639 	int pipe_cnt, i, pipe_idx, vlevel;
1640 	struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
1641 
1642 	ASSERT(pipes);
1643 	if (!pipes)
1644 		return false;
1645 
1646 	context->bw_ctx.dml.vba.maxMpcComb = 0;
1647 	context->bw_ctx.dml.vba.VoltageLevel = 0;
1648 	context->bw_ctx.dml.vba.DRAMClockChangeSupport[0][0] = dm_dram_clock_change_vactive;
1649 	dc->res_pool->funcs->update_soc_for_wm_a(dc, context);
1650 	pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate);
1651 
1652 	if (!pipe_cnt) {
1653 		out = true;
1654 		goto validate_out;
1655 	}
1656 
1657 	dml_log_pipe_params(&context->bw_ctx.dml, pipes, pipe_cnt);
1658 
1659 	if (!fast_validate || !allow_self_refresh_only) {
1660 		/*
1661 		 * DML favors voltage over p-state, but we're more interested in
1662 		 * supporting p-state over voltage. We can't support p-state in
1663 		 * prefetch mode > 0 so try capping the prefetch mode to start.
1664 		 */
1665 		context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank =
1666 			dm_allow_self_refresh_and_mclk_switch;
1667 		vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
1668 		/* This may adjust vlevel and maxMpcComb */
1669 		if (vlevel < context->bw_ctx.dml.soc.num_states)
1670 			vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge);
1671 	}
1672 	if (allow_self_refresh_only &&
1673 	    (fast_validate || vlevel == context->bw_ctx.dml.soc.num_states ||
1674 			vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported)) {
1675 		/*
1676 		 * If mode is unsupported or there's still no p-state support
1677 		 * then fall back to favoring voltage.
1678 		 *
1679 		 * We don't actually support prefetch mode 2, so require that we
1680 		 * at least support prefetch mode 1.
1681 		 */
1682 		context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank =
1683 			dm_allow_self_refresh;
1684 
1685 		vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
1686 		if (vlevel < context->bw_ctx.dml.soc.num_states) {
1687 			memset(split, 0, sizeof(split));
1688 			memset(merge, 0, sizeof(merge));
1689 			vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge);
1690 		}
1691 	}
1692 
1693 	dml_log_mode_support_params(&context->bw_ctx.dml);
1694 
1695 	if (vlevel == context->bw_ctx.dml.soc.num_states)
1696 		goto validate_fail;
1697 
1698 	if (!dc->config.enable_windowed_mpo_odm) {
1699 		for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
1700 			struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1701 			struct pipe_ctx *mpo_pipe = pipe->bottom_pipe;
1702 
1703 			if (!pipe->stream)
1704 				continue;
1705 
1706 			/* We only support full screen mpo with ODM */
1707 			if (vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled
1708 					&& pipe->plane_state && mpo_pipe
1709 					&& memcmp(&mpo_pipe->plane_state->clip_rect,
1710 							&pipe->stream->src,
1711 							sizeof(struct rect)) != 0) {
1712 				ASSERT(mpo_pipe->plane_state != pipe->plane_state);
1713 				goto validate_fail;
1714 			}
1715 			pipe_idx++;
1716 		}
1717 	}
1718 
1719 	/* merge pipes if necessary */
1720 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
1721 		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1722 
1723 		/*skip pipes that don't need merging*/
1724 		if (!merge[i])
1725 			continue;
1726 
1727 		/* if ODM merge we ignore mpc tree, mpo pipes will have their own flags */
1728 		if (pipe->prev_odm_pipe) {
1729 			/*split off odm pipe*/
1730 			pipe->prev_odm_pipe->next_odm_pipe = pipe->next_odm_pipe;
1731 			if (pipe->next_odm_pipe)
1732 				pipe->next_odm_pipe->prev_odm_pipe = pipe->prev_odm_pipe;
1733 
1734 			pipe->bottom_pipe = NULL;
1735 			pipe->next_odm_pipe = NULL;
1736 			pipe->plane_state = NULL;
1737 			pipe->stream = NULL;
1738 			pipe->top_pipe = NULL;
1739 			pipe->prev_odm_pipe = NULL;
1740 			if (pipe->stream_res.dsc)
1741 				dcn20_release_dsc(&context->res_ctx, dc->res_pool, &pipe->stream_res.dsc);
1742 			memset(&pipe->plane_res, 0, sizeof(pipe->plane_res));
1743 			memset(&pipe->stream_res, 0, sizeof(pipe->stream_res));
1744 			repopulate_pipes = true;
1745 		} else if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) {
1746 			struct pipe_ctx *top_pipe = pipe->top_pipe;
1747 			struct pipe_ctx *bottom_pipe = pipe->bottom_pipe;
1748 
1749 			top_pipe->bottom_pipe = bottom_pipe;
1750 			if (bottom_pipe)
1751 				bottom_pipe->top_pipe = top_pipe;
1752 
1753 			pipe->top_pipe = NULL;
1754 			pipe->bottom_pipe = NULL;
1755 			pipe->plane_state = NULL;
1756 			pipe->stream = NULL;
1757 			memset(&pipe->plane_res, 0, sizeof(pipe->plane_res));
1758 			memset(&pipe->stream_res, 0, sizeof(pipe->stream_res));
1759 			repopulate_pipes = true;
1760 		} else
1761 			ASSERT(0); /* Should never try to merge master pipe */
1762 
1763 	}
1764 
1765 	for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) {
1766 		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1767 		struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];
1768 		struct pipe_ctx *hsplit_pipe = NULL;
1769 		bool odm;
1770 		int old_index = -1;
1771 
1772 		if (!pipe->stream || newly_split[i])
1773 			continue;
1774 
1775 		pipe_idx++;
1776 		odm = vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled;
1777 
1778 		if (!pipe->plane_state && !odm)
1779 			continue;
1780 
1781 		if (split[i]) {
1782 			if (odm) {
1783 				if (split[i] == 4 && old_pipe->next_odm_pipe && old_pipe->next_odm_pipe->next_odm_pipe)
1784 					old_index = old_pipe->next_odm_pipe->next_odm_pipe->pipe_idx;
1785 				else if (old_pipe->next_odm_pipe)
1786 					old_index = old_pipe->next_odm_pipe->pipe_idx;
1787 			} else {
1788 				if (split[i] == 4 && old_pipe->bottom_pipe && old_pipe->bottom_pipe->bottom_pipe &&
1789 						old_pipe->bottom_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
1790 					old_index = old_pipe->bottom_pipe->bottom_pipe->pipe_idx;
1791 				else if (old_pipe->bottom_pipe &&
1792 						old_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
1793 					old_index = old_pipe->bottom_pipe->pipe_idx;
1794 			}
1795 			hsplit_pipe = dcn30_find_split_pipe(dc, context, old_index);
1796 			ASSERT(hsplit_pipe);
1797 			if (!hsplit_pipe)
1798 				goto validate_fail;
1799 
1800 			if (!dcn30_split_stream_for_mpc_or_odm(
1801 					dc, &context->res_ctx,
1802 					pipe, hsplit_pipe, odm))
1803 				goto validate_fail;
1804 
1805 			newly_split[hsplit_pipe->pipe_idx] = true;
1806 			repopulate_pipes = true;
1807 		}
1808 		if (split[i] == 4) {
1809 			struct pipe_ctx *pipe_4to1;
1810 
1811 			if (odm && old_pipe->next_odm_pipe)
1812 				old_index = old_pipe->next_odm_pipe->pipe_idx;
1813 			else if (!odm && old_pipe->bottom_pipe &&
1814 						old_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
1815 				old_index = old_pipe->bottom_pipe->pipe_idx;
1816 			else
1817 				old_index = -1;
1818 			pipe_4to1 = dcn30_find_split_pipe(dc, context, old_index);
1819 			ASSERT(pipe_4to1);
1820 			if (!pipe_4to1)
1821 				goto validate_fail;
1822 			if (!dcn30_split_stream_for_mpc_or_odm(
1823 					dc, &context->res_ctx,
1824 					pipe, pipe_4to1, odm))
1825 				goto validate_fail;
1826 			newly_split[pipe_4to1->pipe_idx] = true;
1827 
1828 			if (odm && old_pipe->next_odm_pipe && old_pipe->next_odm_pipe->next_odm_pipe
1829 					&& old_pipe->next_odm_pipe->next_odm_pipe->next_odm_pipe)
1830 				old_index = old_pipe->next_odm_pipe->next_odm_pipe->next_odm_pipe->pipe_idx;
1831 			else if (!odm && old_pipe->bottom_pipe && old_pipe->bottom_pipe->bottom_pipe &&
1832 					old_pipe->bottom_pipe->bottom_pipe->bottom_pipe &&
1833 					old_pipe->bottom_pipe->bottom_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
1834 				old_index = old_pipe->bottom_pipe->bottom_pipe->bottom_pipe->pipe_idx;
1835 			else
1836 				old_index = -1;
1837 			pipe_4to1 = dcn30_find_split_pipe(dc, context, old_index);
1838 			ASSERT(pipe_4to1);
1839 			if (!pipe_4to1)
1840 				goto validate_fail;
1841 			if (!dcn30_split_stream_for_mpc_or_odm(
1842 					dc, &context->res_ctx,
1843 					hsplit_pipe, pipe_4to1, odm))
1844 				goto validate_fail;
1845 			newly_split[pipe_4to1->pipe_idx] = true;
1846 		}
1847 		if (odm)
1848 			dcn20_build_mapped_resource(dc, context, pipe->stream);
1849 	}
1850 
1851 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
1852 		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1853 
1854 		if (pipe->plane_state) {
1855 			if (!resource_build_scaling_params(pipe))
1856 				goto validate_fail;
1857 		}
1858 	}
1859 
1860 	/* Actual dsc count per stream dsc validation*/
1861 	if (!dcn20_validate_dsc(dc, context)) {
1862 		vba->ValidationStatus[vba->soc.num_states] = DML_FAIL_DSC_VALIDATION_FAILURE;
1863 		goto validate_fail;
1864 	}
1865 
1866 	if (repopulate_pipes)
1867 		pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate);
1868 	context->bw_ctx.dml.vba.VoltageLevel = vlevel;
1869 	*vlevel_out = vlevel;
1870 	*pipe_cnt_out = pipe_cnt;
1871 
1872 	out = true;
1873 	goto validate_out;
1874 
1875 validate_fail:
1876 	out = false;
1877 
1878 validate_out:
1879 	return out;
1880 }
1881 
1882 static int get_refresh_rate(struct dc_state *context)
1883 {
1884 	int refresh_rate = 0;
1885 	int h_v_total = 0;
1886 	struct dc_crtc_timing *timing = NULL;
1887 
1888 	if (context == NULL || context->streams[0] == NULL)
1889 		return 0;
1890 
1891 	/* check if refresh rate at least 120hz */
1892 	timing = &context->streams[0]->timing;
1893 	if (timing == NULL)
1894 		return 0;
1895 
1896 	h_v_total = timing->h_total * timing->v_total;
1897 	if (h_v_total == 0)
1898 		return 0;
1899 
1900 	refresh_rate = ((timing->pix_clk_100hz * 100) / (h_v_total)) + 1;
1901 	return refresh_rate;
1902 }
1903 
1904 #define MAX_STRETCHED_V_BLANK 500 // in micro-seconds
1905 /*
1906  * Scaling factor for v_blank stretch calculations considering timing in
1907  * micro-seconds and pixel clock in 100hz.
1908  * Note: the parenthesis are necessary to ensure the correct order of
1909  * operation where V_SCALE is used.
1910  */
1911 #define V_SCALE (10000 / MAX_STRETCHED_V_BLANK)
1912 
1913 static int get_frame_rate_at_max_stretch_100hz(struct dc_state *context)
1914 {
1915 	struct dc_crtc_timing *timing = NULL;
1916 	uint32_t sec_per_100_lines;
1917 	uint32_t max_v_blank;
1918 	uint32_t curr_v_blank;
1919 	uint32_t v_stretch_max;
1920 	uint32_t stretched_frame_pix_cnt;
1921 	uint32_t scaled_stretched_frame_pix_cnt;
1922 	uint32_t scaled_refresh_rate;
1923 
1924 	if (context == NULL || context->streams[0] == NULL)
1925 		return 0;
1926 
1927 	/* check if refresh rate at least 120hz */
1928 	timing = &context->streams[0]->timing;
1929 	if (timing == NULL)
1930 		return 0;
1931 
1932 	sec_per_100_lines = timing->pix_clk_100hz / timing->h_total + 1;
1933 	max_v_blank = sec_per_100_lines / V_SCALE + 1;
1934 	curr_v_blank = timing->v_total - timing->v_addressable;
1935 	v_stretch_max = (max_v_blank > curr_v_blank) ? (max_v_blank - curr_v_blank) : (0);
1936 	stretched_frame_pix_cnt = (v_stretch_max + timing->v_total) * timing->h_total;
1937 	scaled_stretched_frame_pix_cnt = stretched_frame_pix_cnt / 10000;
1938 	scaled_refresh_rate = (timing->pix_clk_100hz) / scaled_stretched_frame_pix_cnt + 1;
1939 
1940 	return scaled_refresh_rate;
1941 }
1942 
1943 static bool is_refresh_rate_support_mclk_switch_using_fw_based_vblank_stretch(struct dc_state *context)
1944 {
1945 	int refresh_rate_max_stretch_100hz;
1946 	int min_refresh_100hz;
1947 
1948 	if (context == NULL || context->streams[0] == NULL)
1949 		return false;
1950 
1951 	refresh_rate_max_stretch_100hz = get_frame_rate_at_max_stretch_100hz(context);
1952 	min_refresh_100hz = context->streams[0]->timing.min_refresh_in_uhz / 10000;
1953 
1954 	if (refresh_rate_max_stretch_100hz < min_refresh_100hz)
1955 		return false;
1956 
1957 	return true;
1958 }
1959 
1960 bool dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch(struct dc *dc, struct dc_state *context)
1961 {
1962 	int refresh_rate = 0;
1963 	const int minimum_refreshrate_supported = 120;
1964 
1965 	if (context == NULL || context->streams[0] == NULL)
1966 		return false;
1967 
1968 	if (context->streams[0]->sink->edid_caps.panel_patch.disable_fams)
1969 		return false;
1970 
1971 	if (dc->debug.disable_fams)
1972 		return false;
1973 
1974 	if (!dc->caps.dmub_caps.mclk_sw)
1975 		return false;
1976 
1977 	if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching_shut_down)
1978 		return false;
1979 
1980 	/* more then 1 monitor connected */
1981 	if (context->stream_count != 1)
1982 		return false;
1983 
1984 	refresh_rate = get_refresh_rate(context);
1985 	if (refresh_rate < minimum_refreshrate_supported)
1986 		return false;
1987 
1988 	if (!is_refresh_rate_support_mclk_switch_using_fw_based_vblank_stretch(context))
1989 		return false;
1990 
1991 	if (!context->streams[0]->allow_freesync)
1992 		return false;
1993 
1994 	if (context->streams[0]->vrr_active_variable && dc->debug.disable_fams_gaming)
1995 		return false;
1996 
1997 	context->streams[0]->fpo_in_use = true;
1998 
1999 	return true;
2000 }
2001 
2002 /*
2003  * set up FPO watermarks, pstate, dram latency
2004  */
2005 void dcn30_setup_mclk_switch_using_fw_based_vblank_stretch(struct dc *dc, struct dc_state *context)
2006 {
2007 	ASSERT(dc != NULL && context != NULL);
2008 	if (dc == NULL || context == NULL)
2009 		return;
2010 
2011 	/* Set wm_a.pstate so high natural MCLK switches are impossible: 4 seconds */
2012 	context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 4U * 1000U * 1000U * 1000U;
2013 }
2014 
2015 void dcn30_update_soc_for_wm_a(struct dc *dc, struct dc_state *context)
2016 {
2017 	DC_FP_START();
2018 	dcn30_fpu_update_soc_for_wm_a(dc, context);
2019 	DC_FP_END();
2020 }
2021 
2022 void dcn30_calculate_wm_and_dlg(
2023 		struct dc *dc, struct dc_state *context,
2024 		display_e2e_pipe_params_st *pipes,
2025 		int pipe_cnt,
2026 		int vlevel)
2027 {
2028 	DC_FP_START();
2029 	dcn30_fpu_calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel);
2030 	DC_FP_END();
2031 }
2032 
2033 bool dcn30_validate_bandwidth(struct dc *dc,
2034 		struct dc_state *context,
2035 		bool fast_validate)
2036 {
2037 	bool out = false;
2038 
2039 	BW_VAL_TRACE_SETUP();
2040 
2041 	int vlevel = 0;
2042 	int pipe_cnt = 0;
2043 	display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL);
2044 	DC_LOGGER_INIT(dc->ctx->logger);
2045 
2046 	BW_VAL_TRACE_COUNT();
2047 
2048 	DC_FP_START();
2049 	out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate, true);
2050 	DC_FP_END();
2051 
2052 	if (pipe_cnt == 0)
2053 		goto validate_out;
2054 
2055 	if (!out)
2056 		goto validate_fail;
2057 
2058 	BW_VAL_TRACE_END_VOLTAGE_LEVEL();
2059 
2060 	if (fast_validate) {
2061 		BW_VAL_TRACE_SKIP(fast);
2062 		goto validate_out;
2063 	}
2064 
2065 	DC_FP_START();
2066 	if (dc->res_pool->funcs->calculate_wm_and_dlg)
2067 		dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel);
2068 	DC_FP_END();
2069 
2070 	BW_VAL_TRACE_END_WATERMARKS();
2071 
2072 	goto validate_out;
2073 
2074 validate_fail:
2075 	DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n",
2076 		dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
2077 
2078 	BW_VAL_TRACE_SKIP(fail);
2079 	out = false;
2080 
2081 validate_out:
2082 	kfree(pipes);
2083 
2084 	BW_VAL_TRACE_FINISH();
2085 
2086 	return out;
2087 }
2088 
2089 void dcn30_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
2090 {
2091 	unsigned int i, j;
2092 	unsigned int num_states = 0;
2093 
2094 	unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0};
2095 	unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0};
2096 	unsigned int optimal_uclk_for_dcfclk_sta_targets[DC__VOLTAGE_STATES] = {0};
2097 	unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0};
2098 
2099 	unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {694, 875, 1000, 1200};
2100 	unsigned int num_dcfclk_sta_targets = 4;
2101 	unsigned int num_uclk_states;
2102 
2103 	struct dc_bounding_box_max_clk dcn30_bb_max_clk;
2104 
2105 	memset(&dcn30_bb_max_clk, 0, sizeof(dcn30_bb_max_clk));
2106 
2107 	if (dc->ctx->dc_bios->vram_info.num_chans)
2108 		dcn3_0_soc.num_chans = dc->ctx->dc_bios->vram_info.num_chans;
2109 
2110 	DC_FP_START();
2111 	dcn30_fpu_update_dram_channel_width_bytes(dc);
2112 	DC_FP_END();
2113 
2114 	if (bw_params->clk_table.entries[0].memclk_mhz) {
2115 
2116 		for (i = 0; i < MAX_NUM_DPM_LVL; i++) {
2117 			if (bw_params->clk_table.entries[i].dcfclk_mhz > dcn30_bb_max_clk.max_dcfclk_mhz)
2118 				dcn30_bb_max_clk.max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz;
2119 			if (bw_params->clk_table.entries[i].dispclk_mhz > dcn30_bb_max_clk.max_dispclk_mhz)
2120 				dcn30_bb_max_clk.max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz;
2121 			if (bw_params->clk_table.entries[i].dppclk_mhz > dcn30_bb_max_clk.max_dppclk_mhz)
2122 				dcn30_bb_max_clk.max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz;
2123 			if (bw_params->clk_table.entries[i].phyclk_mhz > dcn30_bb_max_clk.max_phyclk_mhz)
2124 				dcn30_bb_max_clk.max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz;
2125 		}
2126 
2127 		DC_FP_START();
2128 		dcn30_fpu_update_max_clk(&dcn30_bb_max_clk);
2129 		DC_FP_END();
2130 
2131 		if (dcn30_bb_max_clk.max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
2132 			// If max DCFCLK is greater than the max DCFCLK STA target, insert into the DCFCLK STA target array
2133 			dcfclk_sta_targets[num_dcfclk_sta_targets] = dcn30_bb_max_clk.max_dcfclk_mhz;
2134 			num_dcfclk_sta_targets++;
2135 		} else if (dcn30_bb_max_clk.max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
2136 			// If max DCFCLK is less than the max DCFCLK STA target, cap values and remove duplicates
2137 			for (i = 0; i < num_dcfclk_sta_targets; i++) {
2138 				if (dcfclk_sta_targets[i] > dcn30_bb_max_clk.max_dcfclk_mhz) {
2139 					dcfclk_sta_targets[i] = dcn30_bb_max_clk.max_dcfclk_mhz;
2140 					break;
2141 				}
2142 			}
2143 			// Update size of array since we "removed" duplicates
2144 			num_dcfclk_sta_targets = i + 1;
2145 		}
2146 
2147 		num_uclk_states = bw_params->clk_table.num_entries;
2148 
2149 		// Calculate optimal dcfclk for each uclk
2150 		for (i = 0; i < num_uclk_states; i++) {
2151 			DC_FP_START();
2152 			dcn30_fpu_get_optimal_dcfclk_fclk_for_uclk(bw_params->clk_table.entries[i].memclk_mhz * 16,
2153 					&optimal_dcfclk_for_uclk[i], NULL);
2154 			DC_FP_END();
2155 			if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz) {
2156 				optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz;
2157 			}
2158 		}
2159 
2160 		// Calculate optimal uclk for each dcfclk sta target
2161 		for (i = 0; i < num_dcfclk_sta_targets; i++) {
2162 			for (j = 0; j < num_uclk_states; j++) {
2163 				if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) {
2164 					optimal_uclk_for_dcfclk_sta_targets[i] =
2165 							bw_params->clk_table.entries[j].memclk_mhz * 16;
2166 					break;
2167 				}
2168 			}
2169 		}
2170 
2171 		i = 0;
2172 		j = 0;
2173 		// create the final dcfclk and uclk table
2174 		while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) {
2175 			if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) {
2176 				dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
2177 				dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
2178 			} else {
2179 				if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= dcn30_bb_max_clk.max_dcfclk_mhz) {
2180 					dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
2181 					dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
2182 				} else {
2183 					j = num_uclk_states;
2184 				}
2185 			}
2186 		}
2187 
2188 		while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) {
2189 			dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
2190 			dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
2191 		}
2192 
2193 		while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES &&
2194 				optimal_dcfclk_for_uclk[j] <= dcn30_bb_max_clk.max_dcfclk_mhz) {
2195 			dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
2196 			dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
2197 		}
2198 
2199 		dcn3_0_soc.num_states = num_states;
2200 		DC_FP_START();
2201 		dcn30_fpu_update_bw_bounding_box(dc, bw_params, &dcn30_bb_max_clk, dcfclk_mhz, dram_speed_mts);
2202 		DC_FP_END();
2203 	}
2204 }
2205 
2206 static void dcn30_get_panel_config_defaults(struct dc_panel_config *panel_config)
2207 {
2208 	*panel_config = panel_config_defaults;
2209 }
2210 
2211 static const struct resource_funcs dcn30_res_pool_funcs = {
2212 	.destroy = dcn30_destroy_resource_pool,
2213 	.link_enc_create = dcn30_link_encoder_create,
2214 	.panel_cntl_create = dcn30_panel_cntl_create,
2215 	.validate_bandwidth = dcn30_validate_bandwidth,
2216 	.calculate_wm_and_dlg = dcn30_calculate_wm_and_dlg,
2217 	.update_soc_for_wm_a = dcn30_update_soc_for_wm_a,
2218 	.populate_dml_pipes = dcn30_populate_dml_pipes_from_context,
2219 	.acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer,
2220 	.add_stream_to_ctx = dcn30_add_stream_to_ctx,
2221 	.add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
2222 	.remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
2223 	.populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
2224 	.set_mcif_arb_params = dcn30_set_mcif_arb_params,
2225 	.find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
2226 	.acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
2227 	.release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
2228 	.update_bw_bounding_box = dcn30_update_bw_bounding_box,
2229 	.patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
2230 	.get_panel_config_defaults = dcn30_get_panel_config_defaults,
2231 };
2232 
2233 #define CTX ctx
2234 
2235 #define REG(reg_name) \
2236 	(DCN_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
2237 
2238 static uint32_t read_pipe_fuses(struct dc_context *ctx)
2239 {
2240 	uint32_t value = REG_READ(CC_DC_PIPE_DIS);
2241 	/* Support for max 6 pipes */
2242 	value = value & 0x3f;
2243 	return value;
2244 }
2245 
2246 static bool dcn30_resource_construct(
2247 	uint8_t num_virtual_links,
2248 	struct dc *dc,
2249 	struct dcn30_resource_pool *pool)
2250 {
2251 	int i;
2252 	struct dc_context *ctx = dc->ctx;
2253 	struct irq_service_init_data init_data;
2254 	struct ddc_service_init_data ddc_init_data = {0};
2255 	uint32_t pipe_fuses = read_pipe_fuses(ctx);
2256 	uint32_t num_pipes = 0;
2257 
2258 	if (!(pipe_fuses == 0 || pipe_fuses == 0x3e)) {
2259 		BREAK_TO_DEBUGGER();
2260 		dm_error("DC: Unexpected fuse recipe for navi2x !\n");
2261 		/* fault to single pipe */
2262 		pipe_fuses = 0x3e;
2263 	}
2264 
2265 	DC_FP_START();
2266 
2267 	ctx->dc_bios->regs = &bios_regs;
2268 
2269 	pool->base.res_cap = &res_cap_dcn3;
2270 
2271 	pool->base.funcs = &dcn30_res_pool_funcs;
2272 
2273 	/*************************************************
2274 	 *  Resource + asic cap harcoding                *
2275 	 *************************************************/
2276 	pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
2277 	pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
2278 	pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;
2279 	dc->caps.max_downscale_ratio = 600;
2280 	dc->caps.i2c_speed_in_khz = 100;
2281 	dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a not applied by default*/
2282 	dc->caps.max_cursor_size = 256;
2283 	dc->caps.min_horizontal_blanking_period = 80;
2284 	dc->caps.dmdata_alloc_size = 2048;
2285 	dc->caps.mall_size_per_mem_channel = 8;
2286 	/* total size = mall per channel * num channels * 1024 * 1024 */
2287 	dc->caps.mall_size_total = dc->caps.mall_size_per_mem_channel * dc->ctx->dc_bios->vram_info.num_chans * 1048576;
2288 	dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8;
2289 
2290 	dc->caps.max_slave_planes = 2;
2291 	dc->caps.max_slave_yuv_planes = 2;
2292 	dc->caps.max_slave_rgb_planes = 2;
2293 	dc->caps.post_blend_color_processing = true;
2294 	dc->caps.force_dp_tps4_for_cp2520 = true;
2295 	dc->caps.extended_aux_timeout_support = true;
2296 	dc->caps.dmcub_support = true;
2297 
2298 	/* Color pipeline capabilities */
2299 	dc->caps.color.dpp.dcn_arch = 1;
2300 	dc->caps.color.dpp.input_lut_shared = 0;
2301 	dc->caps.color.dpp.icsc = 1;
2302 	dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
2303 	dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
2304 	dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
2305 	dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
2306 	dc->caps.color.dpp.dgam_rom_caps.pq = 1;
2307 	dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
2308 	dc->caps.color.dpp.post_csc = 1;
2309 	dc->caps.color.dpp.gamma_corr = 1;
2310 	dc->caps.color.dpp.dgam_rom_for_yuv = 0;
2311 
2312 	dc->caps.color.dpp.hw_3d_lut = 1;
2313 	dc->caps.color.dpp.ogam_ram = 1;
2314 	// no OGAM ROM on DCN3
2315 	dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
2316 	dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
2317 	dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
2318 	dc->caps.color.dpp.ogam_rom_caps.pq = 0;
2319 	dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
2320 	dc->caps.color.dpp.ocsc = 0;
2321 
2322 	dc->caps.color.mpc.gamut_remap = 1;
2323 	dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //3
2324 	dc->caps.color.mpc.ogam_ram = 1;
2325 	dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
2326 	dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
2327 	dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
2328 	dc->caps.color.mpc.ogam_rom_caps.pq = 0;
2329 	dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
2330 	dc->caps.color.mpc.ocsc = 1;
2331 
2332 	dc->caps.dp_hdmi21_pcon_support = true;
2333 	dc->caps.max_v_total = (1 << 15) - 1;
2334 
2335 	/* read VBIOS LTTPR caps */
2336 	{
2337 		if (ctx->dc_bios->funcs->get_lttpr_caps) {
2338 			enum bp_result bp_query_result;
2339 			uint8_t is_vbios_lttpr_enable = 0;
2340 
2341 			bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
2342 			dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
2343 		}
2344 
2345 		if (ctx->dc_bios->funcs->get_lttpr_interop) {
2346 			enum bp_result bp_query_result;
2347 			uint8_t is_vbios_interop_enabled = 0;
2348 
2349 			bp_query_result = ctx->dc_bios->funcs->get_lttpr_interop(ctx->dc_bios,
2350 					&is_vbios_interop_enabled);
2351 			dc->caps.vbios_lttpr_aware = (bp_query_result == BP_RESULT_OK) && !!is_vbios_interop_enabled;
2352 		}
2353 	}
2354 
2355 	if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
2356 		dc->debug = debug_defaults_drv;
2357 
2358 	// Init the vm_helper
2359 	if (dc->vm_helper)
2360 		vm_helper_init(dc->vm_helper, 16);
2361 
2362 	/*************************************************
2363 	 *  Create resources                             *
2364 	 *************************************************/
2365 
2366 	/* Clock Sources for Pixel Clock*/
2367 	pool->base.clock_sources[DCN30_CLK_SRC_PLL0] =
2368 			dcn30_clock_source_create(ctx, ctx->dc_bios,
2369 				CLOCK_SOURCE_COMBO_PHY_PLL0,
2370 				&clk_src_regs[0], false);
2371 	pool->base.clock_sources[DCN30_CLK_SRC_PLL1] =
2372 			dcn30_clock_source_create(ctx, ctx->dc_bios,
2373 				CLOCK_SOURCE_COMBO_PHY_PLL1,
2374 				&clk_src_regs[1], false);
2375 	pool->base.clock_sources[DCN30_CLK_SRC_PLL2] =
2376 			dcn30_clock_source_create(ctx, ctx->dc_bios,
2377 				CLOCK_SOURCE_COMBO_PHY_PLL2,
2378 				&clk_src_regs[2], false);
2379 	pool->base.clock_sources[DCN30_CLK_SRC_PLL3] =
2380 			dcn30_clock_source_create(ctx, ctx->dc_bios,
2381 				CLOCK_SOURCE_COMBO_PHY_PLL3,
2382 				&clk_src_regs[3], false);
2383 	pool->base.clock_sources[DCN30_CLK_SRC_PLL4] =
2384 			dcn30_clock_source_create(ctx, ctx->dc_bios,
2385 				CLOCK_SOURCE_COMBO_PHY_PLL4,
2386 				&clk_src_regs[4], false);
2387 	pool->base.clock_sources[DCN30_CLK_SRC_PLL5] =
2388 			dcn30_clock_source_create(ctx, ctx->dc_bios,
2389 				CLOCK_SOURCE_COMBO_PHY_PLL5,
2390 				&clk_src_regs[5], false);
2391 
2392 	pool->base.clk_src_count = DCN30_CLK_SRC_TOTAL;
2393 
2394 	/* todo: not reuse phy_pll registers */
2395 	pool->base.dp_clock_source =
2396 			dcn30_clock_source_create(ctx, ctx->dc_bios,
2397 				CLOCK_SOURCE_ID_DP_DTO,
2398 				&clk_src_regs[0], true);
2399 
2400 	for (i = 0; i < pool->base.clk_src_count; i++) {
2401 		if (pool->base.clock_sources[i] == NULL) {
2402 			dm_error("DC: failed to create clock sources!\n");
2403 			BREAK_TO_DEBUGGER();
2404 			goto create_fail;
2405 		}
2406 	}
2407 
2408 	/* DCCG */
2409 	pool->base.dccg = dccg30_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
2410 	if (pool->base.dccg == NULL) {
2411 		dm_error("DC: failed to create dccg!\n");
2412 		BREAK_TO_DEBUGGER();
2413 		goto create_fail;
2414 	}
2415 
2416 	/* PP Lib and SMU interfaces */
2417 	init_soc_bounding_box(dc, pool);
2418 
2419 	num_pipes = dcn3_0_ip.max_num_dpp;
2420 
2421 	for (i = 0; i < dcn3_0_ip.max_num_dpp; i++)
2422 		if (pipe_fuses & 1 << i)
2423 			num_pipes--;
2424 
2425 	dcn3_0_ip.max_num_dpp = num_pipes;
2426 	dcn3_0_ip.max_num_otg = num_pipes;
2427 
2428 	dml_init_instance(&dc->dml, &dcn3_0_soc, &dcn3_0_ip, DML_PROJECT_DCN30);
2429 
2430 	/* IRQ */
2431 	init_data.ctx = dc->ctx;
2432 	pool->base.irqs = dal_irq_service_dcn30_create(&init_data);
2433 	if (!pool->base.irqs)
2434 		goto create_fail;
2435 
2436 	/* HUBBUB */
2437 	pool->base.hubbub = dcn30_hubbub_create(ctx);
2438 	if (pool->base.hubbub == NULL) {
2439 		BREAK_TO_DEBUGGER();
2440 		dm_error("DC: failed to create hubbub!\n");
2441 		goto create_fail;
2442 	}
2443 
2444 	/* HUBPs, DPPs, OPPs and TGs */
2445 	for (i = 0; i < pool->base.pipe_count; i++) {
2446 		pool->base.hubps[i] = dcn30_hubp_create(ctx, i);
2447 		if (pool->base.hubps[i] == NULL) {
2448 			BREAK_TO_DEBUGGER();
2449 			dm_error(
2450 				"DC: failed to create hubps!\n");
2451 			goto create_fail;
2452 		}
2453 
2454 		pool->base.dpps[i] = dcn30_dpp_create(ctx, i);
2455 		if (pool->base.dpps[i] == NULL) {
2456 			BREAK_TO_DEBUGGER();
2457 			dm_error(
2458 				"DC: failed to create dpps!\n");
2459 			goto create_fail;
2460 		}
2461 	}
2462 
2463 	for (i = 0; i < pool->base.res_cap->num_opp; i++) {
2464 		pool->base.opps[i] = dcn30_opp_create(ctx, i);
2465 		if (pool->base.opps[i] == NULL) {
2466 			BREAK_TO_DEBUGGER();
2467 			dm_error(
2468 				"DC: failed to create output pixel processor!\n");
2469 			goto create_fail;
2470 		}
2471 	}
2472 
2473 	for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2474 		pool->base.timing_generators[i] = dcn30_timing_generator_create(
2475 				ctx, i);
2476 		if (pool->base.timing_generators[i] == NULL) {
2477 			BREAK_TO_DEBUGGER();
2478 			dm_error("DC: failed to create tg!\n");
2479 			goto create_fail;
2480 		}
2481 	}
2482 	pool->base.timing_generator_count = i;
2483 	/* PSR */
2484 	pool->base.psr = dmub_psr_create(ctx);
2485 
2486 	if (pool->base.psr == NULL) {
2487 		dm_error("DC: failed to create PSR obj!\n");
2488 		BREAK_TO_DEBUGGER();
2489 		goto create_fail;
2490 	}
2491 
2492 	/* ABM */
2493 	for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2494 		pool->base.multiple_abms[i] = dmub_abm_create(ctx,
2495 				&abm_regs[i],
2496 				&abm_shift,
2497 				&abm_mask);
2498 		if (pool->base.multiple_abms[i] == NULL) {
2499 			dm_error("DC: failed to create abm for pipe %d!\n", i);
2500 			BREAK_TO_DEBUGGER();
2501 			goto create_fail;
2502 		}
2503 	}
2504 	/* MPC and DSC */
2505 	pool->base.mpc = dcn30_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);
2506 	if (pool->base.mpc == NULL) {
2507 		BREAK_TO_DEBUGGER();
2508 		dm_error("DC: failed to create mpc!\n");
2509 		goto create_fail;
2510 	}
2511 
2512 	for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
2513 		pool->base.dscs[i] = dcn30_dsc_create(ctx, i);
2514 		if (pool->base.dscs[i] == NULL) {
2515 			BREAK_TO_DEBUGGER();
2516 			dm_error("DC: failed to create display stream compressor %d!\n", i);
2517 			goto create_fail;
2518 		}
2519 	}
2520 
2521 	/* DWB and MMHUBBUB */
2522 	if (!dcn30_dwbc_create(ctx, &pool->base)) {
2523 		BREAK_TO_DEBUGGER();
2524 		dm_error("DC: failed to create dwbc!\n");
2525 		goto create_fail;
2526 	}
2527 
2528 	if (!dcn30_mmhubbub_create(ctx, &pool->base)) {
2529 		BREAK_TO_DEBUGGER();
2530 		dm_error("DC: failed to create mcif_wb!\n");
2531 		goto create_fail;
2532 	}
2533 
2534 	/* AUX and I2C */
2535 	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
2536 		pool->base.engines[i] = dcn30_aux_engine_create(ctx, i);
2537 		if (pool->base.engines[i] == NULL) {
2538 			BREAK_TO_DEBUGGER();
2539 			dm_error(
2540 				"DC:failed to create aux engine!!\n");
2541 			goto create_fail;
2542 		}
2543 		pool->base.hw_i2cs[i] = dcn30_i2c_hw_create(ctx, i);
2544 		if (pool->base.hw_i2cs[i] == NULL) {
2545 			BREAK_TO_DEBUGGER();
2546 			dm_error(
2547 				"DC:failed to create hw i2c!!\n");
2548 			goto create_fail;
2549 		}
2550 		pool->base.sw_i2cs[i] = NULL;
2551 	}
2552 
2553 	/* Audio, Stream Encoders including DIG and virtual, MPC 3D LUTs */
2554 	if (!resource_construct(num_virtual_links, dc, &pool->base,
2555 			&res_create_funcs))
2556 		goto create_fail;
2557 
2558 	/* HW Sequencer and Plane caps */
2559 	dcn30_hw_sequencer_construct(dc);
2560 
2561 	dc->caps.max_planes =  pool->base.pipe_count;
2562 
2563 	for (i = 0; i < dc->caps.max_planes; ++i)
2564 		dc->caps.planes[i] = plane_cap;
2565 
2566 	dc->cap_funcs = cap_funcs;
2567 
2568 	if (dc->ctx->dc_bios->fw_info.oem_i2c_present) {
2569 		ddc_init_data.ctx = dc->ctx;
2570 		ddc_init_data.link = NULL;
2571 		ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id;
2572 		ddc_init_data.id.enum_id = 0;
2573 		ddc_init_data.id.type = OBJECT_TYPE_GENERIC;
2574 		pool->base.oem_device = dc->link_srv->create_ddc_service(&ddc_init_data);
2575 	} else {
2576 		pool->base.oem_device = NULL;
2577 	}
2578 
2579 	DC_FP_END();
2580 
2581 	return true;
2582 
2583 create_fail:
2584 
2585 	DC_FP_END();
2586 	dcn30_resource_destruct(pool);
2587 
2588 	return false;
2589 }
2590 
2591 struct resource_pool *dcn30_create_resource_pool(
2592 		const struct dc_init_data *init_data,
2593 		struct dc *dc)
2594 {
2595 	struct dcn30_resource_pool *pool =
2596 		kzalloc(sizeof(struct dcn30_resource_pool), GFP_KERNEL);
2597 
2598 	if (!pool)
2599 		return NULL;
2600 
2601 	if (dcn30_resource_construct(init_data->num_virtual_links, dc, pool))
2602 		return &pool->base;
2603 
2604 	BREAK_TO_DEBUGGER();
2605 	kfree(pool);
2606 	return NULL;
2607 }
2608