1 /*
2  * Copyright 2020 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 
27 #include "dm_services.h"
28 #include "dc.h"
29 
30 #include "dcn30_init.h"
31 
32 #include "resource.h"
33 #include "include/irq_service_interface.h"
34 #include "dcn20/dcn20_resource.h"
35 
36 #include "dcn30_resource.h"
37 
38 #include "dcn10/dcn10_ipp.h"
39 #include "dcn30/dcn30_hubbub.h"
40 #include "dcn30/dcn30_mpc.h"
41 #include "dcn30/dcn30_hubp.h"
42 #include "irq/dcn30/irq_service_dcn30.h"
43 #include "dcn30/dcn30_dpp.h"
44 #include "dcn30/dcn30_optc.h"
45 #include "dcn20/dcn20_hwseq.h"
46 #include "dcn30/dcn30_hwseq.h"
47 #include "dce110/dce110_hw_sequencer.h"
48 #include "dcn30/dcn30_opp.h"
49 #include "dcn20/dcn20_dsc.h"
50 #include "dcn30/dcn30_vpg.h"
51 #include "dcn30/dcn30_afmt.h"
52 #include "dcn30/dcn30_dio_stream_encoder.h"
53 #include "dcn30/dcn30_dio_link_encoder.h"
54 #include "dce/dce_clock_source.h"
55 #include "dce/dce_audio.h"
56 #include "dce/dce_hwseq.h"
57 #include "clk_mgr.h"
58 #include "virtual/virtual_stream_encoder.h"
59 #include "dce110/dce110_resource.h"
60 #include "dml/display_mode_vba.h"
61 #include "dcn30/dcn30_dccg.h"
62 #include "dcn10/dcn10_resource.h"
63 #include "dc_link_ddc.h"
64 #include "dce/dce_panel_cntl.h"
65 
66 #include "dcn30/dcn30_dwb.h"
67 #include "dcn30/dcn30_mmhubbub.h"
68 
69 #include "sienna_cichlid_ip_offset.h"
70 #include "dcn/dcn_3_0_0_offset.h"
71 #include "dcn/dcn_3_0_0_sh_mask.h"
72 
73 #include "nbio/nbio_7_4_offset.h"
74 
75 #include "dcn/dpcs_3_0_0_offset.h"
76 #include "dcn/dpcs_3_0_0_sh_mask.h"
77 
78 #include "mmhub/mmhub_2_0_0_offset.h"
79 #include "mmhub/mmhub_2_0_0_sh_mask.h"
80 
81 #include "reg_helper.h"
82 #include "dce/dmub_abm.h"
83 #include "dce/dmub_psr.h"
84 #include "dce/dce_aux.h"
85 #include "dce/dce_i2c.h"
86 
87 #include "dml/dcn30/display_mode_vba_30.h"
88 #include "vm_helper.h"
89 #include "dcn20/dcn20_vmid.h"
90 #include "amdgpu_socbb.h"
91 
92 #define DC_LOGGER_INIT(logger)
93 
94 struct _vcs_dpi_ip_params_st dcn3_0_ip = {
95 	.use_min_dcfclk = 1,
96 	.clamp_min_dcfclk = 0,
97 	.odm_capable = 1,
98 	.gpuvm_enable = 0,
99 	.hostvm_enable = 0,
100 	.gpuvm_max_page_table_levels = 4,
101 	.hostvm_max_page_table_levels = 4,
102 	.hostvm_cached_page_table_levels = 0,
103 	.pte_group_size_bytes = 2048,
104 	.num_dsc = 6,
105 	.rob_buffer_size_kbytes = 184,
106 	.det_buffer_size_kbytes = 184,
107 	.dpte_buffer_size_in_pte_reqs_luma = 84,
108 	.pde_proc_buffer_size_64k_reqs = 48,
109 	.dpp_output_buffer_pixels = 2560,
110 	.opp_output_buffer_lines = 1,
111 	.pixel_chunk_size_kbytes = 8,
112 	.pte_enable = 1,
113 	.max_page_table_levels = 2,
114 	.pte_chunk_size_kbytes = 2,  // ?
115 	.meta_chunk_size_kbytes = 2,
116 	.writeback_chunk_size_kbytes = 8,
117 	.line_buffer_size_bits = 789504,
118 	.is_line_buffer_bpp_fixed = 0,  // ?
119 	.line_buffer_fixed_bpp = 0,     // ?
120 	.dcc_supported = true,
121 	.writeback_interface_buffer_size_kbytes = 90,
122 	.writeback_line_buffer_buffer_size = 0,
123 	.max_line_buffer_lines = 12,
124 	.writeback_luma_buffer_size_kbytes = 12,  // writeback_line_buffer_buffer_size = 656640
125 	.writeback_chroma_buffer_size_kbytes = 8,
126 	.writeback_chroma_line_buffer_width_pixels = 4,
127 	.writeback_max_hscl_ratio = 1,
128 	.writeback_max_vscl_ratio = 1,
129 	.writeback_min_hscl_ratio = 1,
130 	.writeback_min_vscl_ratio = 1,
131 	.writeback_max_hscl_taps = 1,
132 	.writeback_max_vscl_taps = 1,
133 	.writeback_line_buffer_luma_buffer_size = 0,
134 	.writeback_line_buffer_chroma_buffer_size = 14643,
135 	.cursor_buffer_size = 8,
136 	.cursor_chunk_size = 2,
137 	.max_num_otg = 6,
138 	.max_num_dpp = 6,
139 	.max_num_wb = 1,
140 	.max_dchub_pscl_bw_pix_per_clk = 4,
141 	.max_pscl_lb_bw_pix_per_clk = 2,
142 	.max_lb_vscl_bw_pix_per_clk = 4,
143 	.max_vscl_hscl_bw_pix_per_clk = 4,
144 	.max_hscl_ratio = 6,
145 	.max_vscl_ratio = 6,
146 	.hscl_mults = 4,
147 	.vscl_mults = 4,
148 	.max_hscl_taps = 8,
149 	.max_vscl_taps = 8,
150 	.dispclk_ramp_margin_percent = 1,
151 	.underscan_factor = 1.11,
152 	.min_vblank_lines = 32,
153 	.dppclk_delay_subtotal = 46,
154 	.dynamic_metadata_vm_enabled = true,
155 	.dppclk_delay_scl_lb_only = 16,
156 	.dppclk_delay_scl = 50,
157 	.dppclk_delay_cnvc_formatter = 27,
158 	.dppclk_delay_cnvc_cursor = 6,
159 	.dispclk_delay_subtotal = 119,
160 	.dcfclk_cstate_latency = 5.2, // SRExitTime
161 	.max_inter_dcn_tile_repeaters = 8,
162 	.odm_combine_4to1_supported = true,
163 
164 	.xfc_supported = false,
165 	.xfc_fill_bw_overhead_percent = 10.0,
166 	.xfc_fill_constant_bytes = 0,
167 	.gfx7_compat_tiling_supported = 0,
168 	.number_of_cursors = 1,
169 };
170 
171 struct _vcs_dpi_soc_bounding_box_st dcn3_0_soc = {
172 	.clock_limits = {
173 			{
174 				.state = 0,
175 				.dispclk_mhz = 562.0,
176 				.dppclk_mhz = 300.0,
177 				.phyclk_mhz = 300.0,
178 				.phyclk_d18_mhz = 667.0,
179 				.dscclk_mhz = 405.6,
180 			},
181 		},
182 	.min_dcfclk = 500.0, /* TODO: set this to actual min DCFCLK */
183 	.num_states = 1,
184 	.sr_exit_time_us = 15.5,
185 	.sr_enter_plus_exit_time_us = 20,
186 	.urgent_latency_us = 4.0,
187 	.urgent_latency_pixel_data_only_us = 4.0,
188 	.urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
189 	.urgent_latency_vm_data_only_us = 4.0,
190 	.urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
191 	.urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
192 	.urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
193 	.pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 80.0,
194 	.pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0,
195 	.pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0,
196 	.max_avg_sdp_bw_use_normal_percent = 60.0,
197 	.max_avg_dram_bw_use_normal_percent = 40.0,
198 	.writeback_latency_us = 12.0,
199 	.max_request_size_bytes = 256,
200 	.fabric_datapath_to_dcn_data_return_bytes = 64,
201 	.dcn_downspread_percent = 0.5,
202 	.downspread_percent = 0.38,
203 	.dram_page_open_time_ns = 50.0,
204 	.dram_rw_turnaround_time_ns = 17.5,
205 	.dram_return_buffer_per_channel_bytes = 8192,
206 	.round_trip_ping_latency_dcfclk_cycles = 191,
207 	.urgent_out_of_order_return_per_channel_bytes = 4096,
208 	.channel_interleave_bytes = 256,
209 	.num_banks = 8,
210 	.gpuvm_min_page_size_bytes = 4096,
211 	.hostvm_min_page_size_bytes = 4096,
212 	.dram_clock_change_latency_us = 404,
213 	.dummy_pstate_latency_us = 5,
214 	.writeback_dram_clock_change_latency_us = 23.0,
215 	.return_bus_width_bytes = 64,
216 	.dispclk_dppclk_vco_speed_mhz = 3650,
217 	.xfc_bus_transport_time_us = 20,      // ?
218 	.xfc_xbuf_latency_tolerance_us = 4,  // ?
219 	.use_urgent_burst_bw = 1,            // ?
220 	.do_urgent_latency_adjustment = true,
221 	.urgent_latency_adjustment_fabric_clock_component_us = 1.0,
222 	.urgent_latency_adjustment_fabric_clock_reference_mhz = 1000,
223 };
224 
225 enum dcn30_clk_src_array_id {
226 	DCN30_CLK_SRC_PLL0,
227 	DCN30_CLK_SRC_PLL1,
228 	DCN30_CLK_SRC_PLL2,
229 	DCN30_CLK_SRC_PLL3,
230 	DCN30_CLK_SRC_PLL4,
231 	DCN30_CLK_SRC_PLL5,
232 	DCN30_CLK_SRC_TOTAL
233 };
234 
235 /* begin *********************
236  * macros to expend register list macro defined in HW object header file
237  */
238 
239 /* DCN */
240 /* TODO awful hack. fixup dcn20_dwb.h */
241 #undef BASE_INNER
242 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
243 
244 #define BASE(seg) BASE_INNER(seg)
245 
246 #define SR(reg_name)\
247 		.reg_name = BASE(mm ## reg_name ## _BASE_IDX) +  \
248 					mm ## reg_name
249 
250 #define SRI(reg_name, block, id)\
251 	.reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
252 					mm ## block ## id ## _ ## reg_name
253 
254 #define SRI2(reg_name, block, id)\
255 	.reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
256 					mm ## reg_name
257 
258 #define SRIR(var_name, reg_name, block, id)\
259 	.var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
260 					mm ## block ## id ## _ ## reg_name
261 
262 #define SRII(reg_name, block, id)\
263 	.reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
264 					mm ## block ## id ## _ ## reg_name
265 
266 #define SRII_MPC_RMU(reg_name, block, id)\
267 	.RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
268 					mm ## block ## id ## _ ## reg_name
269 
270 #define SRII_DWB(reg_name, temp_name, block, id)\
271 	.reg_name[id] = BASE(mm ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
272 					mm ## block ## id ## _ ## temp_name
273 
274 #define DCCG_SRII(reg_name, block, id)\
275 	.block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
276 					mm ## block ## id ## _ ## reg_name
277 
278 #define VUPDATE_SRII(reg_name, block, id)\
279 	.reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
280 					mm ## reg_name ## _ ## block ## id
281 
282 /* NBIO */
283 #define NBIO_BASE_INNER(seg) \
284 	NBIO_BASE__INST0_SEG ## seg
285 
286 #define NBIO_BASE(seg) \
287 	NBIO_BASE_INNER(seg)
288 
289 #define NBIO_SR(reg_name)\
290 		.reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
291 					mm ## reg_name
292 
293 /* MMHUB */
294 #define MMHUB_BASE_INNER(seg) \
295 	MMHUB_BASE__INST0_SEG ## seg
296 
297 #define MMHUB_BASE(seg) \
298 	MMHUB_BASE_INNER(seg)
299 
300 #define MMHUB_SR(reg_name)\
301 		.reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \
302 					mmMM ## reg_name
303 
304 /* CLOCK */
305 #define CLK_BASE_INNER(seg) \
306 	CLK_BASE__INST0_SEG ## seg
307 
308 #define CLK_BASE(seg) \
309 	CLK_BASE_INNER(seg)
310 
311 #define CLK_SRI(reg_name, block, inst)\
312 	.reg_name = CLK_BASE(mm ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \
313 					mm ## block ## _ ## inst ## _ ## reg_name
314 
315 
316 static const struct bios_registers bios_regs = {
317 		NBIO_SR(BIOS_SCRATCH_3),
318 		NBIO_SR(BIOS_SCRATCH_6)
319 };
320 
321 #define clk_src_regs(index, pllid)\
322 [index] = {\
323 	CS_COMMON_REG_LIST_DCN2_0(index, pllid),\
324 }
325 
326 static const struct dce110_clk_src_regs clk_src_regs[] = {
327 	clk_src_regs(0, A),
328 	clk_src_regs(1, B),
329 	clk_src_regs(2, C),
330 	clk_src_regs(3, D),
331 	clk_src_regs(4, E),
332 	clk_src_regs(5, F)
333 };
334 
335 static const struct dce110_clk_src_shift cs_shift = {
336 		CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
337 };
338 
339 static const struct dce110_clk_src_mask cs_mask = {
340 		CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
341 };
342 
343 #define abm_regs(id)\
344 [id] = {\
345 		ABM_DCN30_REG_LIST(id)\
346 }
347 
348 static const struct dce_abm_registers abm_regs[] = {
349 		abm_regs(0),
350 		abm_regs(1),
351 		abm_regs(2),
352 		abm_regs(3),
353 		abm_regs(4),
354 		abm_regs(5),
355 };
356 
357 static const struct dce_abm_shift abm_shift = {
358 		ABM_MASK_SH_LIST_DCN30(__SHIFT)
359 };
360 
361 static const struct dce_abm_mask abm_mask = {
362 		ABM_MASK_SH_LIST_DCN30(_MASK)
363 };
364 
365 
366 
367 #define audio_regs(id)\
368 [id] = {\
369 		AUD_COMMON_REG_LIST(id)\
370 }
371 
372 static const struct dce_audio_registers audio_regs[] = {
373 	audio_regs(0),
374 	audio_regs(1),
375 	audio_regs(2),
376 	audio_regs(3),
377 	audio_regs(4),
378 	audio_regs(5),
379 	audio_regs(6)
380 };
381 
382 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
383 		SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
384 		SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
385 		AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
386 
387 static const struct dce_audio_shift audio_shift = {
388 		DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
389 };
390 
391 static const struct dce_audio_mask audio_mask = {
392 		DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
393 };
394 
395 #define vpg_regs(id)\
396 [id] = {\
397 	VPG_DCN3_REG_LIST(id)\
398 }
399 
400 static const struct dcn30_vpg_registers vpg_regs[] = {
401 	vpg_regs(0),
402 	vpg_regs(1),
403 	vpg_regs(2),
404 	vpg_regs(3),
405 	vpg_regs(4),
406 	vpg_regs(5),
407 	vpg_regs(6),
408 };
409 
410 static const struct dcn30_vpg_shift vpg_shift = {
411 	DCN3_VPG_MASK_SH_LIST(__SHIFT)
412 };
413 
414 static const struct dcn30_vpg_mask vpg_mask = {
415 	DCN3_VPG_MASK_SH_LIST(_MASK)
416 };
417 
418 #define afmt_regs(id)\
419 [id] = {\
420 	AFMT_DCN3_REG_LIST(id)\
421 }
422 
423 static const struct dcn30_afmt_registers afmt_regs[] = {
424 	afmt_regs(0),
425 	afmt_regs(1),
426 	afmt_regs(2),
427 	afmt_regs(3),
428 	afmt_regs(4),
429 	afmt_regs(5),
430 	afmt_regs(6),
431 };
432 
433 static const struct dcn30_afmt_shift afmt_shift = {
434 	DCN3_AFMT_MASK_SH_LIST(__SHIFT)
435 };
436 
437 static const struct dcn30_afmt_mask afmt_mask = {
438 	DCN3_AFMT_MASK_SH_LIST(_MASK)
439 };
440 
441 #define stream_enc_regs(id)\
442 [id] = {\
443 	SE_DCN3_REG_LIST(id)\
444 }
445 
446 static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
447 	stream_enc_regs(0),
448 	stream_enc_regs(1),
449 	stream_enc_regs(2),
450 	stream_enc_regs(3),
451 	stream_enc_regs(4),
452 	stream_enc_regs(5)
453 };
454 
455 static const struct dcn10_stream_encoder_shift se_shift = {
456 		SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
457 };
458 
459 static const struct dcn10_stream_encoder_mask se_mask = {
460 		SE_COMMON_MASK_SH_LIST_DCN30(_MASK)
461 };
462 
463 
464 #define aux_regs(id)\
465 [id] = {\
466 	DCN2_AUX_REG_LIST(id)\
467 }
468 
469 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
470 		aux_regs(0),
471 		aux_regs(1),
472 		aux_regs(2),
473 		aux_regs(3),
474 		aux_regs(4),
475 		aux_regs(5)
476 };
477 
478 #define hpd_regs(id)\
479 [id] = {\
480 	HPD_REG_LIST(id)\
481 }
482 
483 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
484 		hpd_regs(0),
485 		hpd_regs(1),
486 		hpd_regs(2),
487 		hpd_regs(3),
488 		hpd_regs(4),
489 		hpd_regs(5)
490 };
491 
492 #define link_regs(id, phyid)\
493 [id] = {\
494 	LE_DCN3_REG_LIST(id), \
495 	UNIPHY_DCN2_REG_LIST(phyid), \
496 	DPCS_DCN2_REG_LIST(id), \
497 	SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
498 }
499 
500 static const struct dce110_aux_registers_shift aux_shift = {
501 	DCN_AUX_MASK_SH_LIST(__SHIFT)
502 };
503 
504 static const struct dce110_aux_registers_mask aux_mask = {
505 	DCN_AUX_MASK_SH_LIST(_MASK)
506 };
507 
508 static const struct dcn10_link_enc_registers link_enc_regs[] = {
509 	link_regs(0, A),
510 	link_regs(1, B),
511 	link_regs(2, C),
512 	link_regs(3, D),
513 	link_regs(4, E),
514 	link_regs(5, F)
515 };
516 
517 static const struct dcn10_link_enc_shift le_shift = {
518 	LINK_ENCODER_MASK_SH_LIST_DCN30(__SHIFT),\
519 	DPCS_DCN2_MASK_SH_LIST(__SHIFT)
520 };
521 
522 static const struct dcn10_link_enc_mask le_mask = {
523 	LINK_ENCODER_MASK_SH_LIST_DCN30(_MASK),\
524 	DPCS_DCN2_MASK_SH_LIST(_MASK)
525 };
526 
527 
528 static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
529 	{ DCN_PANEL_CNTL_REG_LIST() }
530 };
531 
532 static const struct dce_panel_cntl_shift panel_cntl_shift = {
533 	DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
534 };
535 
536 static const struct dce_panel_cntl_mask panel_cntl_mask = {
537 	DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
538 };
539 
540 #define dpp_regs(id)\
541 [id] = {\
542 	DPP_REG_LIST_DCN30(id),\
543 }
544 
545 static const struct dcn3_dpp_registers dpp_regs[] = {
546 	dpp_regs(0),
547 	dpp_regs(1),
548 	dpp_regs(2),
549 	dpp_regs(3),
550 	dpp_regs(4),
551 	dpp_regs(5),
552 };
553 
554 static const struct dcn3_dpp_shift tf_shift = {
555 		DPP_REG_LIST_SH_MASK_DCN30(__SHIFT)
556 };
557 
558 static const struct dcn3_dpp_mask tf_mask = {
559 		DPP_REG_LIST_SH_MASK_DCN30(_MASK)
560 };
561 
562 #define opp_regs(id)\
563 [id] = {\
564 	OPP_REG_LIST_DCN30(id),\
565 }
566 
567 static const struct dcn20_opp_registers opp_regs[] = {
568 	opp_regs(0),
569 	opp_regs(1),
570 	opp_regs(2),
571 	opp_regs(3),
572 	opp_regs(4),
573 	opp_regs(5)
574 };
575 
576 static const struct dcn20_opp_shift opp_shift = {
577 	OPP_MASK_SH_LIST_DCN20(__SHIFT)
578 };
579 
580 static const struct dcn20_opp_mask opp_mask = {
581 	OPP_MASK_SH_LIST_DCN20(_MASK)
582 };
583 
584 #define aux_engine_regs(id)\
585 [id] = {\
586 	AUX_COMMON_REG_LIST0(id), \
587 	.AUXN_IMPCAL = 0, \
588 	.AUXP_IMPCAL = 0, \
589 	.AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
590 }
591 
592 static const struct dce110_aux_registers aux_engine_regs[] = {
593 		aux_engine_regs(0),
594 		aux_engine_regs(1),
595 		aux_engine_regs(2),
596 		aux_engine_regs(3),
597 		aux_engine_regs(4),
598 		aux_engine_regs(5)
599 };
600 
601 #define dwbc_regs_dcn3(id)\
602 [id] = {\
603 	DWBC_COMMON_REG_LIST_DCN30(id),\
604 }
605 
606 static const struct dcn30_dwbc_registers dwbc30_regs[] = {
607 	dwbc_regs_dcn3(0),
608 };
609 
610 static const struct dcn30_dwbc_shift dwbc30_shift = {
611 	DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
612 };
613 
614 static const struct dcn30_dwbc_mask dwbc30_mask = {
615 	DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
616 };
617 
618 #define mcif_wb_regs_dcn3(id)\
619 [id] = {\
620 	MCIF_WB_COMMON_REG_LIST_DCN30(id),\
621 }
622 
623 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = {
624 	mcif_wb_regs_dcn3(0)
625 };
626 
627 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
628 	MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
629 };
630 
631 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
632 	MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK)
633 };
634 
635 #define dsc_regsDCN20(id)\
636 [id] = {\
637 	DSC_REG_LIST_DCN20(id)\
638 }
639 
640 static const struct dcn20_dsc_registers dsc_regs[] = {
641 	dsc_regsDCN20(0),
642 	dsc_regsDCN20(1),
643 	dsc_regsDCN20(2),
644 	dsc_regsDCN20(3),
645 	dsc_regsDCN20(4),
646 	dsc_regsDCN20(5)
647 };
648 
649 static const struct dcn20_dsc_shift dsc_shift = {
650 	DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
651 };
652 
653 static const struct dcn20_dsc_mask dsc_mask = {
654 	DSC_REG_LIST_SH_MASK_DCN20(_MASK)
655 };
656 
657 static const struct dcn30_mpc_registers mpc_regs = {
658 		MPC_REG_LIST_DCN3_0(0),
659 		MPC_REG_LIST_DCN3_0(1),
660 		MPC_REG_LIST_DCN3_0(2),
661 		MPC_REG_LIST_DCN3_0(3),
662 		MPC_REG_LIST_DCN3_0(4),
663 		MPC_REG_LIST_DCN3_0(5),
664 		MPC_OUT_MUX_REG_LIST_DCN3_0(0),
665 		MPC_OUT_MUX_REG_LIST_DCN3_0(1),
666 		MPC_OUT_MUX_REG_LIST_DCN3_0(2),
667 		MPC_OUT_MUX_REG_LIST_DCN3_0(3),
668 		MPC_OUT_MUX_REG_LIST_DCN3_0(4),
669 		MPC_OUT_MUX_REG_LIST_DCN3_0(5),
670 		MPC_RMU_GLOBAL_REG_LIST_DCN3AG,
671 		MPC_RMU_REG_LIST_DCN3AG(0),
672 		MPC_RMU_REG_LIST_DCN3AG(1),
673 		MPC_RMU_REG_LIST_DCN3AG(2),
674 		MPC_DWB_MUX_REG_LIST_DCN3_0(0),
675 };
676 
677 static const struct dcn30_mpc_shift mpc_shift = {
678 	MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
679 };
680 
681 static const struct dcn30_mpc_mask mpc_mask = {
682 	MPC_COMMON_MASK_SH_LIST_DCN30(_MASK)
683 };
684 
685 #define optc_regs(id)\
686 [id] = {OPTC_COMMON_REG_LIST_DCN3_0(id)}
687 
688 
689 static const struct dcn_optc_registers optc_regs[] = {
690 	optc_regs(0),
691 	optc_regs(1),
692 	optc_regs(2),
693 	optc_regs(3),
694 	optc_regs(4),
695 	optc_regs(5)
696 };
697 
698 static const struct dcn_optc_shift optc_shift = {
699 	OPTC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
700 };
701 
702 static const struct dcn_optc_mask optc_mask = {
703 	OPTC_COMMON_MASK_SH_LIST_DCN30(_MASK)
704 };
705 
706 #define hubp_regs(id)\
707 [id] = {\
708 	HUBP_REG_LIST_DCN30(id)\
709 }
710 
711 static const struct dcn_hubp2_registers hubp_regs[] = {
712 		hubp_regs(0),
713 		hubp_regs(1),
714 		hubp_regs(2),
715 		hubp_regs(3),
716 		hubp_regs(4),
717 		hubp_regs(5)
718 };
719 
720 static const struct dcn_hubp2_shift hubp_shift = {
721 		HUBP_MASK_SH_LIST_DCN30(__SHIFT)
722 };
723 
724 static const struct dcn_hubp2_mask hubp_mask = {
725 		HUBP_MASK_SH_LIST_DCN30(_MASK)
726 };
727 
728 static const struct dcn_hubbub_registers hubbub_reg = {
729 		HUBBUB_REG_LIST_DCN30(0)
730 };
731 
732 static const struct dcn_hubbub_shift hubbub_shift = {
733 		HUBBUB_MASK_SH_LIST_DCN30(__SHIFT)
734 };
735 
736 static const struct dcn_hubbub_mask hubbub_mask = {
737 		HUBBUB_MASK_SH_LIST_DCN30(_MASK)
738 };
739 
740 static const struct dccg_registers dccg_regs = {
741 		DCCG_REG_LIST_DCN30()
742 };
743 
744 static const struct dccg_shift dccg_shift = {
745 		DCCG_MASK_SH_LIST_DCN3(__SHIFT)
746 };
747 
748 static const struct dccg_mask dccg_mask = {
749 		DCCG_MASK_SH_LIST_DCN3(_MASK)
750 };
751 
752 static const struct dce_hwseq_registers hwseq_reg = {
753 		HWSEQ_DCN30_REG_LIST()
754 };
755 
756 static const struct dce_hwseq_shift hwseq_shift = {
757 		HWSEQ_DCN30_MASK_SH_LIST(__SHIFT)
758 };
759 
760 static const struct dce_hwseq_mask hwseq_mask = {
761 		HWSEQ_DCN30_MASK_SH_LIST(_MASK)
762 };
763 #define vmid_regs(id)\
764 [id] = {\
765 		DCN20_VMID_REG_LIST(id)\
766 }
767 
768 static const struct dcn_vmid_registers vmid_regs[] = {
769 	vmid_regs(0),
770 	vmid_regs(1),
771 	vmid_regs(2),
772 	vmid_regs(3),
773 	vmid_regs(4),
774 	vmid_regs(5),
775 	vmid_regs(6),
776 	vmid_regs(7),
777 	vmid_regs(8),
778 	vmid_regs(9),
779 	vmid_regs(10),
780 	vmid_regs(11),
781 	vmid_regs(12),
782 	vmid_regs(13),
783 	vmid_regs(14),
784 	vmid_regs(15)
785 };
786 
787 static const struct dcn20_vmid_shift vmid_shifts = {
788 		DCN20_VMID_MASK_SH_LIST(__SHIFT)
789 };
790 
791 static const struct dcn20_vmid_mask vmid_masks = {
792 		DCN20_VMID_MASK_SH_LIST(_MASK)
793 };
794 
795 static const struct resource_caps res_cap_dcn3 = {
796 	.num_timing_generator = 6,
797 	.num_opp = 6,
798 	.num_video_plane = 6,
799 	.num_audio = 6,
800 	.num_stream_encoder = 6,
801 	.num_pll = 6,
802 	.num_dwb = 1,
803 	.num_ddc = 6,
804 	.num_vmid = 16,
805 	.num_mpc_3dlut = 3,
806 	.num_dsc = 6,
807 };
808 
809 static const struct dc_plane_cap plane_cap = {
810 	.type = DC_PLANE_TYPE_DCN_UNIVERSAL,
811 	.blends_with_above = true,
812 	.blends_with_below = true,
813 	.per_pixel_alpha = true,
814 
815 	.pixel_format_support = {
816 			.argb8888 = true,
817 			.nv12 = true,
818 			.fp16 = true,
819 			.p010 = false,
820 			.ayuv = false,
821 	},
822 
823 	.max_upscale_factor = {
824 			.argb8888 = 16000,
825 			.nv12 = 16000,
826 			.fp16 = 16000
827 	},
828 
829 	/* 6:1 downscaling ratio: 1000/6 = 166.666 */
830 	.max_downscale_factor = {
831 			.argb8888 = 167,
832 			.nv12 = 167,
833 			.fp16 = 167
834 	}
835 };
836 
837 static const struct dc_debug_options debug_defaults_drv = {
838 	.disable_dmcu = true, //No DMCU on DCN30
839 	.force_abm_enable = false,
840 	.timing_trace = false,
841 	.clock_trace = true,
842 	.disable_pplib_clock_request = true,
843 	.pipe_split_policy = MPC_SPLIT_DYNAMIC,
844 	.force_single_disp_pipe_split = false,
845 	.disable_dcc = DCC_ENABLE,
846 	.vsr_support = true,
847 	.performance_trace = false,
848 	.max_downscale_src_width = 7680,/*upto 8K*/
849 	.disable_pplib_wm_range = false,
850 	.scl_reset_length10 = true,
851 	.sanity_checks = false,
852 	.underflow_assert_delay_us = 0xFFFFFFFF,
853 	.dwb_fi_phase = -1, // -1 = disable,
854 	.dmub_command_table = true,
855 	.disable_psr = false,
856 	.use_max_lb = true
857 };
858 
859 static const struct dc_debug_options debug_defaults_diags = {
860 	.disable_dmcu = true, //No dmcu on DCN30
861 	.force_abm_enable = false,
862 	.timing_trace = true,
863 	.clock_trace = true,
864 	.disable_dpp_power_gate = true,
865 	.disable_hubp_power_gate = true,
866 	.disable_clock_gate = true,
867 	.disable_pplib_clock_request = true,
868 	.disable_pplib_wm_range = true,
869 	.disable_stutter = false,
870 	.scl_reset_length10 = true,
871 	.dwb_fi_phase = -1, // -1 = disable
872 	.dmub_command_table = true,
873 	.disable_psr = true,
874 	.enable_tri_buf = true,
875 	.use_max_lb = true
876 };
877 
878 void dcn30_dpp_destroy(struct dpp **dpp)
879 {
880 	kfree(TO_DCN20_DPP(*dpp));
881 	*dpp = NULL;
882 }
883 
884 static struct dpp *dcn30_dpp_create(
885 	struct dc_context *ctx,
886 	uint32_t inst)
887 {
888 	struct dcn3_dpp *dpp =
889 		kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);
890 
891 	if (!dpp)
892 		return NULL;
893 
894 	if (dpp3_construct(dpp, ctx, inst,
895 			&dpp_regs[inst], &tf_shift, &tf_mask))
896 		return &dpp->base;
897 
898 	BREAK_TO_DEBUGGER();
899 	kfree(dpp);
900 	return NULL;
901 }
902 
903 static struct output_pixel_processor *dcn30_opp_create(
904 	struct dc_context *ctx, uint32_t inst)
905 {
906 	struct dcn20_opp *opp =
907 		kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
908 
909 	if (!opp) {
910 		BREAK_TO_DEBUGGER();
911 		return NULL;
912 	}
913 
914 	dcn20_opp_construct(opp, ctx, inst,
915 			&opp_regs[inst], &opp_shift, &opp_mask);
916 	return &opp->base;
917 }
918 
919 static struct dce_aux *dcn30_aux_engine_create(
920 	struct dc_context *ctx,
921 	uint32_t inst)
922 {
923 	struct aux_engine_dce110 *aux_engine =
924 		kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
925 
926 	if (!aux_engine)
927 		return NULL;
928 
929 	dce110_aux_engine_construct(aux_engine, ctx, inst,
930 				    SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
931 				    &aux_engine_regs[inst],
932 					&aux_mask,
933 					&aux_shift,
934 					ctx->dc->caps.extended_aux_timeout_support);
935 
936 	return &aux_engine->base;
937 }
938 
939 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) }
940 
941 static const struct dce_i2c_registers i2c_hw_regs[] = {
942 		i2c_inst_regs(1),
943 		i2c_inst_regs(2),
944 		i2c_inst_regs(3),
945 		i2c_inst_regs(4),
946 		i2c_inst_regs(5),
947 		i2c_inst_regs(6),
948 };
949 
950 static const struct dce_i2c_shift i2c_shifts = {
951 		I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
952 };
953 
954 static const struct dce_i2c_mask i2c_masks = {
955 		I2C_COMMON_MASK_SH_LIST_DCN30(_MASK)
956 };
957 
958 static struct dce_i2c_hw *dcn30_i2c_hw_create(
959 	struct dc_context *ctx,
960 	uint32_t inst)
961 {
962 	struct dce_i2c_hw *dce_i2c_hw =
963 		kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
964 
965 	if (!dce_i2c_hw)
966 		return NULL;
967 
968 	dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
969 				    &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
970 
971 	return dce_i2c_hw;
972 }
973 
974 static struct mpc *dcn30_mpc_create(
975 		struct dc_context *ctx,
976 		int num_mpcc,
977 		int num_rmu)
978 {
979 	struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc),
980 					  GFP_KERNEL);
981 
982 	if (!mpc30)
983 		return NULL;
984 
985 	dcn30_mpc_construct(mpc30, ctx,
986 			&mpc_regs,
987 			&mpc_shift,
988 			&mpc_mask,
989 			num_mpcc,
990 			num_rmu);
991 
992 	return &mpc30->base;
993 }
994 
995 struct hubbub *dcn30_hubbub_create(struct dc_context *ctx)
996 {
997 	int i;
998 
999 	struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub),
1000 					  GFP_KERNEL);
1001 
1002 	if (!hubbub3)
1003 		return NULL;
1004 
1005 	hubbub3_construct(hubbub3, ctx,
1006 			&hubbub_reg,
1007 			&hubbub_shift,
1008 			&hubbub_mask);
1009 
1010 
1011 	for (i = 0; i < res_cap_dcn3.num_vmid; i++) {
1012 		struct dcn20_vmid *vmid = &hubbub3->vmid[i];
1013 
1014 		vmid->ctx = ctx;
1015 
1016 		vmid->regs = &vmid_regs[i];
1017 		vmid->shifts = &vmid_shifts;
1018 		vmid->masks = &vmid_masks;
1019 	}
1020 
1021 	return &hubbub3->base;
1022 }
1023 
1024 static struct timing_generator *dcn30_timing_generator_create(
1025 		struct dc_context *ctx,
1026 		uint32_t instance)
1027 {
1028 	struct optc *tgn10 =
1029 		kzalloc(sizeof(struct optc), GFP_KERNEL);
1030 
1031 	if (!tgn10)
1032 		return NULL;
1033 
1034 	tgn10->base.inst = instance;
1035 	tgn10->base.ctx = ctx;
1036 
1037 	tgn10->tg_regs = &optc_regs[instance];
1038 	tgn10->tg_shift = &optc_shift;
1039 	tgn10->tg_mask = &optc_mask;
1040 
1041 	dcn30_timing_generator_init(tgn10);
1042 
1043 	return &tgn10->base;
1044 }
1045 
1046 static const struct encoder_feature_support link_enc_feature = {
1047 		.max_hdmi_deep_color = COLOR_DEPTH_121212,
1048 		.max_hdmi_pixel_clock = 600000,
1049 		.hdmi_ycbcr420_supported = true,
1050 		.dp_ycbcr420_supported = true,
1051 		.fec_supported = true,
1052 		.flags.bits.IS_HBR2_CAPABLE = true,
1053 		.flags.bits.IS_HBR3_CAPABLE = true,
1054 		.flags.bits.IS_TPS3_CAPABLE = true,
1055 		.flags.bits.IS_TPS4_CAPABLE = true
1056 };
1057 
1058 static struct link_encoder *dcn30_link_encoder_create(
1059 	const struct encoder_init_data *enc_init_data)
1060 {
1061 	struct dcn20_link_encoder *enc20 =
1062 		kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1063 
1064 	if (!enc20)
1065 		return NULL;
1066 
1067 	dcn30_link_encoder_construct(enc20,
1068 			enc_init_data,
1069 			&link_enc_feature,
1070 			&link_enc_regs[enc_init_data->transmitter],
1071 			&link_enc_aux_regs[enc_init_data->channel - 1],
1072 			&link_enc_hpd_regs[enc_init_data->hpd_source],
1073 			&le_shift,
1074 			&le_mask);
1075 
1076 	return &enc20->enc10.base;
1077 }
1078 
1079 static struct panel_cntl *dcn30_panel_cntl_create(const struct panel_cntl_init_data *init_data)
1080 {
1081 	struct dce_panel_cntl *panel_cntl =
1082 		kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
1083 
1084 	if (!panel_cntl)
1085 		return NULL;
1086 
1087 	dce_panel_cntl_construct(panel_cntl,
1088 			init_data,
1089 			&panel_cntl_regs[init_data->inst],
1090 			&panel_cntl_shift,
1091 			&panel_cntl_mask);
1092 
1093 	return &panel_cntl->base;
1094 }
1095 
1096 static void read_dce_straps(
1097 	struct dc_context *ctx,
1098 	struct resource_straps *straps)
1099 {
1100 	generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
1101 		FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1102 
1103 }
1104 
1105 static struct audio *dcn30_create_audio(
1106 		struct dc_context *ctx, unsigned int inst)
1107 {
1108 	return dce_audio_create(ctx, inst,
1109 			&audio_regs[inst], &audio_shift, &audio_mask);
1110 }
1111 
1112 static struct vpg *dcn30_vpg_create(
1113 	struct dc_context *ctx,
1114 	uint32_t inst)
1115 {
1116 	struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL);
1117 
1118 	if (!vpg3)
1119 		return NULL;
1120 
1121 	vpg3_construct(vpg3, ctx, inst,
1122 			&vpg_regs[inst],
1123 			&vpg_shift,
1124 			&vpg_mask);
1125 
1126 	return &vpg3->base;
1127 }
1128 
1129 static struct afmt *dcn30_afmt_create(
1130 	struct dc_context *ctx,
1131 	uint32_t inst)
1132 {
1133 	struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL);
1134 
1135 	if (!afmt3)
1136 		return NULL;
1137 
1138 	afmt3_construct(afmt3, ctx, inst,
1139 			&afmt_regs[inst],
1140 			&afmt_shift,
1141 			&afmt_mask);
1142 
1143 	return &afmt3->base;
1144 }
1145 
1146 struct stream_encoder *dcn30_stream_encoder_create(
1147 	enum engine_id eng_id,
1148 	struct dc_context *ctx)
1149 {
1150 	struct dcn10_stream_encoder *enc1;
1151 	struct vpg *vpg;
1152 	struct afmt *afmt;
1153 	int vpg_inst;
1154 	int afmt_inst;
1155 
1156 	/* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
1157 	if (eng_id <= ENGINE_ID_DIGF) {
1158 		vpg_inst = eng_id;
1159 		afmt_inst = eng_id;
1160 	} else
1161 		return NULL;
1162 
1163 	enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1164 	vpg = dcn30_vpg_create(ctx, vpg_inst);
1165 	afmt = dcn30_afmt_create(ctx, afmt_inst);
1166 
1167 	if (!enc1 || !vpg || !afmt)
1168 		return NULL;
1169 
1170 	dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
1171 					eng_id, vpg, afmt,
1172 					&stream_enc_regs[eng_id],
1173 					&se_shift, &se_mask);
1174 
1175 	return &enc1->base;
1176 }
1177 
1178 struct dce_hwseq *dcn30_hwseq_create(
1179 	struct dc_context *ctx)
1180 {
1181 	struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1182 
1183 	if (hws) {
1184 		hws->ctx = ctx;
1185 		hws->regs = &hwseq_reg;
1186 		hws->shifts = &hwseq_shift;
1187 		hws->masks = &hwseq_mask;
1188 	}
1189 	return hws;
1190 }
1191 static const struct resource_create_funcs res_create_funcs = {
1192 	.read_dce_straps = read_dce_straps,
1193 	.create_audio = dcn30_create_audio,
1194 	.create_stream_encoder = dcn30_stream_encoder_create,
1195 	.create_hwseq = dcn30_hwseq_create,
1196 };
1197 
1198 static const struct resource_create_funcs res_create_maximus_funcs = {
1199 	.read_dce_straps = NULL,
1200 	.create_audio = NULL,
1201 	.create_stream_encoder = NULL,
1202 	.create_hwseq = dcn30_hwseq_create,
1203 };
1204 
1205 static void dcn30_resource_destruct(struct dcn30_resource_pool *pool)
1206 {
1207 	unsigned int i;
1208 
1209 	for (i = 0; i < pool->base.stream_enc_count; i++) {
1210 		if (pool->base.stream_enc[i] != NULL) {
1211 			if (pool->base.stream_enc[i]->vpg != NULL) {
1212 				kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
1213 				pool->base.stream_enc[i]->vpg = NULL;
1214 			}
1215 			if (pool->base.stream_enc[i]->afmt != NULL) {
1216 				kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));
1217 				pool->base.stream_enc[i]->afmt = NULL;
1218 			}
1219 			kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1220 			pool->base.stream_enc[i] = NULL;
1221 		}
1222 	}
1223 
1224 	for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1225 		if (pool->base.dscs[i] != NULL)
1226 			dcn20_dsc_destroy(&pool->base.dscs[i]);
1227 	}
1228 
1229 	if (pool->base.mpc != NULL) {
1230 		kfree(TO_DCN20_MPC(pool->base.mpc));
1231 		pool->base.mpc = NULL;
1232 	}
1233 	if (pool->base.hubbub != NULL) {
1234 		kfree(pool->base.hubbub);
1235 		pool->base.hubbub = NULL;
1236 	}
1237 	for (i = 0; i < pool->base.pipe_count; i++) {
1238 		if (pool->base.dpps[i] != NULL)
1239 			dcn30_dpp_destroy(&pool->base.dpps[i]);
1240 
1241 		if (pool->base.ipps[i] != NULL)
1242 			pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1243 
1244 		if (pool->base.hubps[i] != NULL) {
1245 			kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1246 			pool->base.hubps[i] = NULL;
1247 		}
1248 
1249 		if (pool->base.irqs != NULL) {
1250 			dal_irq_service_destroy(&pool->base.irqs);
1251 		}
1252 	}
1253 
1254 	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1255 		if (pool->base.engines[i] != NULL)
1256 			dce110_engine_destroy(&pool->base.engines[i]);
1257 		if (pool->base.hw_i2cs[i] != NULL) {
1258 			kfree(pool->base.hw_i2cs[i]);
1259 			pool->base.hw_i2cs[i] = NULL;
1260 		}
1261 		if (pool->base.sw_i2cs[i] != NULL) {
1262 			kfree(pool->base.sw_i2cs[i]);
1263 			pool->base.sw_i2cs[i] = NULL;
1264 		}
1265 	}
1266 
1267 	for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1268 		if (pool->base.opps[i] != NULL)
1269 			pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1270 	}
1271 
1272 	for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1273 		if (pool->base.timing_generators[i] != NULL)	{
1274 			kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1275 			pool->base.timing_generators[i] = NULL;
1276 		}
1277 	}
1278 
1279 	for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1280 		if (pool->base.dwbc[i] != NULL) {
1281 			kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
1282 			pool->base.dwbc[i] = NULL;
1283 		}
1284 		if (pool->base.mcif_wb[i] != NULL) {
1285 			kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));
1286 			pool->base.mcif_wb[i] = NULL;
1287 		}
1288 	}
1289 
1290 	for (i = 0; i < pool->base.audio_count; i++) {
1291 		if (pool->base.audios[i])
1292 			dce_aud_destroy(&pool->base.audios[i]);
1293 	}
1294 
1295 	for (i = 0; i < pool->base.clk_src_count; i++) {
1296 		if (pool->base.clock_sources[i] != NULL) {
1297 			dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1298 			pool->base.clock_sources[i] = NULL;
1299 		}
1300 	}
1301 
1302 	for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
1303 		if (pool->base.mpc_lut[i] != NULL) {
1304 			dc_3dlut_func_release(pool->base.mpc_lut[i]);
1305 			pool->base.mpc_lut[i] = NULL;
1306 		}
1307 		if (pool->base.mpc_shaper[i] != NULL) {
1308 			dc_transfer_func_release(pool->base.mpc_shaper[i]);
1309 			pool->base.mpc_shaper[i] = NULL;
1310 		}
1311 	}
1312 
1313 	if (pool->base.dp_clock_source != NULL) {
1314 		dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1315 		pool->base.dp_clock_source = NULL;
1316 	}
1317 
1318 	for (i = 0; i < pool->base.pipe_count; i++) {
1319 		if (pool->base.multiple_abms[i] != NULL)
1320 			dce_abm_destroy(&pool->base.multiple_abms[i]);
1321 	}
1322 
1323 	if (pool->base.psr != NULL)
1324 		dmub_psr_destroy(&pool->base.psr);
1325 
1326 	if (pool->base.dccg != NULL)
1327 		dcn_dccg_destroy(&pool->base.dccg);
1328 
1329 	if (pool->base.oem_device != NULL)
1330 		dal_ddc_service_destroy(&pool->base.oem_device);
1331 }
1332 
1333 static struct hubp *dcn30_hubp_create(
1334 	struct dc_context *ctx,
1335 	uint32_t inst)
1336 {
1337 	struct dcn20_hubp *hubp2 =
1338 		kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
1339 
1340 	if (!hubp2)
1341 		return NULL;
1342 
1343 	if (hubp3_construct(hubp2, ctx, inst,
1344 			&hubp_regs[inst], &hubp_shift, &hubp_mask))
1345 		return &hubp2->base;
1346 
1347 	BREAK_TO_DEBUGGER();
1348 	kfree(hubp2);
1349 	return NULL;
1350 }
1351 
1352 static bool dcn30_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
1353 {
1354 	int i;
1355 	uint32_t pipe_count = pool->res_cap->num_dwb;
1356 
1357 	for (i = 0; i < pipe_count; i++) {
1358 		struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc),
1359 						    GFP_KERNEL);
1360 
1361 		if (!dwbc30) {
1362 			dm_error("DC: failed to create dwbc30!\n");
1363 			return false;
1364 		}
1365 
1366 		dcn30_dwbc_construct(dwbc30, ctx,
1367 				&dwbc30_regs[i],
1368 				&dwbc30_shift,
1369 				&dwbc30_mask,
1370 				i);
1371 
1372 		pool->dwbc[i] = &dwbc30->base;
1373 	}
1374 	return true;
1375 }
1376 
1377 static bool dcn30_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
1378 {
1379 	int i;
1380 	uint32_t pipe_count = pool->res_cap->num_dwb;
1381 
1382 	for (i = 0; i < pipe_count; i++) {
1383 		struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub),
1384 						    GFP_KERNEL);
1385 
1386 		if (!mcif_wb30) {
1387 			dm_error("DC: failed to create mcif_wb30!\n");
1388 			return false;
1389 		}
1390 
1391 		dcn30_mmhubbub_construct(mcif_wb30, ctx,
1392 				&mcif_wb30_regs[i],
1393 				&mcif_wb30_shift,
1394 				&mcif_wb30_mask,
1395 				i);
1396 
1397 		pool->mcif_wb[i] = &mcif_wb30->base;
1398 	}
1399 	return true;
1400 }
1401 
1402 static struct display_stream_compressor *dcn30_dsc_create(
1403 	struct dc_context *ctx, uint32_t inst)
1404 {
1405 	struct dcn20_dsc *dsc =
1406 		kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1407 
1408 	if (!dsc) {
1409 		BREAK_TO_DEBUGGER();
1410 		return NULL;
1411 	}
1412 
1413 	dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1414 	return &dsc->base;
1415 }
1416 
1417 enum dc_status dcn30_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream)
1418 {
1419 
1420 	return dcn20_add_stream_to_ctx(dc, new_ctx, dc_stream);
1421 }
1422 
1423 static void dcn30_destroy_resource_pool(struct resource_pool **pool)
1424 {
1425 	struct dcn30_resource_pool *dcn30_pool = TO_DCN30_RES_POOL(*pool);
1426 
1427 	dcn30_resource_destruct(dcn30_pool);
1428 	kfree(dcn30_pool);
1429 	*pool = NULL;
1430 }
1431 
1432 static struct clock_source *dcn30_clock_source_create(
1433 		struct dc_context *ctx,
1434 		struct dc_bios *bios,
1435 		enum clock_source_id id,
1436 		const struct dce110_clk_src_regs *regs,
1437 		bool dp_clk_src)
1438 {
1439 	struct dce110_clk_src *clk_src =
1440 		kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1441 
1442 	if (!clk_src)
1443 		return NULL;
1444 
1445 	if (dcn3_clk_src_construct(clk_src, ctx, bios, id,
1446 			regs, &cs_shift, &cs_mask)) {
1447 		clk_src->base.dp_clk_src = dp_clk_src;
1448 		return &clk_src->base;
1449 	}
1450 
1451 	BREAK_TO_DEBUGGER();
1452 	return NULL;
1453 }
1454 
1455 int dcn30_populate_dml_pipes_from_context(
1456 	struct dc *dc, struct dc_state *context,
1457 	display_e2e_pipe_params_st *pipes,
1458 	bool fast_validate)
1459 {
1460 	int i, pipe_cnt;
1461 	struct resource_context *res_ctx = &context->res_ctx;
1462 
1463 	dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);
1464 
1465 	for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1466 		if (!res_ctx->pipe_ctx[i].stream)
1467 			continue;
1468 
1469 		pipes[pipe_cnt++].pipe.scale_ratio_depth.lb_depth =
1470 			dm_lb_16;
1471 	}
1472 
1473 	return pipe_cnt;
1474 }
1475 
1476 void dcn30_populate_dml_writeback_from_context(
1477 	struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes)
1478 {
1479 	int pipe_cnt, i, j;
1480 	double max_calc_writeback_dispclk;
1481 	double writeback_dispclk;
1482 	struct writeback_st dout_wb;
1483 
1484 	for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1485 		struct dc_stream_state *stream = res_ctx->pipe_ctx[i].stream;
1486 
1487 		if (!stream)
1488 			continue;
1489 		max_calc_writeback_dispclk = 0;
1490 
1491 		/* Set writeback information */
1492 		pipes[pipe_cnt].dout.wb_enable = 0;
1493 		pipes[pipe_cnt].dout.num_active_wb = 0;
1494 		for (j = 0; j < stream->num_wb_info; j++) {
1495 			struct dc_writeback_info *wb_info = &stream->writeback_info[j];
1496 
1497 			if (wb_info->wb_enabled && wb_info->writeback_source_plane &&
1498 					(wb_info->writeback_source_plane == res_ctx->pipe_ctx[i].plane_state)) {
1499 				pipes[pipe_cnt].dout.wb_enable = 1;
1500 				pipes[pipe_cnt].dout.num_active_wb++;
1501 				dout_wb.wb_src_height = wb_info->dwb_params.cnv_params.crop_en ?
1502 					wb_info->dwb_params.cnv_params.crop_height :
1503 					wb_info->dwb_params.cnv_params.src_height;
1504 				dout_wb.wb_src_width = wb_info->dwb_params.cnv_params.crop_en ?
1505 					wb_info->dwb_params.cnv_params.crop_width :
1506 					wb_info->dwb_params.cnv_params.src_width;
1507 				dout_wb.wb_dst_width = wb_info->dwb_params.dest_width;
1508 				dout_wb.wb_dst_height = wb_info->dwb_params.dest_height;
1509 
1510 				/* For IP that doesn't support WB scaling, set h/v taps to 1 to avoid DML validation failure */
1511 				if (dc->dml.ip.writeback_max_hscl_taps > 1) {
1512 					dout_wb.wb_htaps_luma = wb_info->dwb_params.scaler_taps.h_taps;
1513 					dout_wb.wb_vtaps_luma = wb_info->dwb_params.scaler_taps.v_taps;
1514 				} else {
1515 					dout_wb.wb_htaps_luma = 1;
1516 					dout_wb.wb_vtaps_luma = 1;
1517 				}
1518 				dout_wb.wb_htaps_chroma = 0;
1519 				dout_wb.wb_vtaps_chroma = 0;
1520 				dout_wb.wb_hratio = wb_info->dwb_params.cnv_params.crop_en ?
1521 					(double)wb_info->dwb_params.cnv_params.crop_width /
1522 						(double)wb_info->dwb_params.dest_width :
1523 					(double)wb_info->dwb_params.cnv_params.src_width /
1524 						(double)wb_info->dwb_params.dest_width;
1525 				dout_wb.wb_vratio = wb_info->dwb_params.cnv_params.crop_en ?
1526 					(double)wb_info->dwb_params.cnv_params.crop_height /
1527 						(double)wb_info->dwb_params.dest_height :
1528 					(double)wb_info->dwb_params.cnv_params.src_height /
1529 						(double)wb_info->dwb_params.dest_height;
1530 				if (wb_info->dwb_params.cnv_params.fc_out_format == DWB_OUT_FORMAT_64BPP_ARGB ||
1531 					wb_info->dwb_params.cnv_params.fc_out_format == DWB_OUT_FORMAT_64BPP_RGBA)
1532 					dout_wb.wb_pixel_format = dm_444_64;
1533 				else
1534 					dout_wb.wb_pixel_format = dm_444_32;
1535 
1536 				/* Workaround for cases where multiple writebacks are connected to same plane
1537 				 * In which case, need to compute worst case and set the associated writeback parameters
1538 				 * This workaround is necessary due to DML computation assuming only 1 set of writeback
1539 				 * parameters per pipe
1540 				 */
1541 				writeback_dispclk = dml30_CalculateWriteBackDISPCLK(
1542 						dout_wb.wb_pixel_format,
1543 						pipes[pipe_cnt].pipe.dest.pixel_rate_mhz,
1544 						dout_wb.wb_hratio,
1545 						dout_wb.wb_vratio,
1546 						dout_wb.wb_htaps_luma,
1547 						dout_wb.wb_vtaps_luma,
1548 						dout_wb.wb_src_width,
1549 						dout_wb.wb_dst_width,
1550 						pipes[pipe_cnt].pipe.dest.htotal,
1551 						dc->current_state->bw_ctx.dml.ip.writeback_line_buffer_buffer_size);
1552 
1553 				if (writeback_dispclk > max_calc_writeback_dispclk) {
1554 					max_calc_writeback_dispclk = writeback_dispclk;
1555 					pipes[pipe_cnt].dout.wb = dout_wb;
1556 				}
1557 			}
1558 		}
1559 
1560 		pipe_cnt++;
1561 	}
1562 
1563 }
1564 
1565 unsigned int dcn30_calc_max_scaled_time(
1566 		unsigned int time_per_pixel,
1567 		enum mmhubbub_wbif_mode mode,
1568 		unsigned int urgent_watermark)
1569 {
1570 	unsigned int time_per_byte = 0;
1571 	unsigned int total_free_entry = 0xb40;
1572 	unsigned int buf_lh_capability;
1573 	unsigned int max_scaled_time;
1574 
1575 	if (mode == PACKED_444) /* packed mode 32 bpp */
1576 		time_per_byte = time_per_pixel/4;
1577 	else if (mode == PACKED_444_FP16) /* packed mode 64 bpp */
1578 		time_per_byte = time_per_pixel/8;
1579 
1580 	if (time_per_byte == 0)
1581 		time_per_byte = 1;
1582 
1583 	buf_lh_capability = (total_free_entry*time_per_byte*32) >> 6; /* time_per_byte is in u6.6*/
1584 	max_scaled_time   = buf_lh_capability - urgent_watermark;
1585 	return max_scaled_time;
1586 }
1587 
1588 void dcn30_set_mcif_arb_params(
1589 		struct dc *dc,
1590 		struct dc_state *context,
1591 		display_e2e_pipe_params_st *pipes,
1592 		int pipe_cnt)
1593 {
1594 	enum mmhubbub_wbif_mode wbif_mode;
1595 	struct display_mode_lib *dml = &context->bw_ctx.dml;
1596 	struct mcif_arb_params *wb_arb_params;
1597 	int i, j, k, dwb_pipe;
1598 
1599 	/* Writeback MCIF_WB arbitration parameters */
1600 	dwb_pipe = 0;
1601 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
1602 
1603 		if (!context->res_ctx.pipe_ctx[i].stream)
1604 			continue;
1605 
1606 		for (j = 0; j < MAX_DWB_PIPES; j++) {
1607 			struct dc_writeback_info *writeback_info = &context->res_ctx.pipe_ctx[i].stream->writeback_info[j];
1608 
1609 			if (writeback_info->wb_enabled == false)
1610 				continue;
1611 
1612 			//wb_arb_params = &context->res_ctx.pipe_ctx[i].stream->writeback_info[j].mcif_arb_params;
1613 			wb_arb_params = &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[dwb_pipe];
1614 
1615 			if (writeback_info->dwb_params.cnv_params.fc_out_format == DWB_OUT_FORMAT_64BPP_ARGB ||
1616 				writeback_info->dwb_params.cnv_params.fc_out_format == DWB_OUT_FORMAT_64BPP_RGBA)
1617 				wbif_mode = PACKED_444_FP16;
1618 			else
1619 				wbif_mode = PACKED_444;
1620 
1621 			for (k = 0; k < sizeof(wb_arb_params->cli_watermark)/sizeof(wb_arb_params->cli_watermark[0]); k++) {
1622 				wb_arb_params->cli_watermark[k] = get_wm_writeback_urgent(dml, pipes, pipe_cnt) * 1000;
1623 				wb_arb_params->pstate_watermark[k] = get_wm_writeback_dram_clock_change(dml, pipes, pipe_cnt) * 1000;
1624 			}
1625 			wb_arb_params->time_per_pixel = (1000000 << 6) / context->res_ctx.pipe_ctx[i].stream->phy_pix_clk; /* time_per_pixel should be in u6.6 format */
1626 			wb_arb_params->slice_lines = 32;
1627 			wb_arb_params->arbitration_slice = 2; /* irrelevant since there is no YUV output */
1628 			wb_arb_params->max_scaled_time = dcn30_calc_max_scaled_time(wb_arb_params->time_per_pixel,
1629 					wbif_mode,
1630 					wb_arb_params->cli_watermark[0]); /* assume 4 watermark sets have the same value */
1631 			wb_arb_params->dram_speed_change_duration = dml->vba.WritebackAllowDRAMClockChangeEndPosition[j] * pipes[0].clks_cfg.refclk_mhz; /* num_clock_cycles = us * MHz */
1632 
1633 			dwb_pipe++;
1634 
1635 			if (dwb_pipe >= MAX_DWB_PIPES)
1636 				return;
1637 		}
1638 		if (dwb_pipe >= MAX_DWB_PIPES)
1639 			return;
1640 	}
1641 
1642 }
1643 
1644 static struct dc_cap_funcs cap_funcs = {
1645 	.get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1646 };
1647 
1648 bool dcn30_acquire_post_bldn_3dlut(
1649 		struct resource_context *res_ctx,
1650 		const struct resource_pool *pool,
1651 		int mpcc_id,
1652 		struct dc_3dlut **lut,
1653 		struct dc_transfer_func **shaper)
1654 {
1655 	int i;
1656 	bool ret = false;
1657 	union dc_3dlut_state *state;
1658 
1659 	ASSERT(*lut == NULL && *shaper == NULL);
1660 	*lut = NULL;
1661 	*shaper = NULL;
1662 
1663 	for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) {
1664 		if (!res_ctx->is_mpc_3dlut_acquired[i]) {
1665 			*lut = pool->mpc_lut[i];
1666 			*shaper = pool->mpc_shaper[i];
1667 			state = &pool->mpc_lut[i]->state;
1668 			res_ctx->is_mpc_3dlut_acquired[i] = true;
1669 			state->bits.rmu_idx_valid = 1;
1670 			state->bits.rmu_mux_num = i;
1671 			if (state->bits.rmu_mux_num == 0)
1672 				state->bits.mpc_rmu0_mux = mpcc_id;
1673 			else if (state->bits.rmu_mux_num == 1)
1674 				state->bits.mpc_rmu1_mux = mpcc_id;
1675 			else if (state->bits.rmu_mux_num == 2)
1676 				state->bits.mpc_rmu2_mux = mpcc_id;
1677 			ret = true;
1678 			break;
1679 			}
1680 		}
1681 	return ret;
1682 }
1683 
1684 bool dcn30_release_post_bldn_3dlut(
1685 		struct resource_context *res_ctx,
1686 		const struct resource_pool *pool,
1687 		struct dc_3dlut **lut,
1688 		struct dc_transfer_func **shaper)
1689 {
1690 	int i;
1691 	bool ret = false;
1692 
1693 	for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) {
1694 		if (pool->mpc_lut[i] == *lut && pool->mpc_shaper[i] == *shaper) {
1695 			res_ctx->is_mpc_3dlut_acquired[i] = false;
1696 			pool->mpc_lut[i]->state.raw = 0;
1697 			*lut = NULL;
1698 			*shaper = NULL;
1699 			ret = true;
1700 			break;
1701 		}
1702 	}
1703 	return ret;
1704 }
1705 
1706 #define fixed16_to_double(x) (((double) x) / ((double) (1 << 16)))
1707 #define fixed16_to_double_to_cpu(x) fixed16_to_double(le32_to_cpu(x))
1708 
1709 static bool is_soc_bounding_box_valid(struct dc *dc)
1710 {
1711 	uint32_t hw_internal_rev = dc->ctx->asic_id.hw_internal_rev;
1712 
1713 	if (ASICREV_IS_SIENNA_CICHLID_P(hw_internal_rev))
1714 		return true;
1715 
1716 	return false;
1717 }
1718 
1719 static bool init_soc_bounding_box(struct dc *dc,
1720 				  struct dcn30_resource_pool *pool)
1721 {
1722 	struct _vcs_dpi_soc_bounding_box_st *loaded_bb = &dcn3_0_soc;
1723 	struct _vcs_dpi_ip_params_st *loaded_ip = &dcn3_0_ip;
1724 
1725 	DC_LOGGER_INIT(dc->ctx->logger);
1726 
1727 	if (!is_soc_bounding_box_valid(dc)) {
1728 		DC_LOG_ERROR("%s: not valid soc bounding box\n", __func__);
1729 		return false;
1730 	}
1731 
1732 	loaded_ip->max_num_otg = pool->base.res_cap->num_timing_generator;
1733 	loaded_ip->max_num_dpp = pool->base.pipe_count;
1734 	loaded_ip->clamp_min_dcfclk = dc->config.clamp_min_dcfclk;
1735 	dcn20_patch_bounding_box(dc, loaded_bb);
1736 
1737 	if (dc->ctx->dc_bios->funcs->get_soc_bb_info) {
1738 		struct bp_soc_bb_info bb_info = {0};
1739 
1740 		if (dc->ctx->dc_bios->funcs->get_soc_bb_info(dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) {
1741 			if (bb_info.dram_clock_change_latency_100ns > 0)
1742 				dcn3_0_soc.dram_clock_change_latency_us = bb_info.dram_clock_change_latency_100ns * 10;
1743 
1744 			if (bb_info.dram_sr_enter_exit_latency_100ns > 0)
1745 				dcn3_0_soc.sr_enter_plus_exit_time_us = bb_info.dram_sr_enter_exit_latency_100ns * 10;
1746 
1747 			if (bb_info.dram_sr_exit_latency_100ns > 0)
1748 				dcn3_0_soc.sr_exit_time_us = bb_info.dram_sr_exit_latency_100ns * 10;
1749 		}
1750 	}
1751 
1752 	return true;
1753 }
1754 
1755 static bool dcn30_split_stream_for_mpc_or_odm(
1756 		const struct dc *dc,
1757 		struct resource_context *res_ctx,
1758 		struct pipe_ctx *pri_pipe,
1759 		struct pipe_ctx *sec_pipe,
1760 		bool odm)
1761 {
1762 	int pipe_idx = sec_pipe->pipe_idx;
1763 	const struct resource_pool *pool = dc->res_pool;
1764 
1765 	*sec_pipe = *pri_pipe;
1766 
1767 	sec_pipe->pipe_idx = pipe_idx;
1768 	sec_pipe->plane_res.mi = pool->mis[pipe_idx];
1769 	sec_pipe->plane_res.hubp = pool->hubps[pipe_idx];
1770 	sec_pipe->plane_res.ipp = pool->ipps[pipe_idx];
1771 	sec_pipe->plane_res.xfm = pool->transforms[pipe_idx];
1772 	sec_pipe->plane_res.dpp = pool->dpps[pipe_idx];
1773 	sec_pipe->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst;
1774 	sec_pipe->stream_res.dsc = NULL;
1775 	if (odm) {
1776 		if (pri_pipe->next_odm_pipe) {
1777 			ASSERT(pri_pipe->next_odm_pipe != sec_pipe);
1778 			sec_pipe->next_odm_pipe = pri_pipe->next_odm_pipe;
1779 			sec_pipe->next_odm_pipe->prev_odm_pipe = sec_pipe;
1780 		}
1781 		if (pri_pipe->top_pipe && pri_pipe->top_pipe->next_odm_pipe) {
1782 			pri_pipe->top_pipe->next_odm_pipe->bottom_pipe = sec_pipe;
1783 			sec_pipe->top_pipe = pri_pipe->top_pipe->next_odm_pipe;
1784 		}
1785 		if (pri_pipe->bottom_pipe && pri_pipe->bottom_pipe->next_odm_pipe) {
1786 			pri_pipe->bottom_pipe->next_odm_pipe->top_pipe = sec_pipe;
1787 			sec_pipe->bottom_pipe = pri_pipe->bottom_pipe->next_odm_pipe;
1788 		}
1789 		pri_pipe->next_odm_pipe = sec_pipe;
1790 		sec_pipe->prev_odm_pipe = pri_pipe;
1791 		ASSERT(sec_pipe->top_pipe == NULL);
1792 
1793 		if (!sec_pipe->top_pipe)
1794 			sec_pipe->stream_res.opp = pool->opps[pipe_idx];
1795 		else
1796 			sec_pipe->stream_res.opp = sec_pipe->top_pipe->stream_res.opp;
1797 		if (sec_pipe->stream->timing.flags.DSC == 1) {
1798 			dcn20_acquire_dsc(dc, res_ctx, &sec_pipe->stream_res.dsc, pipe_idx);
1799 			ASSERT(sec_pipe->stream_res.dsc);
1800 			if (sec_pipe->stream_res.dsc == NULL)
1801 				return false;
1802 		}
1803 	} else {
1804 		if (pri_pipe->bottom_pipe) {
1805 			ASSERT(pri_pipe->bottom_pipe != sec_pipe);
1806 			sec_pipe->bottom_pipe = pri_pipe->bottom_pipe;
1807 			sec_pipe->bottom_pipe->top_pipe = sec_pipe;
1808 		}
1809 		pri_pipe->bottom_pipe = sec_pipe;
1810 		sec_pipe->top_pipe = pri_pipe;
1811 
1812 		ASSERT(pri_pipe->plane_state);
1813 	}
1814 
1815 	return true;
1816 }
1817 
1818 static struct pipe_ctx *dcn30_find_split_pipe(
1819 		struct dc *dc,
1820 		struct dc_state *context,
1821 		int old_index)
1822 {
1823 	struct pipe_ctx *pipe = NULL;
1824 	int i;
1825 
1826 	if (old_index >= 0 && context->res_ctx.pipe_ctx[old_index].stream == NULL) {
1827 		pipe = &context->res_ctx.pipe_ctx[old_index];
1828 		pipe->pipe_idx = old_index;
1829 	}
1830 
1831 	if (!pipe)
1832 		for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) {
1833 			if (dc->current_state->res_ctx.pipe_ctx[i].top_pipe == NULL
1834 					&& dc->current_state->res_ctx.pipe_ctx[i].prev_odm_pipe == NULL) {
1835 				if (context->res_ctx.pipe_ctx[i].stream == NULL) {
1836 					pipe = &context->res_ctx.pipe_ctx[i];
1837 					pipe->pipe_idx = i;
1838 					break;
1839 				}
1840 			}
1841 		}
1842 
1843 	/*
1844 	 * May need to fix pipes getting tossed from 1 opp to another on flip
1845 	 * Add for debugging transient underflow during topology updates:
1846 	 * ASSERT(pipe);
1847 	 */
1848 	if (!pipe)
1849 		for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) {
1850 			if (context->res_ctx.pipe_ctx[i].stream == NULL) {
1851 				pipe = &context->res_ctx.pipe_ctx[i];
1852 				pipe->pipe_idx = i;
1853 				break;
1854 			}
1855 		}
1856 
1857 	return pipe;
1858 }
1859 
1860 static noinline bool dcn30_internal_validate_bw(
1861 		struct dc *dc,
1862 		struct dc_state *context,
1863 		display_e2e_pipe_params_st *pipes,
1864 		int *pipe_cnt_out,
1865 		int *vlevel_out,
1866 		bool fast_validate)
1867 {
1868 	bool out = false;
1869 	bool repopulate_pipes = false;
1870 	int split[MAX_PIPES] = { 0 };
1871 	bool merge[MAX_PIPES] = { false };
1872 	bool newly_split[MAX_PIPES] = { false };
1873 	int pipe_cnt, i, pipe_idx, vlevel;
1874 	struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
1875 
1876 	ASSERT(pipes);
1877 	if (!pipes)
1878 		return false;
1879 
1880 	dc->res_pool->funcs->update_soc_for_wm_a(dc, context);
1881 	pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate);
1882 
1883 	DC_FP_START();
1884 	if (!pipe_cnt) {
1885 		out = true;
1886 		goto validate_out;
1887 	}
1888 
1889 	dml_log_pipe_params(&context->bw_ctx.dml, pipes, pipe_cnt);
1890 
1891 	if (!fast_validate) {
1892 		/*
1893 		 * DML favors voltage over p-state, but we're more interested in
1894 		 * supporting p-state over voltage. We can't support p-state in
1895 		 * prefetch mode > 0 so try capping the prefetch mode to start.
1896 		 */
1897 		context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank =
1898 			dm_allow_self_refresh_and_mclk_switch;
1899 		vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
1900 		/* This may adjust vlevel and maxMpcComb */
1901 		if (vlevel < context->bw_ctx.dml.soc.num_states)
1902 			vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge);
1903 	}
1904 	if (fast_validate || vlevel == context->bw_ctx.dml.soc.num_states ||
1905 			vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported) {
1906 		/*
1907 		 * If mode is unsupported or there's still no p-state support then
1908 		 * fall back to favoring voltage.
1909 		 *
1910 		 * We don't actually support prefetch mode 2, so require that we
1911 		 * at least support prefetch mode 1.
1912 		 */
1913 		context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank =
1914 			dm_allow_self_refresh;
1915 
1916 		vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
1917 		if (vlevel < context->bw_ctx.dml.soc.num_states) {
1918 			memset(split, 0, sizeof(split));
1919 			memset(merge, 0, sizeof(merge));
1920 			vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge);
1921 		}
1922 	}
1923 
1924 	dml_log_mode_support_params(&context->bw_ctx.dml);
1925 
1926 	if (vlevel == context->bw_ctx.dml.soc.num_states)
1927 		goto validate_fail;
1928 
1929 	for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
1930 		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1931 		struct pipe_ctx *mpo_pipe = pipe->bottom_pipe;
1932 
1933 		if (!pipe->stream)
1934 			continue;
1935 
1936 		/* We only support full screen mpo with ODM */
1937 		if (vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled
1938 				&& pipe->plane_state && mpo_pipe
1939 				&& memcmp(&mpo_pipe->plane_res.scl_data.recout,
1940 						&pipe->plane_res.scl_data.recout,
1941 						sizeof(struct rect)) != 0) {
1942 			ASSERT(mpo_pipe->plane_state != pipe->plane_state);
1943 			goto validate_fail;
1944 		}
1945 		pipe_idx++;
1946 	}
1947 
1948 	/* merge pipes if necessary */
1949 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
1950 		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1951 
1952 		/*skip pipes that don't need merging*/
1953 		if (!merge[i])
1954 			continue;
1955 
1956 		/* if ODM merge we ignore mpc tree, mpo pipes will have their own flags */
1957 		if (pipe->prev_odm_pipe) {
1958 			/*split off odm pipe*/
1959 			pipe->prev_odm_pipe->next_odm_pipe = pipe->next_odm_pipe;
1960 			if (pipe->next_odm_pipe)
1961 				pipe->next_odm_pipe->prev_odm_pipe = pipe->prev_odm_pipe;
1962 
1963 			pipe->bottom_pipe = NULL;
1964 			pipe->next_odm_pipe = NULL;
1965 			pipe->plane_state = NULL;
1966 			pipe->stream = NULL;
1967 			pipe->top_pipe = NULL;
1968 			pipe->prev_odm_pipe = NULL;
1969 			if (pipe->stream_res.dsc)
1970 				dcn20_release_dsc(&context->res_ctx, dc->res_pool, &pipe->stream_res.dsc);
1971 			memset(&pipe->plane_res, 0, sizeof(pipe->plane_res));
1972 			memset(&pipe->stream_res, 0, sizeof(pipe->stream_res));
1973 			repopulate_pipes = true;
1974 		} else if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) {
1975 			struct pipe_ctx *top_pipe = pipe->top_pipe;
1976 			struct pipe_ctx *bottom_pipe = pipe->bottom_pipe;
1977 
1978 			top_pipe->bottom_pipe = bottom_pipe;
1979 			if (bottom_pipe)
1980 				bottom_pipe->top_pipe = top_pipe;
1981 
1982 			pipe->top_pipe = NULL;
1983 			pipe->bottom_pipe = NULL;
1984 			pipe->plane_state = NULL;
1985 			pipe->stream = NULL;
1986 			memset(&pipe->plane_res, 0, sizeof(pipe->plane_res));
1987 			memset(&pipe->stream_res, 0, sizeof(pipe->stream_res));
1988 			repopulate_pipes = true;
1989 		} else
1990 			ASSERT(0); /* Should never try to merge master pipe */
1991 
1992 	}
1993 
1994 	for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) {
1995 		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1996 		struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];
1997 		struct pipe_ctx *hsplit_pipe = NULL;
1998 		bool odm;
1999 		int old_index = -1;
2000 
2001 		if (!pipe->stream || newly_split[i])
2002 			continue;
2003 
2004 		pipe_idx++;
2005 		odm = vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled;
2006 
2007 		if (!pipe->plane_state && !odm)
2008 			continue;
2009 
2010 		if (split[i]) {
2011 			if (odm) {
2012 				if (split[i] == 4 && old_pipe->next_odm_pipe && old_pipe->next_odm_pipe->next_odm_pipe)
2013 					old_index = old_pipe->next_odm_pipe->next_odm_pipe->pipe_idx;
2014 				else if (old_pipe->next_odm_pipe)
2015 					old_index = old_pipe->next_odm_pipe->pipe_idx;
2016 			} else {
2017 				if (split[i] == 4 && old_pipe->bottom_pipe && old_pipe->bottom_pipe->bottom_pipe &&
2018 						old_pipe->bottom_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
2019 					old_index = old_pipe->bottom_pipe->bottom_pipe->pipe_idx;
2020 				else if (old_pipe->bottom_pipe &&
2021 						old_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
2022 					old_index = old_pipe->bottom_pipe->pipe_idx;
2023 			}
2024 			hsplit_pipe = dcn30_find_split_pipe(dc, context, old_index);
2025 			ASSERT(hsplit_pipe);
2026 			if (!hsplit_pipe)
2027 				goto validate_fail;
2028 
2029 			if (!dcn30_split_stream_for_mpc_or_odm(
2030 					dc, &context->res_ctx,
2031 					pipe, hsplit_pipe, odm))
2032 				goto validate_fail;
2033 
2034 			newly_split[hsplit_pipe->pipe_idx] = true;
2035 			repopulate_pipes = true;
2036 		}
2037 		if (split[i] == 4) {
2038 			struct pipe_ctx *pipe_4to1;
2039 
2040 			if (odm && old_pipe->next_odm_pipe)
2041 				old_index = old_pipe->next_odm_pipe->pipe_idx;
2042 			else if (!odm && old_pipe->bottom_pipe &&
2043 						old_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
2044 				old_index = old_pipe->bottom_pipe->pipe_idx;
2045 			else
2046 				old_index = -1;
2047 			pipe_4to1 = dcn30_find_split_pipe(dc, context, old_index);
2048 			ASSERT(pipe_4to1);
2049 			if (!pipe_4to1)
2050 				goto validate_fail;
2051 			if (!dcn30_split_stream_for_mpc_or_odm(
2052 					dc, &context->res_ctx,
2053 					pipe, pipe_4to1, odm))
2054 				goto validate_fail;
2055 			newly_split[pipe_4to1->pipe_idx] = true;
2056 
2057 			if (odm && old_pipe->next_odm_pipe && old_pipe->next_odm_pipe->next_odm_pipe
2058 					&& old_pipe->next_odm_pipe->next_odm_pipe->next_odm_pipe)
2059 				old_index = old_pipe->next_odm_pipe->next_odm_pipe->next_odm_pipe->pipe_idx;
2060 			else if (!odm && old_pipe->bottom_pipe && old_pipe->bottom_pipe->bottom_pipe &&
2061 					old_pipe->bottom_pipe->bottom_pipe->bottom_pipe &&
2062 					old_pipe->bottom_pipe->bottom_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
2063 				old_index = old_pipe->bottom_pipe->bottom_pipe->bottom_pipe->pipe_idx;
2064 			else
2065 				old_index = -1;
2066 			pipe_4to1 = dcn30_find_split_pipe(dc, context, old_index);
2067 			ASSERT(pipe_4to1);
2068 			if (!pipe_4to1)
2069 				goto validate_fail;
2070 			if (!dcn30_split_stream_for_mpc_or_odm(
2071 					dc, &context->res_ctx,
2072 					hsplit_pipe, pipe_4to1, odm))
2073 				goto validate_fail;
2074 			newly_split[pipe_4to1->pipe_idx] = true;
2075 		}
2076 		if (odm)
2077 			dcn20_build_mapped_resource(dc, context, pipe->stream);
2078 	}
2079 
2080 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
2081 		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2082 
2083 		if (pipe->plane_state) {
2084 			if (!resource_build_scaling_params(pipe))
2085 				goto validate_fail;
2086 		}
2087 	}
2088 
2089 	/* Actual dsc count per stream dsc validation*/
2090 	if (!dcn20_validate_dsc(dc, context)) {
2091 		vba->ValidationStatus[vba->soc.num_states] = DML_FAIL_DSC_VALIDATION_FAILURE;
2092 		goto validate_fail;
2093 	}
2094 
2095 	if (repopulate_pipes)
2096 		pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate);
2097 	*vlevel_out = vlevel;
2098 	*pipe_cnt_out = pipe_cnt;
2099 
2100 	out = true;
2101 	goto validate_out;
2102 
2103 validate_fail:
2104 	out = false;
2105 
2106 validate_out:
2107 	DC_FP_END();
2108 	return out;
2109 }
2110 
2111 /*
2112  * This must be noinline to ensure anything that deals with FP registers
2113  * is contained within this call; previously our compiling with hard-float
2114  * would result in fp instructions being emitted outside of the boundaries
2115  * of the DC_FP_START/END macros, which makes sense as the compiler has no
2116  * idea about what is wrapped and what is not
2117  *
2118  * This is largely just a workaround to avoid breakage introduced with 5.6,
2119  * ideally all fp-using code should be moved into its own file, only that
2120  * should be compiled with hard-float, and all code exported from there
2121  * should be strictly wrapped with DC_FP_START/END
2122  */
2123 static noinline void dcn30_calculate_wm_and_dlg_fp(
2124 		struct dc *dc, struct dc_state *context,
2125 		display_e2e_pipe_params_st *pipes,
2126 		int pipe_cnt,
2127 		int vlevel)
2128 {
2129 	int i, pipe_idx;
2130 	double dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
2131 	bool pstate_en = context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] !=
2132 			dm_dram_clock_change_unsupported;
2133 
2134 	if (context->bw_ctx.dml.soc.min_dcfclk > dcfclk)
2135 		dcfclk = context->bw_ctx.dml.soc.min_dcfclk;
2136 
2137 	pipes[0].clks_cfg.voltage = vlevel;
2138 	pipes[0].clks_cfg.dcfclk_mhz = dcfclk;
2139 	pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
2140 
2141 	/* Set B:
2142 	 * DCFCLK: 1GHz or min required above 1GHz
2143 	 * FCLK/UCLK: Max
2144 	 */
2145 	if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].valid) {
2146 		if (vlevel == 0) {
2147 			pipes[0].clks_cfg.voltage = 1;
2148 			pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dcfclk_mhz;
2149 		}
2150 		context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.pstate_latency_us;
2151 		context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_enter_plus_exit_time_us;
2152 		context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_exit_time_us;
2153 	}
2154 	context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2155 	context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2156 	context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2157 	context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2158 	context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2159 	context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2160 	context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2161 	context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2162 
2163 	pipes[0].clks_cfg.voltage = vlevel;
2164 	pipes[0].clks_cfg.dcfclk_mhz = dcfclk;
2165 
2166 	/* Set D:
2167 	 * DCFCLK: Min Required
2168 	 * FCLK(proportional to UCLK): 1GHz or Max
2169 	 * MALL stutter, sr_enter_exit = 4, sr_exit = 2us
2170 	 */
2171 	/*
2172 	if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].valid) {
2173 		context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.pstate_latency_us;
2174 		context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_enter_plus_exit_time_us;
2175 		context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_exit_time_us;
2176 	}
2177 	context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2178 	context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2179 	context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2180 	context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2181 	context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2182 	context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2183 	context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2184 	context->bw_ctx.bw.dcn.watermarks.d.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2185 	*/
2186 
2187 	/* Set C:
2188 	 * DCFCLK: Min Required
2189 	 * FCLK(proportional to UCLK): 1GHz or Max
2190 	 * pstate latency overridden to 5us
2191 	 */
2192 	if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid) {
2193 		unsigned int min_dram_speed_mts = context->bw_ctx.dml.vba.DRAMSpeed;
2194 		unsigned int min_dram_speed_mts_margin = 160;
2195 
2196 		if (context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] == dm_dram_clock_change_unsupported)
2197 			min_dram_speed_mts = dc->clk_mgr->bw_params->clk_table.entries[dc->clk_mgr->bw_params->clk_table.num_entries - 1].memclk_mhz * 16;
2198 
2199 		/* find largest table entry that is lower than dram speed, but lower than DPM0 still uses DPM0 */
2200 		for (i = 3; i > 0; i--)
2201 			if (min_dram_speed_mts + min_dram_speed_mts_margin > dc->clk_mgr->bw_params->dummy_pstate_table[i].dram_speed_mts)
2202 				break;
2203 
2204 		context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->dummy_pstate_table[i].dummy_pstate_latency_us;
2205 		context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_exit_time_us;
2206 		context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us;
2207 	}
2208 	context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2209 	context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2210 	context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2211 	context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2212 	context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2213 	context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2214 	context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2215 	context->bw_ctx.bw.dcn.watermarks.c.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2216 
2217 	if (!pstate_en) {
2218 		/* The only difference between A and C is p-state latency, if p-state is not supported we want to
2219 		 * calculate DLG based on dummy p-state latency, and max out the set A p-state watermark
2220 		 */
2221 		context->bw_ctx.bw.dcn.watermarks.a = context->bw_ctx.bw.dcn.watermarks.c;
2222 		context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 0;
2223 	} else {
2224 		/* Set A:
2225 		 * DCFCLK: Min Required
2226 		 * FCLK(proportional to UCLK): 1GHz or Max
2227 		 *
2228 		 * Set A calculated last so that following calculations are based on Set A
2229 		 */
2230 		dc->res_pool->funcs->update_soc_for_wm_a(dc, context);
2231 		context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2232 		context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2233 		context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2234 		context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2235 		context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2236 		context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2237 		context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2238 		context->bw_ctx.bw.dcn.watermarks.a.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2239 	}
2240 
2241 	context->perf_params.stutter_period_us = context->bw_ctx.dml.vba.StutterPeriod;
2242 
2243 	/* Make set D = set A until set D is enabled */
2244 	context->bw_ctx.bw.dcn.watermarks.d = context->bw_ctx.bw.dcn.watermarks.a;
2245 
2246 	for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
2247 		if (!context->res_ctx.pipe_ctx[i].stream)
2248 			continue;
2249 
2250 		pipes[pipe_idx].clks_cfg.dispclk_mhz = get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt);
2251 		pipes[pipe_idx].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
2252 
2253 		if (dc->config.forced_clocks) {
2254 			pipes[pipe_idx].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz;
2255 			pipes[pipe_idx].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz;
2256 		}
2257 		if (dc->debug.min_disp_clk_khz > pipes[pipe_idx].clks_cfg.dispclk_mhz * 1000)
2258 			pipes[pipe_idx].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0;
2259 		if (dc->debug.min_dpp_clk_khz > pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)
2260 			pipes[pipe_idx].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0;
2261 
2262 		pipe_idx++;
2263 	}
2264 
2265 	dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
2266 
2267 	if (!pstate_en)
2268 		/* Restore full p-state latency */
2269 		context->bw_ctx.dml.soc.dram_clock_change_latency_us =
2270 				dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;
2271 }
2272 
2273 void dcn30_update_soc_for_wm_a(struct dc *dc, struct dc_state *context)
2274 {
2275 	if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].valid) {
2276 		context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;
2277 		context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us;
2278 		context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us;
2279 	}
2280 }
2281 
2282 void dcn30_calculate_wm_and_dlg(
2283 		struct dc *dc, struct dc_state *context,
2284 		display_e2e_pipe_params_st *pipes,
2285 		int pipe_cnt,
2286 		int vlevel)
2287 {
2288 	DC_FP_START();
2289 	dcn30_calculate_wm_and_dlg_fp(dc, context, pipes, pipe_cnt, vlevel);
2290 	DC_FP_END();
2291 }
2292 
2293 bool dcn30_validate_bandwidth(struct dc *dc,
2294 		struct dc_state *context,
2295 		bool fast_validate)
2296 {
2297 	bool out = false;
2298 
2299 	BW_VAL_TRACE_SETUP();
2300 
2301 	int vlevel = 0;
2302 	int pipe_cnt = 0;
2303 	display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL);
2304 	DC_LOGGER_INIT(dc->ctx->logger);
2305 
2306 	BW_VAL_TRACE_COUNT();
2307 
2308 	out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate);
2309 
2310 	if (pipe_cnt == 0)
2311 		goto validate_out;
2312 
2313 	if (!out)
2314 		goto validate_fail;
2315 
2316 	BW_VAL_TRACE_END_VOLTAGE_LEVEL();
2317 
2318 	if (fast_validate) {
2319 		BW_VAL_TRACE_SKIP(fast);
2320 		goto validate_out;
2321 	}
2322 
2323 	dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel);
2324 
2325 	BW_VAL_TRACE_END_WATERMARKS();
2326 
2327 	goto validate_out;
2328 
2329 validate_fail:
2330 	DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n",
2331 		dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
2332 
2333 	BW_VAL_TRACE_SKIP(fail);
2334 	out = false;
2335 
2336 validate_out:
2337 	kfree(pipes);
2338 
2339 	BW_VAL_TRACE_FINISH();
2340 
2341 	return out;
2342 }
2343 
2344 /*
2345  * This must be noinline to ensure anything that deals with FP registers
2346  * is contained within this call; previously our compiling with hard-float
2347  * would result in fp instructions being emitted outside of the boundaries
2348  * of the DC_FP_START/END macros, which makes sense as the compiler has no
2349  * idea about what is wrapped and what is not
2350  *
2351  * This is largely just a workaround to avoid breakage introduced with 5.6,
2352  * ideally all fp-using code should be moved into its own file, only that
2353  * should be compiled with hard-float, and all code exported from there
2354  * should be strictly wrapped with DC_FP_START/END
2355  */
2356 static noinline void dcn30_get_optimal_dcfclk_fclk_for_uclk(unsigned int uclk_mts,
2357 		unsigned int *optimal_dcfclk,
2358 		unsigned int *optimal_fclk)
2359 {
2360        double bw_from_dram, bw_from_dram1, bw_from_dram2;
2361 
2362        bw_from_dram1 = uclk_mts * dcn3_0_soc.num_chans *
2363 		dcn3_0_soc.dram_channel_width_bytes * (dcn3_0_soc.max_avg_dram_bw_use_normal_percent / 100);
2364        bw_from_dram2 = uclk_mts * dcn3_0_soc.num_chans *
2365 		dcn3_0_soc.dram_channel_width_bytes * (dcn3_0_soc.max_avg_sdp_bw_use_normal_percent / 100);
2366 
2367        bw_from_dram = (bw_from_dram1 < bw_from_dram2) ? bw_from_dram1 : bw_from_dram2;
2368 
2369        if (optimal_fclk)
2370                *optimal_fclk = bw_from_dram /
2371                (dcn3_0_soc.fabric_datapath_to_dcn_data_return_bytes * (dcn3_0_soc.max_avg_sdp_bw_use_normal_percent / 100));
2372 
2373        if (optimal_dcfclk)
2374                *optimal_dcfclk =  bw_from_dram /
2375                (dcn3_0_soc.return_bus_width_bytes * (dcn3_0_soc.max_avg_sdp_bw_use_normal_percent / 100));
2376 }
2377 
2378 void dcn30_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
2379 {
2380 	unsigned int i, j;
2381 	unsigned int num_states = 0;
2382 
2383 	unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0};
2384 	unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0};
2385 	unsigned int optimal_uclk_for_dcfclk_sta_targets[DC__VOLTAGE_STATES] = {0};
2386 	unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0};
2387 
2388 	unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {694, 875, 1000, 1200};
2389 	unsigned int num_dcfclk_sta_targets = 4;
2390 	unsigned int num_uclk_states;
2391 
2392 	if (dc->ctx->dc_bios->vram_info.num_chans)
2393 		dcn3_0_soc.num_chans = dc->ctx->dc_bios->vram_info.num_chans;
2394 
2395 	if (dc->ctx->dc_bios->vram_info.dram_channel_width_bytes)
2396 		dcn3_0_soc.dram_channel_width_bytes = dc->ctx->dc_bios->vram_info.dram_channel_width_bytes;
2397 
2398 	dcn3_0_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
2399 	dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
2400 
2401 	if (bw_params->clk_table.entries[0].memclk_mhz) {
2402 
2403 		if (bw_params->clk_table.entries[1].dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
2404 			// If max DCFCLK is greater than the max DCFCLK STA target, insert into the DCFCLK STA target array
2405 			dcfclk_sta_targets[num_dcfclk_sta_targets] = bw_params->clk_table.entries[1].dcfclk_mhz;
2406 			num_dcfclk_sta_targets++;
2407 		} else if (bw_params->clk_table.entries[1].dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
2408 			// If max DCFCLK is less than the max DCFCLK STA target, cap values and remove duplicates
2409 			for (i = 0; i < num_dcfclk_sta_targets; i++) {
2410 				if (dcfclk_sta_targets[i] > bw_params->clk_table.entries[1].dcfclk_mhz) {
2411 					dcfclk_sta_targets[i] = bw_params->clk_table.entries[1].dcfclk_mhz;
2412 					break;
2413 				}
2414 			}
2415 			// Update size of array since we "removed" duplicates
2416 			num_dcfclk_sta_targets = i + 1;
2417 		}
2418 
2419 		num_uclk_states = bw_params->clk_table.num_entries;
2420 
2421 		// Calculate optimal dcfclk for each uclk
2422 		for (i = 0; i < num_uclk_states; i++) {
2423 			DC_FP_START();
2424 			dcn30_get_optimal_dcfclk_fclk_for_uclk(bw_params->clk_table.entries[i].memclk_mhz * 16,
2425 					&optimal_dcfclk_for_uclk[i], NULL);
2426 			DC_FP_END();
2427 			if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz) {
2428 				optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz;
2429 			}
2430 		}
2431 
2432 		// Calculate optimal uclk for each dcfclk sta target
2433 		for (i = 0; i < num_dcfclk_sta_targets; i++) {
2434 			for (j = 0; j < num_uclk_states; j++) {
2435 				if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) {
2436 					optimal_uclk_for_dcfclk_sta_targets[i] =
2437 							bw_params->clk_table.entries[j].memclk_mhz * 16;
2438 					break;
2439 				}
2440 			}
2441 		}
2442 
2443 		i = 0;
2444 		j = 0;
2445 		// create the final dcfclk and uclk table
2446 		while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) {
2447 			if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) {
2448 				dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
2449 				dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
2450 			} else {
2451 				if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= bw_params->clk_table.entries[1].dcfclk_mhz) {
2452 					dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
2453 					dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
2454 				} else {
2455 					j = num_uclk_states;
2456 				}
2457 			}
2458 		}
2459 
2460 		while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) {
2461 			dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
2462 			dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
2463 		}
2464 
2465 		while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES &&
2466 				optimal_dcfclk_for_uclk[j] <= bw_params->clk_table.entries[1].dcfclk_mhz) {
2467 			dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
2468 			dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
2469 		}
2470 
2471 		for (i = 0; i < dcn3_0_soc.num_states; i++) {
2472 			dcn3_0_soc.clock_limits[i].state = i;
2473 			dcn3_0_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i];
2474 			dcn3_0_soc.clock_limits[i].fabricclk_mhz = dcfclk_mhz[i];
2475 			dcn3_0_soc.clock_limits[i].dram_speed_mts = dram_speed_mts[i];
2476 
2477 			/* Fill all states with max values of all other clocks */
2478 			dcn3_0_soc.clock_limits[i].dispclk_mhz = bw_params->clk_table.entries[1].dispclk_mhz;
2479 			dcn3_0_soc.clock_limits[i].dppclk_mhz  = bw_params->clk_table.entries[1].dppclk_mhz;
2480 			dcn3_0_soc.clock_limits[i].phyclk_mhz  = bw_params->clk_table.entries[1].phyclk_mhz;
2481 			dcn3_0_soc.clock_limits[i].dtbclk_mhz = dcn3_0_soc.clock_limits[0].dtbclk_mhz;
2482 			/* These clocks cannot come from bw_params, always fill from dcn3_0_soc[1] */
2483 			/* FCLK, PHYCLK_D18, SOCCLK, DSCCLK */
2484 			dcn3_0_soc.clock_limits[i].phyclk_d18_mhz = dcn3_0_soc.clock_limits[0].phyclk_d18_mhz;
2485 			dcn3_0_soc.clock_limits[i].socclk_mhz = dcn3_0_soc.clock_limits[0].socclk_mhz;
2486 			dcn3_0_soc.clock_limits[i].dscclk_mhz = dcn3_0_soc.clock_limits[0].dscclk_mhz;
2487 		}
2488 		/* re-init DML with updated bb */
2489 		dml_init_instance(&dc->dml, &dcn3_0_soc, &dcn3_0_ip, DML_PROJECT_DCN30);
2490 		if (dc->current_state)
2491 			dml_init_instance(&dc->current_state->bw_ctx.dml, &dcn3_0_soc, &dcn3_0_ip, DML_PROJECT_DCN30);
2492 	}
2493 
2494 	/* re-init DML with updated bb */
2495 	dml_init_instance(&dc->dml, &dcn3_0_soc, &dcn3_0_ip, DML_PROJECT_DCN30);
2496 	if (dc->current_state)
2497 		dml_init_instance(&dc->current_state->bw_ctx.dml, &dcn3_0_soc, &dcn3_0_ip, DML_PROJECT_DCN30);
2498 }
2499 
2500 static const struct resource_funcs dcn30_res_pool_funcs = {
2501 	.destroy = dcn30_destroy_resource_pool,
2502 	.link_enc_create = dcn30_link_encoder_create,
2503 	.panel_cntl_create = dcn30_panel_cntl_create,
2504 	.validate_bandwidth = dcn30_validate_bandwidth,
2505 	.calculate_wm_and_dlg = dcn30_calculate_wm_and_dlg,
2506 	.update_soc_for_wm_a = dcn30_update_soc_for_wm_a,
2507 	.populate_dml_pipes = dcn30_populate_dml_pipes_from_context,
2508 	.acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
2509 	.add_stream_to_ctx = dcn30_add_stream_to_ctx,
2510 	.add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
2511 	.remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
2512 	.populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
2513 	.set_mcif_arb_params = dcn30_set_mcif_arb_params,
2514 	.find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
2515 	.acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
2516 	.release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
2517 	.update_bw_bounding_box = dcn30_update_bw_bounding_box,
2518 	.patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
2519 };
2520 
2521 #define CTX ctx
2522 
2523 #define REG(reg_name) \
2524 	(DCN_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
2525 
2526 static uint32_t read_pipe_fuses(struct dc_context *ctx)
2527 {
2528 	uint32_t value = REG_READ(CC_DC_PIPE_DIS);
2529 	/* Support for max 6 pipes */
2530 	value = value & 0x3f;
2531 	return value;
2532 }
2533 
2534 static bool dcn30_resource_construct(
2535 	uint8_t num_virtual_links,
2536 	struct dc *dc,
2537 	struct dcn30_resource_pool *pool)
2538 {
2539 	int i;
2540 	struct dc_context *ctx = dc->ctx;
2541 	struct irq_service_init_data init_data;
2542 	struct ddc_service_init_data ddc_init_data = {0};
2543 	uint32_t pipe_fuses = read_pipe_fuses(ctx);
2544 	uint32_t num_pipes = 0;
2545 
2546 	if (!(pipe_fuses == 0 || pipe_fuses == 0x3e)) {
2547 		BREAK_TO_DEBUGGER();
2548 		dm_error("DC: Unexpected fuse recipe for navi2x !\n");
2549 		/* fault to single pipe */
2550 		pipe_fuses = 0x3e;
2551 	}
2552 
2553 	DC_FP_START();
2554 
2555 	ctx->dc_bios->regs = &bios_regs;
2556 
2557 	pool->base.res_cap = &res_cap_dcn3;
2558 
2559 	pool->base.funcs = &dcn30_res_pool_funcs;
2560 
2561 	/*************************************************
2562 	 *  Resource + asic cap harcoding                *
2563 	 *************************************************/
2564 	pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
2565 	pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
2566 	pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;
2567 	dc->caps.max_downscale_ratio = 600;
2568 	dc->caps.i2c_speed_in_khz = 100;
2569 	dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a not applied by default*/
2570 	dc->caps.max_cursor_size = 256;
2571 	dc->caps.min_horizontal_blanking_period = 80;
2572 	dc->caps.dmdata_alloc_size = 2048;
2573 	dc->caps.mall_size_per_mem_channel = 8;
2574 	/* total size = mall per channel * num channels * 1024 * 1024 */
2575 	dc->caps.mall_size_total = dc->caps.mall_size_per_mem_channel * dc->ctx->dc_bios->vram_info.num_chans * 1048576;
2576 	dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8;
2577 
2578 	dc->caps.max_slave_planes = 1;
2579 	dc->caps.max_slave_yuv_planes = 1;
2580 	dc->caps.max_slave_rgb_planes = 1;
2581 	dc->caps.post_blend_color_processing = true;
2582 	dc->caps.force_dp_tps4_for_cp2520 = true;
2583 	dc->caps.extended_aux_timeout_support = true;
2584 	dc->caps.dmcub_support = true;
2585 
2586 	/* Color pipeline capabilities */
2587 	dc->caps.color.dpp.dcn_arch = 1;
2588 	dc->caps.color.dpp.input_lut_shared = 0;
2589 	dc->caps.color.dpp.icsc = 1;
2590 	dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
2591 	dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
2592 	dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
2593 	dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
2594 	dc->caps.color.dpp.dgam_rom_caps.pq = 1;
2595 	dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
2596 	dc->caps.color.dpp.post_csc = 1;
2597 	dc->caps.color.dpp.gamma_corr = 1;
2598 	dc->caps.color.dpp.dgam_rom_for_yuv = 0;
2599 
2600 	dc->caps.color.dpp.hw_3d_lut = 1;
2601 	dc->caps.color.dpp.ogam_ram = 1;
2602 	// no OGAM ROM on DCN3
2603 	dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
2604 	dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
2605 	dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
2606 	dc->caps.color.dpp.ogam_rom_caps.pq = 0;
2607 	dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
2608 	dc->caps.color.dpp.ocsc = 0;
2609 
2610 	dc->caps.color.mpc.gamut_remap = 1;
2611 	dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //3
2612 	dc->caps.color.mpc.ogam_ram = 1;
2613 	dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
2614 	dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
2615 	dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
2616 	dc->caps.color.mpc.ogam_rom_caps.pq = 0;
2617 	dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
2618 	dc->caps.color.mpc.ocsc = 1;
2619 
2620 	if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
2621 		dc->debug = debug_defaults_drv;
2622 	else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) {
2623 		dc->debug = debug_defaults_diags;
2624 	} else
2625 		dc->debug = debug_defaults_diags;
2626 	// Init the vm_helper
2627 	if (dc->vm_helper)
2628 		vm_helper_init(dc->vm_helper, 16);
2629 
2630 	/*************************************************
2631 	 *  Create resources                             *
2632 	 *************************************************/
2633 
2634 	/* Clock Sources for Pixel Clock*/
2635 	pool->base.clock_sources[DCN30_CLK_SRC_PLL0] =
2636 			dcn30_clock_source_create(ctx, ctx->dc_bios,
2637 				CLOCK_SOURCE_COMBO_PHY_PLL0,
2638 				&clk_src_regs[0], false);
2639 	pool->base.clock_sources[DCN30_CLK_SRC_PLL1] =
2640 			dcn30_clock_source_create(ctx, ctx->dc_bios,
2641 				CLOCK_SOURCE_COMBO_PHY_PLL1,
2642 				&clk_src_regs[1], false);
2643 	pool->base.clock_sources[DCN30_CLK_SRC_PLL2] =
2644 			dcn30_clock_source_create(ctx, ctx->dc_bios,
2645 				CLOCK_SOURCE_COMBO_PHY_PLL2,
2646 				&clk_src_regs[2], false);
2647 	pool->base.clock_sources[DCN30_CLK_SRC_PLL3] =
2648 			dcn30_clock_source_create(ctx, ctx->dc_bios,
2649 				CLOCK_SOURCE_COMBO_PHY_PLL3,
2650 				&clk_src_regs[3], false);
2651 	pool->base.clock_sources[DCN30_CLK_SRC_PLL4] =
2652 			dcn30_clock_source_create(ctx, ctx->dc_bios,
2653 				CLOCK_SOURCE_COMBO_PHY_PLL4,
2654 				&clk_src_regs[4], false);
2655 	pool->base.clock_sources[DCN30_CLK_SRC_PLL5] =
2656 			dcn30_clock_source_create(ctx, ctx->dc_bios,
2657 				CLOCK_SOURCE_COMBO_PHY_PLL5,
2658 				&clk_src_regs[5], false);
2659 
2660 	pool->base.clk_src_count = DCN30_CLK_SRC_TOTAL;
2661 
2662 	/* todo: not reuse phy_pll registers */
2663 	pool->base.dp_clock_source =
2664 			dcn30_clock_source_create(ctx, ctx->dc_bios,
2665 				CLOCK_SOURCE_ID_DP_DTO,
2666 				&clk_src_regs[0], true);
2667 
2668 	for (i = 0; i < pool->base.clk_src_count; i++) {
2669 		if (pool->base.clock_sources[i] == NULL) {
2670 			dm_error("DC: failed to create clock sources!\n");
2671 			BREAK_TO_DEBUGGER();
2672 			goto create_fail;
2673 		}
2674 	}
2675 
2676 	/* DCCG */
2677 	pool->base.dccg = dccg30_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
2678 	if (pool->base.dccg == NULL) {
2679 		dm_error("DC: failed to create dccg!\n");
2680 		BREAK_TO_DEBUGGER();
2681 		goto create_fail;
2682 	}
2683 
2684 	/* PP Lib and SMU interfaces */
2685 	init_soc_bounding_box(dc, pool);
2686 
2687 	num_pipes = dcn3_0_ip.max_num_dpp;
2688 
2689 	for (i = 0; i < dcn3_0_ip.max_num_dpp; i++)
2690 		if (pipe_fuses & 1 << i)
2691 			num_pipes--;
2692 
2693 	dcn3_0_ip.max_num_dpp = num_pipes;
2694 	dcn3_0_ip.max_num_otg = num_pipes;
2695 
2696 	dml_init_instance(&dc->dml, &dcn3_0_soc, &dcn3_0_ip, DML_PROJECT_DCN30);
2697 
2698 	/* IRQ */
2699 	init_data.ctx = dc->ctx;
2700 	pool->base.irqs = dal_irq_service_dcn30_create(&init_data);
2701 	if (!pool->base.irqs)
2702 		goto create_fail;
2703 
2704 	/* HUBBUB */
2705 	pool->base.hubbub = dcn30_hubbub_create(ctx);
2706 	if (pool->base.hubbub == NULL) {
2707 		BREAK_TO_DEBUGGER();
2708 		dm_error("DC: failed to create hubbub!\n");
2709 		goto create_fail;
2710 	}
2711 
2712 	/* HUBPs, DPPs, OPPs and TGs */
2713 	for (i = 0; i < pool->base.pipe_count; i++) {
2714 		pool->base.hubps[i] = dcn30_hubp_create(ctx, i);
2715 		if (pool->base.hubps[i] == NULL) {
2716 			BREAK_TO_DEBUGGER();
2717 			dm_error(
2718 				"DC: failed to create hubps!\n");
2719 			goto create_fail;
2720 		}
2721 
2722 		pool->base.dpps[i] = dcn30_dpp_create(ctx, i);
2723 		if (pool->base.dpps[i] == NULL) {
2724 			BREAK_TO_DEBUGGER();
2725 			dm_error(
2726 				"DC: failed to create dpps!\n");
2727 			goto create_fail;
2728 		}
2729 	}
2730 
2731 	for (i = 0; i < pool->base.res_cap->num_opp; i++) {
2732 		pool->base.opps[i] = dcn30_opp_create(ctx, i);
2733 		if (pool->base.opps[i] == NULL) {
2734 			BREAK_TO_DEBUGGER();
2735 			dm_error(
2736 				"DC: failed to create output pixel processor!\n");
2737 			goto create_fail;
2738 		}
2739 	}
2740 
2741 	for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2742 		pool->base.timing_generators[i] = dcn30_timing_generator_create(
2743 				ctx, i);
2744 		if (pool->base.timing_generators[i] == NULL) {
2745 			BREAK_TO_DEBUGGER();
2746 			dm_error("DC: failed to create tg!\n");
2747 			goto create_fail;
2748 		}
2749 	}
2750 	pool->base.timing_generator_count = i;
2751 	/* PSR */
2752 	pool->base.psr = dmub_psr_create(ctx);
2753 
2754 	if (pool->base.psr == NULL) {
2755 		dm_error("DC: failed to create PSR obj!\n");
2756 		BREAK_TO_DEBUGGER();
2757 		goto create_fail;
2758 	}
2759 
2760 	/* ABM */
2761 	for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2762 		pool->base.multiple_abms[i] = dmub_abm_create(ctx,
2763 				&abm_regs[i],
2764 				&abm_shift,
2765 				&abm_mask);
2766 		if (pool->base.multiple_abms[i] == NULL) {
2767 			dm_error("DC: failed to create abm for pipe %d!\n", i);
2768 			BREAK_TO_DEBUGGER();
2769 			goto create_fail;
2770 		}
2771 	}
2772 	/* MPC and DSC */
2773 	pool->base.mpc = dcn30_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);
2774 	if (pool->base.mpc == NULL) {
2775 		BREAK_TO_DEBUGGER();
2776 		dm_error("DC: failed to create mpc!\n");
2777 		goto create_fail;
2778 	}
2779 
2780 	for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
2781 		pool->base.dscs[i] = dcn30_dsc_create(ctx, i);
2782 		if (pool->base.dscs[i] == NULL) {
2783 			BREAK_TO_DEBUGGER();
2784 			dm_error("DC: failed to create display stream compressor %d!\n", i);
2785 			goto create_fail;
2786 		}
2787 	}
2788 
2789 	/* DWB and MMHUBBUB */
2790 	if (!dcn30_dwbc_create(ctx, &pool->base)) {
2791 		BREAK_TO_DEBUGGER();
2792 		dm_error("DC: failed to create dwbc!\n");
2793 		goto create_fail;
2794 	}
2795 
2796 	if (!dcn30_mmhubbub_create(ctx, &pool->base)) {
2797 		BREAK_TO_DEBUGGER();
2798 		dm_error("DC: failed to create mcif_wb!\n");
2799 		goto create_fail;
2800 	}
2801 
2802 	/* AUX and I2C */
2803 	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
2804 		pool->base.engines[i] = dcn30_aux_engine_create(ctx, i);
2805 		if (pool->base.engines[i] == NULL) {
2806 			BREAK_TO_DEBUGGER();
2807 			dm_error(
2808 				"DC:failed to create aux engine!!\n");
2809 			goto create_fail;
2810 		}
2811 		pool->base.hw_i2cs[i] = dcn30_i2c_hw_create(ctx, i);
2812 		if (pool->base.hw_i2cs[i] == NULL) {
2813 			BREAK_TO_DEBUGGER();
2814 			dm_error(
2815 				"DC:failed to create hw i2c!!\n");
2816 			goto create_fail;
2817 		}
2818 		pool->base.sw_i2cs[i] = NULL;
2819 	}
2820 
2821 	/* Audio, Stream Encoders including DIG and virtual, MPC 3D LUTs */
2822 	if (!resource_construct(num_virtual_links, dc, &pool->base,
2823 			(!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
2824 			&res_create_funcs : &res_create_maximus_funcs)))
2825 		goto create_fail;
2826 
2827 	/* HW Sequencer and Plane caps */
2828 	dcn30_hw_sequencer_construct(dc);
2829 
2830 	dc->caps.max_planes =  pool->base.pipe_count;
2831 
2832 	for (i = 0; i < dc->caps.max_planes; ++i)
2833 		dc->caps.planes[i] = plane_cap;
2834 
2835 	dc->cap_funcs = cap_funcs;
2836 
2837 	if (dc->ctx->dc_bios->fw_info.oem_i2c_present) {
2838 		ddc_init_data.ctx = dc->ctx;
2839 		ddc_init_data.link = NULL;
2840 		ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id;
2841 		ddc_init_data.id.enum_id = 0;
2842 		ddc_init_data.id.type = OBJECT_TYPE_GENERIC;
2843 		pool->base.oem_device = dal_ddc_service_create(&ddc_init_data);
2844 	} else {
2845 		pool->base.oem_device = NULL;
2846 	}
2847 
2848 	DC_FP_END();
2849 
2850 	return true;
2851 
2852 create_fail:
2853 
2854 	DC_FP_END();
2855 	dcn30_resource_destruct(pool);
2856 
2857 	return false;
2858 }
2859 
2860 struct resource_pool *dcn30_create_resource_pool(
2861 		const struct dc_init_data *init_data,
2862 		struct dc *dc)
2863 {
2864 	struct dcn30_resource_pool *pool =
2865 		kzalloc(sizeof(struct dcn30_resource_pool), GFP_KERNEL);
2866 
2867 	if (!pool)
2868 		return NULL;
2869 
2870 	if (dcn30_resource_construct(init_data->num_virtual_links, dc, pool))
2871 		return &pool->base;
2872 
2873 	BREAK_TO_DEBUGGER();
2874 	kfree(pool);
2875 	return NULL;
2876 }
2877