1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 27 #include "dm_services.h" 28 #include "dc.h" 29 30 #include "dcn30_init.h" 31 32 #include "resource.h" 33 #include "include/irq_service_interface.h" 34 #include "dcn20/dcn20_resource.h" 35 36 #include "dcn30_resource.h" 37 38 #include "dcn10/dcn10_ipp.h" 39 #include "dcn30/dcn30_hubbub.h" 40 #include "dcn30/dcn30_mpc.h" 41 #include "dcn30/dcn30_hubp.h" 42 #include "irq/dcn30/irq_service_dcn30.h" 43 #include "dcn30/dcn30_dpp.h" 44 #include "dcn30/dcn30_optc.h" 45 #include "dcn20/dcn20_hwseq.h" 46 #include "dcn30/dcn30_hwseq.h" 47 #include "dce110/dce110_hw_sequencer.h" 48 #include "dcn30/dcn30_opp.h" 49 #include "dcn20/dcn20_dsc.h" 50 #include "dcn30/dcn30_vpg.h" 51 #include "dcn30/dcn30_afmt.h" 52 #include "dcn30/dcn30_dio_stream_encoder.h" 53 #include "dcn30/dcn30_dio_link_encoder.h" 54 #include "dce/dce_clock_source.h" 55 #include "dce/dce_audio.h" 56 #include "dce/dce_hwseq.h" 57 #include "clk_mgr.h" 58 #include "virtual/virtual_stream_encoder.h" 59 #include "dce110/dce110_resource.h" 60 #include "dml/display_mode_vba.h" 61 #include "dcn30/dcn30_dccg.h" 62 #include "dcn10/dcn10_resource.h" 63 #include "dce/dce_panel_cntl.h" 64 65 #include "dcn30/dcn30_dwb.h" 66 #include "dcn30/dcn30_mmhubbub.h" 67 68 #include "sienna_cichlid_ip_offset.h" 69 #include "dcn/dcn_3_0_0_offset.h" 70 #include "dcn/dcn_3_0_0_sh_mask.h" 71 72 #include "nbio/nbio_7_4_offset.h" 73 74 #include "dcn/dpcs_3_0_0_offset.h" 75 #include "dcn/dpcs_3_0_0_sh_mask.h" 76 77 #include "mmhub/mmhub_2_0_0_offset.h" 78 #include "mmhub/mmhub_2_0_0_sh_mask.h" 79 80 #include "reg_helper.h" 81 #include "dce/dmub_abm.h" 82 #include "dce/dmub_psr.h" 83 #include "dce/dce_aux.h" 84 #include "dce/dce_i2c.h" 85 86 #include "dml/dcn30/display_mode_vba_30.h" 87 #include "vm_helper.h" 88 #include "dcn20/dcn20_vmid.h" 89 #include "amdgpu_socbb.h" 90 91 #define DC_LOGGER_INIT(logger) 92 93 struct _vcs_dpi_ip_params_st dcn3_0_ip = { 94 .use_min_dcfclk = 1, 95 .clamp_min_dcfclk = 0, 96 .odm_capable = 1, 97 .gpuvm_enable = 0, 98 .hostvm_enable = 0, 99 .gpuvm_max_page_table_levels = 4, 100 .hostvm_max_page_table_levels = 4, 101 .hostvm_cached_page_table_levels = 0, 102 .pte_group_size_bytes = 2048, 103 .num_dsc = 6, 104 .rob_buffer_size_kbytes = 184, 105 .det_buffer_size_kbytes = 184, 106 .dpte_buffer_size_in_pte_reqs_luma = 84, 107 .pde_proc_buffer_size_64k_reqs = 48, 108 .dpp_output_buffer_pixels = 2560, 109 .opp_output_buffer_lines = 1, 110 .pixel_chunk_size_kbytes = 8, 111 .pte_enable = 1, 112 .max_page_table_levels = 2, 113 .pte_chunk_size_kbytes = 2, // ? 114 .meta_chunk_size_kbytes = 2, 115 .writeback_chunk_size_kbytes = 8, 116 .line_buffer_size_bits = 789504, 117 .is_line_buffer_bpp_fixed = 0, // ? 118 .line_buffer_fixed_bpp = 0, // ? 119 .dcc_supported = true, 120 .writeback_interface_buffer_size_kbytes = 90, 121 .writeback_line_buffer_buffer_size = 0, 122 .max_line_buffer_lines = 12, 123 .writeback_luma_buffer_size_kbytes = 12, // writeback_line_buffer_buffer_size = 656640 124 .writeback_chroma_buffer_size_kbytes = 8, 125 .writeback_chroma_line_buffer_width_pixels = 4, 126 .writeback_max_hscl_ratio = 1, 127 .writeback_max_vscl_ratio = 1, 128 .writeback_min_hscl_ratio = 1, 129 .writeback_min_vscl_ratio = 1, 130 .writeback_max_hscl_taps = 1, 131 .writeback_max_vscl_taps = 1, 132 .writeback_line_buffer_luma_buffer_size = 0, 133 .writeback_line_buffer_chroma_buffer_size = 14643, 134 .cursor_buffer_size = 8, 135 .cursor_chunk_size = 2, 136 .max_num_otg = 6, 137 .max_num_dpp = 6, 138 .max_num_wb = 1, 139 .max_dchub_pscl_bw_pix_per_clk = 4, 140 .max_pscl_lb_bw_pix_per_clk = 2, 141 .max_lb_vscl_bw_pix_per_clk = 4, 142 .max_vscl_hscl_bw_pix_per_clk = 4, 143 .max_hscl_ratio = 6, 144 .max_vscl_ratio = 6, 145 .hscl_mults = 4, 146 .vscl_mults = 4, 147 .max_hscl_taps = 8, 148 .max_vscl_taps = 8, 149 .dispclk_ramp_margin_percent = 1, 150 .underscan_factor = 1.11, 151 .min_vblank_lines = 32, 152 .dppclk_delay_subtotal = 46, 153 .dynamic_metadata_vm_enabled = true, 154 .dppclk_delay_scl_lb_only = 16, 155 .dppclk_delay_scl = 50, 156 .dppclk_delay_cnvc_formatter = 27, 157 .dppclk_delay_cnvc_cursor = 6, 158 .dispclk_delay_subtotal = 119, 159 .dcfclk_cstate_latency = 5.2, // SRExitTime 160 .max_inter_dcn_tile_repeaters = 8, 161 .odm_combine_4to1_supported = true, 162 163 .xfc_supported = false, 164 .xfc_fill_bw_overhead_percent = 10.0, 165 .xfc_fill_constant_bytes = 0, 166 .gfx7_compat_tiling_supported = 0, 167 .number_of_cursors = 1, 168 }; 169 170 struct _vcs_dpi_soc_bounding_box_st dcn3_0_soc = { 171 .clock_limits = { 172 { 173 .state = 0, 174 .dispclk_mhz = 562.0, 175 .dppclk_mhz = 300.0, 176 .phyclk_mhz = 300.0, 177 .phyclk_d18_mhz = 667.0, 178 .dscclk_mhz = 405.6, 179 }, 180 }, 181 .min_dcfclk = 500.0, /* TODO: set this to actual min DCFCLK */ 182 .num_states = 1, 183 .sr_exit_time_us = 12, 184 .sr_enter_plus_exit_time_us = 20, 185 .urgent_latency_us = 4.0, 186 .urgent_latency_pixel_data_only_us = 4.0, 187 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0, 188 .urgent_latency_vm_data_only_us = 4.0, 189 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096, 190 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096, 191 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096, 192 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 80.0, 193 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0, 194 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0, 195 .max_avg_sdp_bw_use_normal_percent = 60.0, 196 .max_avg_dram_bw_use_normal_percent = 40.0, 197 .writeback_latency_us = 12.0, 198 .max_request_size_bytes = 256, 199 .fabric_datapath_to_dcn_data_return_bytes = 64, 200 .dcn_downspread_percent = 0.5, 201 .downspread_percent = 0.38, 202 .dram_page_open_time_ns = 50.0, 203 .dram_rw_turnaround_time_ns = 17.5, 204 .dram_return_buffer_per_channel_bytes = 8192, 205 .round_trip_ping_latency_dcfclk_cycles = 191, 206 .urgent_out_of_order_return_per_channel_bytes = 4096, 207 .channel_interleave_bytes = 256, 208 .num_banks = 8, 209 .gpuvm_min_page_size_bytes = 4096, 210 .hostvm_min_page_size_bytes = 4096, 211 .dram_clock_change_latency_us = 404, 212 .dummy_pstate_latency_us = 5, 213 .writeback_dram_clock_change_latency_us = 23.0, 214 .return_bus_width_bytes = 64, 215 .dispclk_dppclk_vco_speed_mhz = 3650, 216 .xfc_bus_transport_time_us = 20, // ? 217 .xfc_xbuf_latency_tolerance_us = 4, // ? 218 .use_urgent_burst_bw = 1, // ? 219 .do_urgent_latency_adjustment = true, 220 .urgent_latency_adjustment_fabric_clock_component_us = 1.0, 221 .urgent_latency_adjustment_fabric_clock_reference_mhz = 1000, 222 }; 223 224 enum dcn30_clk_src_array_id { 225 DCN30_CLK_SRC_PLL0, 226 DCN30_CLK_SRC_PLL1, 227 DCN30_CLK_SRC_PLL2, 228 DCN30_CLK_SRC_PLL3, 229 DCN30_CLK_SRC_PLL4, 230 DCN30_CLK_SRC_PLL5, 231 DCN30_CLK_SRC_TOTAL 232 }; 233 234 /* begin ********************* 235 * macros to expend register list macro defined in HW object header file 236 */ 237 238 /* DCN */ 239 /* TODO awful hack. fixup dcn20_dwb.h */ 240 #undef BASE_INNER 241 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg 242 243 #define BASE(seg) BASE_INNER(seg) 244 245 #define SR(reg_name)\ 246 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ 247 mm ## reg_name 248 249 #define SRI(reg_name, block, id)\ 250 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 251 mm ## block ## id ## _ ## reg_name 252 253 #define SRI2(reg_name, block, id)\ 254 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ 255 mm ## reg_name 256 257 #define SRIR(var_name, reg_name, block, id)\ 258 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 259 mm ## block ## id ## _ ## reg_name 260 261 #define SRII(reg_name, block, id)\ 262 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 263 mm ## block ## id ## _ ## reg_name 264 265 #define SRII_MPC_RMU(reg_name, block, id)\ 266 .RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 267 mm ## block ## id ## _ ## reg_name 268 269 #define SRII_DWB(reg_name, temp_name, block, id)\ 270 .reg_name[id] = BASE(mm ## block ## id ## _ ## temp_name ## _BASE_IDX) + \ 271 mm ## block ## id ## _ ## temp_name 272 273 #define DCCG_SRII(reg_name, block, id)\ 274 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 275 mm ## block ## id ## _ ## reg_name 276 277 #define VUPDATE_SRII(reg_name, block, id)\ 278 .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \ 279 mm ## reg_name ## _ ## block ## id 280 281 /* NBIO */ 282 #define NBIO_BASE_INNER(seg) \ 283 NBIO_BASE__INST0_SEG ## seg 284 285 #define NBIO_BASE(seg) \ 286 NBIO_BASE_INNER(seg) 287 288 #define NBIO_SR(reg_name)\ 289 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \ 290 mm ## reg_name 291 292 /* MMHUB */ 293 #define MMHUB_BASE_INNER(seg) \ 294 MMHUB_BASE__INST0_SEG ## seg 295 296 #define MMHUB_BASE(seg) \ 297 MMHUB_BASE_INNER(seg) 298 299 #define MMHUB_SR(reg_name)\ 300 .reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \ 301 mmMM ## reg_name 302 303 /* CLOCK */ 304 #define CLK_BASE_INNER(seg) \ 305 CLK_BASE__INST0_SEG ## seg 306 307 #define CLK_BASE(seg) \ 308 CLK_BASE_INNER(seg) 309 310 #define CLK_SRI(reg_name, block, inst)\ 311 .reg_name = CLK_BASE(mm ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \ 312 mm ## block ## _ ## inst ## _ ## reg_name 313 314 315 static const struct bios_registers bios_regs = { 316 NBIO_SR(BIOS_SCRATCH_3), 317 NBIO_SR(BIOS_SCRATCH_6) 318 }; 319 320 #define clk_src_regs(index, pllid)\ 321 [index] = {\ 322 CS_COMMON_REG_LIST_DCN2_0(index, pllid),\ 323 } 324 325 static const struct dce110_clk_src_regs clk_src_regs[] = { 326 clk_src_regs(0, A), 327 clk_src_regs(1, B), 328 clk_src_regs(2, C), 329 clk_src_regs(3, D), 330 clk_src_regs(4, E), 331 clk_src_regs(5, F) 332 }; 333 334 static const struct dce110_clk_src_shift cs_shift = { 335 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 336 }; 337 338 static const struct dce110_clk_src_mask cs_mask = { 339 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 340 }; 341 342 #define abm_regs(id)\ 343 [id] = {\ 344 ABM_DCN30_REG_LIST(id)\ 345 } 346 347 static const struct dce_abm_registers abm_regs[] = { 348 abm_regs(0), 349 abm_regs(1), 350 abm_regs(2), 351 abm_regs(3), 352 abm_regs(4), 353 abm_regs(5), 354 }; 355 356 static const struct dce_abm_shift abm_shift = { 357 ABM_MASK_SH_LIST_DCN301(__SHIFT) 358 }; 359 360 static const struct dce_abm_mask abm_mask = { 361 ABM_MASK_SH_LIST_DCN301(_MASK) 362 }; 363 364 365 366 #define audio_regs(id)\ 367 [id] = {\ 368 AUD_COMMON_REG_LIST(id)\ 369 } 370 371 static const struct dce_audio_registers audio_regs[] = { 372 audio_regs(0), 373 audio_regs(1), 374 audio_regs(2), 375 audio_regs(3), 376 audio_regs(4), 377 audio_regs(5), 378 audio_regs(6) 379 }; 380 381 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 382 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 383 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 384 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 385 386 static const struct dce_audio_shift audio_shift = { 387 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 388 }; 389 390 static const struct dce_audio_mask audio_mask = { 391 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 392 }; 393 394 #define vpg_regs(id)\ 395 [id] = {\ 396 VPG_DCN3_REG_LIST(id)\ 397 } 398 399 static const struct dcn30_vpg_registers vpg_regs[] = { 400 vpg_regs(0), 401 vpg_regs(1), 402 vpg_regs(2), 403 vpg_regs(3), 404 vpg_regs(4), 405 vpg_regs(5), 406 vpg_regs(6), 407 }; 408 409 static const struct dcn30_vpg_shift vpg_shift = { 410 DCN3_VPG_MASK_SH_LIST(__SHIFT) 411 }; 412 413 static const struct dcn30_vpg_mask vpg_mask = { 414 DCN3_VPG_MASK_SH_LIST(_MASK) 415 }; 416 417 #define afmt_regs(id)\ 418 [id] = {\ 419 AFMT_DCN3_REG_LIST(id)\ 420 } 421 422 static const struct dcn30_afmt_registers afmt_regs[] = { 423 afmt_regs(0), 424 afmt_regs(1), 425 afmt_regs(2), 426 afmt_regs(3), 427 afmt_regs(4), 428 afmt_regs(5), 429 afmt_regs(6), 430 }; 431 432 static const struct dcn30_afmt_shift afmt_shift = { 433 DCN3_AFMT_MASK_SH_LIST(__SHIFT) 434 }; 435 436 static const struct dcn30_afmt_mask afmt_mask = { 437 DCN3_AFMT_MASK_SH_LIST(_MASK) 438 }; 439 440 #define stream_enc_regs(id)\ 441 [id] = {\ 442 SE_DCN3_REG_LIST(id)\ 443 } 444 445 static const struct dcn10_stream_enc_registers stream_enc_regs[] = { 446 stream_enc_regs(0), 447 stream_enc_regs(1), 448 stream_enc_regs(2), 449 stream_enc_regs(3), 450 stream_enc_regs(4), 451 stream_enc_regs(5) 452 }; 453 454 static const struct dcn10_stream_encoder_shift se_shift = { 455 SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 456 }; 457 458 static const struct dcn10_stream_encoder_mask se_mask = { 459 SE_COMMON_MASK_SH_LIST_DCN30(_MASK) 460 }; 461 462 463 #define aux_regs(id)\ 464 [id] = {\ 465 DCN2_AUX_REG_LIST(id)\ 466 } 467 468 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { 469 aux_regs(0), 470 aux_regs(1), 471 aux_regs(2), 472 aux_regs(3), 473 aux_regs(4), 474 aux_regs(5) 475 }; 476 477 #define hpd_regs(id)\ 478 [id] = {\ 479 HPD_REG_LIST(id)\ 480 } 481 482 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { 483 hpd_regs(0), 484 hpd_regs(1), 485 hpd_regs(2), 486 hpd_regs(3), 487 hpd_regs(4), 488 hpd_regs(5) 489 }; 490 491 #define link_regs(id, phyid)\ 492 [id] = {\ 493 LE_DCN3_REG_LIST(id), \ 494 UNIPHY_DCN2_REG_LIST(phyid), \ 495 DPCS_DCN2_REG_LIST(id), \ 496 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \ 497 } 498 499 static const struct dce110_aux_registers_shift aux_shift = { 500 DCN_AUX_MASK_SH_LIST(__SHIFT) 501 }; 502 503 static const struct dce110_aux_registers_mask aux_mask = { 504 DCN_AUX_MASK_SH_LIST(_MASK) 505 }; 506 507 static const struct dcn10_link_enc_registers link_enc_regs[] = { 508 link_regs(0, A), 509 link_regs(1, B), 510 link_regs(2, C), 511 link_regs(3, D), 512 link_regs(4, E), 513 link_regs(5, F) 514 }; 515 516 static const struct dcn10_link_enc_shift le_shift = { 517 LINK_ENCODER_MASK_SH_LIST_DCN30(__SHIFT),\ 518 DPCS_DCN2_MASK_SH_LIST(__SHIFT) 519 }; 520 521 static const struct dcn10_link_enc_mask le_mask = { 522 LINK_ENCODER_MASK_SH_LIST_DCN30(_MASK),\ 523 DPCS_DCN2_MASK_SH_LIST(_MASK) 524 }; 525 526 527 static const struct dce_panel_cntl_registers panel_cntl_regs[] = { 528 { DCN_PANEL_CNTL_REG_LIST() } 529 }; 530 531 static const struct dce_panel_cntl_shift panel_cntl_shift = { 532 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT) 533 }; 534 535 static const struct dce_panel_cntl_mask panel_cntl_mask = { 536 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK) 537 }; 538 539 #define dpp_regs(id)\ 540 [id] = {\ 541 DPP_REG_LIST_DCN30(id),\ 542 } 543 544 static const struct dcn3_dpp_registers dpp_regs[] = { 545 dpp_regs(0), 546 dpp_regs(1), 547 dpp_regs(2), 548 dpp_regs(3), 549 dpp_regs(4), 550 dpp_regs(5), 551 }; 552 553 static const struct dcn3_dpp_shift tf_shift = { 554 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT) 555 }; 556 557 static const struct dcn3_dpp_mask tf_mask = { 558 DPP_REG_LIST_SH_MASK_DCN30(_MASK) 559 }; 560 561 #define opp_regs(id)\ 562 [id] = {\ 563 OPP_REG_LIST_DCN30(id),\ 564 } 565 566 static const struct dcn20_opp_registers opp_regs[] = { 567 opp_regs(0), 568 opp_regs(1), 569 opp_regs(2), 570 opp_regs(3), 571 opp_regs(4), 572 opp_regs(5) 573 }; 574 575 static const struct dcn20_opp_shift opp_shift = { 576 OPP_MASK_SH_LIST_DCN20(__SHIFT) 577 }; 578 579 static const struct dcn20_opp_mask opp_mask = { 580 OPP_MASK_SH_LIST_DCN20(_MASK) 581 }; 582 583 #define aux_engine_regs(id)\ 584 [id] = {\ 585 AUX_COMMON_REG_LIST0(id), \ 586 .AUXN_IMPCAL = 0, \ 587 .AUXP_IMPCAL = 0, \ 588 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \ 589 } 590 591 static const struct dce110_aux_registers aux_engine_regs[] = { 592 aux_engine_regs(0), 593 aux_engine_regs(1), 594 aux_engine_regs(2), 595 aux_engine_regs(3), 596 aux_engine_regs(4), 597 aux_engine_regs(5) 598 }; 599 600 #define dwbc_regs_dcn3(id)\ 601 [id] = {\ 602 DWBC_COMMON_REG_LIST_DCN30(id),\ 603 } 604 605 static const struct dcn30_dwbc_registers dwbc30_regs[] = { 606 dwbc_regs_dcn3(0), 607 }; 608 609 static const struct dcn30_dwbc_shift dwbc30_shift = { 610 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 611 }; 612 613 static const struct dcn30_dwbc_mask dwbc30_mask = { 614 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK) 615 }; 616 617 #define mcif_wb_regs_dcn3(id)\ 618 [id] = {\ 619 MCIF_WB_COMMON_REG_LIST_DCN30(id),\ 620 } 621 622 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = { 623 mcif_wb_regs_dcn3(0) 624 }; 625 626 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = { 627 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 628 }; 629 630 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { 631 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK) 632 }; 633 634 #define dsc_regsDCN20(id)\ 635 [id] = {\ 636 DSC_REG_LIST_DCN20(id)\ 637 } 638 639 static const struct dcn20_dsc_registers dsc_regs[] = { 640 dsc_regsDCN20(0), 641 dsc_regsDCN20(1), 642 dsc_regsDCN20(2), 643 dsc_regsDCN20(3), 644 dsc_regsDCN20(4), 645 dsc_regsDCN20(5) 646 }; 647 648 static const struct dcn20_dsc_shift dsc_shift = { 649 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) 650 }; 651 652 static const struct dcn20_dsc_mask dsc_mask = { 653 DSC_REG_LIST_SH_MASK_DCN20(_MASK) 654 }; 655 656 static const struct dcn30_mpc_registers mpc_regs = { 657 MPC_REG_LIST_DCN3_0(0), 658 MPC_REG_LIST_DCN3_0(1), 659 MPC_REG_LIST_DCN3_0(2), 660 MPC_REG_LIST_DCN3_0(3), 661 MPC_REG_LIST_DCN3_0(4), 662 MPC_REG_LIST_DCN3_0(5), 663 MPC_OUT_MUX_REG_LIST_DCN3_0(0), 664 MPC_OUT_MUX_REG_LIST_DCN3_0(1), 665 MPC_OUT_MUX_REG_LIST_DCN3_0(2), 666 MPC_OUT_MUX_REG_LIST_DCN3_0(3), 667 MPC_OUT_MUX_REG_LIST_DCN3_0(4), 668 MPC_OUT_MUX_REG_LIST_DCN3_0(5), 669 MPC_RMU_GLOBAL_REG_LIST_DCN3AG, 670 MPC_RMU_REG_LIST_DCN3AG(0), 671 MPC_RMU_REG_LIST_DCN3AG(1), 672 MPC_RMU_REG_LIST_DCN3AG(2), 673 MPC_DWB_MUX_REG_LIST_DCN3_0(0), 674 }; 675 676 static const struct dcn30_mpc_shift mpc_shift = { 677 MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 678 }; 679 680 static const struct dcn30_mpc_mask mpc_mask = { 681 MPC_COMMON_MASK_SH_LIST_DCN30(_MASK) 682 }; 683 684 #define optc_regs(id)\ 685 [id] = {OPTC_COMMON_REG_LIST_DCN3_0(id)} 686 687 688 static const struct dcn_optc_registers optc_regs[] = { 689 optc_regs(0), 690 optc_regs(1), 691 optc_regs(2), 692 optc_regs(3), 693 optc_regs(4), 694 optc_regs(5) 695 }; 696 697 static const struct dcn_optc_shift optc_shift = { 698 OPTC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 699 }; 700 701 static const struct dcn_optc_mask optc_mask = { 702 OPTC_COMMON_MASK_SH_LIST_DCN30(_MASK) 703 }; 704 705 #define hubp_regs(id)\ 706 [id] = {\ 707 HUBP_REG_LIST_DCN30(id)\ 708 } 709 710 static const struct dcn_hubp2_registers hubp_regs[] = { 711 hubp_regs(0), 712 hubp_regs(1), 713 hubp_regs(2), 714 hubp_regs(3), 715 hubp_regs(4), 716 hubp_regs(5) 717 }; 718 719 static const struct dcn_hubp2_shift hubp_shift = { 720 HUBP_MASK_SH_LIST_DCN30(__SHIFT) 721 }; 722 723 static const struct dcn_hubp2_mask hubp_mask = { 724 HUBP_MASK_SH_LIST_DCN30(_MASK) 725 }; 726 727 static const struct dcn_hubbub_registers hubbub_reg = { 728 HUBBUB_REG_LIST_DCN30(0) 729 }; 730 731 static const struct dcn_hubbub_shift hubbub_shift = { 732 HUBBUB_MASK_SH_LIST_DCN30(__SHIFT) 733 }; 734 735 static const struct dcn_hubbub_mask hubbub_mask = { 736 HUBBUB_MASK_SH_LIST_DCN30(_MASK) 737 }; 738 739 static const struct dccg_registers dccg_regs = { 740 DCCG_REG_LIST_DCN30() 741 }; 742 743 static const struct dccg_shift dccg_shift = { 744 DCCG_MASK_SH_LIST_DCN3(__SHIFT) 745 }; 746 747 static const struct dccg_mask dccg_mask = { 748 DCCG_MASK_SH_LIST_DCN3(_MASK) 749 }; 750 751 static const struct dce_hwseq_registers hwseq_reg = { 752 HWSEQ_DCN30_REG_LIST() 753 }; 754 755 static const struct dce_hwseq_shift hwseq_shift = { 756 HWSEQ_DCN30_MASK_SH_LIST(__SHIFT) 757 }; 758 759 static const struct dce_hwseq_mask hwseq_mask = { 760 HWSEQ_DCN30_MASK_SH_LIST(_MASK) 761 }; 762 #define vmid_regs(id)\ 763 [id] = {\ 764 DCN20_VMID_REG_LIST(id)\ 765 } 766 767 static const struct dcn_vmid_registers vmid_regs[] = { 768 vmid_regs(0), 769 vmid_regs(1), 770 vmid_regs(2), 771 vmid_regs(3), 772 vmid_regs(4), 773 vmid_regs(5), 774 vmid_regs(6), 775 vmid_regs(7), 776 vmid_regs(8), 777 vmid_regs(9), 778 vmid_regs(10), 779 vmid_regs(11), 780 vmid_regs(12), 781 vmid_regs(13), 782 vmid_regs(14), 783 vmid_regs(15) 784 }; 785 786 static const struct dcn20_vmid_shift vmid_shifts = { 787 DCN20_VMID_MASK_SH_LIST(__SHIFT) 788 }; 789 790 static const struct dcn20_vmid_mask vmid_masks = { 791 DCN20_VMID_MASK_SH_LIST(_MASK) 792 }; 793 794 static const struct resource_caps res_cap_dcn3 = { 795 .num_timing_generator = 6, 796 .num_opp = 6, 797 .num_video_plane = 6, 798 .num_audio = 6, 799 .num_stream_encoder = 6, 800 .num_pll = 6, 801 .num_dwb = 1, 802 .num_ddc = 6, 803 .num_vmid = 16, 804 .num_mpc_3dlut = 3, 805 .num_dsc = 6, 806 }; 807 808 static const struct dc_plane_cap plane_cap = { 809 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 810 .blends_with_above = true, 811 .blends_with_below = true, 812 .per_pixel_alpha = true, 813 814 .pixel_format_support = { 815 .argb8888 = true, 816 .nv12 = true, 817 .fp16 = true, 818 .p010 = false, 819 .ayuv = false, 820 }, 821 822 .max_upscale_factor = { 823 .argb8888 = 16000, 824 .nv12 = 16000, 825 .fp16 = 16000 826 }, 827 828 .max_downscale_factor = { 829 .argb8888 = 600, 830 .nv12 = 600, 831 .fp16 = 600 832 } 833 }; 834 835 static const struct dc_debug_options debug_defaults_drv = { 836 .disable_dmcu = true, //No DMCU on DCN30 837 .force_abm_enable = false, 838 .timing_trace = false, 839 .clock_trace = true, 840 .disable_pplib_clock_request = true, 841 .pipe_split_policy = MPC_SPLIT_DYNAMIC, 842 .force_single_disp_pipe_split = false, 843 .disable_dcc = DCC_ENABLE, 844 .vsr_support = true, 845 .performance_trace = false, 846 .max_downscale_src_width = 7680,/*upto 8K*/ 847 .disable_pplib_wm_range = false, 848 .scl_reset_length10 = true, 849 .sanity_checks = false, 850 .underflow_assert_delay_us = 0xFFFFFFFF, 851 .dwb_fi_phase = -1, // -1 = disable, 852 .dmub_command_table = true, 853 .disable_psr = false, 854 }; 855 856 static const struct dc_debug_options debug_defaults_diags = { 857 .disable_dmcu = true, //No dmcu on DCN30 858 .force_abm_enable = false, 859 .timing_trace = true, 860 .clock_trace = true, 861 .disable_dpp_power_gate = true, 862 .disable_hubp_power_gate = true, 863 .disable_clock_gate = true, 864 .disable_pplib_clock_request = true, 865 .disable_pplib_wm_range = true, 866 .disable_stutter = false, 867 .scl_reset_length10 = true, 868 .dwb_fi_phase = -1, // -1 = disable 869 .dmub_command_table = true, 870 .disable_psr = true, 871 .enable_tri_buf = true, 872 }; 873 874 void dcn30_dpp_destroy(struct dpp **dpp) 875 { 876 kfree(TO_DCN20_DPP(*dpp)); 877 *dpp = NULL; 878 } 879 880 static struct dpp *dcn30_dpp_create( 881 struct dc_context *ctx, 882 uint32_t inst) 883 { 884 struct dcn3_dpp *dpp = 885 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL); 886 887 if (!dpp) 888 return NULL; 889 890 if (dpp3_construct(dpp, ctx, inst, 891 &dpp_regs[inst], &tf_shift, &tf_mask)) 892 return &dpp->base; 893 894 BREAK_TO_DEBUGGER(); 895 kfree(dpp); 896 return NULL; 897 } 898 899 static struct output_pixel_processor *dcn30_opp_create( 900 struct dc_context *ctx, uint32_t inst) 901 { 902 struct dcn20_opp *opp = 903 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); 904 905 if (!opp) { 906 BREAK_TO_DEBUGGER(); 907 return NULL; 908 } 909 910 dcn20_opp_construct(opp, ctx, inst, 911 &opp_regs[inst], &opp_shift, &opp_mask); 912 return &opp->base; 913 } 914 915 static struct dce_aux *dcn30_aux_engine_create( 916 struct dc_context *ctx, 917 uint32_t inst) 918 { 919 struct aux_engine_dce110 *aux_engine = 920 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 921 922 if (!aux_engine) 923 return NULL; 924 925 dce110_aux_engine_construct(aux_engine, ctx, inst, 926 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 927 &aux_engine_regs[inst], 928 &aux_mask, 929 &aux_shift, 930 ctx->dc->caps.extended_aux_timeout_support); 931 932 return &aux_engine->base; 933 } 934 935 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 936 937 static const struct dce_i2c_registers i2c_hw_regs[] = { 938 i2c_inst_regs(1), 939 i2c_inst_regs(2), 940 i2c_inst_regs(3), 941 i2c_inst_regs(4), 942 i2c_inst_regs(5), 943 i2c_inst_regs(6), 944 }; 945 946 static const struct dce_i2c_shift i2c_shifts = { 947 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT) 948 }; 949 950 static const struct dce_i2c_mask i2c_masks = { 951 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK) 952 }; 953 954 static struct dce_i2c_hw *dcn30_i2c_hw_create( 955 struct dc_context *ctx, 956 uint32_t inst) 957 { 958 struct dce_i2c_hw *dce_i2c_hw = 959 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 960 961 if (!dce_i2c_hw) 962 return NULL; 963 964 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, 965 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 966 967 return dce_i2c_hw; 968 } 969 970 static struct mpc *dcn30_mpc_create( 971 struct dc_context *ctx, 972 int num_mpcc, 973 int num_rmu) 974 { 975 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), 976 GFP_KERNEL); 977 978 if (!mpc30) 979 return NULL; 980 981 dcn30_mpc_construct(mpc30, ctx, 982 &mpc_regs, 983 &mpc_shift, 984 &mpc_mask, 985 num_mpcc, 986 num_rmu); 987 988 return &mpc30->base; 989 } 990 991 struct hubbub *dcn30_hubbub_create(struct dc_context *ctx) 992 { 993 int i; 994 995 struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub), 996 GFP_KERNEL); 997 998 if (!hubbub3) 999 return NULL; 1000 1001 hubbub3_construct(hubbub3, ctx, 1002 &hubbub_reg, 1003 &hubbub_shift, 1004 &hubbub_mask); 1005 1006 1007 for (i = 0; i < res_cap_dcn3.num_vmid; i++) { 1008 struct dcn20_vmid *vmid = &hubbub3->vmid[i]; 1009 1010 vmid->ctx = ctx; 1011 1012 vmid->regs = &vmid_regs[i]; 1013 vmid->shifts = &vmid_shifts; 1014 vmid->masks = &vmid_masks; 1015 } 1016 1017 return &hubbub3->base; 1018 } 1019 1020 static struct timing_generator *dcn30_timing_generator_create( 1021 struct dc_context *ctx, 1022 uint32_t instance) 1023 { 1024 struct optc *tgn10 = 1025 kzalloc(sizeof(struct optc), GFP_KERNEL); 1026 1027 if (!tgn10) 1028 return NULL; 1029 1030 tgn10->base.inst = instance; 1031 tgn10->base.ctx = ctx; 1032 1033 tgn10->tg_regs = &optc_regs[instance]; 1034 tgn10->tg_shift = &optc_shift; 1035 tgn10->tg_mask = &optc_mask; 1036 1037 dcn30_timing_generator_init(tgn10); 1038 1039 return &tgn10->base; 1040 } 1041 1042 static const struct encoder_feature_support link_enc_feature = { 1043 .max_hdmi_deep_color = COLOR_DEPTH_121212, 1044 .max_hdmi_pixel_clock = 600000, 1045 .hdmi_ycbcr420_supported = true, 1046 .dp_ycbcr420_supported = true, 1047 .fec_supported = true, 1048 .flags.bits.IS_HBR2_CAPABLE = true, 1049 .flags.bits.IS_HBR3_CAPABLE = true, 1050 .flags.bits.IS_TPS3_CAPABLE = true, 1051 .flags.bits.IS_TPS4_CAPABLE = true 1052 }; 1053 1054 static struct link_encoder *dcn30_link_encoder_create( 1055 const struct encoder_init_data *enc_init_data) 1056 { 1057 struct dcn20_link_encoder *enc20 = 1058 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 1059 1060 if (!enc20) 1061 return NULL; 1062 1063 dcn30_link_encoder_construct(enc20, 1064 enc_init_data, 1065 &link_enc_feature, 1066 &link_enc_regs[enc_init_data->transmitter], 1067 &link_enc_aux_regs[enc_init_data->channel - 1], 1068 &link_enc_hpd_regs[enc_init_data->hpd_source], 1069 &le_shift, 1070 &le_mask); 1071 1072 return &enc20->enc10.base; 1073 } 1074 1075 static struct panel_cntl *dcn30_panel_cntl_create(const struct panel_cntl_init_data *init_data) 1076 { 1077 struct dce_panel_cntl *panel_cntl = 1078 kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL); 1079 1080 if (!panel_cntl) 1081 return NULL; 1082 1083 dce_panel_cntl_construct(panel_cntl, 1084 init_data, 1085 &panel_cntl_regs[init_data->inst], 1086 &panel_cntl_shift, 1087 &panel_cntl_mask); 1088 1089 return &panel_cntl->base; 1090 } 1091 1092 static void read_dce_straps( 1093 struct dc_context *ctx, 1094 struct resource_straps *straps) 1095 { 1096 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX), 1097 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 1098 1099 } 1100 1101 static struct audio *dcn30_create_audio( 1102 struct dc_context *ctx, unsigned int inst) 1103 { 1104 return dce_audio_create(ctx, inst, 1105 &audio_regs[inst], &audio_shift, &audio_mask); 1106 } 1107 1108 static struct vpg *dcn30_vpg_create( 1109 struct dc_context *ctx, 1110 uint32_t inst) 1111 { 1112 struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL); 1113 1114 if (!vpg3) 1115 return NULL; 1116 1117 vpg3_construct(vpg3, ctx, inst, 1118 &vpg_regs[inst], 1119 &vpg_shift, 1120 &vpg_mask); 1121 1122 return &vpg3->base; 1123 } 1124 1125 static struct afmt *dcn30_afmt_create( 1126 struct dc_context *ctx, 1127 uint32_t inst) 1128 { 1129 struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL); 1130 1131 if (!afmt3) 1132 return NULL; 1133 1134 afmt3_construct(afmt3, ctx, inst, 1135 &afmt_regs[inst], 1136 &afmt_shift, 1137 &afmt_mask); 1138 1139 return &afmt3->base; 1140 } 1141 1142 struct stream_encoder *dcn30_stream_encoder_create( 1143 enum engine_id eng_id, 1144 struct dc_context *ctx) 1145 { 1146 struct dcn10_stream_encoder *enc1; 1147 struct vpg *vpg; 1148 struct afmt *afmt; 1149 int vpg_inst; 1150 int afmt_inst; 1151 1152 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */ 1153 if (eng_id <= ENGINE_ID_DIGF) { 1154 vpg_inst = eng_id; 1155 afmt_inst = eng_id; 1156 } else 1157 return NULL; 1158 1159 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 1160 vpg = dcn30_vpg_create(ctx, vpg_inst); 1161 afmt = dcn30_afmt_create(ctx, afmt_inst); 1162 1163 if (!enc1 || !vpg || !afmt) 1164 return NULL; 1165 1166 dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, 1167 eng_id, vpg, afmt, 1168 &stream_enc_regs[eng_id], 1169 &se_shift, &se_mask); 1170 1171 return &enc1->base; 1172 } 1173 1174 struct dce_hwseq *dcn30_hwseq_create( 1175 struct dc_context *ctx) 1176 { 1177 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 1178 1179 if (hws) { 1180 hws->ctx = ctx; 1181 hws->regs = &hwseq_reg; 1182 hws->shifts = &hwseq_shift; 1183 hws->masks = &hwseq_mask; 1184 } 1185 return hws; 1186 } 1187 static const struct resource_create_funcs res_create_funcs = { 1188 .read_dce_straps = read_dce_straps, 1189 .create_audio = dcn30_create_audio, 1190 .create_stream_encoder = dcn30_stream_encoder_create, 1191 .create_hwseq = dcn30_hwseq_create, 1192 }; 1193 1194 static const struct resource_create_funcs res_create_maximus_funcs = { 1195 .read_dce_straps = NULL, 1196 .create_audio = NULL, 1197 .create_stream_encoder = NULL, 1198 .create_hwseq = dcn30_hwseq_create, 1199 }; 1200 1201 static void dcn30_resource_destruct(struct dcn30_resource_pool *pool) 1202 { 1203 unsigned int i; 1204 1205 for (i = 0; i < pool->base.stream_enc_count; i++) { 1206 if (pool->base.stream_enc[i] != NULL) { 1207 if (pool->base.stream_enc[i]->vpg != NULL) { 1208 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg)); 1209 pool->base.stream_enc[i]->vpg = NULL; 1210 } 1211 if (pool->base.stream_enc[i]->afmt != NULL) { 1212 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt)); 1213 pool->base.stream_enc[i]->afmt = NULL; 1214 } 1215 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); 1216 pool->base.stream_enc[i] = NULL; 1217 } 1218 } 1219 1220 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 1221 if (pool->base.dscs[i] != NULL) 1222 dcn20_dsc_destroy(&pool->base.dscs[i]); 1223 } 1224 1225 if (pool->base.mpc != NULL) { 1226 kfree(TO_DCN20_MPC(pool->base.mpc)); 1227 pool->base.mpc = NULL; 1228 } 1229 if (pool->base.hubbub != NULL) { 1230 kfree(pool->base.hubbub); 1231 pool->base.hubbub = NULL; 1232 } 1233 for (i = 0; i < pool->base.pipe_count; i++) { 1234 if (pool->base.dpps[i] != NULL) 1235 dcn30_dpp_destroy(&pool->base.dpps[i]); 1236 1237 if (pool->base.ipps[i] != NULL) 1238 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); 1239 1240 if (pool->base.hubps[i] != NULL) { 1241 kfree(TO_DCN20_HUBP(pool->base.hubps[i])); 1242 pool->base.hubps[i] = NULL; 1243 } 1244 1245 if (pool->base.irqs != NULL) { 1246 dal_irq_service_destroy(&pool->base.irqs); 1247 } 1248 } 1249 1250 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1251 if (pool->base.engines[i] != NULL) 1252 dce110_engine_destroy(&pool->base.engines[i]); 1253 if (pool->base.hw_i2cs[i] != NULL) { 1254 kfree(pool->base.hw_i2cs[i]); 1255 pool->base.hw_i2cs[i] = NULL; 1256 } 1257 if (pool->base.sw_i2cs[i] != NULL) { 1258 kfree(pool->base.sw_i2cs[i]); 1259 pool->base.sw_i2cs[i] = NULL; 1260 } 1261 } 1262 1263 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 1264 if (pool->base.opps[i] != NULL) 1265 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); 1266 } 1267 1268 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1269 if (pool->base.timing_generators[i] != NULL) { 1270 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); 1271 pool->base.timing_generators[i] = NULL; 1272 } 1273 } 1274 1275 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { 1276 if (pool->base.dwbc[i] != NULL) { 1277 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); 1278 pool->base.dwbc[i] = NULL; 1279 } 1280 if (pool->base.mcif_wb[i] != NULL) { 1281 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i])); 1282 pool->base.mcif_wb[i] = NULL; 1283 } 1284 } 1285 1286 for (i = 0; i < pool->base.audio_count; i++) { 1287 if (pool->base.audios[i]) 1288 dce_aud_destroy(&pool->base.audios[i]); 1289 } 1290 1291 for (i = 0; i < pool->base.clk_src_count; i++) { 1292 if (pool->base.clock_sources[i] != NULL) { 1293 dcn20_clock_source_destroy(&pool->base.clock_sources[i]); 1294 pool->base.clock_sources[i] = NULL; 1295 } 1296 } 1297 1298 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { 1299 if (pool->base.mpc_lut[i] != NULL) { 1300 dc_3dlut_func_release(pool->base.mpc_lut[i]); 1301 pool->base.mpc_lut[i] = NULL; 1302 } 1303 if (pool->base.mpc_shaper[i] != NULL) { 1304 dc_transfer_func_release(pool->base.mpc_shaper[i]); 1305 pool->base.mpc_shaper[i] = NULL; 1306 } 1307 } 1308 1309 if (pool->base.dp_clock_source != NULL) { 1310 dcn20_clock_source_destroy(&pool->base.dp_clock_source); 1311 pool->base.dp_clock_source = NULL; 1312 } 1313 1314 for (i = 0; i < pool->base.pipe_count; i++) { 1315 if (pool->base.multiple_abms[i] != NULL) 1316 dce_abm_destroy(&pool->base.multiple_abms[i]); 1317 } 1318 1319 if (pool->base.psr != NULL) 1320 dmub_psr_destroy(&pool->base.psr); 1321 1322 if (pool->base.dccg != NULL) 1323 dcn_dccg_destroy(&pool->base.dccg); 1324 } 1325 1326 static struct hubp *dcn30_hubp_create( 1327 struct dc_context *ctx, 1328 uint32_t inst) 1329 { 1330 struct dcn20_hubp *hubp2 = 1331 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL); 1332 1333 if (!hubp2) 1334 return NULL; 1335 1336 if (hubp3_construct(hubp2, ctx, inst, 1337 &hubp_regs[inst], &hubp_shift, &hubp_mask)) 1338 return &hubp2->base; 1339 1340 BREAK_TO_DEBUGGER(); 1341 kfree(hubp2); 1342 return NULL; 1343 } 1344 1345 static bool dcn30_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) 1346 { 1347 int i; 1348 uint32_t pipe_count = pool->res_cap->num_dwb; 1349 1350 for (i = 0; i < pipe_count; i++) { 1351 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), 1352 GFP_KERNEL); 1353 1354 if (!dwbc30) { 1355 dm_error("DC: failed to create dwbc30!\n"); 1356 return false; 1357 } 1358 1359 dcn30_dwbc_construct(dwbc30, ctx, 1360 &dwbc30_regs[i], 1361 &dwbc30_shift, 1362 &dwbc30_mask, 1363 i); 1364 1365 pool->dwbc[i] = &dwbc30->base; 1366 } 1367 return true; 1368 } 1369 1370 static bool dcn30_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) 1371 { 1372 int i; 1373 uint32_t pipe_count = pool->res_cap->num_dwb; 1374 1375 for (i = 0; i < pipe_count; i++) { 1376 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), 1377 GFP_KERNEL); 1378 1379 if (!mcif_wb30) { 1380 dm_error("DC: failed to create mcif_wb30!\n"); 1381 return false; 1382 } 1383 1384 dcn30_mmhubbub_construct(mcif_wb30, ctx, 1385 &mcif_wb30_regs[i], 1386 &mcif_wb30_shift, 1387 &mcif_wb30_mask, 1388 i); 1389 1390 pool->mcif_wb[i] = &mcif_wb30->base; 1391 } 1392 return true; 1393 } 1394 1395 static struct display_stream_compressor *dcn30_dsc_create( 1396 struct dc_context *ctx, uint32_t inst) 1397 { 1398 struct dcn20_dsc *dsc = 1399 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); 1400 1401 if (!dsc) { 1402 BREAK_TO_DEBUGGER(); 1403 return NULL; 1404 } 1405 1406 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 1407 return &dsc->base; 1408 } 1409 1410 enum dc_status dcn30_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream) 1411 { 1412 1413 return dcn20_add_stream_to_ctx(dc, new_ctx, dc_stream); 1414 } 1415 1416 static void dcn30_destroy_resource_pool(struct resource_pool **pool) 1417 { 1418 struct dcn30_resource_pool *dcn30_pool = TO_DCN30_RES_POOL(*pool); 1419 1420 dcn30_resource_destruct(dcn30_pool); 1421 kfree(dcn30_pool); 1422 *pool = NULL; 1423 } 1424 1425 static struct clock_source *dcn30_clock_source_create( 1426 struct dc_context *ctx, 1427 struct dc_bios *bios, 1428 enum clock_source_id id, 1429 const struct dce110_clk_src_regs *regs, 1430 bool dp_clk_src) 1431 { 1432 struct dce110_clk_src *clk_src = 1433 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 1434 1435 if (!clk_src) 1436 return NULL; 1437 1438 if (dcn3_clk_src_construct(clk_src, ctx, bios, id, 1439 regs, &cs_shift, &cs_mask)) { 1440 clk_src->base.dp_clk_src = dp_clk_src; 1441 return &clk_src->base; 1442 } 1443 1444 BREAK_TO_DEBUGGER(); 1445 return NULL; 1446 } 1447 1448 int dcn30_populate_dml_pipes_from_context( 1449 struct dc *dc, struct dc_state *context, 1450 display_e2e_pipe_params_st *pipes) 1451 { 1452 int i, pipe_cnt; 1453 struct resource_context *res_ctx = &context->res_ctx; 1454 1455 dcn20_populate_dml_pipes_from_context(dc, context, pipes); 1456 1457 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { 1458 if (!res_ctx->pipe_ctx[i].stream) 1459 continue; 1460 1461 pipes[pipe_cnt++].pipe.scale_ratio_depth.lb_depth = 1462 dm_lb_16; 1463 } 1464 1465 return pipe_cnt; 1466 } 1467 1468 void dcn30_populate_dml_writeback_from_context( 1469 struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes) 1470 { 1471 int pipe_cnt, i, j; 1472 double max_calc_writeback_dispclk; 1473 double writeback_dispclk; 1474 struct writeback_st dout_wb; 1475 1476 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { 1477 struct dc_stream_state *stream = res_ctx->pipe_ctx[i].stream; 1478 1479 if (!stream) 1480 continue; 1481 max_calc_writeback_dispclk = 0; 1482 1483 /* Set writeback information */ 1484 pipes[pipe_cnt].dout.wb_enable = 0; 1485 pipes[pipe_cnt].dout.num_active_wb = 0; 1486 for (j = 0; j < stream->num_wb_info; j++) { 1487 struct dc_writeback_info *wb_info = &stream->writeback_info[j]; 1488 1489 if (wb_info->wb_enabled && wb_info->writeback_source_plane && 1490 (wb_info->writeback_source_plane == res_ctx->pipe_ctx[i].plane_state)) { 1491 pipes[pipe_cnt].dout.wb_enable = 1; 1492 pipes[pipe_cnt].dout.num_active_wb++; 1493 dout_wb.wb_src_height = wb_info->dwb_params.cnv_params.crop_en ? 1494 wb_info->dwb_params.cnv_params.crop_height : 1495 wb_info->dwb_params.cnv_params.src_height; 1496 dout_wb.wb_src_width = wb_info->dwb_params.cnv_params.crop_en ? 1497 wb_info->dwb_params.cnv_params.crop_width : 1498 wb_info->dwb_params.cnv_params.src_width; 1499 dout_wb.wb_dst_width = wb_info->dwb_params.dest_width; 1500 dout_wb.wb_dst_height = wb_info->dwb_params.dest_height; 1501 1502 /* For IP that doesn't support WB scaling, set h/v taps to 1 to avoid DML validation failure */ 1503 if (dc->dml.ip.writeback_max_hscl_taps > 1) { 1504 dout_wb.wb_htaps_luma = wb_info->dwb_params.scaler_taps.h_taps; 1505 dout_wb.wb_vtaps_luma = wb_info->dwb_params.scaler_taps.v_taps; 1506 } else { 1507 dout_wb.wb_htaps_luma = 1; 1508 dout_wb.wb_vtaps_luma = 1; 1509 } 1510 dout_wb.wb_htaps_chroma = 0; 1511 dout_wb.wb_vtaps_chroma = 0; 1512 dout_wb.wb_hratio = wb_info->dwb_params.cnv_params.crop_en ? 1513 (double)wb_info->dwb_params.cnv_params.crop_width / 1514 (double)wb_info->dwb_params.dest_width : 1515 (double)wb_info->dwb_params.cnv_params.src_width / 1516 (double)wb_info->dwb_params.dest_width; 1517 dout_wb.wb_vratio = wb_info->dwb_params.cnv_params.crop_en ? 1518 (double)wb_info->dwb_params.cnv_params.crop_height / 1519 (double)wb_info->dwb_params.dest_height : 1520 (double)wb_info->dwb_params.cnv_params.src_height / 1521 (double)wb_info->dwb_params.dest_height; 1522 if (wb_info->dwb_params.cnv_params.fc_out_format == DWB_OUT_FORMAT_64BPP_ARGB || 1523 wb_info->dwb_params.cnv_params.fc_out_format == DWB_OUT_FORMAT_64BPP_RGBA) 1524 dout_wb.wb_pixel_format = dm_444_64; 1525 else 1526 dout_wb.wb_pixel_format = dm_444_32; 1527 1528 /* Workaround for cases where multiple writebacks are connected to same plane 1529 * In which case, need to compute worst case and set the associated writeback parameters 1530 * This workaround is necessary due to DML computation assuming only 1 set of writeback 1531 * parameters per pipe 1532 */ 1533 writeback_dispclk = dml30_CalculateWriteBackDISPCLK( 1534 dout_wb.wb_pixel_format, 1535 pipes[pipe_cnt].pipe.dest.pixel_rate_mhz, 1536 dout_wb.wb_hratio, 1537 dout_wb.wb_vratio, 1538 dout_wb.wb_htaps_luma, 1539 dout_wb.wb_vtaps_luma, 1540 dout_wb.wb_src_width, 1541 dout_wb.wb_dst_width, 1542 pipes[pipe_cnt].pipe.dest.htotal, 1543 dc->current_state->bw_ctx.dml.ip.writeback_line_buffer_buffer_size); 1544 1545 if (writeback_dispclk > max_calc_writeback_dispclk) { 1546 max_calc_writeback_dispclk = writeback_dispclk; 1547 pipes[pipe_cnt].dout.wb = dout_wb; 1548 } 1549 } 1550 } 1551 1552 pipe_cnt++; 1553 } 1554 1555 } 1556 1557 unsigned int dcn30_calc_max_scaled_time( 1558 unsigned int time_per_pixel, 1559 enum mmhubbub_wbif_mode mode, 1560 unsigned int urgent_watermark) 1561 { 1562 unsigned int time_per_byte = 0; 1563 unsigned int total_free_entry = 0xb40; 1564 unsigned int buf_lh_capability; 1565 unsigned int max_scaled_time; 1566 1567 if (mode == PACKED_444) /* packed mode 32 bpp */ 1568 time_per_byte = time_per_pixel/4; 1569 else if (mode == PACKED_444_FP16) /* packed mode 64 bpp */ 1570 time_per_byte = time_per_pixel/8; 1571 1572 if (time_per_byte == 0) 1573 time_per_byte = 1; 1574 1575 buf_lh_capability = (total_free_entry*time_per_byte*32) >> 6; /* time_per_byte is in u6.6*/ 1576 max_scaled_time = buf_lh_capability - urgent_watermark; 1577 return max_scaled_time; 1578 } 1579 1580 void dcn30_set_mcif_arb_params( 1581 struct dc *dc, 1582 struct dc_state *context, 1583 display_e2e_pipe_params_st *pipes, 1584 int pipe_cnt) 1585 { 1586 enum mmhubbub_wbif_mode wbif_mode; 1587 struct display_mode_lib *dml = &context->bw_ctx.dml; 1588 struct mcif_arb_params *wb_arb_params; 1589 int i, j, k, dwb_pipe; 1590 1591 /* Writeback MCIF_WB arbitration parameters */ 1592 dwb_pipe = 0; 1593 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1594 1595 if (!context->res_ctx.pipe_ctx[i].stream) 1596 continue; 1597 1598 for (j = 0; j < MAX_DWB_PIPES; j++) { 1599 struct dc_writeback_info *writeback_info = &context->res_ctx.pipe_ctx[i].stream->writeback_info[j]; 1600 1601 if (writeback_info->wb_enabled == false) 1602 continue; 1603 1604 //wb_arb_params = &context->res_ctx.pipe_ctx[i].stream->writeback_info[j].mcif_arb_params; 1605 wb_arb_params = &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[dwb_pipe]; 1606 1607 if (writeback_info->dwb_params.cnv_params.fc_out_format == DWB_OUT_FORMAT_64BPP_ARGB || 1608 writeback_info->dwb_params.cnv_params.fc_out_format == DWB_OUT_FORMAT_64BPP_RGBA) 1609 wbif_mode = PACKED_444_FP16; 1610 else 1611 wbif_mode = PACKED_444; 1612 1613 for (k = 0; k < sizeof(wb_arb_params->cli_watermark)/sizeof(wb_arb_params->cli_watermark[0]); k++) { 1614 wb_arb_params->cli_watermark[k] = get_wm_writeback_urgent(dml, pipes, pipe_cnt) * 1000; 1615 wb_arb_params->pstate_watermark[k] = get_wm_writeback_dram_clock_change(dml, pipes, pipe_cnt) * 1000; 1616 } 1617 wb_arb_params->time_per_pixel = (1000000 << 6) / context->res_ctx.pipe_ctx[i].stream->phy_pix_clk; /* time_per_pixel should be in u6.6 format */ 1618 wb_arb_params->slice_lines = 32; 1619 wb_arb_params->arbitration_slice = 2; /* irrelevant since there is no YUV output */ 1620 wb_arb_params->max_scaled_time = dcn30_calc_max_scaled_time(wb_arb_params->time_per_pixel, 1621 wbif_mode, 1622 wb_arb_params->cli_watermark[0]); /* assume 4 watermark sets have the same value */ 1623 wb_arb_params->dram_speed_change_duration = dml->vba.WritebackAllowDRAMClockChangeEndPosition[j] * pipes[0].clks_cfg.refclk_mhz; /* num_clock_cycles = us * MHz */ 1624 1625 dwb_pipe++; 1626 1627 if (dwb_pipe >= MAX_DWB_PIPES) 1628 return; 1629 } 1630 if (dwb_pipe >= MAX_DWB_PIPES) 1631 return; 1632 } 1633 1634 } 1635 1636 static struct dc_cap_funcs cap_funcs = { 1637 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap 1638 }; 1639 1640 bool dcn30_acquire_post_bldn_3dlut( 1641 struct resource_context *res_ctx, 1642 const struct resource_pool *pool, 1643 int mpcc_id, 1644 struct dc_3dlut **lut, 1645 struct dc_transfer_func **shaper) 1646 { 1647 int i; 1648 bool ret = false; 1649 union dc_3dlut_state *state; 1650 1651 ASSERT(*lut == NULL && *shaper == NULL); 1652 *lut = NULL; 1653 *shaper = NULL; 1654 1655 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { 1656 if (!res_ctx->is_mpc_3dlut_acquired[i]) { 1657 *lut = pool->mpc_lut[i]; 1658 *shaper = pool->mpc_shaper[i]; 1659 state = &pool->mpc_lut[i]->state; 1660 res_ctx->is_mpc_3dlut_acquired[i] = true; 1661 state->bits.rmu_idx_valid = 1; 1662 state->bits.rmu_mux_num = i; 1663 if (state->bits.rmu_mux_num == 0) 1664 state->bits.mpc_rmu0_mux = mpcc_id; 1665 else if (state->bits.rmu_mux_num == 1) 1666 state->bits.mpc_rmu1_mux = mpcc_id; 1667 else if (state->bits.rmu_mux_num == 2) 1668 state->bits.mpc_rmu2_mux = mpcc_id; 1669 ret = true; 1670 break; 1671 } 1672 } 1673 return ret; 1674 } 1675 1676 bool dcn30_release_post_bldn_3dlut( 1677 struct resource_context *res_ctx, 1678 const struct resource_pool *pool, 1679 struct dc_3dlut **lut, 1680 struct dc_transfer_func **shaper) 1681 { 1682 int i; 1683 bool ret = false; 1684 1685 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { 1686 if (pool->mpc_lut[i] == *lut && pool->mpc_shaper[i] == *shaper) { 1687 res_ctx->is_mpc_3dlut_acquired[i] = false; 1688 pool->mpc_lut[i]->state.raw = 0; 1689 *lut = NULL; 1690 *shaper = NULL; 1691 ret = true; 1692 break; 1693 } 1694 } 1695 return ret; 1696 } 1697 1698 #define fixed16_to_double(x) (((double) x) / ((double) (1 << 16))) 1699 #define fixed16_to_double_to_cpu(x) fixed16_to_double(le32_to_cpu(x)) 1700 1701 static bool is_soc_bounding_box_valid(struct dc *dc) 1702 { 1703 uint32_t hw_internal_rev = dc->ctx->asic_id.hw_internal_rev; 1704 1705 if (ASICREV_IS_SIENNA_CICHLID_P(hw_internal_rev)) 1706 return true; 1707 1708 return false; 1709 } 1710 1711 static bool init_soc_bounding_box(struct dc *dc, 1712 struct dcn30_resource_pool *pool) 1713 { 1714 const struct gpu_info_soc_bounding_box_v1_0 *bb = dc->soc_bounding_box; 1715 struct _vcs_dpi_soc_bounding_box_st *loaded_bb = &dcn3_0_soc; 1716 struct _vcs_dpi_ip_params_st *loaded_ip = &dcn3_0_ip; 1717 1718 DC_LOGGER_INIT(dc->ctx->logger); 1719 1720 if (!bb && !is_soc_bounding_box_valid(dc)) { 1721 DC_LOG_ERROR("%s: not valid soc bounding box/n", __func__); 1722 return false; 1723 } 1724 1725 if (bb && !is_soc_bounding_box_valid(dc)) { 1726 int i; 1727 1728 dcn3_0_soc.sr_exit_time_us = 1729 fixed16_to_double_to_cpu(bb->sr_exit_time_us); 1730 dcn3_0_soc.sr_enter_plus_exit_time_us = 1731 fixed16_to_double_to_cpu(bb->sr_enter_plus_exit_time_us); 1732 dcn3_0_soc.urgent_latency_us = 1733 fixed16_to_double_to_cpu(bb->urgent_latency_us); 1734 dcn3_0_soc.urgent_latency_pixel_data_only_us = 1735 fixed16_to_double_to_cpu(bb->urgent_latency_pixel_data_only_us); 1736 dcn3_0_soc.urgent_latency_pixel_mixed_with_vm_data_us = 1737 fixed16_to_double_to_cpu(bb->urgent_latency_pixel_mixed_with_vm_data_us); 1738 dcn3_0_soc.urgent_latency_vm_data_only_us = 1739 fixed16_to_double_to_cpu(bb->urgent_latency_vm_data_only_us); 1740 dcn3_0_soc.urgent_out_of_order_return_per_channel_pixel_only_bytes = 1741 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_pixel_only_bytes); 1742 dcn3_0_soc.urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 1743 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_pixel_and_vm_bytes); 1744 dcn3_0_soc.urgent_out_of_order_return_per_channel_vm_only_bytes = 1745 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_vm_only_bytes); 1746 dcn3_0_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 1747 fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_pixel_only); 1748 dcn3_0_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 1749 fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm); 1750 dcn3_0_soc.pct_ideal_dram_sdp_bw_after_urgent_vm_only = 1751 fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_vm_only); 1752 dcn3_0_soc.max_avg_sdp_bw_use_normal_percent = 1753 fixed16_to_double_to_cpu(bb->max_avg_sdp_bw_use_normal_percent); 1754 dcn3_0_soc.max_avg_dram_bw_use_normal_percent = 1755 fixed16_to_double_to_cpu(bb->max_avg_dram_bw_use_normal_percent); 1756 dcn3_0_soc.writeback_latency_us = 1757 fixed16_to_double_to_cpu(bb->writeback_latency_us); 1758 dcn3_0_soc.ideal_dram_bw_after_urgent_percent = 1759 fixed16_to_double_to_cpu(bb->ideal_dram_bw_after_urgent_percent); 1760 dcn3_0_soc.max_request_size_bytes = 1761 le32_to_cpu(bb->max_request_size_bytes); 1762 dcn3_0_soc.dram_channel_width_bytes = 1763 le32_to_cpu(bb->dram_channel_width_bytes); 1764 dcn3_0_soc.fabric_datapath_to_dcn_data_return_bytes = 1765 le32_to_cpu(bb->fabric_datapath_to_dcn_data_return_bytes); 1766 dcn3_0_soc.dcn_downspread_percent = 1767 fixed16_to_double_to_cpu(bb->dcn_downspread_percent); 1768 dcn3_0_soc.downspread_percent = 1769 fixed16_to_double_to_cpu(bb->downspread_percent); 1770 dcn3_0_soc.dram_page_open_time_ns = 1771 fixed16_to_double_to_cpu(bb->dram_page_open_time_ns); 1772 dcn3_0_soc.dram_rw_turnaround_time_ns = 1773 fixed16_to_double_to_cpu(bb->dram_rw_turnaround_time_ns); 1774 dcn3_0_soc.dram_return_buffer_per_channel_bytes = 1775 le32_to_cpu(bb->dram_return_buffer_per_channel_bytes); 1776 dcn3_0_soc.round_trip_ping_latency_dcfclk_cycles = 1777 le32_to_cpu(bb->round_trip_ping_latency_dcfclk_cycles); 1778 dcn3_0_soc.urgent_out_of_order_return_per_channel_bytes = 1779 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_bytes); 1780 dcn3_0_soc.channel_interleave_bytes = 1781 le32_to_cpu(bb->channel_interleave_bytes); 1782 dcn3_0_soc.num_banks = 1783 le32_to_cpu(bb->num_banks); 1784 dcn3_0_soc.num_chans = 1785 le32_to_cpu(bb->num_chans); 1786 dcn3_0_soc.gpuvm_min_page_size_bytes = 1787 le32_to_cpu(bb->vmm_page_size_bytes); 1788 dcn3_0_soc.dram_clock_change_latency_us = 1789 fixed16_to_double_to_cpu(bb->dram_clock_change_latency_us); 1790 dcn3_0_soc.writeback_dram_clock_change_latency_us = 1791 fixed16_to_double_to_cpu(bb->writeback_dram_clock_change_latency_us); 1792 dcn3_0_soc.return_bus_width_bytes = 1793 le32_to_cpu(bb->return_bus_width_bytes); 1794 dcn3_0_soc.dispclk_dppclk_vco_speed_mhz = 1795 le32_to_cpu(bb->dispclk_dppclk_vco_speed_mhz); 1796 dcn3_0_soc.xfc_bus_transport_time_us = 1797 le32_to_cpu(bb->xfc_bus_transport_time_us); 1798 dcn3_0_soc.xfc_xbuf_latency_tolerance_us = 1799 le32_to_cpu(bb->xfc_xbuf_latency_tolerance_us); 1800 dcn3_0_soc.use_urgent_burst_bw = 1801 le32_to_cpu(bb->use_urgent_burst_bw); 1802 dcn3_0_soc.num_states = 1803 le32_to_cpu(bb->num_states); 1804 1805 for (i = 0; i < dcn3_0_soc.num_states; i++) { 1806 dcn3_0_soc.clock_limits[i].state = 1807 le32_to_cpu(bb->clock_limits[i].state); 1808 dcn3_0_soc.clock_limits[i].dcfclk_mhz = 1809 fixed16_to_double_to_cpu(bb->clock_limits[i].dcfclk_mhz); 1810 dcn3_0_soc.clock_limits[i].fabricclk_mhz = 1811 fixed16_to_double_to_cpu(bb->clock_limits[i].fabricclk_mhz); 1812 dcn3_0_soc.clock_limits[i].dispclk_mhz = 1813 fixed16_to_double_to_cpu(bb->clock_limits[i].dispclk_mhz); 1814 dcn3_0_soc.clock_limits[i].dppclk_mhz = 1815 fixed16_to_double_to_cpu(bb->clock_limits[i].dppclk_mhz); 1816 dcn3_0_soc.clock_limits[i].phyclk_mhz = 1817 fixed16_to_double_to_cpu(bb->clock_limits[i].phyclk_mhz); 1818 dcn3_0_soc.clock_limits[i].socclk_mhz = 1819 fixed16_to_double_to_cpu(bb->clock_limits[i].socclk_mhz); 1820 dcn3_0_soc.clock_limits[i].dscclk_mhz = 1821 fixed16_to_double_to_cpu(bb->clock_limits[i].dscclk_mhz); 1822 dcn3_0_soc.clock_limits[i].dram_speed_mts = 1823 fixed16_to_double_to_cpu(bb->clock_limits[i].dram_speed_mts); 1824 } 1825 } 1826 1827 loaded_ip->max_num_otg = pool->base.res_cap->num_timing_generator; 1828 loaded_ip->max_num_dpp = pool->base.pipe_count; 1829 loaded_ip->clamp_min_dcfclk = dc->config.clamp_min_dcfclk; 1830 dcn20_patch_bounding_box(dc, loaded_bb); 1831 1832 if (!bb && dc->ctx->dc_bios->funcs->get_soc_bb_info) { 1833 struct bp_soc_bb_info bb_info = {0}; 1834 1835 if (dc->ctx->dc_bios->funcs->get_soc_bb_info(dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) { 1836 if (bb_info.dram_clock_change_latency_100ns > 0) 1837 dcn3_0_soc.dram_clock_change_latency_us = bb_info.dram_clock_change_latency_100ns * 10; 1838 1839 if (bb_info.dram_sr_enter_exit_latency_100ns > 0) 1840 dcn3_0_soc.sr_enter_plus_exit_time_us = bb_info.dram_sr_enter_exit_latency_100ns * 10; 1841 1842 if (bb_info.dram_sr_exit_latency_100ns > 0) 1843 dcn3_0_soc.sr_exit_time_us = bb_info.dram_sr_exit_latency_100ns * 10; 1844 } 1845 } 1846 1847 return true; 1848 } 1849 1850 static bool dcn30_split_stream_for_mpc_or_odm( 1851 const struct dc *dc, 1852 struct resource_context *res_ctx, 1853 struct pipe_ctx *pri_pipe, 1854 struct pipe_ctx *sec_pipe, 1855 bool odm) 1856 { 1857 int pipe_idx = sec_pipe->pipe_idx; 1858 const struct resource_pool *pool = dc->res_pool; 1859 1860 *sec_pipe = *pri_pipe; 1861 1862 sec_pipe->pipe_idx = pipe_idx; 1863 sec_pipe->plane_res.mi = pool->mis[pipe_idx]; 1864 sec_pipe->plane_res.hubp = pool->hubps[pipe_idx]; 1865 sec_pipe->plane_res.ipp = pool->ipps[pipe_idx]; 1866 sec_pipe->plane_res.xfm = pool->transforms[pipe_idx]; 1867 sec_pipe->plane_res.dpp = pool->dpps[pipe_idx]; 1868 sec_pipe->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst; 1869 sec_pipe->stream_res.dsc = NULL; 1870 if (odm) { 1871 if (pri_pipe->next_odm_pipe) { 1872 ASSERT(pri_pipe->next_odm_pipe != sec_pipe); 1873 sec_pipe->next_odm_pipe = pri_pipe->next_odm_pipe; 1874 sec_pipe->next_odm_pipe->prev_odm_pipe = sec_pipe; 1875 } 1876 pri_pipe->next_odm_pipe = sec_pipe; 1877 sec_pipe->prev_odm_pipe = pri_pipe; 1878 ASSERT(sec_pipe->top_pipe == NULL); 1879 1880 sec_pipe->stream_res.opp = pool->opps[pipe_idx]; 1881 if (sec_pipe->stream->timing.flags.DSC == 1) { 1882 dcn20_acquire_dsc(dc, res_ctx, &sec_pipe->stream_res.dsc, pipe_idx); 1883 ASSERT(sec_pipe->stream_res.dsc); 1884 if (sec_pipe->stream_res.dsc == NULL) 1885 return false; 1886 } 1887 } else { 1888 if (pri_pipe->bottom_pipe) { 1889 ASSERT(pri_pipe->bottom_pipe != sec_pipe); 1890 sec_pipe->bottom_pipe = pri_pipe->bottom_pipe; 1891 sec_pipe->bottom_pipe->top_pipe = sec_pipe; 1892 } 1893 pri_pipe->bottom_pipe = sec_pipe; 1894 sec_pipe->top_pipe = pri_pipe; 1895 1896 ASSERT(pri_pipe->plane_state); 1897 } 1898 1899 return true; 1900 } 1901 1902 static bool dcn30_internal_validate_bw( 1903 struct dc *dc, 1904 struct dc_state *context, 1905 display_e2e_pipe_params_st *pipes, 1906 int *pipe_cnt_out, 1907 int *vlevel_out, 1908 bool fast_validate) 1909 { 1910 bool out = false; 1911 bool repopulate_pipes = false; 1912 int split[MAX_PIPES] = { 0 }; 1913 bool merge[MAX_PIPES] = { false }; 1914 bool newly_split[MAX_PIPES] = { false }; 1915 int pipe_cnt, i, pipe_idx, vlevel; 1916 struct vba_vars_st *vba = &context->bw_ctx.dml.vba; 1917 1918 ASSERT(pipes); 1919 if (!pipes) 1920 return false; 1921 1922 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes); 1923 1924 if (!pipe_cnt) { 1925 out = true; 1926 goto validate_out; 1927 } 1928 1929 dml_log_pipe_params(&context->bw_ctx.dml, pipes, pipe_cnt); 1930 1931 if (!fast_validate) { 1932 /* 1933 * DML favors voltage over p-state, but we're more interested in 1934 * supporting p-state over voltage. We can't support p-state in 1935 * prefetch mode > 0 so try capping the prefetch mode to start. 1936 */ 1937 context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank = 1938 dm_allow_self_refresh_and_mclk_switch; 1939 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); 1940 /* This may adjust vlevel and maxMpcComb */ 1941 if (vlevel < context->bw_ctx.dml.soc.num_states) 1942 vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge); 1943 } 1944 if (fast_validate || vlevel == context->bw_ctx.dml.soc.num_states || 1945 vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported) { 1946 /* 1947 * If mode is unsupported or there's still no p-state support then 1948 * fall back to favoring voltage. 1949 * 1950 * We don't actually support prefetch mode 2, so require that we 1951 * at least support prefetch mode 1. 1952 */ 1953 context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank = 1954 dm_allow_self_refresh; 1955 1956 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); 1957 if (vlevel < context->bw_ctx.dml.soc.num_states) { 1958 memset(split, 0, sizeof(split)); 1959 memset(merge, 0, sizeof(merge)); 1960 vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge); 1961 } 1962 } 1963 1964 dml_log_mode_support_params(&context->bw_ctx.dml); 1965 1966 /* TODO: Need to check calculated vlevel why that fails validation of below resolutions */ 1967 if (context->res_ctx.pipe_ctx[0].stream != NULL) { 1968 if (context->res_ctx.pipe_ctx[0].stream->timing.h_addressable == 640 && context->res_ctx.pipe_ctx[0].stream->timing.v_addressable == 480) 1969 vlevel = 0; 1970 if (context->res_ctx.pipe_ctx[0].stream->timing.h_addressable == 1280 && context->res_ctx.pipe_ctx[0].stream->timing.v_addressable == 800) 1971 vlevel = 0; 1972 if (context->res_ctx.pipe_ctx[0].stream->timing.h_addressable == 1280 && context->res_ctx.pipe_ctx[0].stream->timing.v_addressable == 768) 1973 vlevel = 0; 1974 if (context->res_ctx.pipe_ctx[0].stream->timing.h_addressable == 1280 && context->res_ctx.pipe_ctx[0].stream->timing.v_addressable == 1024) 1975 vlevel = 0; 1976 if (context->res_ctx.pipe_ctx[0].stream->timing.h_addressable == 2048 && context->res_ctx.pipe_ctx[0].stream->timing.v_addressable == 1536) 1977 vlevel = 0; 1978 } 1979 1980 if (vlevel == context->bw_ctx.dml.soc.num_states) 1981 goto validate_fail; 1982 1983 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 1984 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1985 struct pipe_ctx *mpo_pipe = pipe->bottom_pipe; 1986 1987 if (!pipe->stream) 1988 continue; 1989 1990 /* We only support full screen mpo with ODM */ 1991 if (vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled 1992 && pipe->plane_state && mpo_pipe 1993 && memcmp(&mpo_pipe->plane_res.scl_data.recout, 1994 &pipe->plane_res.scl_data.recout, 1995 sizeof(struct rect)) != 0) { 1996 ASSERT(mpo_pipe->plane_state != pipe->plane_state); 1997 goto validate_fail; 1998 } 1999 pipe_idx++; 2000 } 2001 2002 /* merge pipes if necessary */ 2003 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2004 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 2005 2006 /*skip pipes that don't need merging*/ 2007 if (!merge[i]) 2008 continue; 2009 2010 /* if ODM merge we ignore mpc tree, mpo pipes will have their own flags */ 2011 if (pipe->prev_odm_pipe) { 2012 /*split off odm pipe*/ 2013 pipe->prev_odm_pipe->next_odm_pipe = pipe->next_odm_pipe; 2014 if (pipe->next_odm_pipe) 2015 pipe->next_odm_pipe->prev_odm_pipe = pipe->prev_odm_pipe; 2016 2017 pipe->bottom_pipe = NULL; 2018 pipe->next_odm_pipe = NULL; 2019 pipe->plane_state = NULL; 2020 pipe->stream = NULL; 2021 pipe->top_pipe = NULL; 2022 pipe->prev_odm_pipe = NULL; 2023 if (pipe->stream_res.dsc) 2024 dcn20_release_dsc(&context->res_ctx, dc->res_pool, &pipe->stream_res.dsc); 2025 memset(&pipe->plane_res, 0, sizeof(pipe->plane_res)); 2026 memset(&pipe->stream_res, 0, sizeof(pipe->stream_res)); 2027 } else if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) { 2028 struct pipe_ctx *top_pipe = pipe->top_pipe; 2029 struct pipe_ctx *bottom_pipe = pipe->bottom_pipe; 2030 2031 top_pipe->bottom_pipe = bottom_pipe; 2032 if (bottom_pipe) 2033 bottom_pipe->top_pipe = top_pipe; 2034 2035 pipe->top_pipe = NULL; 2036 pipe->bottom_pipe = NULL; 2037 pipe->plane_state = NULL; 2038 pipe->stream = NULL; 2039 memset(&pipe->plane_res, 0, sizeof(pipe->plane_res)); 2040 memset(&pipe->stream_res, 0, sizeof(pipe->stream_res)); 2041 } else 2042 ASSERT(0); /* Should never try to merge master pipe */ 2043 2044 } 2045 2046 for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) { 2047 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 2048 struct pipe_ctx *hsplit_pipe = NULL; 2049 bool odm; 2050 2051 if (!pipe->stream || newly_split[i]) 2052 continue; 2053 2054 pipe_idx++; 2055 odm = vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled; 2056 2057 if (!pipe->plane_state && !odm) 2058 continue; 2059 2060 if (split[i]) { 2061 hsplit_pipe = find_idle_secondary_pipe(&context->res_ctx, dc->res_pool, pipe); 2062 ASSERT(hsplit_pipe); 2063 if (!hsplit_pipe) 2064 goto validate_fail; 2065 2066 if (!dcn30_split_stream_for_mpc_or_odm( 2067 dc, &context->res_ctx, 2068 pipe, hsplit_pipe, odm)) 2069 goto validate_fail; 2070 2071 newly_split[hsplit_pipe->pipe_idx] = true; 2072 repopulate_pipes = true; 2073 } 2074 if (split[i] == 4) { 2075 struct pipe_ctx *pipe_4to1 = find_idle_secondary_pipe(&context->res_ctx, dc->res_pool, pipe); 2076 2077 ASSERT(pipe_4to1); 2078 if (!pipe_4to1) 2079 goto validate_fail; 2080 if (!dcn30_split_stream_for_mpc_or_odm( 2081 dc, &context->res_ctx, 2082 pipe, pipe_4to1, odm)) 2083 goto validate_fail; 2084 newly_split[pipe_4to1->pipe_idx] = true; 2085 2086 pipe_4to1 = find_idle_secondary_pipe(&context->res_ctx, dc->res_pool, pipe); 2087 ASSERT(pipe_4to1); 2088 if (!pipe_4to1) 2089 goto validate_fail; 2090 if (!dcn30_split_stream_for_mpc_or_odm( 2091 dc, &context->res_ctx, 2092 hsplit_pipe, pipe_4to1, odm)) 2093 goto validate_fail; 2094 newly_split[pipe_4to1->pipe_idx] = true; 2095 } 2096 if (odm) 2097 dcn20_build_mapped_resource(dc, context, pipe->stream); 2098 } 2099 2100 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2101 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 2102 2103 if (pipe->plane_state) { 2104 if (!resource_build_scaling_params(pipe)) 2105 goto validate_fail; 2106 } 2107 } 2108 2109 /* Actual dsc count per stream dsc validation*/ 2110 if (!dcn20_validate_dsc(dc, context)) { 2111 vba->ValidationStatus[vba->soc.num_states] = DML_FAIL_DSC_VALIDATION_FAILURE; 2112 goto validate_fail; 2113 } 2114 2115 if (repopulate_pipes) 2116 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes); 2117 *vlevel_out = vlevel; 2118 *pipe_cnt_out = pipe_cnt; 2119 2120 out = true; 2121 goto validate_out; 2122 2123 validate_fail: 2124 out = false; 2125 2126 validate_out: 2127 return out; 2128 } 2129 2130 static void dcn30_calculate_wm( 2131 struct dc *dc, struct dc_state *context, 2132 display_e2e_pipe_params_st *pipes, 2133 int pipe_cnt, 2134 int vlevel) 2135 { 2136 int i, pipe_idx; 2137 double dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; 2138 2139 if (context->bw_ctx.dml.soc.min_dcfclk > dcfclk) 2140 dcfclk = context->bw_ctx.dml.soc.min_dcfclk; 2141 2142 pipes[0].clks_cfg.voltage = vlevel; 2143 pipes[0].clks_cfg.dcfclk_mhz = dcfclk; 2144 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz; 2145 2146 /* Set B: 2147 * DCFCLK: 1GHz or min required above 1GHz 2148 * FCLK/UCLK: Max 2149 */ 2150 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].valid) { 2151 if (vlevel == 0) { 2152 pipes[0].clks_cfg.voltage = 1; 2153 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dcfclk_mhz; 2154 } 2155 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.pstate_latency_us; 2156 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_enter_plus_exit_time_us; 2157 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_exit_time_us; 2158 } 2159 context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2160 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2161 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2162 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2163 context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2164 context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2165 context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2166 context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2167 2168 pipes[0].clks_cfg.voltage = vlevel; 2169 pipes[0].clks_cfg.dcfclk_mhz = dcfclk; 2170 2171 /* Set C: 2172 * DCFCLK: Min Required 2173 * FCLK(proportional to UCLK): 1GHz or Max 2174 * pstate latency overriden to 5us 2175 */ 2176 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid) { 2177 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.pstate_latency_us; 2178 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_exit_time_us; 2179 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us; 2180 } 2181 context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2182 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2183 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2184 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2185 context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2186 context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2187 context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2188 context->bw_ctx.bw.dcn.watermarks.c.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2189 2190 /* Set D: 2191 * DCFCLK: Min Required 2192 * FCLK(proportional to UCLK): 1GHz or Max 2193 * sr_enter_exit = 4, sr_exit = 2us 2194 */ 2195 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].valid) { 2196 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.pstate_latency_us; 2197 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_enter_plus_exit_time_us; 2198 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_exit_time_us; 2199 } 2200 context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2201 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2202 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2203 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2204 context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2205 context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2206 context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2207 context->bw_ctx.bw.dcn.watermarks.d.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2208 2209 /* Set A: 2210 * DCFCLK: Min Required 2211 * FCLK(proportional to UCLK): 1GHz or Max 2212 * 2213 * Set A calculated last so that following calculations are based on Set A 2214 */ 2215 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].valid) { 2216 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us; 2217 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us; 2218 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us; 2219 } 2220 context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2221 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2222 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2223 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2224 context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2225 context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2226 context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2227 context->bw_ctx.bw.dcn.watermarks.a.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; 2228 2229 context->perf_params.stutter_period_us = 2230 context->bw_ctx.dml.vba.StutterPeriod; 2231 2232 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 2233 if (!context->res_ctx.pipe_ctx[i].stream) 2234 continue; 2235 2236 pipes[pipe_idx].clks_cfg.dispclk_mhz = get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt); 2237 pipes[pipe_idx].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); 2238 2239 if (dc->config.forced_clocks) { 2240 pipes[pipe_idx].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz; 2241 pipes[pipe_idx].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz; 2242 } 2243 if (dc->debug.min_disp_clk_khz > pipes[pipe_idx].clks_cfg.dispclk_mhz * 1000) 2244 pipes[pipe_idx].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0; 2245 if (dc->debug.min_dpp_clk_khz > pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000) 2246 pipes[pipe_idx].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0; 2247 2248 pipe_idx++; 2249 } 2250 } 2251 2252 bool dcn30_validate_bandwidth(struct dc *dc, 2253 struct dc_state *context, 2254 bool fast_validate) 2255 { 2256 bool out = false; 2257 2258 BW_VAL_TRACE_SETUP(); 2259 2260 int vlevel = 0; 2261 int pipe_cnt = 0; 2262 display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL); 2263 DC_LOGGER_INIT(dc->ctx->logger); 2264 2265 BW_VAL_TRACE_COUNT(); 2266 2267 out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate); 2268 2269 if (pipe_cnt == 0) 2270 goto validate_out; 2271 2272 if (!out) 2273 goto validate_fail; 2274 2275 BW_VAL_TRACE_END_VOLTAGE_LEVEL(); 2276 2277 if (fast_validate) { 2278 BW_VAL_TRACE_SKIP(fast); 2279 goto validate_out; 2280 } 2281 2282 dcn30_calculate_wm(dc, context, pipes, pipe_cnt, vlevel); 2283 dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel); 2284 2285 BW_VAL_TRACE_END_WATERMARKS(); 2286 2287 goto validate_out; 2288 2289 validate_fail: 2290 DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n", 2291 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states])); 2292 2293 BW_VAL_TRACE_SKIP(fail); 2294 out = false; 2295 2296 validate_out: 2297 kfree(pipes); 2298 2299 BW_VAL_TRACE_FINISH(); 2300 2301 return out; 2302 } 2303 2304 static void get_optimal_dcfclk_fclk_for_uclk(unsigned int uclk_mts, 2305 unsigned int *optimal_dcfclk, 2306 unsigned int *optimal_fclk) 2307 { 2308 double bw_from_dram, bw_from_dram1, bw_from_dram2; 2309 2310 bw_from_dram1 = uclk_mts * dcn3_0_soc.num_chans * 2311 dcn3_0_soc.dram_channel_width_bytes * (dcn3_0_soc.max_avg_dram_bw_use_normal_percent / 100); 2312 bw_from_dram2 = uclk_mts * dcn3_0_soc.num_chans * 2313 dcn3_0_soc.dram_channel_width_bytes * (dcn3_0_soc.max_avg_sdp_bw_use_normal_percent / 100); 2314 2315 bw_from_dram = (bw_from_dram1 < bw_from_dram2) ? bw_from_dram1 : bw_from_dram2; 2316 2317 if (optimal_fclk) 2318 *optimal_fclk = bw_from_dram / 2319 (dcn3_0_soc.fabric_datapath_to_dcn_data_return_bytes * (dcn3_0_soc.max_avg_sdp_bw_use_normal_percent / 100)); 2320 2321 if (optimal_dcfclk) 2322 *optimal_dcfclk = bw_from_dram / 2323 (dcn3_0_soc.return_bus_width_bytes * (dcn3_0_soc.max_avg_sdp_bw_use_normal_percent / 100)); 2324 } 2325 2326 void dcn30_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) 2327 { 2328 unsigned int i, j; 2329 unsigned int num_states = 0; 2330 2331 unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0}; 2332 unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0}; 2333 unsigned int optimal_uclk_for_dcfclk_sta_targets[DC__VOLTAGE_STATES] = {0}; 2334 unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0}; 2335 2336 unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {694, 875, 1000, 1200}; 2337 unsigned int num_dcfclk_sta_targets = 4; 2338 unsigned int num_uclk_states; 2339 2340 if (dc->ctx->dc_bios->vram_info.num_chans) 2341 dcn3_0_soc.num_chans = dc->ctx->dc_bios->vram_info.num_chans; 2342 2343 if (dc->ctx->dc_bios->vram_info.dram_channel_width_bytes) 2344 dcn3_0_soc.dram_channel_width_bytes = dc->ctx->dc_bios->vram_info.dram_channel_width_bytes; 2345 2346 dcn3_0_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0; 2347 dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0; 2348 2349 if (bw_params->clk_table.entries[0].memclk_mhz) { 2350 2351 if (bw_params->clk_table.entries[1].dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { 2352 // If max DCFCLK is greater than the max DCFCLK STA target, insert into the DCFCLK STA target array 2353 dcfclk_sta_targets[num_dcfclk_sta_targets] = bw_params->clk_table.entries[1].dcfclk_mhz; 2354 num_dcfclk_sta_targets++; 2355 } else if (bw_params->clk_table.entries[1].dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { 2356 // If max DCFCLK is less than the max DCFCLK STA target, cap values and remove duplicates 2357 for (i = 0; i < num_dcfclk_sta_targets; i++) { 2358 if (dcfclk_sta_targets[i] > bw_params->clk_table.entries[1].dcfclk_mhz) { 2359 dcfclk_sta_targets[i] = bw_params->clk_table.entries[1].dcfclk_mhz; 2360 break; 2361 } 2362 } 2363 // Update size of array since we "removed" duplicates 2364 num_dcfclk_sta_targets = i + 1; 2365 } 2366 2367 num_uclk_states = bw_params->clk_table.num_entries; 2368 2369 // Calculate optimal dcfclk for each uclk 2370 for (i = 0; i < num_uclk_states; i++) { 2371 get_optimal_dcfclk_fclk_for_uclk(bw_params->clk_table.entries[i].memclk_mhz * 16, 2372 &optimal_dcfclk_for_uclk[i], NULL); 2373 if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz) { 2374 optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz; 2375 } 2376 } 2377 2378 // Calculate optimal uclk for each dcfclk sta target 2379 for (i = 0; i < num_dcfclk_sta_targets; i++) { 2380 for (j = 0; j < num_uclk_states; j++) { 2381 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) { 2382 optimal_uclk_for_dcfclk_sta_targets[i] = 2383 bw_params->clk_table.entries[j].memclk_mhz * 16; 2384 break; 2385 } 2386 } 2387 } 2388 2389 i = 0; 2390 j = 0; 2391 // create the final dcfclk and uclk table 2392 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { 2393 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) { 2394 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; 2395 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; 2396 } else { 2397 if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= bw_params->clk_table.entries[1].dcfclk_mhz) { 2398 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; 2399 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16; 2400 } else { 2401 j = num_uclk_states; 2402 } 2403 } 2404 } 2405 2406 while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) { 2407 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; 2408 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; 2409 } 2410 2411 while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES && 2412 optimal_dcfclk_for_uclk[j] <= bw_params->clk_table.entries[1].dcfclk_mhz) { 2413 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; 2414 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16; 2415 } 2416 2417 for (i = 0; i < dcn3_0_soc.num_states; i++) { 2418 dcn3_0_soc.clock_limits[i].state = i; 2419 dcn3_0_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i]; 2420 dcn3_0_soc.clock_limits[i].fabricclk_mhz = dcfclk_mhz[i]; 2421 dcn3_0_soc.clock_limits[i].dram_speed_mts = dram_speed_mts[i]; 2422 2423 /* Fill all states with max values of all other clocks */ 2424 dcn3_0_soc.clock_limits[i].dispclk_mhz = bw_params->clk_table.entries[1].dispclk_mhz; 2425 dcn3_0_soc.clock_limits[i].dppclk_mhz = bw_params->clk_table.entries[1].dppclk_mhz; 2426 dcn3_0_soc.clock_limits[i].phyclk_mhz = bw_params->clk_table.entries[1].phyclk_mhz; 2427 dcn3_0_soc.clock_limits[i].dtbclk_mhz = dcn3_0_soc.clock_limits[0].dtbclk_mhz; 2428 /* These clocks cannot come from bw_params, always fill from dcn3_0_soc[1] */ 2429 /* FCLK, PHYCLK_D18, SOCCLK, DSCCLK */ 2430 dcn3_0_soc.clock_limits[i].phyclk_d18_mhz = dcn3_0_soc.clock_limits[0].phyclk_d18_mhz; 2431 dcn3_0_soc.clock_limits[i].socclk_mhz = dcn3_0_soc.clock_limits[0].socclk_mhz; 2432 dcn3_0_soc.clock_limits[i].dscclk_mhz = dcn3_0_soc.clock_limits[0].dscclk_mhz; 2433 } 2434 /* re-init DML with updated bb */ 2435 dml_init_instance(&dc->dml, &dcn3_0_soc, &dcn3_0_ip, DML_PROJECT_DCN30); 2436 if (dc->current_state) 2437 dml_init_instance(&dc->current_state->bw_ctx.dml, &dcn3_0_soc, &dcn3_0_ip, DML_PROJECT_DCN30); 2438 } 2439 2440 /* re-init DML with updated bb */ 2441 dml_init_instance(&dc->dml, &dcn3_0_soc, &dcn3_0_ip, DML_PROJECT_DCN30); 2442 if (dc->current_state) 2443 dml_init_instance(&dc->current_state->bw_ctx.dml, &dcn3_0_soc, &dcn3_0_ip, DML_PROJECT_DCN30); 2444 } 2445 2446 static const struct resource_funcs dcn30_res_pool_funcs = { 2447 .destroy = dcn30_destroy_resource_pool, 2448 .link_enc_create = dcn30_link_encoder_create, 2449 .panel_cntl_create = dcn30_panel_cntl_create, 2450 .validate_bandwidth = dcn30_validate_bandwidth, 2451 .populate_dml_pipes = dcn30_populate_dml_pipes_from_context, 2452 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer, 2453 .add_stream_to_ctx = dcn30_add_stream_to_ctx, 2454 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, 2455 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 2456 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, 2457 .set_mcif_arb_params = dcn30_set_mcif_arb_params, 2458 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, 2459 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut, 2460 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut, 2461 .update_bw_bounding_box = dcn30_update_bw_bounding_box, 2462 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, 2463 }; 2464 2465 static bool dcn30_resource_construct( 2466 uint8_t num_virtual_links, 2467 struct dc *dc, 2468 struct dcn30_resource_pool *pool) 2469 { 2470 int i; 2471 struct dc_context *ctx = dc->ctx; 2472 struct irq_service_init_data init_data; 2473 2474 ctx->dc_bios->regs = &bios_regs; 2475 2476 pool->base.res_cap = &res_cap_dcn3; 2477 2478 pool->base.funcs = &dcn30_res_pool_funcs; 2479 2480 /************************************************* 2481 * Resource + asic cap harcoding * 2482 *************************************************/ 2483 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 2484 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; 2485 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator; 2486 dc->caps.max_downscale_ratio = 600; 2487 dc->caps.i2c_speed_in_khz = 100; 2488 dc->caps.max_cursor_size = 256; 2489 dc->caps.dmdata_alloc_size = 2048; 2490 2491 dc->caps.max_slave_planes = 1; 2492 dc->caps.post_blend_color_processing = true; 2493 dc->caps.force_dp_tps4_for_cp2520 = true; 2494 dc->caps.extended_aux_timeout_support = true; 2495 dc->caps.dmcub_support = true; 2496 2497 /* Color pipeline capabilities */ 2498 dc->caps.color.dpp.dcn_arch = 1; 2499 dc->caps.color.dpp.input_lut_shared = 0; 2500 dc->caps.color.dpp.icsc = 1; 2501 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr 2502 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; 2503 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; 2504 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1; 2505 dc->caps.color.dpp.dgam_rom_caps.pq = 1; 2506 dc->caps.color.dpp.dgam_rom_caps.hlg = 1; 2507 dc->caps.color.dpp.post_csc = 1; 2508 dc->caps.color.dpp.gamma_corr = 1; 2509 2510 dc->caps.color.dpp.hw_3d_lut = 1; 2511 dc->caps.color.dpp.ogam_ram = 1; 2512 // no OGAM ROM on DCN3 2513 dc->caps.color.dpp.ogam_rom_caps.srgb = 0; 2514 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; 2515 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; 2516 dc->caps.color.dpp.ogam_rom_caps.pq = 0; 2517 dc->caps.color.dpp.ogam_rom_caps.hlg = 0; 2518 dc->caps.color.dpp.ocsc = 0; 2519 2520 dc->caps.color.mpc.gamut_remap = 1; 2521 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //3 2522 dc->caps.color.mpc.ogam_ram = 1; 2523 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; 2524 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; 2525 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; 2526 dc->caps.color.mpc.ogam_rom_caps.pq = 0; 2527 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 2528 dc->caps.color.mpc.ocsc = 1; 2529 2530 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 2531 dc->debug = debug_defaults_drv; 2532 else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) { 2533 dc->debug = debug_defaults_diags; 2534 } else 2535 dc->debug = debug_defaults_diags; 2536 // Init the vm_helper 2537 if (dc->vm_helper) 2538 vm_helper_init(dc->vm_helper, 16); 2539 2540 /************************************************* 2541 * Create resources * 2542 *************************************************/ 2543 2544 /* Clock Sources for Pixel Clock*/ 2545 pool->base.clock_sources[DCN30_CLK_SRC_PLL0] = 2546 dcn30_clock_source_create(ctx, ctx->dc_bios, 2547 CLOCK_SOURCE_COMBO_PHY_PLL0, 2548 &clk_src_regs[0], false); 2549 pool->base.clock_sources[DCN30_CLK_SRC_PLL1] = 2550 dcn30_clock_source_create(ctx, ctx->dc_bios, 2551 CLOCK_SOURCE_COMBO_PHY_PLL1, 2552 &clk_src_regs[1], false); 2553 pool->base.clock_sources[DCN30_CLK_SRC_PLL2] = 2554 dcn30_clock_source_create(ctx, ctx->dc_bios, 2555 CLOCK_SOURCE_COMBO_PHY_PLL2, 2556 &clk_src_regs[2], false); 2557 pool->base.clock_sources[DCN30_CLK_SRC_PLL3] = 2558 dcn30_clock_source_create(ctx, ctx->dc_bios, 2559 CLOCK_SOURCE_COMBO_PHY_PLL3, 2560 &clk_src_regs[3], false); 2561 pool->base.clock_sources[DCN30_CLK_SRC_PLL4] = 2562 dcn30_clock_source_create(ctx, ctx->dc_bios, 2563 CLOCK_SOURCE_COMBO_PHY_PLL4, 2564 &clk_src_regs[4], false); 2565 pool->base.clock_sources[DCN30_CLK_SRC_PLL5] = 2566 dcn30_clock_source_create(ctx, ctx->dc_bios, 2567 CLOCK_SOURCE_COMBO_PHY_PLL5, 2568 &clk_src_regs[5], false); 2569 2570 pool->base.clk_src_count = DCN30_CLK_SRC_TOTAL; 2571 2572 /* todo: not reuse phy_pll registers */ 2573 pool->base.dp_clock_source = 2574 dcn30_clock_source_create(ctx, ctx->dc_bios, 2575 CLOCK_SOURCE_ID_DP_DTO, 2576 &clk_src_regs[0], true); 2577 2578 for (i = 0; i < pool->base.clk_src_count; i++) { 2579 if (pool->base.clock_sources[i] == NULL) { 2580 dm_error("DC: failed to create clock sources!\n"); 2581 BREAK_TO_DEBUGGER(); 2582 goto create_fail; 2583 } 2584 } 2585 2586 /* DCCG */ 2587 pool->base.dccg = dccg30_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 2588 if (pool->base.dccg == NULL) { 2589 dm_error("DC: failed to create dccg!\n"); 2590 BREAK_TO_DEBUGGER(); 2591 goto create_fail; 2592 } 2593 2594 /* PP Lib and SMU interfaces */ 2595 init_soc_bounding_box(dc, pool); 2596 2597 dml_init_instance(&dc->dml, &dcn3_0_soc, &dcn3_0_ip, DML_PROJECT_DCN30); 2598 2599 /* IRQ */ 2600 init_data.ctx = dc->ctx; 2601 pool->base.irqs = dal_irq_service_dcn30_create(&init_data); 2602 if (!pool->base.irqs) 2603 goto create_fail; 2604 2605 /* HUBBUB */ 2606 pool->base.hubbub = dcn30_hubbub_create(ctx); 2607 if (pool->base.hubbub == NULL) { 2608 BREAK_TO_DEBUGGER(); 2609 dm_error("DC: failed to create hubbub!\n"); 2610 goto create_fail; 2611 } 2612 2613 /* HUBPs, DPPs, OPPs and TGs */ 2614 for (i = 0; i < pool->base.pipe_count; i++) { 2615 pool->base.hubps[i] = dcn30_hubp_create(ctx, i); 2616 if (pool->base.hubps[i] == NULL) { 2617 BREAK_TO_DEBUGGER(); 2618 dm_error( 2619 "DC: failed to create hubps!\n"); 2620 goto create_fail; 2621 } 2622 2623 pool->base.dpps[i] = dcn30_dpp_create(ctx, i); 2624 if (pool->base.dpps[i] == NULL) { 2625 BREAK_TO_DEBUGGER(); 2626 dm_error( 2627 "DC: failed to create dpps!\n"); 2628 goto create_fail; 2629 } 2630 } 2631 2632 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 2633 pool->base.opps[i] = dcn30_opp_create(ctx, i); 2634 if (pool->base.opps[i] == NULL) { 2635 BREAK_TO_DEBUGGER(); 2636 dm_error( 2637 "DC: failed to create output pixel processor!\n"); 2638 goto create_fail; 2639 } 2640 } 2641 2642 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 2643 pool->base.timing_generators[i] = dcn30_timing_generator_create( 2644 ctx, i); 2645 if (pool->base.timing_generators[i] == NULL) { 2646 BREAK_TO_DEBUGGER(); 2647 dm_error("DC: failed to create tg!\n"); 2648 goto create_fail; 2649 } 2650 } 2651 pool->base.timing_generator_count = i; 2652 /* PSR */ 2653 pool->base.psr = dmub_psr_create(ctx); 2654 2655 if (pool->base.psr == NULL) { 2656 dm_error("DC: failed to create PSR obj!\n"); 2657 BREAK_TO_DEBUGGER(); 2658 goto create_fail; 2659 } 2660 2661 /* ABM */ 2662 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 2663 pool->base.multiple_abms[i] = dmub_abm_create(ctx, 2664 &abm_regs[i], 2665 &abm_shift, 2666 &abm_mask); 2667 if (pool->base.multiple_abms[i] == NULL) { 2668 dm_error("DC: failed to create abm for pipe %d!\n", i); 2669 BREAK_TO_DEBUGGER(); 2670 goto create_fail; 2671 } 2672 } 2673 /* MPC and DSC */ 2674 pool->base.mpc = dcn30_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut); 2675 if (pool->base.mpc == NULL) { 2676 BREAK_TO_DEBUGGER(); 2677 dm_error("DC: failed to create mpc!\n"); 2678 goto create_fail; 2679 } 2680 2681 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 2682 pool->base.dscs[i] = dcn30_dsc_create(ctx, i); 2683 if (pool->base.dscs[i] == NULL) { 2684 BREAK_TO_DEBUGGER(); 2685 dm_error("DC: failed to create display stream compressor %d!\n", i); 2686 goto create_fail; 2687 } 2688 } 2689 2690 /* DWB and MMHUBBUB */ 2691 if (!dcn30_dwbc_create(ctx, &pool->base)) { 2692 BREAK_TO_DEBUGGER(); 2693 dm_error("DC: failed to create dwbc!\n"); 2694 goto create_fail; 2695 } 2696 2697 if (!dcn30_mmhubbub_create(ctx, &pool->base)) { 2698 BREAK_TO_DEBUGGER(); 2699 dm_error("DC: failed to create mcif_wb!\n"); 2700 goto create_fail; 2701 } 2702 2703 /* AUX and I2C */ 2704 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 2705 pool->base.engines[i] = dcn30_aux_engine_create(ctx, i); 2706 if (pool->base.engines[i] == NULL) { 2707 BREAK_TO_DEBUGGER(); 2708 dm_error( 2709 "DC:failed to create aux engine!!\n"); 2710 goto create_fail; 2711 } 2712 pool->base.hw_i2cs[i] = dcn30_i2c_hw_create(ctx, i); 2713 if (pool->base.hw_i2cs[i] == NULL) { 2714 BREAK_TO_DEBUGGER(); 2715 dm_error( 2716 "DC:failed to create hw i2c!!\n"); 2717 goto create_fail; 2718 } 2719 pool->base.sw_i2cs[i] = NULL; 2720 } 2721 2722 /* Audio, Stream Encoders including DIG and virtual, MPC 3D LUTs */ 2723 if (!resource_construct(num_virtual_links, dc, &pool->base, 2724 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? 2725 &res_create_funcs : &res_create_maximus_funcs))) 2726 goto create_fail; 2727 2728 /* HW Sequencer and Plane caps */ 2729 dcn30_hw_sequencer_construct(dc); 2730 2731 dc->caps.max_planes = pool->base.pipe_count; 2732 2733 for (i = 0; i < dc->caps.max_planes; ++i) 2734 dc->caps.planes[i] = plane_cap; 2735 2736 dc->cap_funcs = cap_funcs; 2737 2738 return true; 2739 2740 create_fail: 2741 2742 dcn30_resource_destruct(pool); 2743 2744 return false; 2745 } 2746 2747 struct resource_pool *dcn30_create_resource_pool( 2748 const struct dc_init_data *init_data, 2749 struct dc *dc) 2750 { 2751 struct dcn30_resource_pool *pool = 2752 kzalloc(sizeof(struct dcn30_resource_pool), GFP_KERNEL); 2753 2754 if (!pool) 2755 return NULL; 2756 2757 if (dcn30_resource_construct(init_data->num_virtual_links, dc, pool)) 2758 return &pool->base; 2759 2760 BREAK_TO_DEBUGGER(); 2761 kfree(pool); 2762 return NULL; 2763 } 2764