1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 27 #include "dm_services.h" 28 #include "dc.h" 29 30 #include "dcn30_init.h" 31 32 #include "resource.h" 33 #include "include/irq_service_interface.h" 34 #include "dcn20/dcn20_resource.h" 35 36 #include "dcn30_resource.h" 37 38 #include "dcn10/dcn10_ipp.h" 39 #include "dcn30/dcn30_hubbub.h" 40 #include "dcn30/dcn30_mpc.h" 41 #include "dcn30/dcn30_hubp.h" 42 #include "irq/dcn30/irq_service_dcn30.h" 43 #include "dcn30/dcn30_dpp.h" 44 #include "dcn30/dcn30_optc.h" 45 #include "dcn20/dcn20_hwseq.h" 46 #include "dcn30/dcn30_hwseq.h" 47 #include "dce110/dce110_hw_sequencer.h" 48 #include "dcn30/dcn30_opp.h" 49 #include "dcn20/dcn20_dsc.h" 50 #include "dcn30/dcn30_vpg.h" 51 #include "dcn30/dcn30_afmt.h" 52 #include "dcn30/dcn30_dio_stream_encoder.h" 53 #include "dcn30/dcn30_dio_link_encoder.h" 54 #include "dce/dce_clock_source.h" 55 #include "dce/dce_audio.h" 56 #include "dce/dce_hwseq.h" 57 #include "clk_mgr.h" 58 #include "virtual/virtual_stream_encoder.h" 59 #include "dce110/dce110_resource.h" 60 #include "dml/display_mode_vba.h" 61 #include "dcn30/dcn30_dccg.h" 62 #include "dcn10/dcn10_resource.h" 63 #include "dc_link_ddc.h" 64 #include "dce/dce_panel_cntl.h" 65 66 #include "dcn30/dcn30_dwb.h" 67 #include "dcn30/dcn30_mmhubbub.h" 68 69 #include "sienna_cichlid_ip_offset.h" 70 #include "dcn/dcn_3_0_0_offset.h" 71 #include "dcn/dcn_3_0_0_sh_mask.h" 72 73 #include "nbio/nbio_7_4_offset.h" 74 75 #include "dpcs/dpcs_3_0_0_offset.h" 76 #include "dpcs/dpcs_3_0_0_sh_mask.h" 77 78 #include "mmhub/mmhub_2_0_0_offset.h" 79 #include "mmhub/mmhub_2_0_0_sh_mask.h" 80 81 #include "reg_helper.h" 82 #include "dce/dmub_abm.h" 83 #include "dce/dmub_psr.h" 84 #include "dce/dce_aux.h" 85 #include "dce/dce_i2c.h" 86 87 #include "dml/dcn30/dcn30_fpu.h" 88 #include "dml/dcn30/display_mode_vba_30.h" 89 #include "vm_helper.h" 90 #include "dcn20/dcn20_vmid.h" 91 #include "amdgpu_socbb.h" 92 #include "dc_dmub_srv.h" 93 94 #define DC_LOGGER_INIT(logger) 95 96 enum dcn30_clk_src_array_id { 97 DCN30_CLK_SRC_PLL0, 98 DCN30_CLK_SRC_PLL1, 99 DCN30_CLK_SRC_PLL2, 100 DCN30_CLK_SRC_PLL3, 101 DCN30_CLK_SRC_PLL4, 102 DCN30_CLK_SRC_PLL5, 103 DCN30_CLK_SRC_TOTAL 104 }; 105 106 /* begin ********************* 107 * macros to expend register list macro defined in HW object header file 108 */ 109 110 /* DCN */ 111 /* TODO awful hack. fixup dcn20_dwb.h */ 112 #undef BASE_INNER 113 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg 114 115 #define BASE(seg) BASE_INNER(seg) 116 117 #define SR(reg_name)\ 118 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ 119 mm ## reg_name 120 121 #define SRI(reg_name, block, id)\ 122 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 123 mm ## block ## id ## _ ## reg_name 124 125 #define SRI2(reg_name, block, id)\ 126 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ 127 mm ## reg_name 128 129 #define SRIR(var_name, reg_name, block, id)\ 130 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 131 mm ## block ## id ## _ ## reg_name 132 133 #define SRII(reg_name, block, id)\ 134 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 135 mm ## block ## id ## _ ## reg_name 136 137 #define SRII_MPC_RMU(reg_name, block, id)\ 138 .RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 139 mm ## block ## id ## _ ## reg_name 140 141 #define SRII_DWB(reg_name, temp_name, block, id)\ 142 .reg_name[id] = BASE(mm ## block ## id ## _ ## temp_name ## _BASE_IDX) + \ 143 mm ## block ## id ## _ ## temp_name 144 145 #define DCCG_SRII(reg_name, block, id)\ 146 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 147 mm ## block ## id ## _ ## reg_name 148 149 #define VUPDATE_SRII(reg_name, block, id)\ 150 .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \ 151 mm ## reg_name ## _ ## block ## id 152 153 /* NBIO */ 154 #define NBIO_BASE_INNER(seg) \ 155 NBIO_BASE__INST0_SEG ## seg 156 157 #define NBIO_BASE(seg) \ 158 NBIO_BASE_INNER(seg) 159 160 #define NBIO_SR(reg_name)\ 161 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \ 162 mm ## reg_name 163 164 /* MMHUB */ 165 #define MMHUB_BASE_INNER(seg) \ 166 MMHUB_BASE__INST0_SEG ## seg 167 168 #define MMHUB_BASE(seg) \ 169 MMHUB_BASE_INNER(seg) 170 171 #define MMHUB_SR(reg_name)\ 172 .reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \ 173 mmMM ## reg_name 174 175 /* CLOCK */ 176 #define CLK_BASE_INNER(seg) \ 177 CLK_BASE__INST0_SEG ## seg 178 179 #define CLK_BASE(seg) \ 180 CLK_BASE_INNER(seg) 181 182 #define CLK_SRI(reg_name, block, inst)\ 183 .reg_name = CLK_BASE(mm ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \ 184 mm ## block ## _ ## inst ## _ ## reg_name 185 186 187 static const struct bios_registers bios_regs = { 188 NBIO_SR(BIOS_SCRATCH_3), 189 NBIO_SR(BIOS_SCRATCH_6) 190 }; 191 192 #define clk_src_regs(index, pllid)\ 193 [index] = {\ 194 CS_COMMON_REG_LIST_DCN2_0(index, pllid),\ 195 } 196 197 static const struct dce110_clk_src_regs clk_src_regs[] = { 198 clk_src_regs(0, A), 199 clk_src_regs(1, B), 200 clk_src_regs(2, C), 201 clk_src_regs(3, D), 202 clk_src_regs(4, E), 203 clk_src_regs(5, F) 204 }; 205 206 static const struct dce110_clk_src_shift cs_shift = { 207 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 208 }; 209 210 static const struct dce110_clk_src_mask cs_mask = { 211 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 212 }; 213 214 #define abm_regs(id)\ 215 [id] = {\ 216 ABM_DCN30_REG_LIST(id)\ 217 } 218 219 static const struct dce_abm_registers abm_regs[] = { 220 abm_regs(0), 221 abm_regs(1), 222 abm_regs(2), 223 abm_regs(3), 224 abm_regs(4), 225 abm_regs(5), 226 }; 227 228 static const struct dce_abm_shift abm_shift = { 229 ABM_MASK_SH_LIST_DCN30(__SHIFT) 230 }; 231 232 static const struct dce_abm_mask abm_mask = { 233 ABM_MASK_SH_LIST_DCN30(_MASK) 234 }; 235 236 237 238 #define audio_regs(id)\ 239 [id] = {\ 240 AUD_COMMON_REG_LIST(id)\ 241 } 242 243 static const struct dce_audio_registers audio_regs[] = { 244 audio_regs(0), 245 audio_regs(1), 246 audio_regs(2), 247 audio_regs(3), 248 audio_regs(4), 249 audio_regs(5), 250 audio_regs(6) 251 }; 252 253 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 254 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 255 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 256 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 257 258 static const struct dce_audio_shift audio_shift = { 259 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 260 }; 261 262 static const struct dce_audio_mask audio_mask = { 263 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 264 }; 265 266 #define vpg_regs(id)\ 267 [id] = {\ 268 VPG_DCN3_REG_LIST(id)\ 269 } 270 271 static const struct dcn30_vpg_registers vpg_regs[] = { 272 vpg_regs(0), 273 vpg_regs(1), 274 vpg_regs(2), 275 vpg_regs(3), 276 vpg_regs(4), 277 vpg_regs(5), 278 vpg_regs(6), 279 }; 280 281 static const struct dcn30_vpg_shift vpg_shift = { 282 DCN3_VPG_MASK_SH_LIST(__SHIFT) 283 }; 284 285 static const struct dcn30_vpg_mask vpg_mask = { 286 DCN3_VPG_MASK_SH_LIST(_MASK) 287 }; 288 289 #define afmt_regs(id)\ 290 [id] = {\ 291 AFMT_DCN3_REG_LIST(id)\ 292 } 293 294 static const struct dcn30_afmt_registers afmt_regs[] = { 295 afmt_regs(0), 296 afmt_regs(1), 297 afmt_regs(2), 298 afmt_regs(3), 299 afmt_regs(4), 300 afmt_regs(5), 301 afmt_regs(6), 302 }; 303 304 static const struct dcn30_afmt_shift afmt_shift = { 305 DCN3_AFMT_MASK_SH_LIST(__SHIFT) 306 }; 307 308 static const struct dcn30_afmt_mask afmt_mask = { 309 DCN3_AFMT_MASK_SH_LIST(_MASK) 310 }; 311 312 #define stream_enc_regs(id)\ 313 [id] = {\ 314 SE_DCN3_REG_LIST(id)\ 315 } 316 317 static const struct dcn10_stream_enc_registers stream_enc_regs[] = { 318 stream_enc_regs(0), 319 stream_enc_regs(1), 320 stream_enc_regs(2), 321 stream_enc_regs(3), 322 stream_enc_regs(4), 323 stream_enc_regs(5) 324 }; 325 326 static const struct dcn10_stream_encoder_shift se_shift = { 327 SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 328 }; 329 330 static const struct dcn10_stream_encoder_mask se_mask = { 331 SE_COMMON_MASK_SH_LIST_DCN30(_MASK) 332 }; 333 334 335 #define aux_regs(id)\ 336 [id] = {\ 337 DCN2_AUX_REG_LIST(id)\ 338 } 339 340 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { 341 aux_regs(0), 342 aux_regs(1), 343 aux_regs(2), 344 aux_regs(3), 345 aux_regs(4), 346 aux_regs(5) 347 }; 348 349 #define hpd_regs(id)\ 350 [id] = {\ 351 HPD_REG_LIST(id)\ 352 } 353 354 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { 355 hpd_regs(0), 356 hpd_regs(1), 357 hpd_regs(2), 358 hpd_regs(3), 359 hpd_regs(4), 360 hpd_regs(5) 361 }; 362 363 #define link_regs(id, phyid)\ 364 [id] = {\ 365 LE_DCN3_REG_LIST(id), \ 366 UNIPHY_DCN2_REG_LIST(phyid), \ 367 DPCS_DCN2_REG_LIST(id), \ 368 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \ 369 } 370 371 static const struct dce110_aux_registers_shift aux_shift = { 372 DCN_AUX_MASK_SH_LIST(__SHIFT) 373 }; 374 375 static const struct dce110_aux_registers_mask aux_mask = { 376 DCN_AUX_MASK_SH_LIST(_MASK) 377 }; 378 379 static const struct dcn10_link_enc_registers link_enc_regs[] = { 380 link_regs(0, A), 381 link_regs(1, B), 382 link_regs(2, C), 383 link_regs(3, D), 384 link_regs(4, E), 385 link_regs(5, F) 386 }; 387 388 static const struct dcn10_link_enc_shift le_shift = { 389 LINK_ENCODER_MASK_SH_LIST_DCN30(__SHIFT),\ 390 DPCS_DCN2_MASK_SH_LIST(__SHIFT) 391 }; 392 393 static const struct dcn10_link_enc_mask le_mask = { 394 LINK_ENCODER_MASK_SH_LIST_DCN30(_MASK),\ 395 DPCS_DCN2_MASK_SH_LIST(_MASK) 396 }; 397 398 399 static const struct dce_panel_cntl_registers panel_cntl_regs[] = { 400 { DCN_PANEL_CNTL_REG_LIST() } 401 }; 402 403 static const struct dce_panel_cntl_shift panel_cntl_shift = { 404 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT) 405 }; 406 407 static const struct dce_panel_cntl_mask panel_cntl_mask = { 408 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK) 409 }; 410 411 #define dpp_regs(id)\ 412 [id] = {\ 413 DPP_REG_LIST_DCN30(id),\ 414 } 415 416 static const struct dcn3_dpp_registers dpp_regs[] = { 417 dpp_regs(0), 418 dpp_regs(1), 419 dpp_regs(2), 420 dpp_regs(3), 421 dpp_regs(4), 422 dpp_regs(5), 423 }; 424 425 static const struct dcn3_dpp_shift tf_shift = { 426 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT) 427 }; 428 429 static const struct dcn3_dpp_mask tf_mask = { 430 DPP_REG_LIST_SH_MASK_DCN30(_MASK) 431 }; 432 433 #define opp_regs(id)\ 434 [id] = {\ 435 OPP_REG_LIST_DCN30(id),\ 436 } 437 438 static const struct dcn20_opp_registers opp_regs[] = { 439 opp_regs(0), 440 opp_regs(1), 441 opp_regs(2), 442 opp_regs(3), 443 opp_regs(4), 444 opp_regs(5) 445 }; 446 447 static const struct dcn20_opp_shift opp_shift = { 448 OPP_MASK_SH_LIST_DCN20(__SHIFT) 449 }; 450 451 static const struct dcn20_opp_mask opp_mask = { 452 OPP_MASK_SH_LIST_DCN20(_MASK) 453 }; 454 455 #define aux_engine_regs(id)\ 456 [id] = {\ 457 AUX_COMMON_REG_LIST0(id), \ 458 .AUXN_IMPCAL = 0, \ 459 .AUXP_IMPCAL = 0, \ 460 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \ 461 } 462 463 static const struct dce110_aux_registers aux_engine_regs[] = { 464 aux_engine_regs(0), 465 aux_engine_regs(1), 466 aux_engine_regs(2), 467 aux_engine_regs(3), 468 aux_engine_regs(4), 469 aux_engine_regs(5) 470 }; 471 472 #define dwbc_regs_dcn3(id)\ 473 [id] = {\ 474 DWBC_COMMON_REG_LIST_DCN30(id),\ 475 } 476 477 static const struct dcn30_dwbc_registers dwbc30_regs[] = { 478 dwbc_regs_dcn3(0), 479 }; 480 481 static const struct dcn30_dwbc_shift dwbc30_shift = { 482 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 483 }; 484 485 static const struct dcn30_dwbc_mask dwbc30_mask = { 486 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK) 487 }; 488 489 #define mcif_wb_regs_dcn3(id)\ 490 [id] = {\ 491 MCIF_WB_COMMON_REG_LIST_DCN30(id),\ 492 } 493 494 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = { 495 mcif_wb_regs_dcn3(0) 496 }; 497 498 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = { 499 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 500 }; 501 502 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { 503 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK) 504 }; 505 506 #define dsc_regsDCN20(id)\ 507 [id] = {\ 508 DSC_REG_LIST_DCN20(id)\ 509 } 510 511 static const struct dcn20_dsc_registers dsc_regs[] = { 512 dsc_regsDCN20(0), 513 dsc_regsDCN20(1), 514 dsc_regsDCN20(2), 515 dsc_regsDCN20(3), 516 dsc_regsDCN20(4), 517 dsc_regsDCN20(5) 518 }; 519 520 static const struct dcn20_dsc_shift dsc_shift = { 521 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) 522 }; 523 524 static const struct dcn20_dsc_mask dsc_mask = { 525 DSC_REG_LIST_SH_MASK_DCN20(_MASK) 526 }; 527 528 static const struct dcn30_mpc_registers mpc_regs = { 529 MPC_REG_LIST_DCN3_0(0), 530 MPC_REG_LIST_DCN3_0(1), 531 MPC_REG_LIST_DCN3_0(2), 532 MPC_REG_LIST_DCN3_0(3), 533 MPC_REG_LIST_DCN3_0(4), 534 MPC_REG_LIST_DCN3_0(5), 535 MPC_OUT_MUX_REG_LIST_DCN3_0(0), 536 MPC_OUT_MUX_REG_LIST_DCN3_0(1), 537 MPC_OUT_MUX_REG_LIST_DCN3_0(2), 538 MPC_OUT_MUX_REG_LIST_DCN3_0(3), 539 MPC_OUT_MUX_REG_LIST_DCN3_0(4), 540 MPC_OUT_MUX_REG_LIST_DCN3_0(5), 541 MPC_RMU_GLOBAL_REG_LIST_DCN3AG, 542 MPC_RMU_REG_LIST_DCN3AG(0), 543 MPC_RMU_REG_LIST_DCN3AG(1), 544 MPC_RMU_REG_LIST_DCN3AG(2), 545 MPC_DWB_MUX_REG_LIST_DCN3_0(0), 546 }; 547 548 static const struct dcn30_mpc_shift mpc_shift = { 549 MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 550 }; 551 552 static const struct dcn30_mpc_mask mpc_mask = { 553 MPC_COMMON_MASK_SH_LIST_DCN30(_MASK) 554 }; 555 556 #define optc_regs(id)\ 557 [id] = {OPTC_COMMON_REG_LIST_DCN3_0(id)} 558 559 560 static const struct dcn_optc_registers optc_regs[] = { 561 optc_regs(0), 562 optc_regs(1), 563 optc_regs(2), 564 optc_regs(3), 565 optc_regs(4), 566 optc_regs(5) 567 }; 568 569 static const struct dcn_optc_shift optc_shift = { 570 OPTC_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 571 }; 572 573 static const struct dcn_optc_mask optc_mask = { 574 OPTC_COMMON_MASK_SH_LIST_DCN30(_MASK) 575 }; 576 577 #define hubp_regs(id)\ 578 [id] = {\ 579 HUBP_REG_LIST_DCN30(id)\ 580 } 581 582 static const struct dcn_hubp2_registers hubp_regs[] = { 583 hubp_regs(0), 584 hubp_regs(1), 585 hubp_regs(2), 586 hubp_regs(3), 587 hubp_regs(4), 588 hubp_regs(5) 589 }; 590 591 static const struct dcn_hubp2_shift hubp_shift = { 592 HUBP_MASK_SH_LIST_DCN30(__SHIFT) 593 }; 594 595 static const struct dcn_hubp2_mask hubp_mask = { 596 HUBP_MASK_SH_LIST_DCN30(_MASK) 597 }; 598 599 static const struct dcn_hubbub_registers hubbub_reg = { 600 HUBBUB_REG_LIST_DCN30(0) 601 }; 602 603 static const struct dcn_hubbub_shift hubbub_shift = { 604 HUBBUB_MASK_SH_LIST_DCN30(__SHIFT) 605 }; 606 607 static const struct dcn_hubbub_mask hubbub_mask = { 608 HUBBUB_MASK_SH_LIST_DCN30(_MASK) 609 }; 610 611 static const struct dccg_registers dccg_regs = { 612 DCCG_REG_LIST_DCN30() 613 }; 614 615 static const struct dccg_shift dccg_shift = { 616 DCCG_MASK_SH_LIST_DCN3(__SHIFT) 617 }; 618 619 static const struct dccg_mask dccg_mask = { 620 DCCG_MASK_SH_LIST_DCN3(_MASK) 621 }; 622 623 static const struct dce_hwseq_registers hwseq_reg = { 624 HWSEQ_DCN30_REG_LIST() 625 }; 626 627 static const struct dce_hwseq_shift hwseq_shift = { 628 HWSEQ_DCN30_MASK_SH_LIST(__SHIFT) 629 }; 630 631 static const struct dce_hwseq_mask hwseq_mask = { 632 HWSEQ_DCN30_MASK_SH_LIST(_MASK) 633 }; 634 #define vmid_regs(id)\ 635 [id] = {\ 636 DCN20_VMID_REG_LIST(id)\ 637 } 638 639 static const struct dcn_vmid_registers vmid_regs[] = { 640 vmid_regs(0), 641 vmid_regs(1), 642 vmid_regs(2), 643 vmid_regs(3), 644 vmid_regs(4), 645 vmid_regs(5), 646 vmid_regs(6), 647 vmid_regs(7), 648 vmid_regs(8), 649 vmid_regs(9), 650 vmid_regs(10), 651 vmid_regs(11), 652 vmid_regs(12), 653 vmid_regs(13), 654 vmid_regs(14), 655 vmid_regs(15) 656 }; 657 658 static const struct dcn20_vmid_shift vmid_shifts = { 659 DCN20_VMID_MASK_SH_LIST(__SHIFT) 660 }; 661 662 static const struct dcn20_vmid_mask vmid_masks = { 663 DCN20_VMID_MASK_SH_LIST(_MASK) 664 }; 665 666 static const struct resource_caps res_cap_dcn3 = { 667 .num_timing_generator = 6, 668 .num_opp = 6, 669 .num_video_plane = 6, 670 .num_audio = 6, 671 .num_stream_encoder = 6, 672 .num_pll = 6, 673 .num_dwb = 1, 674 .num_ddc = 6, 675 .num_vmid = 16, 676 .num_mpc_3dlut = 3, 677 .num_dsc = 6, 678 }; 679 680 static const struct dc_plane_cap plane_cap = { 681 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 682 .blends_with_above = true, 683 .blends_with_below = true, 684 .per_pixel_alpha = true, 685 686 .pixel_format_support = { 687 .argb8888 = true, 688 .nv12 = true, 689 .fp16 = true, 690 .p010 = true, 691 .ayuv = false, 692 }, 693 694 .max_upscale_factor = { 695 .argb8888 = 16000, 696 .nv12 = 16000, 697 .fp16 = 16000 698 }, 699 700 /* 6:1 downscaling ratio: 1000/6 = 166.666 */ 701 .max_downscale_factor = { 702 .argb8888 = 167, 703 .nv12 = 167, 704 .fp16 = 167 705 } 706 }; 707 708 static const struct dc_debug_options debug_defaults_drv = { 709 .disable_dmcu = true, //No DMCU on DCN30 710 .force_abm_enable = false, 711 .timing_trace = false, 712 .clock_trace = true, 713 .disable_pplib_clock_request = true, 714 .pipe_split_policy = MPC_SPLIT_DYNAMIC, 715 .force_single_disp_pipe_split = false, 716 .disable_dcc = DCC_ENABLE, 717 .vsr_support = true, 718 .performance_trace = false, 719 .max_downscale_src_width = 7680,/*upto 8K*/ 720 .disable_pplib_wm_range = false, 721 .scl_reset_length10 = true, 722 .sanity_checks = false, 723 .underflow_assert_delay_us = 0xFFFFFFFF, 724 .dwb_fi_phase = -1, // -1 = disable, 725 .dmub_command_table = true, 726 .disable_psr = false, 727 .use_max_lb = true 728 }; 729 730 static const struct dc_debug_options debug_defaults_diags = { 731 .disable_dmcu = true, //No dmcu on DCN30 732 .force_abm_enable = false, 733 .timing_trace = true, 734 .clock_trace = true, 735 .disable_dpp_power_gate = true, 736 .disable_hubp_power_gate = true, 737 .disable_clock_gate = true, 738 .disable_pplib_clock_request = true, 739 .disable_pplib_wm_range = true, 740 .disable_stutter = false, 741 .scl_reset_length10 = true, 742 .dwb_fi_phase = -1, // -1 = disable 743 .dmub_command_table = true, 744 .disable_psr = true, 745 .enable_tri_buf = true, 746 .use_max_lb = true 747 }; 748 749 static void dcn30_dpp_destroy(struct dpp **dpp) 750 { 751 kfree(TO_DCN20_DPP(*dpp)); 752 *dpp = NULL; 753 } 754 755 static struct dpp *dcn30_dpp_create( 756 struct dc_context *ctx, 757 uint32_t inst) 758 { 759 struct dcn3_dpp *dpp = 760 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL); 761 762 if (!dpp) 763 return NULL; 764 765 if (dpp3_construct(dpp, ctx, inst, 766 &dpp_regs[inst], &tf_shift, &tf_mask)) 767 return &dpp->base; 768 769 BREAK_TO_DEBUGGER(); 770 kfree(dpp); 771 return NULL; 772 } 773 774 static struct output_pixel_processor *dcn30_opp_create( 775 struct dc_context *ctx, uint32_t inst) 776 { 777 struct dcn20_opp *opp = 778 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); 779 780 if (!opp) { 781 BREAK_TO_DEBUGGER(); 782 return NULL; 783 } 784 785 dcn20_opp_construct(opp, ctx, inst, 786 &opp_regs[inst], &opp_shift, &opp_mask); 787 return &opp->base; 788 } 789 790 static struct dce_aux *dcn30_aux_engine_create( 791 struct dc_context *ctx, 792 uint32_t inst) 793 { 794 struct aux_engine_dce110 *aux_engine = 795 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 796 797 if (!aux_engine) 798 return NULL; 799 800 dce110_aux_engine_construct(aux_engine, ctx, inst, 801 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 802 &aux_engine_regs[inst], 803 &aux_mask, 804 &aux_shift, 805 ctx->dc->caps.extended_aux_timeout_support); 806 807 return &aux_engine->base; 808 } 809 810 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) } 811 812 static const struct dce_i2c_registers i2c_hw_regs[] = { 813 i2c_inst_regs(1), 814 i2c_inst_regs(2), 815 i2c_inst_regs(3), 816 i2c_inst_regs(4), 817 i2c_inst_regs(5), 818 i2c_inst_regs(6), 819 }; 820 821 static const struct dce_i2c_shift i2c_shifts = { 822 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT) 823 }; 824 825 static const struct dce_i2c_mask i2c_masks = { 826 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK) 827 }; 828 829 static struct dce_i2c_hw *dcn30_i2c_hw_create( 830 struct dc_context *ctx, 831 uint32_t inst) 832 { 833 struct dce_i2c_hw *dce_i2c_hw = 834 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 835 836 if (!dce_i2c_hw) 837 return NULL; 838 839 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, 840 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 841 842 return dce_i2c_hw; 843 } 844 845 static struct mpc *dcn30_mpc_create( 846 struct dc_context *ctx, 847 int num_mpcc, 848 int num_rmu) 849 { 850 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), 851 GFP_KERNEL); 852 853 if (!mpc30) 854 return NULL; 855 856 dcn30_mpc_construct(mpc30, ctx, 857 &mpc_regs, 858 &mpc_shift, 859 &mpc_mask, 860 num_mpcc, 861 num_rmu); 862 863 return &mpc30->base; 864 } 865 866 static struct hubbub *dcn30_hubbub_create(struct dc_context *ctx) 867 { 868 int i; 869 870 struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub), 871 GFP_KERNEL); 872 873 if (!hubbub3) 874 return NULL; 875 876 hubbub3_construct(hubbub3, ctx, 877 &hubbub_reg, 878 &hubbub_shift, 879 &hubbub_mask); 880 881 882 for (i = 0; i < res_cap_dcn3.num_vmid; i++) { 883 struct dcn20_vmid *vmid = &hubbub3->vmid[i]; 884 885 vmid->ctx = ctx; 886 887 vmid->regs = &vmid_regs[i]; 888 vmid->shifts = &vmid_shifts; 889 vmid->masks = &vmid_masks; 890 } 891 892 return &hubbub3->base; 893 } 894 895 static struct timing_generator *dcn30_timing_generator_create( 896 struct dc_context *ctx, 897 uint32_t instance) 898 { 899 struct optc *tgn10 = 900 kzalloc(sizeof(struct optc), GFP_KERNEL); 901 902 if (!tgn10) 903 return NULL; 904 905 tgn10->base.inst = instance; 906 tgn10->base.ctx = ctx; 907 908 tgn10->tg_regs = &optc_regs[instance]; 909 tgn10->tg_shift = &optc_shift; 910 tgn10->tg_mask = &optc_mask; 911 912 dcn30_timing_generator_init(tgn10); 913 914 return &tgn10->base; 915 } 916 917 static const struct encoder_feature_support link_enc_feature = { 918 .max_hdmi_deep_color = COLOR_DEPTH_121212, 919 .max_hdmi_pixel_clock = 600000, 920 .hdmi_ycbcr420_supported = true, 921 .dp_ycbcr420_supported = true, 922 .fec_supported = true, 923 .flags.bits.IS_HBR2_CAPABLE = true, 924 .flags.bits.IS_HBR3_CAPABLE = true, 925 .flags.bits.IS_TPS3_CAPABLE = true, 926 .flags.bits.IS_TPS4_CAPABLE = true 927 }; 928 929 static struct link_encoder *dcn30_link_encoder_create( 930 const struct encoder_init_data *enc_init_data) 931 { 932 struct dcn20_link_encoder *enc20 = 933 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 934 935 if (!enc20) 936 return NULL; 937 938 dcn30_link_encoder_construct(enc20, 939 enc_init_data, 940 &link_enc_feature, 941 &link_enc_regs[enc_init_data->transmitter], 942 &link_enc_aux_regs[enc_init_data->channel - 1], 943 &link_enc_hpd_regs[enc_init_data->hpd_source], 944 &le_shift, 945 &le_mask); 946 947 return &enc20->enc10.base; 948 } 949 950 static struct panel_cntl *dcn30_panel_cntl_create(const struct panel_cntl_init_data *init_data) 951 { 952 struct dce_panel_cntl *panel_cntl = 953 kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL); 954 955 if (!panel_cntl) 956 return NULL; 957 958 dce_panel_cntl_construct(panel_cntl, 959 init_data, 960 &panel_cntl_regs[init_data->inst], 961 &panel_cntl_shift, 962 &panel_cntl_mask); 963 964 return &panel_cntl->base; 965 } 966 967 static void read_dce_straps( 968 struct dc_context *ctx, 969 struct resource_straps *straps) 970 { 971 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX), 972 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 973 974 } 975 976 static struct audio *dcn30_create_audio( 977 struct dc_context *ctx, unsigned int inst) 978 { 979 return dce_audio_create(ctx, inst, 980 &audio_regs[inst], &audio_shift, &audio_mask); 981 } 982 983 static struct vpg *dcn30_vpg_create( 984 struct dc_context *ctx, 985 uint32_t inst) 986 { 987 struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL); 988 989 if (!vpg3) 990 return NULL; 991 992 vpg3_construct(vpg3, ctx, inst, 993 &vpg_regs[inst], 994 &vpg_shift, 995 &vpg_mask); 996 997 return &vpg3->base; 998 } 999 1000 static struct afmt *dcn30_afmt_create( 1001 struct dc_context *ctx, 1002 uint32_t inst) 1003 { 1004 struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL); 1005 1006 if (!afmt3) 1007 return NULL; 1008 1009 afmt3_construct(afmt3, ctx, inst, 1010 &afmt_regs[inst], 1011 &afmt_shift, 1012 &afmt_mask); 1013 1014 return &afmt3->base; 1015 } 1016 1017 static struct stream_encoder *dcn30_stream_encoder_create(enum engine_id eng_id, 1018 struct dc_context *ctx) 1019 { 1020 struct dcn10_stream_encoder *enc1; 1021 struct vpg *vpg; 1022 struct afmt *afmt; 1023 int vpg_inst; 1024 int afmt_inst; 1025 1026 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */ 1027 if (eng_id <= ENGINE_ID_DIGF) { 1028 vpg_inst = eng_id; 1029 afmt_inst = eng_id; 1030 } else 1031 return NULL; 1032 1033 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 1034 vpg = dcn30_vpg_create(ctx, vpg_inst); 1035 afmt = dcn30_afmt_create(ctx, afmt_inst); 1036 1037 if (!enc1 || !vpg || !afmt) { 1038 kfree(enc1); 1039 kfree(vpg); 1040 kfree(afmt); 1041 return NULL; 1042 } 1043 1044 dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, 1045 eng_id, vpg, afmt, 1046 &stream_enc_regs[eng_id], 1047 &se_shift, &se_mask); 1048 1049 return &enc1->base; 1050 } 1051 1052 static struct dce_hwseq *dcn30_hwseq_create(struct dc_context *ctx) 1053 { 1054 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 1055 1056 if (hws) { 1057 hws->ctx = ctx; 1058 hws->regs = &hwseq_reg; 1059 hws->shifts = &hwseq_shift; 1060 hws->masks = &hwseq_mask; 1061 } 1062 return hws; 1063 } 1064 static const struct resource_create_funcs res_create_funcs = { 1065 .read_dce_straps = read_dce_straps, 1066 .create_audio = dcn30_create_audio, 1067 .create_stream_encoder = dcn30_stream_encoder_create, 1068 .create_hwseq = dcn30_hwseq_create, 1069 }; 1070 1071 static const struct resource_create_funcs res_create_maximus_funcs = { 1072 .read_dce_straps = NULL, 1073 .create_audio = NULL, 1074 .create_stream_encoder = NULL, 1075 .create_hwseq = dcn30_hwseq_create, 1076 }; 1077 1078 static void dcn30_resource_destruct(struct dcn30_resource_pool *pool) 1079 { 1080 unsigned int i; 1081 1082 for (i = 0; i < pool->base.stream_enc_count; i++) { 1083 if (pool->base.stream_enc[i] != NULL) { 1084 if (pool->base.stream_enc[i]->vpg != NULL) { 1085 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg)); 1086 pool->base.stream_enc[i]->vpg = NULL; 1087 } 1088 if (pool->base.stream_enc[i]->afmt != NULL) { 1089 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt)); 1090 pool->base.stream_enc[i]->afmt = NULL; 1091 } 1092 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); 1093 pool->base.stream_enc[i] = NULL; 1094 } 1095 } 1096 1097 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 1098 if (pool->base.dscs[i] != NULL) 1099 dcn20_dsc_destroy(&pool->base.dscs[i]); 1100 } 1101 1102 if (pool->base.mpc != NULL) { 1103 kfree(TO_DCN20_MPC(pool->base.mpc)); 1104 pool->base.mpc = NULL; 1105 } 1106 if (pool->base.hubbub != NULL) { 1107 kfree(pool->base.hubbub); 1108 pool->base.hubbub = NULL; 1109 } 1110 for (i = 0; i < pool->base.pipe_count; i++) { 1111 if (pool->base.dpps[i] != NULL) 1112 dcn30_dpp_destroy(&pool->base.dpps[i]); 1113 1114 if (pool->base.ipps[i] != NULL) 1115 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); 1116 1117 if (pool->base.hubps[i] != NULL) { 1118 kfree(TO_DCN20_HUBP(pool->base.hubps[i])); 1119 pool->base.hubps[i] = NULL; 1120 } 1121 1122 if (pool->base.irqs != NULL) { 1123 dal_irq_service_destroy(&pool->base.irqs); 1124 } 1125 } 1126 1127 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1128 if (pool->base.engines[i] != NULL) 1129 dce110_engine_destroy(&pool->base.engines[i]); 1130 if (pool->base.hw_i2cs[i] != NULL) { 1131 kfree(pool->base.hw_i2cs[i]); 1132 pool->base.hw_i2cs[i] = NULL; 1133 } 1134 if (pool->base.sw_i2cs[i] != NULL) { 1135 kfree(pool->base.sw_i2cs[i]); 1136 pool->base.sw_i2cs[i] = NULL; 1137 } 1138 } 1139 1140 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 1141 if (pool->base.opps[i] != NULL) 1142 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); 1143 } 1144 1145 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1146 if (pool->base.timing_generators[i] != NULL) { 1147 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); 1148 pool->base.timing_generators[i] = NULL; 1149 } 1150 } 1151 1152 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { 1153 if (pool->base.dwbc[i] != NULL) { 1154 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); 1155 pool->base.dwbc[i] = NULL; 1156 } 1157 if (pool->base.mcif_wb[i] != NULL) { 1158 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i])); 1159 pool->base.mcif_wb[i] = NULL; 1160 } 1161 } 1162 1163 for (i = 0; i < pool->base.audio_count; i++) { 1164 if (pool->base.audios[i]) 1165 dce_aud_destroy(&pool->base.audios[i]); 1166 } 1167 1168 for (i = 0; i < pool->base.clk_src_count; i++) { 1169 if (pool->base.clock_sources[i] != NULL) { 1170 dcn20_clock_source_destroy(&pool->base.clock_sources[i]); 1171 pool->base.clock_sources[i] = NULL; 1172 } 1173 } 1174 1175 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { 1176 if (pool->base.mpc_lut[i] != NULL) { 1177 dc_3dlut_func_release(pool->base.mpc_lut[i]); 1178 pool->base.mpc_lut[i] = NULL; 1179 } 1180 if (pool->base.mpc_shaper[i] != NULL) { 1181 dc_transfer_func_release(pool->base.mpc_shaper[i]); 1182 pool->base.mpc_shaper[i] = NULL; 1183 } 1184 } 1185 1186 if (pool->base.dp_clock_source != NULL) { 1187 dcn20_clock_source_destroy(&pool->base.dp_clock_source); 1188 pool->base.dp_clock_source = NULL; 1189 } 1190 1191 for (i = 0; i < pool->base.pipe_count; i++) { 1192 if (pool->base.multiple_abms[i] != NULL) 1193 dce_abm_destroy(&pool->base.multiple_abms[i]); 1194 } 1195 1196 if (pool->base.psr != NULL) 1197 dmub_psr_destroy(&pool->base.psr); 1198 1199 if (pool->base.dccg != NULL) 1200 dcn_dccg_destroy(&pool->base.dccg); 1201 1202 if (pool->base.oem_device != NULL) 1203 dal_ddc_service_destroy(&pool->base.oem_device); 1204 } 1205 1206 static struct hubp *dcn30_hubp_create( 1207 struct dc_context *ctx, 1208 uint32_t inst) 1209 { 1210 struct dcn20_hubp *hubp2 = 1211 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL); 1212 1213 if (!hubp2) 1214 return NULL; 1215 1216 if (hubp3_construct(hubp2, ctx, inst, 1217 &hubp_regs[inst], &hubp_shift, &hubp_mask)) 1218 return &hubp2->base; 1219 1220 BREAK_TO_DEBUGGER(); 1221 kfree(hubp2); 1222 return NULL; 1223 } 1224 1225 static bool dcn30_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) 1226 { 1227 int i; 1228 uint32_t pipe_count = pool->res_cap->num_dwb; 1229 1230 for (i = 0; i < pipe_count; i++) { 1231 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), 1232 GFP_KERNEL); 1233 1234 if (!dwbc30) { 1235 dm_error("DC: failed to create dwbc30!\n"); 1236 return false; 1237 } 1238 1239 dcn30_dwbc_construct(dwbc30, ctx, 1240 &dwbc30_regs[i], 1241 &dwbc30_shift, 1242 &dwbc30_mask, 1243 i); 1244 1245 pool->dwbc[i] = &dwbc30->base; 1246 } 1247 return true; 1248 } 1249 1250 static bool dcn30_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) 1251 { 1252 int i; 1253 uint32_t pipe_count = pool->res_cap->num_dwb; 1254 1255 for (i = 0; i < pipe_count; i++) { 1256 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), 1257 GFP_KERNEL); 1258 1259 if (!mcif_wb30) { 1260 dm_error("DC: failed to create mcif_wb30!\n"); 1261 return false; 1262 } 1263 1264 dcn30_mmhubbub_construct(mcif_wb30, ctx, 1265 &mcif_wb30_regs[i], 1266 &mcif_wb30_shift, 1267 &mcif_wb30_mask, 1268 i); 1269 1270 pool->mcif_wb[i] = &mcif_wb30->base; 1271 } 1272 return true; 1273 } 1274 1275 static struct display_stream_compressor *dcn30_dsc_create( 1276 struct dc_context *ctx, uint32_t inst) 1277 { 1278 struct dcn20_dsc *dsc = 1279 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL); 1280 1281 if (!dsc) { 1282 BREAK_TO_DEBUGGER(); 1283 return NULL; 1284 } 1285 1286 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 1287 return &dsc->base; 1288 } 1289 1290 enum dc_status dcn30_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream) 1291 { 1292 1293 return dcn20_add_stream_to_ctx(dc, new_ctx, dc_stream); 1294 } 1295 1296 static void dcn30_destroy_resource_pool(struct resource_pool **pool) 1297 { 1298 struct dcn30_resource_pool *dcn30_pool = TO_DCN30_RES_POOL(*pool); 1299 1300 dcn30_resource_destruct(dcn30_pool); 1301 kfree(dcn30_pool); 1302 *pool = NULL; 1303 } 1304 1305 static struct clock_source *dcn30_clock_source_create( 1306 struct dc_context *ctx, 1307 struct dc_bios *bios, 1308 enum clock_source_id id, 1309 const struct dce110_clk_src_regs *regs, 1310 bool dp_clk_src) 1311 { 1312 struct dce110_clk_src *clk_src = 1313 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 1314 1315 if (!clk_src) 1316 return NULL; 1317 1318 if (dcn3_clk_src_construct(clk_src, ctx, bios, id, 1319 regs, &cs_shift, &cs_mask)) { 1320 clk_src->base.dp_clk_src = dp_clk_src; 1321 return &clk_src->base; 1322 } 1323 1324 BREAK_TO_DEBUGGER(); 1325 return NULL; 1326 } 1327 1328 int dcn30_populate_dml_pipes_from_context( 1329 struct dc *dc, struct dc_state *context, 1330 display_e2e_pipe_params_st *pipes, 1331 bool fast_validate) 1332 { 1333 int i, pipe_cnt; 1334 struct resource_context *res_ctx = &context->res_ctx; 1335 1336 DC_FP_START(); 1337 dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate); 1338 DC_FP_END(); 1339 1340 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { 1341 if (!res_ctx->pipe_ctx[i].stream) 1342 continue; 1343 1344 pipes[pipe_cnt++].pipe.scale_ratio_depth.lb_depth = 1345 dm_lb_16; 1346 } 1347 1348 return pipe_cnt; 1349 } 1350 1351 void dcn30_populate_dml_writeback_from_context( 1352 struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes) 1353 { 1354 DC_FP_START(); 1355 dcn30_fpu_populate_dml_writeback_from_context(dc, res_ctx, pipes); 1356 DC_FP_END(); 1357 } 1358 1359 unsigned int dcn30_calc_max_scaled_time( 1360 unsigned int time_per_pixel, 1361 enum mmhubbub_wbif_mode mode, 1362 unsigned int urgent_watermark) 1363 { 1364 unsigned int time_per_byte = 0; 1365 unsigned int total_free_entry = 0xb40; 1366 unsigned int buf_lh_capability; 1367 unsigned int max_scaled_time; 1368 1369 if (mode == PACKED_444) /* packed mode 32 bpp */ 1370 time_per_byte = time_per_pixel/4; 1371 else if (mode == PACKED_444_FP16) /* packed mode 64 bpp */ 1372 time_per_byte = time_per_pixel/8; 1373 1374 if (time_per_byte == 0) 1375 time_per_byte = 1; 1376 1377 buf_lh_capability = (total_free_entry*time_per_byte*32) >> 6; /* time_per_byte is in u6.6*/ 1378 max_scaled_time = buf_lh_capability - urgent_watermark; 1379 return max_scaled_time; 1380 } 1381 1382 void dcn30_set_mcif_arb_params( 1383 struct dc *dc, 1384 struct dc_state *context, 1385 display_e2e_pipe_params_st *pipes, 1386 int pipe_cnt) 1387 { 1388 enum mmhubbub_wbif_mode wbif_mode; 1389 struct display_mode_lib *dml = &context->bw_ctx.dml; 1390 struct mcif_arb_params *wb_arb_params; 1391 int i, j, dwb_pipe; 1392 1393 /* Writeback MCIF_WB arbitration parameters */ 1394 dwb_pipe = 0; 1395 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1396 1397 if (!context->res_ctx.pipe_ctx[i].stream) 1398 continue; 1399 1400 for (j = 0; j < MAX_DWB_PIPES; j++) { 1401 struct dc_writeback_info *writeback_info = &context->res_ctx.pipe_ctx[i].stream->writeback_info[j]; 1402 1403 if (writeback_info->wb_enabled == false) 1404 continue; 1405 1406 //wb_arb_params = &context->res_ctx.pipe_ctx[i].stream->writeback_info[j].mcif_arb_params; 1407 wb_arb_params = &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[dwb_pipe]; 1408 1409 if (writeback_info->dwb_params.cnv_params.fc_out_format == DWB_OUT_FORMAT_64BPP_ARGB || 1410 writeback_info->dwb_params.cnv_params.fc_out_format == DWB_OUT_FORMAT_64BPP_RGBA) 1411 wbif_mode = PACKED_444_FP16; 1412 else 1413 wbif_mode = PACKED_444; 1414 1415 DC_FP_START(); 1416 dcn30_fpu_set_mcif_arb_params(wb_arb_params, dml, pipes, pipe_cnt, j); 1417 DC_FP_END(); 1418 wb_arb_params->time_per_pixel = (1000000 << 6) / context->res_ctx.pipe_ctx[i].stream->phy_pix_clk; /* time_per_pixel should be in u6.6 format */ 1419 wb_arb_params->slice_lines = 32; 1420 wb_arb_params->arbitration_slice = 2; /* irrelevant since there is no YUV output */ 1421 wb_arb_params->max_scaled_time = dcn30_calc_max_scaled_time(wb_arb_params->time_per_pixel, 1422 wbif_mode, 1423 wb_arb_params->cli_watermark[0]); /* assume 4 watermark sets have the same value */ 1424 1425 dwb_pipe++; 1426 1427 if (dwb_pipe >= MAX_DWB_PIPES) 1428 return; 1429 } 1430 if (dwb_pipe >= MAX_DWB_PIPES) 1431 return; 1432 } 1433 1434 } 1435 1436 static struct dc_cap_funcs cap_funcs = { 1437 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap 1438 }; 1439 1440 bool dcn30_acquire_post_bldn_3dlut( 1441 struct resource_context *res_ctx, 1442 const struct resource_pool *pool, 1443 int mpcc_id, 1444 struct dc_3dlut **lut, 1445 struct dc_transfer_func **shaper) 1446 { 1447 int i; 1448 bool ret = false; 1449 union dc_3dlut_state *state; 1450 1451 ASSERT(*lut == NULL && *shaper == NULL); 1452 *lut = NULL; 1453 *shaper = NULL; 1454 1455 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { 1456 if (!res_ctx->is_mpc_3dlut_acquired[i]) { 1457 *lut = pool->mpc_lut[i]; 1458 *shaper = pool->mpc_shaper[i]; 1459 state = &pool->mpc_lut[i]->state; 1460 res_ctx->is_mpc_3dlut_acquired[i] = true; 1461 state->bits.rmu_idx_valid = 1; 1462 state->bits.rmu_mux_num = i; 1463 if (state->bits.rmu_mux_num == 0) 1464 state->bits.mpc_rmu0_mux = mpcc_id; 1465 else if (state->bits.rmu_mux_num == 1) 1466 state->bits.mpc_rmu1_mux = mpcc_id; 1467 else if (state->bits.rmu_mux_num == 2) 1468 state->bits.mpc_rmu2_mux = mpcc_id; 1469 ret = true; 1470 break; 1471 } 1472 } 1473 return ret; 1474 } 1475 1476 bool dcn30_release_post_bldn_3dlut( 1477 struct resource_context *res_ctx, 1478 const struct resource_pool *pool, 1479 struct dc_3dlut **lut, 1480 struct dc_transfer_func **shaper) 1481 { 1482 int i; 1483 bool ret = false; 1484 1485 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { 1486 if (pool->mpc_lut[i] == *lut && pool->mpc_shaper[i] == *shaper) { 1487 res_ctx->is_mpc_3dlut_acquired[i] = false; 1488 pool->mpc_lut[i]->state.raw = 0; 1489 *lut = NULL; 1490 *shaper = NULL; 1491 ret = true; 1492 break; 1493 } 1494 } 1495 return ret; 1496 } 1497 1498 static bool is_soc_bounding_box_valid(struct dc *dc) 1499 { 1500 uint32_t hw_internal_rev = dc->ctx->asic_id.hw_internal_rev; 1501 1502 if (ASICREV_IS_SIENNA_CICHLID_P(hw_internal_rev)) 1503 return true; 1504 1505 return false; 1506 } 1507 1508 static bool init_soc_bounding_box(struct dc *dc, 1509 struct dcn30_resource_pool *pool) 1510 { 1511 struct _vcs_dpi_soc_bounding_box_st *loaded_bb = &dcn3_0_soc; 1512 struct _vcs_dpi_ip_params_st *loaded_ip = &dcn3_0_ip; 1513 1514 DC_LOGGER_INIT(dc->ctx->logger); 1515 1516 if (!is_soc_bounding_box_valid(dc)) { 1517 DC_LOG_ERROR("%s: not valid soc bounding box\n", __func__); 1518 return false; 1519 } 1520 1521 loaded_ip->max_num_otg = pool->base.res_cap->num_timing_generator; 1522 loaded_ip->max_num_dpp = pool->base.pipe_count; 1523 loaded_ip->clamp_min_dcfclk = dc->config.clamp_min_dcfclk; 1524 1525 DC_FP_START(); 1526 dcn20_patch_bounding_box(dc, loaded_bb); 1527 DC_FP_END(); 1528 1529 if (dc->ctx->dc_bios->funcs->get_soc_bb_info) { 1530 struct bp_soc_bb_info bb_info = {0}; 1531 1532 if (dc->ctx->dc_bios->funcs->get_soc_bb_info(dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) { 1533 if (bb_info.dram_clock_change_latency_100ns > 0) 1534 dcn3_0_soc.dram_clock_change_latency_us = bb_info.dram_clock_change_latency_100ns * 10; 1535 1536 if (bb_info.dram_sr_enter_exit_latency_100ns > 0) 1537 dcn3_0_soc.sr_enter_plus_exit_time_us = bb_info.dram_sr_enter_exit_latency_100ns * 10; 1538 1539 if (bb_info.dram_sr_exit_latency_100ns > 0) 1540 dcn3_0_soc.sr_exit_time_us = bb_info.dram_sr_exit_latency_100ns * 10; 1541 } 1542 } 1543 1544 return true; 1545 } 1546 1547 static bool dcn30_split_stream_for_mpc_or_odm( 1548 const struct dc *dc, 1549 struct resource_context *res_ctx, 1550 struct pipe_ctx *pri_pipe, 1551 struct pipe_ctx *sec_pipe, 1552 bool odm) 1553 { 1554 int pipe_idx = sec_pipe->pipe_idx; 1555 const struct resource_pool *pool = dc->res_pool; 1556 1557 *sec_pipe = *pri_pipe; 1558 1559 sec_pipe->pipe_idx = pipe_idx; 1560 sec_pipe->plane_res.mi = pool->mis[pipe_idx]; 1561 sec_pipe->plane_res.hubp = pool->hubps[pipe_idx]; 1562 sec_pipe->plane_res.ipp = pool->ipps[pipe_idx]; 1563 sec_pipe->plane_res.xfm = pool->transforms[pipe_idx]; 1564 sec_pipe->plane_res.dpp = pool->dpps[pipe_idx]; 1565 sec_pipe->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst; 1566 sec_pipe->stream_res.dsc = NULL; 1567 if (odm) { 1568 if (pri_pipe->next_odm_pipe) { 1569 ASSERT(pri_pipe->next_odm_pipe != sec_pipe); 1570 sec_pipe->next_odm_pipe = pri_pipe->next_odm_pipe; 1571 sec_pipe->next_odm_pipe->prev_odm_pipe = sec_pipe; 1572 } 1573 if (pri_pipe->top_pipe && pri_pipe->top_pipe->next_odm_pipe) { 1574 pri_pipe->top_pipe->next_odm_pipe->bottom_pipe = sec_pipe; 1575 sec_pipe->top_pipe = pri_pipe->top_pipe->next_odm_pipe; 1576 } 1577 if (pri_pipe->bottom_pipe && pri_pipe->bottom_pipe->next_odm_pipe) { 1578 pri_pipe->bottom_pipe->next_odm_pipe->top_pipe = sec_pipe; 1579 sec_pipe->bottom_pipe = pri_pipe->bottom_pipe->next_odm_pipe; 1580 } 1581 pri_pipe->next_odm_pipe = sec_pipe; 1582 sec_pipe->prev_odm_pipe = pri_pipe; 1583 1584 if (!sec_pipe->top_pipe) 1585 sec_pipe->stream_res.opp = pool->opps[pipe_idx]; 1586 else 1587 sec_pipe->stream_res.opp = sec_pipe->top_pipe->stream_res.opp; 1588 if (sec_pipe->stream->timing.flags.DSC == 1) { 1589 dcn20_acquire_dsc(dc, res_ctx, &sec_pipe->stream_res.dsc, pipe_idx); 1590 ASSERT(sec_pipe->stream_res.dsc); 1591 if (sec_pipe->stream_res.dsc == NULL) 1592 return false; 1593 } 1594 } else { 1595 if (pri_pipe->bottom_pipe) { 1596 ASSERT(pri_pipe->bottom_pipe != sec_pipe); 1597 sec_pipe->bottom_pipe = pri_pipe->bottom_pipe; 1598 sec_pipe->bottom_pipe->top_pipe = sec_pipe; 1599 } 1600 pri_pipe->bottom_pipe = sec_pipe; 1601 sec_pipe->top_pipe = pri_pipe; 1602 1603 ASSERT(pri_pipe->plane_state); 1604 } 1605 1606 return true; 1607 } 1608 1609 static struct pipe_ctx *dcn30_find_split_pipe( 1610 struct dc *dc, 1611 struct dc_state *context, 1612 int old_index) 1613 { 1614 struct pipe_ctx *pipe = NULL; 1615 int i; 1616 1617 if (old_index >= 0 && context->res_ctx.pipe_ctx[old_index].stream == NULL) { 1618 pipe = &context->res_ctx.pipe_ctx[old_index]; 1619 pipe->pipe_idx = old_index; 1620 } 1621 1622 if (!pipe) 1623 for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) { 1624 if (dc->current_state->res_ctx.pipe_ctx[i].top_pipe == NULL 1625 && dc->current_state->res_ctx.pipe_ctx[i].prev_odm_pipe == NULL) { 1626 if (context->res_ctx.pipe_ctx[i].stream == NULL) { 1627 pipe = &context->res_ctx.pipe_ctx[i]; 1628 pipe->pipe_idx = i; 1629 break; 1630 } 1631 } 1632 } 1633 1634 /* 1635 * May need to fix pipes getting tossed from 1 opp to another on flip 1636 * Add for debugging transient underflow during topology updates: 1637 * ASSERT(pipe); 1638 */ 1639 if (!pipe) 1640 for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) { 1641 if (context->res_ctx.pipe_ctx[i].stream == NULL) { 1642 pipe = &context->res_ctx.pipe_ctx[i]; 1643 pipe->pipe_idx = i; 1644 break; 1645 } 1646 } 1647 1648 return pipe; 1649 } 1650 1651 noinline bool dcn30_internal_validate_bw( 1652 struct dc *dc, 1653 struct dc_state *context, 1654 display_e2e_pipe_params_st *pipes, 1655 int *pipe_cnt_out, 1656 int *vlevel_out, 1657 bool fast_validate) 1658 { 1659 bool out = false; 1660 bool repopulate_pipes = false; 1661 int split[MAX_PIPES] = { 0 }; 1662 bool merge[MAX_PIPES] = { false }; 1663 bool newly_split[MAX_PIPES] = { false }; 1664 int pipe_cnt, i, pipe_idx, vlevel; 1665 struct vba_vars_st *vba = &context->bw_ctx.dml.vba; 1666 1667 ASSERT(pipes); 1668 if (!pipes) 1669 return false; 1670 1671 dc->res_pool->funcs->update_soc_for_wm_a(dc, context); 1672 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate); 1673 1674 if (!pipe_cnt) { 1675 out = true; 1676 goto validate_out; 1677 } 1678 1679 dml_log_pipe_params(&context->bw_ctx.dml, pipes, pipe_cnt); 1680 1681 if (!fast_validate) { 1682 /* 1683 * DML favors voltage over p-state, but we're more interested in 1684 * supporting p-state over voltage. We can't support p-state in 1685 * prefetch mode > 0 so try capping the prefetch mode to start. 1686 */ 1687 context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank = 1688 dm_allow_self_refresh_and_mclk_switch; 1689 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); 1690 /* This may adjust vlevel and maxMpcComb */ 1691 if (vlevel < context->bw_ctx.dml.soc.num_states) 1692 vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge); 1693 } 1694 if (fast_validate || vlevel == context->bw_ctx.dml.soc.num_states || 1695 vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported) { 1696 /* 1697 * If mode is unsupported or there's still no p-state support then 1698 * fall back to favoring voltage. 1699 * 1700 * We don't actually support prefetch mode 2, so require that we 1701 * at least support prefetch mode 1. 1702 */ 1703 context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank = 1704 dm_allow_self_refresh; 1705 1706 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); 1707 if (vlevel < context->bw_ctx.dml.soc.num_states) { 1708 memset(split, 0, sizeof(split)); 1709 memset(merge, 0, sizeof(merge)); 1710 vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge); 1711 } 1712 } 1713 1714 dml_log_mode_support_params(&context->bw_ctx.dml); 1715 1716 if (vlevel == context->bw_ctx.dml.soc.num_states) 1717 goto validate_fail; 1718 1719 if (!dc->config.enable_windowed_mpo_odm) { 1720 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 1721 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1722 struct pipe_ctx *mpo_pipe = pipe->bottom_pipe; 1723 1724 if (!pipe->stream) 1725 continue; 1726 1727 /* We only support full screen mpo with ODM */ 1728 if (vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled 1729 && pipe->plane_state && mpo_pipe 1730 && memcmp(&mpo_pipe->plane_res.scl_data.recout, 1731 &pipe->plane_res.scl_data.recout, 1732 sizeof(struct rect)) != 0) { 1733 ASSERT(mpo_pipe->plane_state != pipe->plane_state); 1734 goto validate_fail; 1735 } 1736 pipe_idx++; 1737 } 1738 } 1739 1740 /* merge pipes if necessary */ 1741 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1742 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1743 1744 /*skip pipes that don't need merging*/ 1745 if (!merge[i]) 1746 continue; 1747 1748 /* if ODM merge we ignore mpc tree, mpo pipes will have their own flags */ 1749 if (pipe->prev_odm_pipe) { 1750 /*split off odm pipe*/ 1751 pipe->prev_odm_pipe->next_odm_pipe = pipe->next_odm_pipe; 1752 if (pipe->next_odm_pipe) 1753 pipe->next_odm_pipe->prev_odm_pipe = pipe->prev_odm_pipe; 1754 1755 pipe->bottom_pipe = NULL; 1756 pipe->next_odm_pipe = NULL; 1757 pipe->plane_state = NULL; 1758 pipe->stream = NULL; 1759 pipe->top_pipe = NULL; 1760 pipe->prev_odm_pipe = NULL; 1761 if (pipe->stream_res.dsc) 1762 dcn20_release_dsc(&context->res_ctx, dc->res_pool, &pipe->stream_res.dsc); 1763 memset(&pipe->plane_res, 0, sizeof(pipe->plane_res)); 1764 memset(&pipe->stream_res, 0, sizeof(pipe->stream_res)); 1765 repopulate_pipes = true; 1766 } else if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) { 1767 struct pipe_ctx *top_pipe = pipe->top_pipe; 1768 struct pipe_ctx *bottom_pipe = pipe->bottom_pipe; 1769 1770 top_pipe->bottom_pipe = bottom_pipe; 1771 if (bottom_pipe) 1772 bottom_pipe->top_pipe = top_pipe; 1773 1774 pipe->top_pipe = NULL; 1775 pipe->bottom_pipe = NULL; 1776 pipe->plane_state = NULL; 1777 pipe->stream = NULL; 1778 memset(&pipe->plane_res, 0, sizeof(pipe->plane_res)); 1779 memset(&pipe->stream_res, 0, sizeof(pipe->stream_res)); 1780 repopulate_pipes = true; 1781 } else 1782 ASSERT(0); /* Should never try to merge master pipe */ 1783 1784 } 1785 1786 for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) { 1787 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1788 struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i]; 1789 struct pipe_ctx *hsplit_pipe = NULL; 1790 bool odm; 1791 int old_index = -1; 1792 1793 if (!pipe->stream || newly_split[i]) 1794 continue; 1795 1796 pipe_idx++; 1797 odm = vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled; 1798 1799 if (!pipe->plane_state && !odm) 1800 continue; 1801 1802 if (split[i]) { 1803 if (odm) { 1804 if (split[i] == 4 && old_pipe->next_odm_pipe && old_pipe->next_odm_pipe->next_odm_pipe) 1805 old_index = old_pipe->next_odm_pipe->next_odm_pipe->pipe_idx; 1806 else if (old_pipe->next_odm_pipe) 1807 old_index = old_pipe->next_odm_pipe->pipe_idx; 1808 } else { 1809 if (split[i] == 4 && old_pipe->bottom_pipe && old_pipe->bottom_pipe->bottom_pipe && 1810 old_pipe->bottom_pipe->bottom_pipe->plane_state == old_pipe->plane_state) 1811 old_index = old_pipe->bottom_pipe->bottom_pipe->pipe_idx; 1812 else if (old_pipe->bottom_pipe && 1813 old_pipe->bottom_pipe->plane_state == old_pipe->plane_state) 1814 old_index = old_pipe->bottom_pipe->pipe_idx; 1815 } 1816 hsplit_pipe = dcn30_find_split_pipe(dc, context, old_index); 1817 ASSERT(hsplit_pipe); 1818 if (!hsplit_pipe) 1819 goto validate_fail; 1820 1821 if (!dcn30_split_stream_for_mpc_or_odm( 1822 dc, &context->res_ctx, 1823 pipe, hsplit_pipe, odm)) 1824 goto validate_fail; 1825 1826 newly_split[hsplit_pipe->pipe_idx] = true; 1827 repopulate_pipes = true; 1828 } 1829 if (split[i] == 4) { 1830 struct pipe_ctx *pipe_4to1; 1831 1832 if (odm && old_pipe->next_odm_pipe) 1833 old_index = old_pipe->next_odm_pipe->pipe_idx; 1834 else if (!odm && old_pipe->bottom_pipe && 1835 old_pipe->bottom_pipe->plane_state == old_pipe->plane_state) 1836 old_index = old_pipe->bottom_pipe->pipe_idx; 1837 else 1838 old_index = -1; 1839 pipe_4to1 = dcn30_find_split_pipe(dc, context, old_index); 1840 ASSERT(pipe_4to1); 1841 if (!pipe_4to1) 1842 goto validate_fail; 1843 if (!dcn30_split_stream_for_mpc_or_odm( 1844 dc, &context->res_ctx, 1845 pipe, pipe_4to1, odm)) 1846 goto validate_fail; 1847 newly_split[pipe_4to1->pipe_idx] = true; 1848 1849 if (odm && old_pipe->next_odm_pipe && old_pipe->next_odm_pipe->next_odm_pipe 1850 && old_pipe->next_odm_pipe->next_odm_pipe->next_odm_pipe) 1851 old_index = old_pipe->next_odm_pipe->next_odm_pipe->next_odm_pipe->pipe_idx; 1852 else if (!odm && old_pipe->bottom_pipe && old_pipe->bottom_pipe->bottom_pipe && 1853 old_pipe->bottom_pipe->bottom_pipe->bottom_pipe && 1854 old_pipe->bottom_pipe->bottom_pipe->bottom_pipe->plane_state == old_pipe->plane_state) 1855 old_index = old_pipe->bottom_pipe->bottom_pipe->bottom_pipe->pipe_idx; 1856 else 1857 old_index = -1; 1858 pipe_4to1 = dcn30_find_split_pipe(dc, context, old_index); 1859 ASSERT(pipe_4to1); 1860 if (!pipe_4to1) 1861 goto validate_fail; 1862 if (!dcn30_split_stream_for_mpc_or_odm( 1863 dc, &context->res_ctx, 1864 hsplit_pipe, pipe_4to1, odm)) 1865 goto validate_fail; 1866 newly_split[pipe_4to1->pipe_idx] = true; 1867 } 1868 if (odm) 1869 dcn20_build_mapped_resource(dc, context, pipe->stream); 1870 } 1871 1872 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1873 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1874 1875 if (pipe->plane_state) { 1876 if (!resource_build_scaling_params(pipe)) 1877 goto validate_fail; 1878 } 1879 } 1880 1881 /* Actual dsc count per stream dsc validation*/ 1882 if (!dcn20_validate_dsc(dc, context)) { 1883 vba->ValidationStatus[vba->soc.num_states] = DML_FAIL_DSC_VALIDATION_FAILURE; 1884 goto validate_fail; 1885 } 1886 1887 if (repopulate_pipes) 1888 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate); 1889 *vlevel_out = vlevel; 1890 *pipe_cnt_out = pipe_cnt; 1891 1892 out = true; 1893 goto validate_out; 1894 1895 validate_fail: 1896 out = false; 1897 1898 validate_out: 1899 return out; 1900 } 1901 1902 int get_refresh_rate(struct dc_state *context) 1903 { 1904 int refresh_rate = 0; 1905 int h_v_total = 0; 1906 struct dc_crtc_timing *timing = NULL; 1907 1908 if (context == NULL || context->streams[0] == NULL) 1909 return 0; 1910 1911 /* check if refresh rate at least 120hz */ 1912 timing = &context->streams[0]->timing; 1913 if (timing == NULL) 1914 return 0; 1915 1916 h_v_total = timing->h_total * timing->v_total; 1917 if (h_v_total == 0) 1918 return 0; 1919 1920 refresh_rate = ((timing->pix_clk_100hz * 100) / (h_v_total)) + 1; 1921 return refresh_rate; 1922 } 1923 1924 #define MAX_STRETCHED_V_BLANK 500 // in micro-seconds 1925 /* 1926 * Scaling factor for v_blank stretch calculations considering timing in 1927 * micro-seconds and pixel clock in 100hz. 1928 * Note: the parenthesis are necessary to ensure the correct order of 1929 * operation where V_SCALE is used. 1930 */ 1931 #define V_SCALE (10000 / MAX_STRETCHED_V_BLANK) 1932 1933 int get_frame_rate_at_max_stretch_100hz(struct dc_state *context) 1934 { 1935 struct dc_crtc_timing *timing = NULL; 1936 uint32_t sec_per_100_lines; 1937 uint32_t max_v_blank; 1938 uint32_t curr_v_blank; 1939 uint32_t v_stretch_max; 1940 uint32_t stretched_frame_pix_cnt; 1941 uint32_t scaled_stretched_frame_pix_cnt; 1942 uint32_t scaled_refresh_rate; 1943 1944 if (context == NULL || context->streams[0] == NULL) 1945 return 0; 1946 1947 /* check if refresh rate at least 120hz */ 1948 timing = &context->streams[0]->timing; 1949 if (timing == NULL) 1950 return 0; 1951 1952 sec_per_100_lines = timing->pix_clk_100hz / timing->h_total + 1; 1953 max_v_blank = sec_per_100_lines / V_SCALE + 1; 1954 curr_v_blank = timing->v_total - timing->v_addressable; 1955 v_stretch_max = (max_v_blank > curr_v_blank) ? (max_v_blank - curr_v_blank) : (0); 1956 stretched_frame_pix_cnt = (v_stretch_max + timing->v_total) * timing->h_total; 1957 scaled_stretched_frame_pix_cnt = stretched_frame_pix_cnt / 10000; 1958 scaled_refresh_rate = (timing->pix_clk_100hz) / scaled_stretched_frame_pix_cnt + 1; 1959 1960 return scaled_refresh_rate; 1961 } 1962 1963 bool is_refresh_rate_support_mclk_switch_using_fw_based_vblank_stretch(struct dc_state *context) 1964 { 1965 int refresh_rate_max_stretch_100hz; 1966 int min_refresh_100hz; 1967 1968 if (context == NULL || context->streams[0] == NULL) 1969 return false; 1970 1971 refresh_rate_max_stretch_100hz = get_frame_rate_at_max_stretch_100hz(context); 1972 min_refresh_100hz = context->streams[0]->timing.min_refresh_in_uhz / 10000; 1973 1974 if (refresh_rate_max_stretch_100hz < min_refresh_100hz) 1975 return false; 1976 1977 return true; 1978 } 1979 1980 bool dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch(struct dc *dc, struct dc_state *context) 1981 { 1982 int refresh_rate = 0; 1983 const int minimum_refreshrate_supported = 120; 1984 1985 if (context == NULL || context->streams[0] == NULL) 1986 return false; 1987 1988 if (context->streams[0]->sink->edid_caps.panel_patch.disable_fams) 1989 return false; 1990 1991 if (dc->debug.disable_fams) 1992 return false; 1993 1994 if (!dc->caps.dmub_caps.mclk_sw) 1995 return false; 1996 1997 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching_shut_down) 1998 return false; 1999 2000 /* more then 1 monitor connected */ 2001 if (context->stream_count != 1) 2002 return false; 2003 2004 refresh_rate = get_refresh_rate(context); 2005 if (refresh_rate < minimum_refreshrate_supported) 2006 return false; 2007 2008 if (!is_refresh_rate_support_mclk_switch_using_fw_based_vblank_stretch(context)) 2009 return false; 2010 2011 // check if freesync enabled 2012 if (!context->streams[0]->allow_freesync) 2013 return false; 2014 2015 if (context->streams[0]->vrr_active_variable) 2016 return false; 2017 2018 return true; 2019 } 2020 2021 /* 2022 * set up FPO watermarks, pstate, dram latency 2023 */ 2024 void dcn30_setup_mclk_switch_using_fw_based_vblank_stretch(struct dc *dc, struct dc_state *context) 2025 { 2026 ASSERT(dc != NULL && context != NULL); 2027 if (dc == NULL || context == NULL) 2028 return; 2029 2030 /* Set wm_a.pstate so high natural MCLK switches are impossible: 4 seconds */ 2031 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 4U * 1000U * 1000U * 1000U; 2032 } 2033 2034 /* 2035 * Finds dummy_latency_index when MCLK switching using firmware based 2036 * vblank stretch is enabled. This function will iterate through the 2037 * table of dummy pstate latencies until the lowest value that allows 2038 * dm_allow_self_refresh_and_mclk_switch to happen is found 2039 */ 2040 int dcn30_find_dummy_latency_index_for_fw_based_mclk_switch(struct dc *dc, struct dc_state *context, 2041 display_e2e_pipe_params_st *pipes, int pipe_cnt, int vlevel) 2042 { 2043 const int max_latency_table_entries = 4; 2044 int dummy_latency_index = 0; 2045 2046 while (dummy_latency_index < max_latency_table_entries) { 2047 context->bw_ctx.dml.soc.dram_clock_change_latency_us = 2048 dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us; 2049 dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, false); 2050 2051 if (context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank == 2052 dm_allow_self_refresh_and_mclk_switch) 2053 break; 2054 2055 dummy_latency_index++; 2056 } 2057 2058 if (dummy_latency_index == max_latency_table_entries) { 2059 ASSERT(dummy_latency_index != max_latency_table_entries); 2060 /* If the execution gets here, it means dummy p_states are 2061 * not possible. This should never happen and would mean 2062 * something is severely wrong. 2063 * Here we reset dummy_latency_index to 3, because it is 2064 * better to have underflows than system crashes. 2065 */ 2066 dummy_latency_index = 3; 2067 } 2068 2069 return dummy_latency_index; 2070 } 2071 2072 void dcn30_update_soc_for_wm_a(struct dc *dc, struct dc_state *context) 2073 { 2074 DC_FP_START(); 2075 dcn30_fpu_update_soc_for_wm_a(dc, context); 2076 DC_FP_END(); 2077 } 2078 2079 void dcn30_calculate_wm_and_dlg( 2080 struct dc *dc, struct dc_state *context, 2081 display_e2e_pipe_params_st *pipes, 2082 int pipe_cnt, 2083 int vlevel) 2084 { 2085 DC_FP_START(); 2086 dcn30_fpu_calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel); 2087 DC_FP_END(); 2088 } 2089 2090 bool dcn30_validate_bandwidth(struct dc *dc, 2091 struct dc_state *context, 2092 bool fast_validate) 2093 { 2094 bool out = false; 2095 2096 BW_VAL_TRACE_SETUP(); 2097 2098 int vlevel = 0; 2099 int pipe_cnt = 0; 2100 display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL); 2101 DC_LOGGER_INIT(dc->ctx->logger); 2102 2103 BW_VAL_TRACE_COUNT(); 2104 2105 DC_FP_START(); 2106 out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate); 2107 DC_FP_END(); 2108 2109 if (pipe_cnt == 0) 2110 goto validate_out; 2111 2112 if (!out) 2113 goto validate_fail; 2114 2115 BW_VAL_TRACE_END_VOLTAGE_LEVEL(); 2116 2117 if (fast_validate) { 2118 BW_VAL_TRACE_SKIP(fast); 2119 goto validate_out; 2120 } 2121 2122 DC_FP_START(); 2123 dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel); 2124 DC_FP_END(); 2125 2126 BW_VAL_TRACE_END_WATERMARKS(); 2127 2128 goto validate_out; 2129 2130 validate_fail: 2131 DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n", 2132 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states])); 2133 2134 BW_VAL_TRACE_SKIP(fail); 2135 out = false; 2136 2137 validate_out: 2138 kfree(pipes); 2139 2140 BW_VAL_TRACE_FINISH(); 2141 2142 return out; 2143 } 2144 2145 void dcn30_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) 2146 { 2147 unsigned int i, j; 2148 unsigned int num_states = 0; 2149 2150 unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0}; 2151 unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0}; 2152 unsigned int optimal_uclk_for_dcfclk_sta_targets[DC__VOLTAGE_STATES] = {0}; 2153 unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0}; 2154 2155 unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {694, 875, 1000, 1200}; 2156 unsigned int num_dcfclk_sta_targets = 4; 2157 unsigned int num_uclk_states; 2158 2159 struct dc_bounding_box_max_clk dcn30_bb_max_clk; 2160 2161 memset(&dcn30_bb_max_clk, 0, sizeof(dcn30_bb_max_clk)); 2162 2163 if (dc->ctx->dc_bios->vram_info.num_chans) 2164 dcn3_0_soc.num_chans = dc->ctx->dc_bios->vram_info.num_chans; 2165 2166 DC_FP_START(); 2167 dcn30_fpu_update_dram_channel_width_bytes(dc); 2168 DC_FP_END(); 2169 2170 if (bw_params->clk_table.entries[0].memclk_mhz) { 2171 2172 for (i = 0; i < MAX_NUM_DPM_LVL; i++) { 2173 if (bw_params->clk_table.entries[i].dcfclk_mhz > dcn30_bb_max_clk.max_dcfclk_mhz) 2174 dcn30_bb_max_clk.max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; 2175 if (bw_params->clk_table.entries[i].dispclk_mhz > dcn30_bb_max_clk.max_dispclk_mhz) 2176 dcn30_bb_max_clk.max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz; 2177 if (bw_params->clk_table.entries[i].dppclk_mhz > dcn30_bb_max_clk.max_dppclk_mhz) 2178 dcn30_bb_max_clk.max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz; 2179 if (bw_params->clk_table.entries[i].phyclk_mhz > dcn30_bb_max_clk.max_phyclk_mhz) 2180 dcn30_bb_max_clk.max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz; 2181 } 2182 2183 DC_FP_START(); 2184 dcn30_fpu_update_max_clk(&dcn30_bb_max_clk); 2185 DC_FP_END(); 2186 2187 if (dcn30_bb_max_clk.max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { 2188 // If max DCFCLK is greater than the max DCFCLK STA target, insert into the DCFCLK STA target array 2189 dcfclk_sta_targets[num_dcfclk_sta_targets] = dcn30_bb_max_clk.max_dcfclk_mhz; 2190 num_dcfclk_sta_targets++; 2191 } else if (dcn30_bb_max_clk.max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { 2192 // If max DCFCLK is less than the max DCFCLK STA target, cap values and remove duplicates 2193 for (i = 0; i < num_dcfclk_sta_targets; i++) { 2194 if (dcfclk_sta_targets[i] > dcn30_bb_max_clk.max_dcfclk_mhz) { 2195 dcfclk_sta_targets[i] = dcn30_bb_max_clk.max_dcfclk_mhz; 2196 break; 2197 } 2198 } 2199 // Update size of array since we "removed" duplicates 2200 num_dcfclk_sta_targets = i + 1; 2201 } 2202 2203 num_uclk_states = bw_params->clk_table.num_entries; 2204 2205 // Calculate optimal dcfclk for each uclk 2206 for (i = 0; i < num_uclk_states; i++) { 2207 DC_FP_START(); 2208 dcn30_fpu_get_optimal_dcfclk_fclk_for_uclk(bw_params->clk_table.entries[i].memclk_mhz * 16, 2209 &optimal_dcfclk_for_uclk[i], NULL); 2210 DC_FP_END(); 2211 if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz) { 2212 optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz; 2213 } 2214 } 2215 2216 // Calculate optimal uclk for each dcfclk sta target 2217 for (i = 0; i < num_dcfclk_sta_targets; i++) { 2218 for (j = 0; j < num_uclk_states; j++) { 2219 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) { 2220 optimal_uclk_for_dcfclk_sta_targets[i] = 2221 bw_params->clk_table.entries[j].memclk_mhz * 16; 2222 break; 2223 } 2224 } 2225 } 2226 2227 i = 0; 2228 j = 0; 2229 // create the final dcfclk and uclk table 2230 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { 2231 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) { 2232 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; 2233 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; 2234 } else { 2235 if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= dcn30_bb_max_clk.max_dcfclk_mhz) { 2236 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; 2237 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16; 2238 } else { 2239 j = num_uclk_states; 2240 } 2241 } 2242 } 2243 2244 while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) { 2245 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; 2246 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; 2247 } 2248 2249 while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES && 2250 optimal_dcfclk_for_uclk[j] <= dcn30_bb_max_clk.max_dcfclk_mhz) { 2251 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; 2252 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16; 2253 } 2254 2255 dcn3_0_soc.num_states = num_states; 2256 DC_FP_START(); 2257 dcn30_fpu_update_bw_bounding_box(dc, bw_params, &dcn30_bb_max_clk, dcfclk_mhz, dram_speed_mts); 2258 DC_FP_END(); 2259 } 2260 } 2261 2262 static const struct resource_funcs dcn30_res_pool_funcs = { 2263 .destroy = dcn30_destroy_resource_pool, 2264 .link_enc_create = dcn30_link_encoder_create, 2265 .panel_cntl_create = dcn30_panel_cntl_create, 2266 .validate_bandwidth = dcn30_validate_bandwidth, 2267 .calculate_wm_and_dlg = dcn30_calculate_wm_and_dlg, 2268 .update_soc_for_wm_a = dcn30_update_soc_for_wm_a, 2269 .populate_dml_pipes = dcn30_populate_dml_pipes_from_context, 2270 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer, 2271 .add_stream_to_ctx = dcn30_add_stream_to_ctx, 2272 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, 2273 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 2274 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, 2275 .set_mcif_arb_params = dcn30_set_mcif_arb_params, 2276 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, 2277 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut, 2278 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut, 2279 .update_bw_bounding_box = dcn30_update_bw_bounding_box, 2280 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, 2281 }; 2282 2283 #define CTX ctx 2284 2285 #define REG(reg_name) \ 2286 (DCN_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name) 2287 2288 static uint32_t read_pipe_fuses(struct dc_context *ctx) 2289 { 2290 uint32_t value = REG_READ(CC_DC_PIPE_DIS); 2291 /* Support for max 6 pipes */ 2292 value = value & 0x3f; 2293 return value; 2294 } 2295 2296 static bool dcn30_resource_construct( 2297 uint8_t num_virtual_links, 2298 struct dc *dc, 2299 struct dcn30_resource_pool *pool) 2300 { 2301 int i; 2302 struct dc_context *ctx = dc->ctx; 2303 struct irq_service_init_data init_data; 2304 struct ddc_service_init_data ddc_init_data = {0}; 2305 uint32_t pipe_fuses = read_pipe_fuses(ctx); 2306 uint32_t num_pipes = 0; 2307 2308 if (!(pipe_fuses == 0 || pipe_fuses == 0x3e)) { 2309 BREAK_TO_DEBUGGER(); 2310 dm_error("DC: Unexpected fuse recipe for navi2x !\n"); 2311 /* fault to single pipe */ 2312 pipe_fuses = 0x3e; 2313 } 2314 2315 DC_FP_START(); 2316 2317 ctx->dc_bios->regs = &bios_regs; 2318 2319 pool->base.res_cap = &res_cap_dcn3; 2320 2321 pool->base.funcs = &dcn30_res_pool_funcs; 2322 2323 /************************************************* 2324 * Resource + asic cap harcoding * 2325 *************************************************/ 2326 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 2327 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; 2328 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator; 2329 dc->caps.max_downscale_ratio = 600; 2330 dc->caps.i2c_speed_in_khz = 100; 2331 dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a not applied by default*/ 2332 dc->caps.max_cursor_size = 256; 2333 dc->caps.min_horizontal_blanking_period = 80; 2334 dc->caps.dmdata_alloc_size = 2048; 2335 dc->caps.mall_size_per_mem_channel = 8; 2336 /* total size = mall per channel * num channels * 1024 * 1024 */ 2337 dc->caps.mall_size_total = dc->caps.mall_size_per_mem_channel * dc->ctx->dc_bios->vram_info.num_chans * 1048576; 2338 dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8; 2339 2340 dc->caps.max_slave_planes = 2; 2341 dc->caps.max_slave_yuv_planes = 2; 2342 dc->caps.max_slave_rgb_planes = 2; 2343 dc->caps.post_blend_color_processing = true; 2344 dc->caps.force_dp_tps4_for_cp2520 = true; 2345 dc->caps.extended_aux_timeout_support = true; 2346 dc->caps.dmcub_support = true; 2347 2348 /* Color pipeline capabilities */ 2349 dc->caps.color.dpp.dcn_arch = 1; 2350 dc->caps.color.dpp.input_lut_shared = 0; 2351 dc->caps.color.dpp.icsc = 1; 2352 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr 2353 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; 2354 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; 2355 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1; 2356 dc->caps.color.dpp.dgam_rom_caps.pq = 1; 2357 dc->caps.color.dpp.dgam_rom_caps.hlg = 1; 2358 dc->caps.color.dpp.post_csc = 1; 2359 dc->caps.color.dpp.gamma_corr = 1; 2360 dc->caps.color.dpp.dgam_rom_for_yuv = 0; 2361 2362 dc->caps.color.dpp.hw_3d_lut = 1; 2363 dc->caps.color.dpp.ogam_ram = 1; 2364 // no OGAM ROM on DCN3 2365 dc->caps.color.dpp.ogam_rom_caps.srgb = 0; 2366 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; 2367 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; 2368 dc->caps.color.dpp.ogam_rom_caps.pq = 0; 2369 dc->caps.color.dpp.ogam_rom_caps.hlg = 0; 2370 dc->caps.color.dpp.ocsc = 0; 2371 2372 dc->caps.color.mpc.gamut_remap = 1; 2373 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //3 2374 dc->caps.color.mpc.ogam_ram = 1; 2375 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; 2376 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; 2377 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; 2378 dc->caps.color.mpc.ogam_rom_caps.pq = 0; 2379 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 2380 dc->caps.color.mpc.ocsc = 1; 2381 2382 dc->caps.hdmi_frl_pcon_support = true; 2383 2384 /* read VBIOS LTTPR caps */ 2385 { 2386 if (ctx->dc_bios->funcs->get_lttpr_caps) { 2387 enum bp_result bp_query_result; 2388 uint8_t is_vbios_lttpr_enable = 0; 2389 2390 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable); 2391 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable; 2392 } 2393 2394 if (ctx->dc_bios->funcs->get_lttpr_interop) { 2395 enum bp_result bp_query_result; 2396 uint8_t is_vbios_interop_enabled = 0; 2397 2398 bp_query_result = ctx->dc_bios->funcs->get_lttpr_interop(ctx->dc_bios, 2399 &is_vbios_interop_enabled); 2400 dc->caps.vbios_lttpr_aware = (bp_query_result == BP_RESULT_OK) && !!is_vbios_interop_enabled; 2401 } 2402 } 2403 2404 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 2405 dc->debug = debug_defaults_drv; 2406 else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) { 2407 dc->debug = debug_defaults_diags; 2408 } else 2409 dc->debug = debug_defaults_diags; 2410 // Init the vm_helper 2411 if (dc->vm_helper) 2412 vm_helper_init(dc->vm_helper, 16); 2413 2414 /************************************************* 2415 * Create resources * 2416 *************************************************/ 2417 2418 /* Clock Sources for Pixel Clock*/ 2419 pool->base.clock_sources[DCN30_CLK_SRC_PLL0] = 2420 dcn30_clock_source_create(ctx, ctx->dc_bios, 2421 CLOCK_SOURCE_COMBO_PHY_PLL0, 2422 &clk_src_regs[0], false); 2423 pool->base.clock_sources[DCN30_CLK_SRC_PLL1] = 2424 dcn30_clock_source_create(ctx, ctx->dc_bios, 2425 CLOCK_SOURCE_COMBO_PHY_PLL1, 2426 &clk_src_regs[1], false); 2427 pool->base.clock_sources[DCN30_CLK_SRC_PLL2] = 2428 dcn30_clock_source_create(ctx, ctx->dc_bios, 2429 CLOCK_SOURCE_COMBO_PHY_PLL2, 2430 &clk_src_regs[2], false); 2431 pool->base.clock_sources[DCN30_CLK_SRC_PLL3] = 2432 dcn30_clock_source_create(ctx, ctx->dc_bios, 2433 CLOCK_SOURCE_COMBO_PHY_PLL3, 2434 &clk_src_regs[3], false); 2435 pool->base.clock_sources[DCN30_CLK_SRC_PLL4] = 2436 dcn30_clock_source_create(ctx, ctx->dc_bios, 2437 CLOCK_SOURCE_COMBO_PHY_PLL4, 2438 &clk_src_regs[4], false); 2439 pool->base.clock_sources[DCN30_CLK_SRC_PLL5] = 2440 dcn30_clock_source_create(ctx, ctx->dc_bios, 2441 CLOCK_SOURCE_COMBO_PHY_PLL5, 2442 &clk_src_regs[5], false); 2443 2444 pool->base.clk_src_count = DCN30_CLK_SRC_TOTAL; 2445 2446 /* todo: not reuse phy_pll registers */ 2447 pool->base.dp_clock_source = 2448 dcn30_clock_source_create(ctx, ctx->dc_bios, 2449 CLOCK_SOURCE_ID_DP_DTO, 2450 &clk_src_regs[0], true); 2451 2452 for (i = 0; i < pool->base.clk_src_count; i++) { 2453 if (pool->base.clock_sources[i] == NULL) { 2454 dm_error("DC: failed to create clock sources!\n"); 2455 BREAK_TO_DEBUGGER(); 2456 goto create_fail; 2457 } 2458 } 2459 2460 /* DCCG */ 2461 pool->base.dccg = dccg30_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 2462 if (pool->base.dccg == NULL) { 2463 dm_error("DC: failed to create dccg!\n"); 2464 BREAK_TO_DEBUGGER(); 2465 goto create_fail; 2466 } 2467 2468 /* PP Lib and SMU interfaces */ 2469 init_soc_bounding_box(dc, pool); 2470 2471 num_pipes = dcn3_0_ip.max_num_dpp; 2472 2473 for (i = 0; i < dcn3_0_ip.max_num_dpp; i++) 2474 if (pipe_fuses & 1 << i) 2475 num_pipes--; 2476 2477 dcn3_0_ip.max_num_dpp = num_pipes; 2478 dcn3_0_ip.max_num_otg = num_pipes; 2479 2480 dml_init_instance(&dc->dml, &dcn3_0_soc, &dcn3_0_ip, DML_PROJECT_DCN30); 2481 2482 /* IRQ */ 2483 init_data.ctx = dc->ctx; 2484 pool->base.irqs = dal_irq_service_dcn30_create(&init_data); 2485 if (!pool->base.irqs) 2486 goto create_fail; 2487 2488 /* HUBBUB */ 2489 pool->base.hubbub = dcn30_hubbub_create(ctx); 2490 if (pool->base.hubbub == NULL) { 2491 BREAK_TO_DEBUGGER(); 2492 dm_error("DC: failed to create hubbub!\n"); 2493 goto create_fail; 2494 } 2495 2496 /* HUBPs, DPPs, OPPs and TGs */ 2497 for (i = 0; i < pool->base.pipe_count; i++) { 2498 pool->base.hubps[i] = dcn30_hubp_create(ctx, i); 2499 if (pool->base.hubps[i] == NULL) { 2500 BREAK_TO_DEBUGGER(); 2501 dm_error( 2502 "DC: failed to create hubps!\n"); 2503 goto create_fail; 2504 } 2505 2506 pool->base.dpps[i] = dcn30_dpp_create(ctx, i); 2507 if (pool->base.dpps[i] == NULL) { 2508 BREAK_TO_DEBUGGER(); 2509 dm_error( 2510 "DC: failed to create dpps!\n"); 2511 goto create_fail; 2512 } 2513 } 2514 2515 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 2516 pool->base.opps[i] = dcn30_opp_create(ctx, i); 2517 if (pool->base.opps[i] == NULL) { 2518 BREAK_TO_DEBUGGER(); 2519 dm_error( 2520 "DC: failed to create output pixel processor!\n"); 2521 goto create_fail; 2522 } 2523 } 2524 2525 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 2526 pool->base.timing_generators[i] = dcn30_timing_generator_create( 2527 ctx, i); 2528 if (pool->base.timing_generators[i] == NULL) { 2529 BREAK_TO_DEBUGGER(); 2530 dm_error("DC: failed to create tg!\n"); 2531 goto create_fail; 2532 } 2533 } 2534 pool->base.timing_generator_count = i; 2535 /* PSR */ 2536 pool->base.psr = dmub_psr_create(ctx); 2537 2538 if (pool->base.psr == NULL) { 2539 dm_error("DC: failed to create PSR obj!\n"); 2540 BREAK_TO_DEBUGGER(); 2541 goto create_fail; 2542 } 2543 2544 /* ABM */ 2545 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 2546 pool->base.multiple_abms[i] = dmub_abm_create(ctx, 2547 &abm_regs[i], 2548 &abm_shift, 2549 &abm_mask); 2550 if (pool->base.multiple_abms[i] == NULL) { 2551 dm_error("DC: failed to create abm for pipe %d!\n", i); 2552 BREAK_TO_DEBUGGER(); 2553 goto create_fail; 2554 } 2555 } 2556 /* MPC and DSC */ 2557 pool->base.mpc = dcn30_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut); 2558 if (pool->base.mpc == NULL) { 2559 BREAK_TO_DEBUGGER(); 2560 dm_error("DC: failed to create mpc!\n"); 2561 goto create_fail; 2562 } 2563 2564 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 2565 pool->base.dscs[i] = dcn30_dsc_create(ctx, i); 2566 if (pool->base.dscs[i] == NULL) { 2567 BREAK_TO_DEBUGGER(); 2568 dm_error("DC: failed to create display stream compressor %d!\n", i); 2569 goto create_fail; 2570 } 2571 } 2572 2573 /* DWB and MMHUBBUB */ 2574 if (!dcn30_dwbc_create(ctx, &pool->base)) { 2575 BREAK_TO_DEBUGGER(); 2576 dm_error("DC: failed to create dwbc!\n"); 2577 goto create_fail; 2578 } 2579 2580 if (!dcn30_mmhubbub_create(ctx, &pool->base)) { 2581 BREAK_TO_DEBUGGER(); 2582 dm_error("DC: failed to create mcif_wb!\n"); 2583 goto create_fail; 2584 } 2585 2586 /* AUX and I2C */ 2587 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 2588 pool->base.engines[i] = dcn30_aux_engine_create(ctx, i); 2589 if (pool->base.engines[i] == NULL) { 2590 BREAK_TO_DEBUGGER(); 2591 dm_error( 2592 "DC:failed to create aux engine!!\n"); 2593 goto create_fail; 2594 } 2595 pool->base.hw_i2cs[i] = dcn30_i2c_hw_create(ctx, i); 2596 if (pool->base.hw_i2cs[i] == NULL) { 2597 BREAK_TO_DEBUGGER(); 2598 dm_error( 2599 "DC:failed to create hw i2c!!\n"); 2600 goto create_fail; 2601 } 2602 pool->base.sw_i2cs[i] = NULL; 2603 } 2604 2605 /* Audio, Stream Encoders including DIG and virtual, MPC 3D LUTs */ 2606 if (!resource_construct(num_virtual_links, dc, &pool->base, 2607 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? 2608 &res_create_funcs : &res_create_maximus_funcs))) 2609 goto create_fail; 2610 2611 /* HW Sequencer and Plane caps */ 2612 dcn30_hw_sequencer_construct(dc); 2613 2614 dc->caps.max_planes = pool->base.pipe_count; 2615 2616 for (i = 0; i < dc->caps.max_planes; ++i) 2617 dc->caps.planes[i] = plane_cap; 2618 2619 dc->cap_funcs = cap_funcs; 2620 2621 if (dc->ctx->dc_bios->fw_info.oem_i2c_present) { 2622 ddc_init_data.ctx = dc->ctx; 2623 ddc_init_data.link = NULL; 2624 ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id; 2625 ddc_init_data.id.enum_id = 0; 2626 ddc_init_data.id.type = OBJECT_TYPE_GENERIC; 2627 pool->base.oem_device = dal_ddc_service_create(&ddc_init_data); 2628 } else { 2629 pool->base.oem_device = NULL; 2630 } 2631 2632 DC_FP_END(); 2633 2634 return true; 2635 2636 create_fail: 2637 2638 DC_FP_END(); 2639 dcn30_resource_destruct(pool); 2640 2641 return false; 2642 } 2643 2644 struct resource_pool *dcn30_create_resource_pool( 2645 const struct dc_init_data *init_data, 2646 struct dc *dc) 2647 { 2648 struct dcn30_resource_pool *pool = 2649 kzalloc(sizeof(struct dcn30_resource_pool), GFP_KERNEL); 2650 2651 if (!pool) 2652 return NULL; 2653 2654 if (dcn30_resource_construct(init_data->num_virtual_links, dc, pool)) 2655 return &pool->base; 2656 2657 BREAK_TO_DEBUGGER(); 2658 kfree(pool); 2659 return NULL; 2660 } 2661