1 /*
2  * Copyright 2020 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 #include "reg_helper.h"
27 #include "dcn30_optc.h"
28 #include "dc.h"
29 #include "dcn_calc_math.h"
30 
31 #define REG(reg)\
32 	optc1->tg_regs->reg
33 
34 #define CTX \
35 	optc1->base.ctx
36 
37 #undef FN
38 #define FN(reg_name, field_name) \
39 	optc1->tg_shift->field_name, optc1->tg_mask->field_name
40 
41 void optc3_triplebuffer_lock(struct timing_generator *optc)
42 {
43 	struct optc *optc1 = DCN10TG_FROM_TG(optc);
44 
45 	REG_UPDATE(OTG_GLOBAL_CONTROL2,
46 		OTG_MASTER_UPDATE_LOCK_SEL, optc->inst);
47 
48 	REG_SET(OTG_VUPDATE_KEEPOUT, 0,
49 		OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, 1);
50 
51 	REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
52 		OTG_MASTER_UPDATE_LOCK, 1);
53 
54 	if (optc->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS)
55 		REG_WAIT(OTG_MASTER_UPDATE_LOCK,
56 				UPDATE_LOCK_STATUS, 1,
57 				1, 10);
58 }
59 
60 void optc3_lock_doublebuffer_enable(struct timing_generator *optc)
61 {
62 	struct optc *optc1 = DCN10TG_FROM_TG(optc);
63 	uint32_t v_blank_start = 0;
64 	uint32_t v_blank_end = 0;
65 	uint32_t h_blank_start = 0;
66 	uint32_t h_blank_end = 0;
67 
68 	REG_GET_2(OTG_V_BLANK_START_END,
69 		OTG_V_BLANK_START, &v_blank_start,
70 		OTG_V_BLANK_END, &v_blank_end);
71 	REG_GET_2(OTG_H_BLANK_START_END,
72 		OTG_H_BLANK_START, &h_blank_start,
73 		OTG_H_BLANK_END, &h_blank_end);
74 
75 	REG_UPDATE_2(OTG_GLOBAL_CONTROL1,
76 		MASTER_UPDATE_LOCK_DB_START_Y, v_blank_start,
77 		MASTER_UPDATE_LOCK_DB_END_Y, v_blank_end);
78 	REG_UPDATE_2(OTG_GLOBAL_CONTROL4,
79 		DIG_UPDATE_POSITION_X, 20,
80 		DIG_UPDATE_POSITION_Y, v_blank_start);
81 	REG_UPDATE_3(OTG_GLOBAL_CONTROL0,
82 		MASTER_UPDATE_LOCK_DB_START_X, h_blank_start - 200 - 1,
83 		MASTER_UPDATE_LOCK_DB_END_X, h_blank_end,
84 		MASTER_UPDATE_LOCK_DB_EN, 1);
85 	REG_UPDATE(OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, 1);
86 }
87 
88 void optc3_lock_doublebuffer_disable(struct timing_generator *optc)
89 {
90 	struct optc *optc1 = DCN10TG_FROM_TG(optc);
91 
92 	REG_UPDATE_2(OTG_GLOBAL_CONTROL0,
93 		MASTER_UPDATE_LOCK_DB_START_X, 0,
94 		MASTER_UPDATE_LOCK_DB_END_X, 0);
95 	REG_UPDATE_2(OTG_GLOBAL_CONTROL1,
96 		MASTER_UPDATE_LOCK_DB_START_Y, 0,
97 		MASTER_UPDATE_LOCK_DB_END_Y, 0);
98 
99 	REG_UPDATE(OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, 0);
100 	REG_UPDATE(OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_EN, 1);
101 }
102 
103 void optc3_lock(struct timing_generator *optc)
104 {
105 	struct optc *optc1 = DCN10TG_FROM_TG(optc);
106 
107 	REG_UPDATE(OTG_GLOBAL_CONTROL2,
108 		OTG_MASTER_UPDATE_LOCK_SEL, optc->inst);
109 	REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
110 		OTG_MASTER_UPDATE_LOCK, 1);
111 
112 	/* Should be fast, status does not update on maximus */
113 	if (optc->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS)
114 		REG_WAIT(OTG_MASTER_UPDATE_LOCK,
115 				UPDATE_LOCK_STATUS, 1,
116 				1, 10);
117 }
118 
119 void optc3_set_out_mux(struct timing_generator *optc, enum otg_out_mux_dest dest)
120 {
121 	struct optc *optc1 = DCN10TG_FROM_TG(optc);
122 
123 	REG_UPDATE(OTG_CONTROL, OTG_OUT_MUX, dest);
124 }
125 
126 void optc3_program_blank_color(struct timing_generator *optc,
127 		const struct tg_color *blank_color)
128 {
129 	struct optc *optc1 = DCN10TG_FROM_TG(optc);
130 
131 	REG_SET_3(OTG_BLANK_DATA_COLOR, 0,
132 		OTG_BLANK_DATA_COLOR_BLUE_CB, blank_color->color_b_cb,
133 		OTG_BLANK_DATA_COLOR_GREEN_Y, blank_color->color_g_y,
134 		OTG_BLANK_DATA_COLOR_RED_CR, blank_color->color_r_cr);
135 
136 	REG_SET_3(OTG_BLANK_DATA_COLOR_EXT, 0,
137 		OTG_BLANK_DATA_COLOR_BLUE_CB_EXT, blank_color->color_b_cb >> 10,
138 		OTG_BLANK_DATA_COLOR_GREEN_Y_EXT, blank_color->color_g_y >> 10,
139 		OTG_BLANK_DATA_COLOR_RED_CR_EXT, blank_color->color_r_cr >> 10);
140 }
141 
142 void optc3_set_drr_trigger_window(struct timing_generator *optc,
143 		uint32_t window_start, uint32_t window_end)
144 {
145 	struct optc *optc1 = DCN10TG_FROM_TG(optc);
146 
147 	REG_SET_2(OTG_DRR_TRIGGER_WINDOW, 0,
148 		OTG_DRR_TRIGGER_WINDOW_START_X, window_start,
149 		OTG_DRR_TRIGGER_WINDOW_END_X, window_end);
150 }
151 
152 void optc3_set_vtotal_change_limit(struct timing_generator *optc,
153 		uint32_t limit)
154 {
155 	struct optc *optc1 = DCN10TG_FROM_TG(optc);
156 
157 
158 	REG_SET(OTG_DRR_V_TOTAL_CHANGE, 0,
159 		OTG_DRR_V_TOTAL_CHANGE_LIMIT, limit);
160 }
161 
162 
163 /* Set DSC-related configuration.
164  *   dsc_mode: 0 disables DSC, other values enable DSC in specified format
165  *   sc_bytes_per_pixel: Bytes per pixel in u3.28 format
166  *   dsc_slice_width: Slice width in pixels
167  */
168 void optc3_set_dsc_config(struct timing_generator *optc,
169 		enum optc_dsc_mode dsc_mode,
170 		uint32_t dsc_bytes_per_pixel,
171 		uint32_t dsc_slice_width)
172 {
173 	struct optc *optc1 = DCN10TG_FROM_TG(optc);
174 
175 	optc2_set_dsc_config(optc, dsc_mode, dsc_bytes_per_pixel,
176 		dsc_slice_width);
177 
178 		REG_UPDATE(OTG_V_SYNC_A_CNTL, OTG_V_SYNC_MODE, 0);
179 
180 }
181 
182 void optc3_set_odm_bypass(struct timing_generator *optc,
183 		const struct dc_crtc_timing *dc_crtc_timing)
184 {
185 	struct optc *optc1 = DCN10TG_FROM_TG(optc);
186 	enum h_timing_div_mode h_div = H_TIMING_NO_DIV;
187 
188 	REG_SET_5(OPTC_DATA_SOURCE_SELECT, 0,
189 			OPTC_NUM_OF_INPUT_SEGMENT, 0,
190 			OPTC_SEG0_SRC_SEL, optc->inst,
191 			OPTC_SEG1_SRC_SEL, 0xf,
192 			OPTC_SEG2_SRC_SEL, 0xf,
193 			OPTC_SEG3_SRC_SEL, 0xf
194 			);
195 
196 	h_div = optc1_is_two_pixels_per_containter(dc_crtc_timing);
197 	REG_SET(OTG_H_TIMING_CNTL, 0,
198 			OTG_H_TIMING_DIV_MODE, h_div);
199 
200 	REG_SET(OPTC_MEMORY_CONFIG, 0,
201 			OPTC_MEM_SEL, 0);
202 	optc1->opp_count = 1;
203 }
204 
205 static void optc3_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt,
206 		struct dc_crtc_timing *timing)
207 {
208 	struct optc *optc1 = DCN10TG_FROM_TG(optc);
209 	int mpcc_hactive = (timing->h_addressable + timing->h_border_left + timing->h_border_right)
210 			/ opp_cnt;
211 	uint32_t memory_mask = 0;
212 
213 	/* TODO: In pseudocode but does not affect maximus, delete comment if we dont need on asic
214 	 * REG_SET(OTG_GLOBAL_CONTROL2, 0, GLOBAL_UPDATE_LOCK_EN, 1);
215 	 * Program OTG register MASTER_UPDATE_LOCK_DB_X/Y to the position before DP frame start
216 	 * REG_SET_2(OTG_GLOBAL_CONTROL1, 0,
217 	 *		MASTER_UPDATE_LOCK_DB_X, 160,
218 	 *		MASTER_UPDATE_LOCK_DB_Y, 240);
219 	 */
220 
221 	ASSERT(opp_cnt == 2 || opp_cnt == 4);
222 
223 	/* 2 pieces of memory required for up to 5120 displays, 4 for up to 8192,
224 	 * however, for ODM combine we can simplify by always using 4.
225 	 */
226 	if (opp_cnt == 2) {
227 		/* To make sure there's no memory overlap, each instance "reserves" 2
228 		 * memories and they are uniquely combined here.
229 		 */
230 		memory_mask = 0x3 << (opp_id[0] * 2) | 0x3 << (opp_id[1] * 2);
231 	} else if (opp_cnt == 4) {
232 		/* To make sure there's no memory overlap, each instance "reserves" 1
233 		 * memory and they are uniquely combined here.
234 		 */
235 		memory_mask = 0x1 << (opp_id[0] * 2) | 0x1 << (opp_id[1] * 2) | 0x1 << (opp_id[2] * 2) | 0x1 << (opp_id[3] * 2);
236 	}
237 
238 	if (REG(OPTC_MEMORY_CONFIG))
239 		REG_SET(OPTC_MEMORY_CONFIG, 0,
240 			OPTC_MEM_SEL, memory_mask);
241 
242 	if (opp_cnt == 2) {
243 		REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0,
244 				OPTC_NUM_OF_INPUT_SEGMENT, 1,
245 				OPTC_SEG0_SRC_SEL, opp_id[0],
246 				OPTC_SEG1_SRC_SEL, opp_id[1]);
247 	} else if (opp_cnt == 4) {
248 		REG_SET_5(OPTC_DATA_SOURCE_SELECT, 0,
249 				OPTC_NUM_OF_INPUT_SEGMENT, 3,
250 				OPTC_SEG0_SRC_SEL, opp_id[0],
251 				OPTC_SEG1_SRC_SEL, opp_id[1],
252 				OPTC_SEG2_SRC_SEL, opp_id[2],
253 				OPTC_SEG3_SRC_SEL, opp_id[3]);
254 	}
255 
256 	REG_UPDATE(OPTC_WIDTH_CONTROL,
257 			OPTC_SEGMENT_WIDTH, mpcc_hactive);
258 
259 	REG_SET(OTG_H_TIMING_CNTL, 0, OTG_H_TIMING_DIV_MODE, opp_cnt - 1);
260 	optc1->opp_count = opp_cnt;
261 }
262 
263 /**
264  * optc3_set_timing_double_buffer() - DRR double buffering control
265  *
266  * Sets double buffer point for V_TOTAL, H_TOTAL, VTOTAL_MIN,
267  * VTOTAL_MAX, VTOTAL_MIN_SEL and VTOTAL_MAX_SEL registers.
268  *
269  * Options: any time,  start of frame, dp start of frame (range timing)
270  */
271 static void optc3_set_timing_double_buffer(struct timing_generator *optc, bool enable)
272 {
273 	struct optc *optc1 = DCN10TG_FROM_TG(optc);
274 	uint32_t mode = enable ? 2 : 0;
275 
276 	REG_UPDATE(OTG_DOUBLE_BUFFER_CONTROL,
277 		   OTG_DRR_TIMING_DBUF_UPDATE_MODE, mode);
278 }
279 
280 void optc3_tg_init(struct timing_generator *optc)
281 {
282 	optc3_set_timing_double_buffer(optc, true);
283 	optc1_clear_optc_underflow(optc);
284 }
285 
286 static struct timing_generator_funcs dcn30_tg_funcs = {
287 		.validate_timing = optc1_validate_timing,
288 		.program_timing = optc1_program_timing,
289 		.setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0,
290 		.setup_vertical_interrupt1 = optc1_setup_vertical_interrupt1,
291 		.setup_vertical_interrupt2 = optc1_setup_vertical_interrupt2,
292 		.program_global_sync = optc1_program_global_sync,
293 		.enable_crtc = optc2_enable_crtc,
294 		.disable_crtc = optc1_disable_crtc,
295 		/* used by enable_timing_synchronization. Not need for FPGA */
296 		.is_counter_moving = optc1_is_counter_moving,
297 		.get_position = optc1_get_position,
298 		.get_frame_count = optc1_get_vblank_counter,
299 		.get_scanoutpos = optc1_get_crtc_scanoutpos,
300 		.get_otg_active_size = optc1_get_otg_active_size,
301 		.set_early_control = optc1_set_early_control,
302 		/* used by enable_timing_synchronization. Not need for FPGA */
303 		.wait_for_state = optc1_wait_for_state,
304 		.set_blank_color = optc3_program_blank_color,
305 		.did_triggered_reset_occur = optc1_did_triggered_reset_occur,
306 		.triplebuffer_lock = optc3_triplebuffer_lock,
307 		.triplebuffer_unlock = optc2_triplebuffer_unlock,
308 		.enable_reset_trigger = optc1_enable_reset_trigger,
309 		.enable_crtc_reset = optc1_enable_crtc_reset,
310 		.disable_reset_trigger = optc1_disable_reset_trigger,
311 		.lock = optc3_lock,
312 		.is_locked = optc1_is_locked,
313 		.unlock = optc1_unlock,
314 		.lock_doublebuffer_enable = optc3_lock_doublebuffer_enable,
315 		.lock_doublebuffer_disable = optc3_lock_doublebuffer_disable,
316 		.enable_optc_clock = optc1_enable_optc_clock,
317 		.set_drr = optc1_set_drr,
318 		.set_static_screen_control = optc1_set_static_screen_control,
319 		.program_stereo = optc1_program_stereo,
320 		.is_stereo_left_eye = optc1_is_stereo_left_eye,
321 		.tg_init = optc3_tg_init,
322 		.is_tg_enabled = optc1_is_tg_enabled,
323 		.is_optc_underflow_occurred = optc1_is_optc_underflow_occurred,
324 		.clear_optc_underflow = optc1_clear_optc_underflow,
325 		.setup_global_swap_lock = NULL,
326 		.get_crc = optc1_get_crc,
327 		.configure_crc = optc2_configure_crc,
328 		.set_dsc_config = optc3_set_dsc_config,
329 		.set_dwb_source = NULL,
330 		.set_odm_bypass = optc3_set_odm_bypass,
331 		.set_odm_combine = optc3_set_odm_combine,
332 		.get_optc_source = optc2_get_optc_source,
333 		.set_out_mux = optc3_set_out_mux,
334 		.set_drr_trigger_window = optc3_set_drr_trigger_window,
335 		.set_vtotal_change_limit = optc3_set_vtotal_change_limit,
336 		.set_gsl = optc2_set_gsl,
337 		.set_gsl_source_select = optc2_set_gsl_source_select,
338 		.set_vtg_params = optc1_set_vtg_params,
339 		.program_manual_trigger = optc2_program_manual_trigger,
340 		.setup_manual_trigger = optc2_setup_manual_trigger,
341 		.get_hw_timing = optc1_get_hw_timing,
342 };
343 
344 void dcn30_timing_generator_init(struct optc *optc1)
345 {
346 	optc1->base.funcs = &dcn30_tg_funcs;
347 
348 	optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1;
349 	optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1;
350 
351 	optc1->min_h_blank = 32;
352 	optc1->min_v_blank = 3;
353 	optc1->min_v_blank_interlace = 5;
354 	optc1->min_h_sync_width = 4;
355 	optc1->min_v_sync_width = 1;
356 }
357 
358