1 /* Copyright 2020 Advanced Micro Devices, Inc. 2 * 3 * Permission is hereby granted, free of charge, to any person obtaining a 4 * copy of this software and associated documentation files (the "Software"), 5 * to deal in the Software without restriction, including without limitation 6 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 7 * and/or sell copies of the Software, and to permit persons to whom the 8 * Software is furnished to do so, subject to the following conditions: 9 * 10 * The above copyright notice and this permission notice shall be included in 11 * all copies or substantial portions of the Software. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 17 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 19 * OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * Authors: AMD 22 * 23 */ 24 25 #ifndef __DC_MPCC_DCN30_H__ 26 #define __DC_MPCC_DCN30_H__ 27 28 #include "dcn20/dcn20_mpc.h" 29 30 #define MAX_RMU 3 31 32 #define TO_DCN30_MPC(mpc_base) \ 33 container_of(mpc_base, struct dcn30_mpc, base) 34 35 #ifdef SRII_MPC_RMU 36 #undef SRII_MPC_RMU 37 38 #define SRII_MPC_RMU(reg_name, block, id)\ 39 .RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 40 mm ## block ## id ## _ ## reg_name 41 42 #endif 43 44 45 #define MPC_REG_LIST_DCN3_0(inst)\ 46 MPC_COMMON_REG_LIST_DCN1_0(inst),\ 47 SRII(MPCC_TOP_GAIN, MPCC, inst),\ 48 SRII(MPCC_BOT_GAIN_INSIDE, MPCC, inst),\ 49 SRII(MPCC_BOT_GAIN_OUTSIDE, MPCC, inst),\ 50 SRII(MPCC_MEM_PWR_CTRL, MPCC, inst),\ 51 SRII(MPCC_OGAM_LUT_INDEX, MPCC_OGAM, inst),\ 52 SRII(MPCC_OGAM_LUT_DATA, MPCC_OGAM, inst), \ 53 SRII(MPCC_GAMUT_REMAP_COEF_FORMAT, MPCC_OGAM, inst),\ 54 SRII(MPCC_GAMUT_REMAP_MODE, MPCC_OGAM, inst),\ 55 SRII(MPC_GAMUT_REMAP_C11_C12_A, MPCC_OGAM, inst),\ 56 SRII(MPC_GAMUT_REMAP_C33_C34_A, MPCC_OGAM, inst),\ 57 SRII(MPC_GAMUT_REMAP_C11_C12_B, MPCC_OGAM, inst),\ 58 SRII(MPC_GAMUT_REMAP_C33_C34_B, MPCC_OGAM, inst),\ 59 SRII(MPCC_OGAM_RAMA_START_CNTL_B, MPCC_OGAM, inst),\ 60 SRII(MPCC_OGAM_RAMA_START_CNTL_G, MPCC_OGAM, inst),\ 61 SRII(MPCC_OGAM_RAMA_START_CNTL_R, MPCC_OGAM, inst),\ 62 SRII(MPCC_OGAM_RAMA_START_SLOPE_CNTL_B, MPCC_OGAM, inst),\ 63 SRII(MPCC_OGAM_RAMA_START_SLOPE_CNTL_G, MPCC_OGAM, inst),\ 64 SRII(MPCC_OGAM_RAMA_START_SLOPE_CNTL_R, MPCC_OGAM, inst),\ 65 SRII(MPCC_OGAM_RAMA_END_CNTL1_B, MPCC_OGAM, inst),\ 66 SRII(MPCC_OGAM_RAMA_END_CNTL2_B, MPCC_OGAM, inst),\ 67 SRII(MPCC_OGAM_RAMA_END_CNTL1_G, MPCC_OGAM, inst),\ 68 SRII(MPCC_OGAM_RAMA_END_CNTL2_G, MPCC_OGAM, inst),\ 69 SRII(MPCC_OGAM_RAMA_END_CNTL1_R, MPCC_OGAM, inst),\ 70 SRII(MPCC_OGAM_RAMA_END_CNTL2_R, MPCC_OGAM, inst),\ 71 SRII(MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM, inst),\ 72 SRII(MPCC_OGAM_RAMA_REGION_32_33, MPCC_OGAM, inst),\ 73 SRII(MPCC_OGAM_RAMA_OFFSET_B, MPCC_OGAM, inst),\ 74 SRII(MPCC_OGAM_RAMA_OFFSET_G, MPCC_OGAM, inst),\ 75 SRII(MPCC_OGAM_RAMA_OFFSET_R, MPCC_OGAM, inst),\ 76 SRII(MPCC_OGAM_RAMA_START_BASE_CNTL_B, MPCC_OGAM, inst),\ 77 SRII(MPCC_OGAM_RAMA_START_BASE_CNTL_G, MPCC_OGAM, inst),\ 78 SRII(MPCC_OGAM_RAMA_START_BASE_CNTL_R, MPCC_OGAM, inst),\ 79 SRII(MPCC_OGAM_RAMB_START_CNTL_B, MPCC_OGAM, inst),\ 80 SRII(MPCC_OGAM_RAMB_START_CNTL_G, MPCC_OGAM, inst),\ 81 SRII(MPCC_OGAM_RAMB_START_CNTL_R, MPCC_OGAM, inst),\ 82 SRII(MPCC_OGAM_RAMB_START_SLOPE_CNTL_B, MPCC_OGAM, inst),\ 83 SRII(MPCC_OGAM_RAMB_START_SLOPE_CNTL_G, MPCC_OGAM, inst),\ 84 SRII(MPCC_OGAM_RAMB_START_SLOPE_CNTL_R, MPCC_OGAM, inst),\ 85 SRII(MPCC_OGAM_RAMB_END_CNTL1_B, MPCC_OGAM, inst),\ 86 SRII(MPCC_OGAM_RAMB_END_CNTL2_B, MPCC_OGAM, inst),\ 87 SRII(MPCC_OGAM_RAMB_END_CNTL1_G, MPCC_OGAM, inst),\ 88 SRII(MPCC_OGAM_RAMB_END_CNTL2_G, MPCC_OGAM, inst),\ 89 SRII(MPCC_OGAM_RAMB_END_CNTL1_R, MPCC_OGAM, inst),\ 90 SRII(MPCC_OGAM_RAMB_END_CNTL2_R, MPCC_OGAM, inst),\ 91 SRII(MPCC_OGAM_RAMB_REGION_0_1, MPCC_OGAM, inst),\ 92 SRII(MPCC_OGAM_RAMB_REGION_32_33, MPCC_OGAM, inst),\ 93 SRII(MPCC_OGAM_RAMB_OFFSET_B, MPCC_OGAM, inst),\ 94 SRII(MPCC_OGAM_RAMB_OFFSET_G, MPCC_OGAM, inst),\ 95 SRII(MPCC_OGAM_RAMB_OFFSET_R, MPCC_OGAM, inst),\ 96 SRII(MPCC_OGAM_RAMB_START_BASE_CNTL_B, MPCC_OGAM, inst),\ 97 SRII(MPCC_OGAM_RAMB_START_BASE_CNTL_G, MPCC_OGAM, inst),\ 98 SRII(MPCC_OGAM_RAMB_START_BASE_CNTL_R, MPCC_OGAM, inst),\ 99 SRII(MPCC_OGAM_CONTROL, MPCC_OGAM, inst),\ 100 SRII(MPCC_OGAM_LUT_CONTROL, MPCC_OGAM, inst) 101 102 /* 103 SRII(MPCC_OGAM_LUT_RAM_CONTROL, MPCC_OGAM, inst),\ 104 SRII(MPCC_OGAM_MODE, MPCC_OGAM, inst) 105 */ 106 107 #define MPC_OUT_MUX_REG_LIST_DCN3_0(inst) \ 108 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(inst),\ 109 SRII(CSC_MODE, MPC_OUT, inst),\ 110 SRII(CSC_C11_C12_A, MPC_OUT, inst),\ 111 SRII(CSC_C33_C34_A, MPC_OUT, inst),\ 112 SRII(CSC_C11_C12_B, MPC_OUT, inst),\ 113 SRII(CSC_C33_C34_B, MPC_OUT, inst),\ 114 SRII(DENORM_CONTROL, MPC_OUT, inst),\ 115 SRII(DENORM_CLAMP_G_Y, MPC_OUT, inst),\ 116 SRII(DENORM_CLAMP_B_CB, MPC_OUT, inst), \ 117 SR(MPC_OUT_CSC_COEF_FORMAT) 118 119 #define MPC_RMU_GLOBAL_REG_LIST_DCN3AG \ 120 SR(MPC_RMU_CONTROL),\ 121 SR(MPC_RMU_MEM_PWR_CTRL) 122 123 #define MPC_RMU_REG_LIST_DCN3AG(inst) \ 124 SRII(SHAPER_CONTROL, MPC_RMU, inst),\ 125 SRII(SHAPER_OFFSET_R, MPC_RMU, inst),\ 126 SRII(SHAPER_OFFSET_G, MPC_RMU, inst),\ 127 SRII(SHAPER_OFFSET_B, MPC_RMU, inst),\ 128 SRII(SHAPER_SCALE_R, MPC_RMU, inst),\ 129 SRII(SHAPER_SCALE_G_B, MPC_RMU, inst),\ 130 SRII(SHAPER_LUT_INDEX, MPC_RMU, inst),\ 131 SRII(SHAPER_LUT_DATA, MPC_RMU, inst),\ 132 SRII(SHAPER_LUT_WRITE_EN_MASK, MPC_RMU, inst),\ 133 SRII(SHAPER_RAMA_START_CNTL_B, MPC_RMU, inst),\ 134 SRII(SHAPER_RAMA_START_CNTL_G, MPC_RMU, inst),\ 135 SRII(SHAPER_RAMA_START_CNTL_R, MPC_RMU, inst),\ 136 SRII(SHAPER_RAMA_END_CNTL_B, MPC_RMU, inst),\ 137 SRII(SHAPER_RAMA_END_CNTL_G, MPC_RMU, inst),\ 138 SRII(SHAPER_RAMA_END_CNTL_R, MPC_RMU, inst),\ 139 SRII(SHAPER_RAMA_REGION_0_1, MPC_RMU, inst),\ 140 SRII(SHAPER_RAMA_REGION_2_3, MPC_RMU, inst),\ 141 SRII(SHAPER_RAMA_REGION_4_5, MPC_RMU, inst),\ 142 SRII(SHAPER_RAMA_REGION_6_7, MPC_RMU, inst),\ 143 SRII(SHAPER_RAMA_REGION_8_9, MPC_RMU, inst),\ 144 SRII(SHAPER_RAMA_REGION_10_11, MPC_RMU, inst),\ 145 SRII(SHAPER_RAMA_REGION_12_13, MPC_RMU, inst),\ 146 SRII(SHAPER_RAMA_REGION_14_15, MPC_RMU, inst),\ 147 SRII(SHAPER_RAMA_REGION_16_17, MPC_RMU, inst),\ 148 SRII(SHAPER_RAMA_REGION_18_19, MPC_RMU, inst),\ 149 SRII(SHAPER_RAMA_REGION_20_21, MPC_RMU, inst),\ 150 SRII(SHAPER_RAMA_REGION_22_23, MPC_RMU, inst),\ 151 SRII(SHAPER_RAMA_REGION_24_25, MPC_RMU, inst),\ 152 SRII(SHAPER_RAMA_REGION_26_27, MPC_RMU, inst),\ 153 SRII(SHAPER_RAMA_REGION_28_29, MPC_RMU, inst),\ 154 SRII(SHAPER_RAMA_REGION_30_31, MPC_RMU, inst),\ 155 SRII(SHAPER_RAMA_REGION_32_33, MPC_RMU, inst),\ 156 SRII(SHAPER_RAMB_START_CNTL_B, MPC_RMU, inst),\ 157 SRII(SHAPER_RAMB_START_CNTL_G, MPC_RMU, inst),\ 158 SRII(SHAPER_RAMB_START_CNTL_R, MPC_RMU, inst),\ 159 SRII(SHAPER_RAMB_END_CNTL_B, MPC_RMU, inst),\ 160 SRII(SHAPER_RAMB_END_CNTL_G, MPC_RMU, inst),\ 161 SRII(SHAPER_RAMB_END_CNTL_R, MPC_RMU, inst),\ 162 SRII(SHAPER_RAMB_REGION_0_1, MPC_RMU, inst),\ 163 SRII(SHAPER_RAMB_REGION_2_3, MPC_RMU, inst),\ 164 SRII(SHAPER_RAMB_REGION_4_5, MPC_RMU, inst),\ 165 SRII(SHAPER_RAMB_REGION_6_7, MPC_RMU, inst),\ 166 SRII(SHAPER_RAMB_REGION_8_9, MPC_RMU, inst),\ 167 SRII(SHAPER_RAMB_REGION_10_11, MPC_RMU, inst),\ 168 SRII(SHAPER_RAMB_REGION_12_13, MPC_RMU, inst),\ 169 SRII(SHAPER_RAMB_REGION_14_15, MPC_RMU, inst),\ 170 SRII(SHAPER_RAMB_REGION_16_17, MPC_RMU, inst),\ 171 SRII(SHAPER_RAMB_REGION_18_19, MPC_RMU, inst),\ 172 SRII(SHAPER_RAMB_REGION_20_21, MPC_RMU, inst),\ 173 SRII(SHAPER_RAMB_REGION_22_23, MPC_RMU, inst),\ 174 SRII(SHAPER_RAMB_REGION_24_25, MPC_RMU, inst),\ 175 SRII(SHAPER_RAMB_REGION_26_27, MPC_RMU, inst),\ 176 SRII(SHAPER_RAMB_REGION_28_29, MPC_RMU, inst),\ 177 SRII(SHAPER_RAMB_REGION_30_31, MPC_RMU, inst),\ 178 SRII(SHAPER_RAMB_REGION_32_33, MPC_RMU, inst),\ 179 SRII_MPC_RMU(3DLUT_MODE, MPC_RMU, inst),\ 180 SRII_MPC_RMU(3DLUT_INDEX, MPC_RMU, inst),\ 181 SRII_MPC_RMU(3DLUT_DATA, MPC_RMU, inst),\ 182 SRII_MPC_RMU(3DLUT_DATA_30BIT, MPC_RMU, inst),\ 183 SRII_MPC_RMU(3DLUT_READ_WRITE_CONTROL, MPC_RMU, inst),\ 184 SRII_MPC_RMU(3DLUT_OUT_NORM_FACTOR, MPC_RMU, inst),\ 185 SRII_MPC_RMU(3DLUT_OUT_OFFSET_R, MPC_RMU, inst),\ 186 SRII_MPC_RMU(3DLUT_OUT_OFFSET_G, MPC_RMU, inst),\ 187 SRII_MPC_RMU(3DLUT_OUT_OFFSET_B, MPC_RMU, inst) 188 189 190 #define MPC_DWB_MUX_REG_LIST_DCN3_0(inst) \ 191 SRII_DWB(DWB_MUX, MUX, MPC_DWB, inst) 192 193 #define MPC_REG_VARIABLE_LIST_DCN3_0 \ 194 MPC_REG_VARIABLE_LIST_DCN2_0 \ 195 uint32_t DWB_MUX[MAX_DWB]; \ 196 uint32_t MPCC_GAMUT_REMAP_COEF_FORMAT[MAX_MPCC]; \ 197 uint32_t MPCC_GAMUT_REMAP_MODE[MAX_MPCC]; \ 198 uint32_t MPC_GAMUT_REMAP_C11_C12_A[MAX_MPCC]; \ 199 uint32_t MPC_GAMUT_REMAP_C33_C34_A[MAX_MPCC]; \ 200 uint32_t MPC_GAMUT_REMAP_C11_C12_B[MAX_MPCC]; \ 201 uint32_t MPC_GAMUT_REMAP_C33_C34_B[MAX_MPCC]; \ 202 uint32_t MPC_RMU_CONTROL; \ 203 uint32_t MPC_RMU_MEM_PWR_CTRL; \ 204 uint32_t SHAPER_CONTROL[MAX_RMU]; \ 205 uint32_t SHAPER_OFFSET_R[MAX_RMU]; \ 206 uint32_t SHAPER_OFFSET_G[MAX_RMU]; \ 207 uint32_t SHAPER_OFFSET_B[MAX_RMU]; \ 208 uint32_t SHAPER_SCALE_R[MAX_RMU]; \ 209 uint32_t SHAPER_SCALE_G_B[MAX_RMU]; \ 210 uint32_t SHAPER_LUT_INDEX[MAX_RMU]; \ 211 uint32_t SHAPER_LUT_DATA[MAX_RMU]; \ 212 uint32_t SHAPER_LUT_WRITE_EN_MASK[MAX_RMU]; \ 213 uint32_t SHAPER_RAMA_START_CNTL_B[MAX_RMU]; \ 214 uint32_t SHAPER_RAMA_START_CNTL_G[MAX_RMU]; \ 215 uint32_t SHAPER_RAMA_START_CNTL_R[MAX_RMU]; \ 216 uint32_t SHAPER_RAMA_END_CNTL_B[MAX_RMU]; \ 217 uint32_t SHAPER_RAMA_END_CNTL_G[MAX_RMU]; \ 218 uint32_t SHAPER_RAMA_END_CNTL_R[MAX_RMU]; \ 219 uint32_t SHAPER_RAMA_REGION_0_1[MAX_RMU]; \ 220 uint32_t SHAPER_RAMA_REGION_2_3[MAX_RMU]; \ 221 uint32_t SHAPER_RAMA_REGION_4_5[MAX_RMU]; \ 222 uint32_t SHAPER_RAMA_REGION_6_7[MAX_RMU]; \ 223 uint32_t SHAPER_RAMA_REGION_8_9[MAX_RMU]; \ 224 uint32_t SHAPER_RAMA_REGION_10_11[MAX_RMU]; \ 225 uint32_t SHAPER_RAMA_REGION_12_13[MAX_RMU]; \ 226 uint32_t SHAPER_RAMA_REGION_14_15[MAX_RMU]; \ 227 uint32_t SHAPER_RAMA_REGION_16_17[MAX_RMU]; \ 228 uint32_t SHAPER_RAMA_REGION_18_19[MAX_RMU]; \ 229 uint32_t SHAPER_RAMA_REGION_20_21[MAX_RMU]; \ 230 uint32_t SHAPER_RAMA_REGION_22_23[MAX_RMU]; \ 231 uint32_t SHAPER_RAMA_REGION_24_25[MAX_RMU]; \ 232 uint32_t SHAPER_RAMA_REGION_26_27[MAX_RMU]; \ 233 uint32_t SHAPER_RAMA_REGION_28_29[MAX_RMU]; \ 234 uint32_t SHAPER_RAMA_REGION_30_31[MAX_RMU]; \ 235 uint32_t SHAPER_RAMA_REGION_32_33[MAX_RMU]; \ 236 uint32_t MPCC_OGAM_RAMA_START_SLOPE_CNTL_B[MAX_MPCC]; \ 237 uint32_t MPCC_OGAM_RAMA_START_SLOPE_CNTL_G[MAX_MPCC]; \ 238 uint32_t MPCC_OGAM_RAMA_START_SLOPE_CNTL_R[MAX_MPCC]; \ 239 uint32_t MPCC_OGAM_RAMA_OFFSET_B[MAX_MPCC]; \ 240 uint32_t MPCC_OGAM_RAMA_OFFSET_G[MAX_MPCC]; \ 241 uint32_t MPCC_OGAM_RAMA_OFFSET_R[MAX_MPCC]; \ 242 uint32_t MPCC_OGAM_RAMA_START_BASE_CNTL_B[MAX_MPCC]; \ 243 uint32_t MPCC_OGAM_RAMA_START_BASE_CNTL_G[MAX_MPCC]; \ 244 uint32_t MPCC_OGAM_RAMA_START_BASE_CNTL_R[MAX_MPCC];\ 245 uint32_t SHAPER_RAMB_START_CNTL_B[MAX_RMU]; \ 246 uint32_t SHAPER_RAMB_START_CNTL_G[MAX_RMU]; \ 247 uint32_t SHAPER_RAMB_START_CNTL_R[MAX_RMU]; \ 248 uint32_t SHAPER_RAMB_END_CNTL_B[MAX_RMU]; \ 249 uint32_t SHAPER_RAMB_END_CNTL_G[MAX_RMU]; \ 250 uint32_t SHAPER_RAMB_END_CNTL_R[MAX_RMU]; \ 251 uint32_t SHAPER_RAMB_REGION_0_1[MAX_RMU]; \ 252 uint32_t SHAPER_RAMB_REGION_2_3[MAX_RMU]; \ 253 uint32_t SHAPER_RAMB_REGION_4_5[MAX_RMU]; \ 254 uint32_t SHAPER_RAMB_REGION_6_7[MAX_RMU]; \ 255 uint32_t SHAPER_RAMB_REGION_8_9[MAX_RMU]; \ 256 uint32_t SHAPER_RAMB_REGION_10_11[MAX_RMU]; \ 257 uint32_t SHAPER_RAMB_REGION_12_13[MAX_RMU]; \ 258 uint32_t SHAPER_RAMB_REGION_14_15[MAX_RMU]; \ 259 uint32_t SHAPER_RAMB_REGION_16_17[MAX_RMU]; \ 260 uint32_t SHAPER_RAMB_REGION_18_19[MAX_RMU]; \ 261 uint32_t SHAPER_RAMB_REGION_20_21[MAX_RMU]; \ 262 uint32_t SHAPER_RAMB_REGION_22_23[MAX_RMU]; \ 263 uint32_t SHAPER_RAMB_REGION_24_25[MAX_RMU]; \ 264 uint32_t SHAPER_RAMB_REGION_26_27[MAX_RMU]; \ 265 uint32_t SHAPER_RAMB_REGION_28_29[MAX_RMU]; \ 266 uint32_t SHAPER_RAMB_REGION_30_31[MAX_RMU]; \ 267 uint32_t SHAPER_RAMB_REGION_32_33[MAX_RMU]; \ 268 uint32_t RMU_3DLUT_MODE[MAX_RMU]; \ 269 uint32_t RMU_3DLUT_INDEX[MAX_RMU]; \ 270 uint32_t RMU_3DLUT_DATA[MAX_RMU]; \ 271 uint32_t RMU_3DLUT_DATA_30BIT[MAX_RMU]; \ 272 uint32_t RMU_3DLUT_READ_WRITE_CONTROL[MAX_RMU]; \ 273 uint32_t RMU_3DLUT_OUT_NORM_FACTOR[MAX_RMU]; \ 274 uint32_t RMU_3DLUT_OUT_OFFSET_R[MAX_RMU]; \ 275 uint32_t RMU_3DLUT_OUT_OFFSET_G[MAX_RMU]; \ 276 uint32_t RMU_3DLUT_OUT_OFFSET_B[MAX_RMU]; \ 277 uint32_t MPCC_OGAM_RAMB_START_SLOPE_CNTL_B[MAX_MPCC]; \ 278 uint32_t MPCC_OGAM_RAMB_START_SLOPE_CNTL_G[MAX_MPCC]; \ 279 uint32_t MPCC_OGAM_RAMB_START_SLOPE_CNTL_R[MAX_MPCC]; \ 280 uint32_t MPCC_OGAM_CONTROL[MAX_MPCC]; \ 281 uint32_t MPCC_OGAM_LUT_CONTROL[MAX_MPCC]; \ 282 uint32_t MPCC_OGAM_RAMB_OFFSET_B[MAX_MPCC]; \ 283 uint32_t MPCC_OGAM_RAMB_OFFSET_G[MAX_MPCC]; \ 284 uint32_t MPCC_OGAM_RAMB_OFFSET_R[MAX_MPCC]; \ 285 uint32_t MPCC_OGAM_RAMB_START_BASE_CNTL_B[MAX_MPCC]; \ 286 uint32_t MPCC_OGAM_RAMB_START_BASE_CNTL_G[MAX_MPCC]; \ 287 uint32_t MPCC_OGAM_RAMB_START_BASE_CNTL_R[MAX_MPCC]; \ 288 uint32_t MPC_OUT_CSC_COEF_FORMAT 289 290 #define MPC_COMMON_MASK_SH_LIST_DCN3_0(mask_sh) \ 291 MPC_COMMON_MASK_SH_LIST_DCN1_0(mask_sh),\ 292 SF(MPCC0_MPCC_CONTROL, MPCC_BG_BPC, mask_sh),\ 293 SF(MPCC0_MPCC_CONTROL, MPCC_BOT_GAIN_MODE, mask_sh),\ 294 SF(MPCC0_MPCC_TOP_GAIN, MPCC_TOP_GAIN, mask_sh),\ 295 SF(MPCC0_MPCC_BOT_GAIN_INSIDE, MPCC_BOT_GAIN_INSIDE, mask_sh),\ 296 SF(MPCC0_MPCC_BOT_GAIN_OUTSIDE, MPCC_BOT_GAIN_OUTSIDE, mask_sh),\ 297 SF(MPC_OUT0_CSC_MODE, MPC_OCSC_MODE, mask_sh),\ 298 SF(MPC_OUT0_CSC_C11_C12_A, MPC_OCSC_C11_A, mask_sh),\ 299 SF(MPC_OUT0_CSC_C11_C12_A, MPC_OCSC_C12_A, mask_sh),\ 300 SF(MPCC0_MPCC_STATUS, MPCC_DISABLED, mask_sh),\ 301 SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_FORCE, mask_sh),\ 302 SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_DIS, mask_sh),\ 303 SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_STATE, mask_sh),\ 304 SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_MODE, mask_sh),\ 305 SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_CLAMP_MAX_R_CR, mask_sh),\ 306 SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_CLAMP_MIN_R_CR, mask_sh),\ 307 SF(MPC_OUT0_DENORM_CLAMP_G_Y, MPC_OUT_DENORM_CLAMP_MAX_G_Y, mask_sh),\ 308 SF(MPC_OUT0_DENORM_CLAMP_G_Y, MPC_OUT_DENORM_CLAMP_MIN_G_Y, mask_sh),\ 309 SF(MPC_OUT0_DENORM_CLAMP_B_CB, MPC_OUT_DENORM_CLAMP_MAX_B_CB, mask_sh),\ 310 SF(MPC_OUT0_DENORM_CLAMP_B_CB, MPC_OUT_DENORM_CLAMP_MIN_B_CB, mask_sh),\ 311 SF(MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE, MPCC_GAMUT_REMAP_MODE, mask_sh),\ 312 SF(MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE, MPCC_GAMUT_REMAP_MODE_CURRENT, mask_sh),\ 313 SF(MPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT, MPCC_GAMUT_REMAP_COEF_FORMAT, mask_sh),\ 314 SF(MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A, MPCC_GAMUT_REMAP_C11_A, mask_sh),\ 315 SF(MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A, MPCC_GAMUT_REMAP_C12_A, mask_sh),\ 316 SF(MPC_DWB0_MUX, MPC_DWB0_MUX, mask_sh),\ 317 SF(MPC_DWB0_MUX, MPC_DWB0_MUX_STATUS, mask_sh),\ 318 SF(MPC_OUT0_MUX, MPC_OUT_RATE_CONTROL, mask_sh),\ 319 SF(MPC_OUT0_MUX, MPC_OUT_RATE_CONTROL_DISABLE, mask_sh),\ 320 SF(MPC_OUT0_MUX, MPC_OUT_FLOW_CONTROL_MODE, mask_sh),\ 321 SF(MPC_OUT0_MUX, MPC_OUT_FLOW_CONTROL_COUNT, mask_sh), \ 322 SF(MPC_RMU_CONTROL, MPC_RMU0_MUX, mask_sh), \ 323 SF(MPC_RMU_CONTROL, MPC_RMU1_MUX, mask_sh), \ 324 SF(MPC_RMU_CONTROL, MPC_RMU0_MUX_STATUS, mask_sh), \ 325 SF(MPC_RMU_CONTROL, MPC_RMU1_MUX_STATUS, mask_sh), \ 326 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh),\ 327 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\ 328 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh),\ 329 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\ 330 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B, MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B, mask_sh),\ 331 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B, MPCC_OGAM_RAMA_EXP_REGION_END_B, mask_sh),\ 332 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B, MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B, mask_sh),\ 333 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B, mask_sh),\ 334 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B, mask_sh),\ 335 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_B, mask_sh),\ 336 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh),\ 337 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B, MPCC_OGAM_RAMA_OFFSET_B, mask_sh),\ 338 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G, MPCC_OGAM_RAMA_OFFSET_G, mask_sh),\ 339 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R, MPCC_OGAM_RAMA_OFFSET_R, mask_sh),\ 340 SF(MPCC_OGAM0_MPCC_OGAM_LUT_INDEX, MPCC_OGAM_LUT_INDEX, mask_sh),\ 341 SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_MODE, mask_sh),\ 342 SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_SELECT, mask_sh),\ 343 SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_PWL_DISABLE, mask_sh),\ 344 SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_MODE_CURRENT, mask_sh),\ 345 SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_SELECT_CURRENT, mask_sh),\ 346 SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_WRITE_COLOR_MASK, mask_sh),\ 347 SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_READ_COLOR_SEL, mask_sh),\ 348 SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_READ_DBG, mask_sh),\ 349 SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_HOST_SEL, mask_sh),\ 350 SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_CONFIG_MODE, mask_sh),\ 351 SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_STATUS, mask_sh),\ 352 SF(MPCC_OGAM0_MPCC_OGAM_LUT_DATA, MPCC_OGAM_LUT_DATA, mask_sh),\ 353 SF(MPC_RMU0_3DLUT_MODE, MPC_RMU_3DLUT_MODE, mask_sh),\ 354 SF(MPC_RMU0_3DLUT_MODE, MPC_RMU_3DLUT_SIZE, mask_sh),\ 355 SF(MPC_RMU0_3DLUT_MODE, MPC_RMU_3DLUT_MODE_CURRENT, mask_sh),\ 356 SF(MPC_RMU0_3DLUT_READ_WRITE_CONTROL, MPC_RMU_3DLUT_WRITE_EN_MASK, mask_sh),\ 357 SF(MPC_RMU0_3DLUT_READ_WRITE_CONTROL, MPC_RMU_3DLUT_RAM_SEL, mask_sh),\ 358 SF(MPC_RMU0_3DLUT_READ_WRITE_CONTROL, MPC_RMU_3DLUT_30BIT_EN, mask_sh),\ 359 SF(MPC_RMU0_3DLUT_READ_WRITE_CONTROL, MPC_RMU_3DLUT_CONFIG_STATUS, mask_sh),\ 360 SF(MPC_RMU0_3DLUT_READ_WRITE_CONTROL, MPC_RMU_3DLUT_READ_SEL, mask_sh),\ 361 SF(MPC_RMU0_3DLUT_INDEX, MPC_RMU_3DLUT_INDEX, mask_sh),\ 362 SF(MPC_RMU0_3DLUT_DATA, MPC_RMU_3DLUT_DATA0, mask_sh),\ 363 SF(MPC_RMU0_3DLUT_DATA, MPC_RMU_3DLUT_DATA1, mask_sh),\ 364 SF(MPC_RMU0_3DLUT_DATA_30BIT, MPC_RMU_3DLUT_DATA_30BIT, mask_sh),\ 365 SF(MPC_RMU0_SHAPER_CONTROL, MPC_RMU_SHAPER_LUT_MODE, mask_sh),\ 366 SF(MPC_RMU0_SHAPER_CONTROL, MPC_RMU_SHAPER_LUT_MODE_CURRENT, mask_sh),\ 367 SF(MPC_RMU0_SHAPER_OFFSET_R, MPC_RMU_SHAPER_OFFSET_R, mask_sh),\ 368 SF(MPC_RMU0_SHAPER_OFFSET_G, MPC_RMU_SHAPER_OFFSET_G, mask_sh),\ 369 SF(MPC_RMU0_SHAPER_OFFSET_B, MPC_RMU_SHAPER_OFFSET_B, mask_sh),\ 370 SF(MPC_RMU0_SHAPER_SCALE_R, MPC_RMU_SHAPER_SCALE_R, mask_sh),\ 371 SF(MPC_RMU0_SHAPER_SCALE_G_B, MPC_RMU_SHAPER_SCALE_G, mask_sh),\ 372 SF(MPC_RMU0_SHAPER_SCALE_G_B, MPC_RMU_SHAPER_SCALE_B, mask_sh),\ 373 SF(MPC_RMU0_SHAPER_LUT_INDEX, MPC_RMU_SHAPER_LUT_INDEX, mask_sh),\ 374 SF(MPC_RMU0_SHAPER_LUT_DATA, MPC_RMU_SHAPER_LUT_DATA, mask_sh),\ 375 SF(MPC_RMU0_SHAPER_LUT_WRITE_EN_MASK, MPC_RMU_SHAPER_LUT_WRITE_EN_MASK, mask_sh),\ 376 SF(MPC_RMU0_SHAPER_LUT_WRITE_EN_MASK, MPC_RMU_SHAPER_LUT_WRITE_SEL, mask_sh),\ 377 SF(MPC_RMU0_SHAPER_LUT_WRITE_EN_MASK, MPC_RMU_SHAPER_CONFIG_STATUS, mask_sh),\ 378 SF(MPC_RMU0_SHAPER_RAMA_START_CNTL_B, MPC_RMU_SHAPER_RAMA_EXP_REGION_START_B, mask_sh),\ 379 SF(MPC_RMU0_SHAPER_RAMA_START_CNTL_B, MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh),\ 380 SF(MPC_RMU0_SHAPER_RAMA_END_CNTL_B, MPC_RMU_SHAPER_RAMA_EXP_REGION_END_B, mask_sh),\ 381 SF(MPC_RMU0_SHAPER_RAMA_END_CNTL_B, MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_B, mask_sh),\ 382 SF(MPC_RMU0_SHAPER_RAMA_REGION_0_1, MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh),\ 383 SF(MPC_RMU0_SHAPER_RAMA_REGION_0_1, MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\ 384 SF(MPC_RMU0_SHAPER_RAMA_REGION_0_1, MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh),\ 385 SF(MPC_RMU0_SHAPER_RAMA_REGION_0_1, MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\ 386 SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_MEM_PWR_FORCE, mask_sh),\ 387 SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_MEM_PWR_DIS, mask_sh),\ 388 SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_SHAPER_MEM_PWR_STATE, mask_sh),\ 389 SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_3DLUT_MEM_PWR_STATE, mask_sh),\ 390 SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU1_MEM_PWR_FORCE, mask_sh),\ 391 SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU1_MEM_PWR_DIS, mask_sh),\ 392 SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU1_SHAPER_MEM_PWR_STATE, mask_sh),\ 393 SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU1_3DLUT_MEM_PWR_STATE, mask_sh),\ 394 SF(CUR_VUPDATE_LOCK_SET0, CUR_VUPDATE_LOCK_SET, mask_sh) 395 396 397 #define MPC_COMMON_MASK_SH_LIST_DCN30(mask_sh) \ 398 MPC_COMMON_MASK_SH_LIST_DCN1_0(mask_sh),\ 399 SF(MPCC0_MPCC_CONTROL, MPCC_BG_BPC, mask_sh),\ 400 SF(MPCC0_MPCC_CONTROL, MPCC_BOT_GAIN_MODE, mask_sh),\ 401 SF(MPCC0_MPCC_TOP_GAIN, MPCC_TOP_GAIN, mask_sh),\ 402 SF(MPCC0_MPCC_BOT_GAIN_INSIDE, MPCC_BOT_GAIN_INSIDE, mask_sh),\ 403 SF(MPCC0_MPCC_BOT_GAIN_OUTSIDE, MPCC_BOT_GAIN_OUTSIDE, mask_sh),\ 404 SF(MPC_OUT0_CSC_MODE, MPC_OCSC_MODE, mask_sh),\ 405 SF(MPC_OUT0_CSC_C11_C12_A, MPC_OCSC_C11_A, mask_sh),\ 406 SF(MPC_OUT0_CSC_C11_C12_A, MPC_OCSC_C12_A, mask_sh),\ 407 SF(MPCC0_MPCC_STATUS, MPCC_DISABLED, mask_sh),\ 408 SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_FORCE, mask_sh),\ 409 SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_DIS, mask_sh),\ 410 SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_LOW_PWR_MODE, mask_sh),\ 411 SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_STATE, mask_sh),\ 412 SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_MODE, mask_sh),\ 413 SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_CLAMP_MAX_R_CR, mask_sh),\ 414 SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_CLAMP_MIN_R_CR, mask_sh),\ 415 SF(MPC_OUT0_DENORM_CLAMP_G_Y, MPC_OUT_DENORM_CLAMP_MAX_G_Y, mask_sh),\ 416 SF(MPC_OUT0_DENORM_CLAMP_G_Y, MPC_OUT_DENORM_CLAMP_MIN_G_Y, mask_sh),\ 417 SF(MPC_OUT0_DENORM_CLAMP_B_CB, MPC_OUT_DENORM_CLAMP_MAX_B_CB, mask_sh),\ 418 SF(MPC_OUT0_DENORM_CLAMP_B_CB, MPC_OUT_DENORM_CLAMP_MIN_B_CB, mask_sh),\ 419 SF(MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE, MPCC_GAMUT_REMAP_MODE, mask_sh),\ 420 SF(MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE, MPCC_GAMUT_REMAP_MODE_CURRENT, mask_sh),\ 421 SF(MPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT, MPCC_GAMUT_REMAP_COEF_FORMAT, mask_sh),\ 422 SF(MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A, MPCC_GAMUT_REMAP_C11_A, mask_sh),\ 423 SF(MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A, MPCC_GAMUT_REMAP_C12_A, mask_sh),\ 424 SF(MPC_DWB0_MUX, MPC_DWB0_MUX, mask_sh),\ 425 SF(MPC_DWB0_MUX, MPC_DWB0_MUX_STATUS, mask_sh),\ 426 SF(MPC_OUT0_MUX, MPC_OUT_RATE_CONTROL, mask_sh),\ 427 SF(MPC_OUT0_MUX, MPC_OUT_RATE_CONTROL_DISABLE, mask_sh),\ 428 SF(MPC_OUT0_MUX, MPC_OUT_FLOW_CONTROL_MODE, mask_sh),\ 429 SF(MPC_OUT0_MUX, MPC_OUT_FLOW_CONTROL_COUNT, mask_sh), \ 430 SF(MPC_RMU_CONTROL, MPC_RMU0_MUX, mask_sh), \ 431 SF(MPC_RMU_CONTROL, MPC_RMU1_MUX, mask_sh), \ 432 SF(MPC_RMU_CONTROL, MPC_RMU0_MUX_STATUS, mask_sh), \ 433 SF(MPC_RMU_CONTROL, MPC_RMU1_MUX_STATUS, mask_sh), \ 434 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh),\ 435 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\ 436 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh),\ 437 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\ 438 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B, MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B, mask_sh),\ 439 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B, MPCC_OGAM_RAMA_EXP_REGION_END_B, mask_sh),\ 440 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B, MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B, mask_sh),\ 441 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B, mask_sh),\ 442 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B, mask_sh),\ 443 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_B, mask_sh),\ 444 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh),\ 445 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B, MPCC_OGAM_RAMA_OFFSET_B, mask_sh),\ 446 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G, MPCC_OGAM_RAMA_OFFSET_G, mask_sh),\ 447 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R, MPCC_OGAM_RAMA_OFFSET_R, mask_sh),\ 448 SF(MPCC_OGAM0_MPCC_OGAM_LUT_INDEX, MPCC_OGAM_LUT_INDEX, mask_sh),\ 449 SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_MODE, mask_sh),\ 450 SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_SELECT, mask_sh),\ 451 SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_PWL_DISABLE, mask_sh),\ 452 SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_MODE_CURRENT, mask_sh),\ 453 SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_SELECT_CURRENT, mask_sh),\ 454 SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_WRITE_COLOR_MASK, mask_sh),\ 455 SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_READ_COLOR_SEL, mask_sh),\ 456 SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_READ_DBG, mask_sh),\ 457 SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_HOST_SEL, mask_sh),\ 458 SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_CONFIG_MODE, mask_sh),\ 459 /*SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_STATUS, mask_sh),*/\ 460 SF(MPCC_OGAM0_MPCC_OGAM_LUT_DATA, MPCC_OGAM_LUT_DATA, mask_sh),\ 461 SF(MPC_RMU0_3DLUT_MODE, MPC_RMU_3DLUT_MODE, mask_sh),\ 462 SF(MPC_RMU0_3DLUT_MODE, MPC_RMU_3DLUT_SIZE, mask_sh),\ 463 /*SF(MPC_RMU0_3DLUT_MODE, MPC_RMU_3DLUT_MODE_CURRENT, mask_sh),*/\ 464 SF(MPC_RMU0_3DLUT_READ_WRITE_CONTROL, MPC_RMU_3DLUT_WRITE_EN_MASK, mask_sh),\ 465 SF(MPC_RMU0_3DLUT_READ_WRITE_CONTROL, MPC_RMU_3DLUT_RAM_SEL, mask_sh),\ 466 SF(MPC_RMU0_3DLUT_READ_WRITE_CONTROL, MPC_RMU_3DLUT_30BIT_EN, mask_sh),\ 467 /*SF(MPC_RMU0_3DLUT_READ_WRITE_CONTROL, MPC_RMU_3DLUT_CONFIG_STATUS, mask_sh),*/\ 468 SF(MPC_RMU0_3DLUT_READ_WRITE_CONTROL, MPC_RMU_3DLUT_READ_SEL, mask_sh),\ 469 SF(MPC_RMU0_3DLUT_INDEX, MPC_RMU_3DLUT_INDEX, mask_sh),\ 470 SF(MPC_RMU0_3DLUT_DATA, MPC_RMU_3DLUT_DATA0, mask_sh),\ 471 SF(MPC_RMU0_3DLUT_DATA, MPC_RMU_3DLUT_DATA1, mask_sh),\ 472 SF(MPC_RMU0_3DLUT_DATA_30BIT, MPC_RMU_3DLUT_DATA_30BIT, mask_sh),\ 473 SF(MPC_RMU0_SHAPER_CONTROL, MPC_RMU_SHAPER_LUT_MODE, mask_sh),\ 474 /*SF(MPC_RMU0_SHAPER_CONTROL, MPC_RMU_SHAPER_LUT_MODE_CURRENT, mask_sh),*/\ 475 SF(MPC_RMU0_SHAPER_OFFSET_R, MPC_RMU_SHAPER_OFFSET_R, mask_sh),\ 476 SF(MPC_RMU0_SHAPER_OFFSET_G, MPC_RMU_SHAPER_OFFSET_G, mask_sh),\ 477 SF(MPC_RMU0_SHAPER_OFFSET_B, MPC_RMU_SHAPER_OFFSET_B, mask_sh),\ 478 SF(MPC_RMU0_SHAPER_SCALE_R, MPC_RMU_SHAPER_SCALE_R, mask_sh),\ 479 SF(MPC_RMU0_SHAPER_SCALE_G_B, MPC_RMU_SHAPER_SCALE_G, mask_sh),\ 480 SF(MPC_RMU0_SHAPER_SCALE_G_B, MPC_RMU_SHAPER_SCALE_B, mask_sh),\ 481 SF(MPC_RMU0_SHAPER_LUT_INDEX, MPC_RMU_SHAPER_LUT_INDEX, mask_sh),\ 482 SF(MPC_RMU0_SHAPER_LUT_DATA, MPC_RMU_SHAPER_LUT_DATA, mask_sh),\ 483 SF(MPC_RMU0_SHAPER_LUT_WRITE_EN_MASK, MPC_RMU_SHAPER_LUT_WRITE_EN_MASK, mask_sh),\ 484 SF(MPC_RMU0_SHAPER_LUT_WRITE_EN_MASK, MPC_RMU_SHAPER_LUT_WRITE_SEL, mask_sh),\ 485 /*SF(MPC_RMU0_SHAPER_LUT_WRITE_EN_MASK, MPC_RMU_SHAPER_CONFIG_STATUS, mask_sh),*/\ 486 SF(MPC_RMU0_SHAPER_RAMA_START_CNTL_B, MPC_RMU_SHAPER_RAMA_EXP_REGION_START_B, mask_sh),\ 487 SF(MPC_RMU0_SHAPER_RAMA_START_CNTL_B, MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh),\ 488 SF(MPC_RMU0_SHAPER_RAMA_END_CNTL_B, MPC_RMU_SHAPER_RAMA_EXP_REGION_END_B, mask_sh),\ 489 SF(MPC_RMU0_SHAPER_RAMA_END_CNTL_B, MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_B, mask_sh),\ 490 SF(MPC_RMU0_SHAPER_RAMA_REGION_0_1, MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh),\ 491 SF(MPC_RMU0_SHAPER_RAMA_REGION_0_1, MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\ 492 SF(MPC_RMU0_SHAPER_RAMA_REGION_0_1, MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh),\ 493 SF(MPC_RMU0_SHAPER_RAMA_REGION_0_1, MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\ 494 SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_MEM_PWR_FORCE, mask_sh),\ 495 SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_MEM_PWR_DIS, mask_sh),\ 496 SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_SHAPER_MEM_PWR_STATE, mask_sh),\ 497 SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_3DLUT_MEM_PWR_STATE, mask_sh),\ 498 SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_MEM_LOW_PWR_MODE, mask_sh),\ 499 SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU1_MEM_PWR_FORCE, mask_sh),\ 500 SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU1_MEM_PWR_DIS, mask_sh),\ 501 SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU1_SHAPER_MEM_PWR_STATE, mask_sh),\ 502 SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU1_3DLUT_MEM_PWR_STATE, mask_sh),\ 503 SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU1_MEM_LOW_PWR_MODE, mask_sh),\ 504 SF(MPC_RMU0_SHAPER_CONTROL, MPC_RMU_SHAPER_MODE_CURRENT, mask_sh),\ 505 SF(CUR_VUPDATE_LOCK_SET0, CUR_VUPDATE_LOCK_SET, mask_sh) 506 507 508 #define MPC_REG_FIELD_LIST_DCN3_0(type) \ 509 MPC_REG_FIELD_LIST_DCN2_0(type) \ 510 type MPC_DWB0_MUX;\ 511 type MPC_DWB0_MUX_STATUS;\ 512 type MPC_OUT_RATE_CONTROL;\ 513 type MPC_OUT_RATE_CONTROL_DISABLE;\ 514 type MPC_OUT_FLOW_CONTROL_MODE;\ 515 type MPC_OUT_FLOW_CONTROL_COUNT; \ 516 type MPCC_GAMUT_REMAP_MODE; \ 517 type MPCC_GAMUT_REMAP_MODE_CURRENT;\ 518 type MPCC_GAMUT_REMAP_COEF_FORMAT; \ 519 type MPCC_GAMUT_REMAP_C11_A; \ 520 type MPCC_GAMUT_REMAP_C12_A; \ 521 type MPC_RMU0_MUX; \ 522 type MPC_RMU1_MUX; \ 523 type MPC_RMU0_MUX_STATUS; \ 524 type MPC_RMU1_MUX_STATUS; \ 525 type MPC_RMU0_MEM_PWR_FORCE;\ 526 type MPC_RMU0_MEM_PWR_DIS;\ 527 type MPC_RMU0_MEM_LOW_PWR_MODE;\ 528 type MPC_RMU0_SHAPER_MEM_PWR_STATE;\ 529 type MPC_RMU0_3DLUT_MEM_PWR_STATE;\ 530 type MPC_RMU1_MEM_PWR_FORCE;\ 531 type MPC_RMU1_MEM_PWR_DIS;\ 532 type MPC_RMU1_MEM_LOW_PWR_MODE;\ 533 type MPC_RMU1_SHAPER_MEM_PWR_STATE;\ 534 type MPC_RMU1_3DLUT_MEM_PWR_STATE;\ 535 type MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B; \ 536 type MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B;\ 537 type MPCC_OGAM_RAMA_OFFSET_B;\ 538 type MPCC_OGAM_RAMA_OFFSET_G;\ 539 type MPCC_OGAM_RAMA_OFFSET_R;\ 540 type MPCC_OGAM_SELECT; \ 541 type MPCC_OGAM_PWL_DISABLE; \ 542 type MPCC_OGAM_MODE_CURRENT; \ 543 type MPCC_OGAM_SELECT_CURRENT; \ 544 type MPCC_OGAM_LUT_WRITE_COLOR_MASK; \ 545 type MPCC_OGAM_LUT_READ_COLOR_SEL; \ 546 type MPCC_OGAM_LUT_READ_DBG; \ 547 type MPCC_OGAM_LUT_HOST_SEL; \ 548 type MPCC_OGAM_LUT_CONFIG_MODE; \ 549 type MPCC_OGAM_LUT_STATUS; \ 550 type MPCC_OGAM_RAMA_START_BASE_CNTL_B;\ 551 type MPCC_OGAM_MEM_LOW_PWR_MODE;\ 552 type MPCC_OGAM_MEM_PWR_STATE;\ 553 type MPC_RMU_3DLUT_MODE; \ 554 type MPC_RMU_3DLUT_SIZE; \ 555 type MPC_RMU_3DLUT_MODE_CURRENT; \ 556 type MPC_RMU_3DLUT_WRITE_EN_MASK;\ 557 type MPC_RMU_3DLUT_RAM_SEL;\ 558 type MPC_RMU_3DLUT_30BIT_EN;\ 559 type MPC_RMU_3DLUT_CONFIG_STATUS;\ 560 type MPC_RMU_3DLUT_READ_SEL;\ 561 type MPC_RMU_3DLUT_INDEX;\ 562 type MPC_RMU_3DLUT_DATA0;\ 563 type MPC_RMU_3DLUT_DATA1;\ 564 type MPC_RMU_3DLUT_DATA_30BIT;\ 565 type MPC_RMU_SHAPER_LUT_MODE;\ 566 type MPC_RMU_SHAPER_LUT_MODE_CURRENT;\ 567 type MPC_RMU_SHAPER_OFFSET_R;\ 568 type MPC_RMU_SHAPER_OFFSET_G;\ 569 type MPC_RMU_SHAPER_OFFSET_B;\ 570 type MPC_RMU_SHAPER_SCALE_R;\ 571 type MPC_RMU_SHAPER_SCALE_G;\ 572 type MPC_RMU_SHAPER_SCALE_B;\ 573 type MPC_RMU_SHAPER_LUT_INDEX;\ 574 type MPC_RMU_SHAPER_LUT_DATA;\ 575 type MPC_RMU_SHAPER_LUT_WRITE_EN_MASK;\ 576 type MPC_RMU_SHAPER_LUT_WRITE_SEL;\ 577 type MPC_RMU_SHAPER_CONFIG_STATUS;\ 578 type MPC_RMU_SHAPER_RAMA_EXP_REGION_START_B;\ 579 type MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B;\ 580 type MPC_RMU_SHAPER_RAMA_EXP_REGION_END_B;\ 581 type MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_B;\ 582 type MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET;\ 583 type MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS;\ 584 type MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET;\ 585 type MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS;\ 586 type MPC_RMU_SHAPER_MODE_CURRENT 587 588 589 struct dcn30_mpc_registers { 590 MPC_REG_VARIABLE_LIST_DCN3_0; 591 }; 592 593 struct dcn30_mpc_shift { 594 MPC_REG_FIELD_LIST_DCN3_0(uint8_t); 595 }; 596 597 struct dcn30_mpc_mask { 598 MPC_REG_FIELD_LIST_DCN3_0(uint32_t); 599 }; 600 601 struct dcn30_mpc { 602 struct mpc base; 603 604 int mpcc_in_use_mask; 605 int num_mpcc; 606 const struct dcn30_mpc_registers *mpc_regs; 607 const struct dcn30_mpc_shift *mpc_shift; 608 const struct dcn30_mpc_mask *mpc_mask; 609 int num_rmu; 610 }; 611 612 void dcn30_mpc_construct(struct dcn30_mpc *mpc30, 613 struct dc_context *ctx, 614 const struct dcn30_mpc_registers *mpc_regs, 615 const struct dcn30_mpc_shift *mpc_shift, 616 const struct dcn30_mpc_mask *mpc_mask, 617 int num_mpcc, 618 int num_rmu); 619 620 bool mpc3_program_shaper( 621 struct mpc *mpc, 622 const struct pwl_params *params, 623 uint32_t rmu_idx); 624 625 bool mpc3_program_3dlut( 626 struct mpc *mpc, 627 const struct tetrahedral_params *params, 628 int rmu_idx); 629 630 uint32_t mpcc3_acquire_rmu(struct mpc *mpc, 631 int mpcc_id, int rmu_idx); 632 633 void mpc3_set_denorm( 634 struct mpc *mpc, 635 int opp_id, 636 enum dc_color_depth output_depth); 637 638 void mpc3_set_denorm_clamp( 639 struct mpc *mpc, 640 int opp_id, 641 struct mpc_denorm_clamp denorm_clamp); 642 643 void mpc3_set_output_csc( 644 struct mpc *mpc, 645 int opp_id, 646 const uint16_t *regval, 647 enum mpc_output_csc_mode ocsc_mode); 648 649 void mpc3_set_ocsc_default( 650 struct mpc *mpc, 651 int opp_id, 652 enum dc_color_space color_space, 653 enum mpc_output_csc_mode ocsc_mode); 654 655 void mpc3_set_output_gamma( 656 struct mpc *mpc, 657 int mpcc_id, 658 const struct pwl_params *params); 659 660 uint32_t mpc3_get_rmu_mux_status( 661 struct mpc *mpc, 662 int rmu_idx); 663 664 void mpc3_set_gamut_remap( 665 struct mpc *mpc, 666 int mpcc_id, 667 const struct mpc_grph_gamut_adjustment *adjust); 668 669 void mpc3_set_rmu_mux( 670 struct mpc *mpc, 671 int rmu_idx, 672 int value); 673 674 #endif 675