1 /* Copyright 2020 Advanced Micro Devices, Inc. 2 * 3 * Permission is hereby granted, free of charge, to any person obtaining a 4 * copy of this software and associated documentation files (the "Software"), 5 * to deal in the Software without restriction, including without limitation 6 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 7 * and/or sell copies of the Software, and to permit persons to whom the 8 * Software is furnished to do so, subject to the following conditions: 9 * 10 * The above copyright notice and this permission notice shall be included in 11 * all copies or substantial portions of the Software. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 17 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 19 * OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * Authors: AMD 22 * 23 */ 24 25 #ifndef __DC_MPCC_DCN30_H__ 26 #define __DC_MPCC_DCN30_H__ 27 28 #include "dcn20/dcn20_mpc.h" 29 30 #define MAX_RMU 3 31 32 #define TO_DCN30_MPC(mpc_base) \ 33 container_of(mpc_base, struct dcn30_mpc, base) 34 35 #ifdef SRII_MPC_RMU 36 #undef SRII_MPC_RMU 37 38 #define SRII_MPC_RMU(reg_name, block, id)\ 39 .RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 40 mm ## block ## id ## _ ## reg_name 41 42 #endif 43 44 45 #define MPC_REG_LIST_DCN3_0(inst)\ 46 MPC_COMMON_REG_LIST_DCN1_0(inst),\ 47 SRII(MPCC_TOP_GAIN, MPCC, inst),\ 48 SRII(MPCC_BOT_GAIN_INSIDE, MPCC, inst),\ 49 SRII(MPCC_BOT_GAIN_OUTSIDE, MPCC, inst),\ 50 SRII(MPCC_MEM_PWR_CTRL, MPCC, inst),\ 51 SRII(MPCC_OGAM_LUT_INDEX, MPCC_OGAM, inst),\ 52 SRII(MPCC_OGAM_LUT_DATA, MPCC_OGAM, inst), \ 53 SRII(MPCC_GAMUT_REMAP_COEF_FORMAT, MPCC_OGAM, inst),\ 54 SRII(MPCC_GAMUT_REMAP_MODE, MPCC_OGAM, inst),\ 55 SRII(MPC_GAMUT_REMAP_C11_C12_A, MPCC_OGAM, inst),\ 56 SRII(MPC_GAMUT_REMAP_C33_C34_A, MPCC_OGAM, inst),\ 57 SRII(MPC_GAMUT_REMAP_C11_C12_B, MPCC_OGAM, inst),\ 58 SRII(MPC_GAMUT_REMAP_C33_C34_B, MPCC_OGAM, inst),\ 59 SRII(MPCC_OGAM_RAMA_START_CNTL_B, MPCC_OGAM, inst),\ 60 SRII(MPCC_OGAM_RAMA_START_CNTL_G, MPCC_OGAM, inst),\ 61 SRII(MPCC_OGAM_RAMA_START_CNTL_R, MPCC_OGAM, inst),\ 62 SRII(MPCC_OGAM_RAMA_START_SLOPE_CNTL_B, MPCC_OGAM, inst),\ 63 SRII(MPCC_OGAM_RAMA_START_SLOPE_CNTL_G, MPCC_OGAM, inst),\ 64 SRII(MPCC_OGAM_RAMA_START_SLOPE_CNTL_R, MPCC_OGAM, inst),\ 65 SRII(MPCC_OGAM_RAMA_END_CNTL1_B, MPCC_OGAM, inst),\ 66 SRII(MPCC_OGAM_RAMA_END_CNTL2_B, MPCC_OGAM, inst),\ 67 SRII(MPCC_OGAM_RAMA_END_CNTL1_G, MPCC_OGAM, inst),\ 68 SRII(MPCC_OGAM_RAMA_END_CNTL2_G, MPCC_OGAM, inst),\ 69 SRII(MPCC_OGAM_RAMA_END_CNTL1_R, MPCC_OGAM, inst),\ 70 SRII(MPCC_OGAM_RAMA_END_CNTL2_R, MPCC_OGAM, inst),\ 71 SRII(MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM, inst),\ 72 SRII(MPCC_OGAM_RAMA_REGION_32_33, MPCC_OGAM, inst),\ 73 SRII(MPCC_OGAM_RAMA_OFFSET_B, MPCC_OGAM, inst),\ 74 SRII(MPCC_OGAM_RAMA_OFFSET_G, MPCC_OGAM, inst),\ 75 SRII(MPCC_OGAM_RAMA_OFFSET_R, MPCC_OGAM, inst),\ 76 SRII(MPCC_OGAM_RAMA_START_BASE_CNTL_B, MPCC_OGAM, inst),\ 77 SRII(MPCC_OGAM_RAMA_START_BASE_CNTL_G, MPCC_OGAM, inst),\ 78 SRII(MPCC_OGAM_RAMA_START_BASE_CNTL_R, MPCC_OGAM, inst),\ 79 SRII(MPCC_OGAM_RAMB_START_CNTL_B, MPCC_OGAM, inst),\ 80 SRII(MPCC_OGAM_RAMB_START_CNTL_G, MPCC_OGAM, inst),\ 81 SRII(MPCC_OGAM_RAMB_START_CNTL_R, MPCC_OGAM, inst),\ 82 SRII(MPCC_OGAM_RAMB_START_SLOPE_CNTL_B, MPCC_OGAM, inst),\ 83 SRII(MPCC_OGAM_RAMB_START_SLOPE_CNTL_G, MPCC_OGAM, inst),\ 84 SRII(MPCC_OGAM_RAMB_START_SLOPE_CNTL_R, MPCC_OGAM, inst),\ 85 SRII(MPCC_OGAM_RAMB_END_CNTL1_B, MPCC_OGAM, inst),\ 86 SRII(MPCC_OGAM_RAMB_END_CNTL2_B, MPCC_OGAM, inst),\ 87 SRII(MPCC_OGAM_RAMB_END_CNTL1_G, MPCC_OGAM, inst),\ 88 SRII(MPCC_OGAM_RAMB_END_CNTL2_G, MPCC_OGAM, inst),\ 89 SRII(MPCC_OGAM_RAMB_END_CNTL1_R, MPCC_OGAM, inst),\ 90 SRII(MPCC_OGAM_RAMB_END_CNTL2_R, MPCC_OGAM, inst),\ 91 SRII(MPCC_OGAM_RAMB_REGION_0_1, MPCC_OGAM, inst),\ 92 SRII(MPCC_OGAM_RAMB_REGION_32_33, MPCC_OGAM, inst),\ 93 SRII(MPCC_OGAM_RAMB_OFFSET_B, MPCC_OGAM, inst),\ 94 SRII(MPCC_OGAM_RAMB_OFFSET_G, MPCC_OGAM, inst),\ 95 SRII(MPCC_OGAM_RAMB_OFFSET_R, MPCC_OGAM, inst),\ 96 SRII(MPCC_OGAM_RAMB_START_BASE_CNTL_B, MPCC_OGAM, inst),\ 97 SRII(MPCC_OGAM_RAMB_START_BASE_CNTL_G, MPCC_OGAM, inst),\ 98 SRII(MPCC_OGAM_RAMB_START_BASE_CNTL_R, MPCC_OGAM, inst),\ 99 SRII(MPCC_OGAM_CONTROL, MPCC_OGAM, inst),\ 100 SRII(MPCC_OGAM_LUT_CONTROL, MPCC_OGAM, inst) 101 102 #define MPC_OUT_MUX_REG_LIST_DCN3_0(inst) \ 103 MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(inst),\ 104 SRII(CSC_MODE, MPC_OUT, inst),\ 105 SRII(CSC_C11_C12_A, MPC_OUT, inst),\ 106 SRII(CSC_C33_C34_A, MPC_OUT, inst),\ 107 SRII(CSC_C11_C12_B, MPC_OUT, inst),\ 108 SRII(CSC_C33_C34_B, MPC_OUT, inst),\ 109 SRII(DENORM_CONTROL, MPC_OUT, inst),\ 110 SRII(DENORM_CLAMP_G_Y, MPC_OUT, inst),\ 111 SRII(DENORM_CLAMP_B_CB, MPC_OUT, inst), \ 112 SR(MPC_OUT_CSC_COEF_FORMAT) 113 114 #define MPC_RMU_GLOBAL_REG_LIST_DCN3AG \ 115 SR(MPC_RMU_CONTROL),\ 116 SR(MPC_RMU_MEM_PWR_CTRL) 117 118 #define MPC_RMU_REG_LIST_DCN3AG(inst) \ 119 SRII(SHAPER_CONTROL, MPC_RMU, inst),\ 120 SRII(SHAPER_OFFSET_R, MPC_RMU, inst),\ 121 SRII(SHAPER_OFFSET_G, MPC_RMU, inst),\ 122 SRII(SHAPER_OFFSET_B, MPC_RMU, inst),\ 123 SRII(SHAPER_SCALE_R, MPC_RMU, inst),\ 124 SRII(SHAPER_SCALE_G_B, MPC_RMU, inst),\ 125 SRII(SHAPER_LUT_INDEX, MPC_RMU, inst),\ 126 SRII(SHAPER_LUT_DATA, MPC_RMU, inst),\ 127 SRII(SHAPER_LUT_WRITE_EN_MASK, MPC_RMU, inst),\ 128 SRII(SHAPER_RAMA_START_CNTL_B, MPC_RMU, inst),\ 129 SRII(SHAPER_RAMA_START_CNTL_G, MPC_RMU, inst),\ 130 SRII(SHAPER_RAMA_START_CNTL_R, MPC_RMU, inst),\ 131 SRII(SHAPER_RAMA_END_CNTL_B, MPC_RMU, inst),\ 132 SRII(SHAPER_RAMA_END_CNTL_G, MPC_RMU, inst),\ 133 SRII(SHAPER_RAMA_END_CNTL_R, MPC_RMU, inst),\ 134 SRII(SHAPER_RAMA_REGION_0_1, MPC_RMU, inst),\ 135 SRII(SHAPER_RAMA_REGION_2_3, MPC_RMU, inst),\ 136 SRII(SHAPER_RAMA_REGION_4_5, MPC_RMU, inst),\ 137 SRII(SHAPER_RAMA_REGION_6_7, MPC_RMU, inst),\ 138 SRII(SHAPER_RAMA_REGION_8_9, MPC_RMU, inst),\ 139 SRII(SHAPER_RAMA_REGION_10_11, MPC_RMU, inst),\ 140 SRII(SHAPER_RAMA_REGION_12_13, MPC_RMU, inst),\ 141 SRII(SHAPER_RAMA_REGION_14_15, MPC_RMU, inst),\ 142 SRII(SHAPER_RAMA_REGION_16_17, MPC_RMU, inst),\ 143 SRII(SHAPER_RAMA_REGION_18_19, MPC_RMU, inst),\ 144 SRII(SHAPER_RAMA_REGION_20_21, MPC_RMU, inst),\ 145 SRII(SHAPER_RAMA_REGION_22_23, MPC_RMU, inst),\ 146 SRII(SHAPER_RAMA_REGION_24_25, MPC_RMU, inst),\ 147 SRII(SHAPER_RAMA_REGION_26_27, MPC_RMU, inst),\ 148 SRII(SHAPER_RAMA_REGION_28_29, MPC_RMU, inst),\ 149 SRII(SHAPER_RAMA_REGION_30_31, MPC_RMU, inst),\ 150 SRII(SHAPER_RAMA_REGION_32_33, MPC_RMU, inst),\ 151 SRII(SHAPER_RAMB_START_CNTL_B, MPC_RMU, inst),\ 152 SRII(SHAPER_RAMB_START_CNTL_G, MPC_RMU, inst),\ 153 SRII(SHAPER_RAMB_START_CNTL_R, MPC_RMU, inst),\ 154 SRII(SHAPER_RAMB_END_CNTL_B, MPC_RMU, inst),\ 155 SRII(SHAPER_RAMB_END_CNTL_G, MPC_RMU, inst),\ 156 SRII(SHAPER_RAMB_END_CNTL_R, MPC_RMU, inst),\ 157 SRII(SHAPER_RAMB_REGION_0_1, MPC_RMU, inst),\ 158 SRII(SHAPER_RAMB_REGION_2_3, MPC_RMU, inst),\ 159 SRII(SHAPER_RAMB_REGION_4_5, MPC_RMU, inst),\ 160 SRII(SHAPER_RAMB_REGION_6_7, MPC_RMU, inst),\ 161 SRII(SHAPER_RAMB_REGION_8_9, MPC_RMU, inst),\ 162 SRII(SHAPER_RAMB_REGION_10_11, MPC_RMU, inst),\ 163 SRII(SHAPER_RAMB_REGION_12_13, MPC_RMU, inst),\ 164 SRII(SHAPER_RAMB_REGION_14_15, MPC_RMU, inst),\ 165 SRII(SHAPER_RAMB_REGION_16_17, MPC_RMU, inst),\ 166 SRII(SHAPER_RAMB_REGION_18_19, MPC_RMU, inst),\ 167 SRII(SHAPER_RAMB_REGION_20_21, MPC_RMU, inst),\ 168 SRII(SHAPER_RAMB_REGION_22_23, MPC_RMU, inst),\ 169 SRII(SHAPER_RAMB_REGION_24_25, MPC_RMU, inst),\ 170 SRII(SHAPER_RAMB_REGION_26_27, MPC_RMU, inst),\ 171 SRII(SHAPER_RAMB_REGION_28_29, MPC_RMU, inst),\ 172 SRII(SHAPER_RAMB_REGION_30_31, MPC_RMU, inst),\ 173 SRII(SHAPER_RAMB_REGION_32_33, MPC_RMU, inst),\ 174 SRII_MPC_RMU(3DLUT_MODE, MPC_RMU, inst),\ 175 SRII_MPC_RMU(3DLUT_INDEX, MPC_RMU, inst),\ 176 SRII_MPC_RMU(3DLUT_DATA, MPC_RMU, inst),\ 177 SRII_MPC_RMU(3DLUT_DATA_30BIT, MPC_RMU, inst),\ 178 SRII_MPC_RMU(3DLUT_READ_WRITE_CONTROL, MPC_RMU, inst),\ 179 SRII_MPC_RMU(3DLUT_OUT_NORM_FACTOR, MPC_RMU, inst),\ 180 SRII_MPC_RMU(3DLUT_OUT_OFFSET_R, MPC_RMU, inst),\ 181 SRII_MPC_RMU(3DLUT_OUT_OFFSET_G, MPC_RMU, inst),\ 182 SRII_MPC_RMU(3DLUT_OUT_OFFSET_B, MPC_RMU, inst) 183 184 185 #define MPC_DWB_MUX_REG_LIST_DCN3_0(inst) \ 186 SRII_DWB(DWB_MUX, MUX, MPC_DWB, inst) 187 188 #define MPC_REG_VARIABLE_LIST_DCN3_0 \ 189 MPC_REG_VARIABLE_LIST_DCN2_0 \ 190 uint32_t DWB_MUX[MAX_DWB]; \ 191 uint32_t MPCC_GAMUT_REMAP_COEF_FORMAT[MAX_MPCC]; \ 192 uint32_t MPCC_GAMUT_REMAP_MODE[MAX_MPCC]; \ 193 uint32_t MPC_GAMUT_REMAP_C11_C12_A[MAX_MPCC]; \ 194 uint32_t MPC_GAMUT_REMAP_C33_C34_A[MAX_MPCC]; \ 195 uint32_t MPC_GAMUT_REMAP_C11_C12_B[MAX_MPCC]; \ 196 uint32_t MPC_GAMUT_REMAP_C33_C34_B[MAX_MPCC]; \ 197 uint32_t MPC_RMU_CONTROL; \ 198 uint32_t MPC_RMU_MEM_PWR_CTRL; \ 199 uint32_t SHAPER_CONTROL[MAX_RMU]; \ 200 uint32_t SHAPER_OFFSET_R[MAX_RMU]; \ 201 uint32_t SHAPER_OFFSET_G[MAX_RMU]; \ 202 uint32_t SHAPER_OFFSET_B[MAX_RMU]; \ 203 uint32_t SHAPER_SCALE_R[MAX_RMU]; \ 204 uint32_t SHAPER_SCALE_G_B[MAX_RMU]; \ 205 uint32_t SHAPER_LUT_INDEX[MAX_RMU]; \ 206 uint32_t SHAPER_LUT_DATA[MAX_RMU]; \ 207 uint32_t SHAPER_LUT_WRITE_EN_MASK[MAX_RMU]; \ 208 uint32_t SHAPER_RAMA_START_CNTL_B[MAX_RMU]; \ 209 uint32_t SHAPER_RAMA_START_CNTL_G[MAX_RMU]; \ 210 uint32_t SHAPER_RAMA_START_CNTL_R[MAX_RMU]; \ 211 uint32_t SHAPER_RAMA_END_CNTL_B[MAX_RMU]; \ 212 uint32_t SHAPER_RAMA_END_CNTL_G[MAX_RMU]; \ 213 uint32_t SHAPER_RAMA_END_CNTL_R[MAX_RMU]; \ 214 uint32_t SHAPER_RAMA_REGION_0_1[MAX_RMU]; \ 215 uint32_t SHAPER_RAMA_REGION_2_3[MAX_RMU]; \ 216 uint32_t SHAPER_RAMA_REGION_4_5[MAX_RMU]; \ 217 uint32_t SHAPER_RAMA_REGION_6_7[MAX_RMU]; \ 218 uint32_t SHAPER_RAMA_REGION_8_9[MAX_RMU]; \ 219 uint32_t SHAPER_RAMA_REGION_10_11[MAX_RMU]; \ 220 uint32_t SHAPER_RAMA_REGION_12_13[MAX_RMU]; \ 221 uint32_t SHAPER_RAMA_REGION_14_15[MAX_RMU]; \ 222 uint32_t SHAPER_RAMA_REGION_16_17[MAX_RMU]; \ 223 uint32_t SHAPER_RAMA_REGION_18_19[MAX_RMU]; \ 224 uint32_t SHAPER_RAMA_REGION_20_21[MAX_RMU]; \ 225 uint32_t SHAPER_RAMA_REGION_22_23[MAX_RMU]; \ 226 uint32_t SHAPER_RAMA_REGION_24_25[MAX_RMU]; \ 227 uint32_t SHAPER_RAMA_REGION_26_27[MAX_RMU]; \ 228 uint32_t SHAPER_RAMA_REGION_28_29[MAX_RMU]; \ 229 uint32_t SHAPER_RAMA_REGION_30_31[MAX_RMU]; \ 230 uint32_t SHAPER_RAMA_REGION_32_33[MAX_RMU]; \ 231 uint32_t MPCC_OGAM_RAMA_START_SLOPE_CNTL_B[MAX_MPCC]; \ 232 uint32_t MPCC_OGAM_RAMA_START_SLOPE_CNTL_G[MAX_MPCC]; \ 233 uint32_t MPCC_OGAM_RAMA_START_SLOPE_CNTL_R[MAX_MPCC]; \ 234 uint32_t MPCC_OGAM_RAMA_OFFSET_B[MAX_MPCC]; \ 235 uint32_t MPCC_OGAM_RAMA_OFFSET_G[MAX_MPCC]; \ 236 uint32_t MPCC_OGAM_RAMA_OFFSET_R[MAX_MPCC]; \ 237 uint32_t MPCC_OGAM_RAMA_START_BASE_CNTL_B[MAX_MPCC]; \ 238 uint32_t MPCC_OGAM_RAMA_START_BASE_CNTL_G[MAX_MPCC]; \ 239 uint32_t MPCC_OGAM_RAMA_START_BASE_CNTL_R[MAX_MPCC];\ 240 uint32_t SHAPER_RAMB_START_CNTL_B[MAX_RMU]; \ 241 uint32_t SHAPER_RAMB_START_CNTL_G[MAX_RMU]; \ 242 uint32_t SHAPER_RAMB_START_CNTL_R[MAX_RMU]; \ 243 uint32_t SHAPER_RAMB_END_CNTL_B[MAX_RMU]; \ 244 uint32_t SHAPER_RAMB_END_CNTL_G[MAX_RMU]; \ 245 uint32_t SHAPER_RAMB_END_CNTL_R[MAX_RMU]; \ 246 uint32_t SHAPER_RAMB_REGION_0_1[MAX_RMU]; \ 247 uint32_t SHAPER_RAMB_REGION_2_3[MAX_RMU]; \ 248 uint32_t SHAPER_RAMB_REGION_4_5[MAX_RMU]; \ 249 uint32_t SHAPER_RAMB_REGION_6_7[MAX_RMU]; \ 250 uint32_t SHAPER_RAMB_REGION_8_9[MAX_RMU]; \ 251 uint32_t SHAPER_RAMB_REGION_10_11[MAX_RMU]; \ 252 uint32_t SHAPER_RAMB_REGION_12_13[MAX_RMU]; \ 253 uint32_t SHAPER_RAMB_REGION_14_15[MAX_RMU]; \ 254 uint32_t SHAPER_RAMB_REGION_16_17[MAX_RMU]; \ 255 uint32_t SHAPER_RAMB_REGION_18_19[MAX_RMU]; \ 256 uint32_t SHAPER_RAMB_REGION_20_21[MAX_RMU]; \ 257 uint32_t SHAPER_RAMB_REGION_22_23[MAX_RMU]; \ 258 uint32_t SHAPER_RAMB_REGION_24_25[MAX_RMU]; \ 259 uint32_t SHAPER_RAMB_REGION_26_27[MAX_RMU]; \ 260 uint32_t SHAPER_RAMB_REGION_28_29[MAX_RMU]; \ 261 uint32_t SHAPER_RAMB_REGION_30_31[MAX_RMU]; \ 262 uint32_t SHAPER_RAMB_REGION_32_33[MAX_RMU]; \ 263 uint32_t RMU_3DLUT_MODE[MAX_RMU]; \ 264 uint32_t RMU_3DLUT_INDEX[MAX_RMU]; \ 265 uint32_t RMU_3DLUT_DATA[MAX_RMU]; \ 266 uint32_t RMU_3DLUT_DATA_30BIT[MAX_RMU]; \ 267 uint32_t RMU_3DLUT_READ_WRITE_CONTROL[MAX_RMU]; \ 268 uint32_t RMU_3DLUT_OUT_NORM_FACTOR[MAX_RMU]; \ 269 uint32_t RMU_3DLUT_OUT_OFFSET_R[MAX_RMU]; \ 270 uint32_t RMU_3DLUT_OUT_OFFSET_G[MAX_RMU]; \ 271 uint32_t RMU_3DLUT_OUT_OFFSET_B[MAX_RMU]; \ 272 uint32_t MPCC_OGAM_RAMB_START_SLOPE_CNTL_B[MAX_MPCC]; \ 273 uint32_t MPCC_OGAM_RAMB_START_SLOPE_CNTL_G[MAX_MPCC]; \ 274 uint32_t MPCC_OGAM_RAMB_START_SLOPE_CNTL_R[MAX_MPCC]; \ 275 uint32_t MPCC_OGAM_CONTROL[MAX_MPCC]; \ 276 uint32_t MPCC_OGAM_LUT_CONTROL[MAX_MPCC]; \ 277 uint32_t MPCC_OGAM_RAMB_OFFSET_B[MAX_MPCC]; \ 278 uint32_t MPCC_OGAM_RAMB_OFFSET_G[MAX_MPCC]; \ 279 uint32_t MPCC_OGAM_RAMB_OFFSET_R[MAX_MPCC]; \ 280 uint32_t MPCC_OGAM_RAMB_START_BASE_CNTL_B[MAX_MPCC]; \ 281 uint32_t MPCC_OGAM_RAMB_START_BASE_CNTL_G[MAX_MPCC]; \ 282 uint32_t MPCC_OGAM_RAMB_START_BASE_CNTL_R[MAX_MPCC]; \ 283 uint32_t MPC_OUT_CSC_COEF_FORMAT 284 285 #define MPC_REG_VARIABLE_LIST_DCN32 \ 286 uint32_t MPCC_MCM_SHAPER_CONTROL[MAX_MPCC]; \ 287 uint32_t MPCC_MCM_SHAPER_OFFSET_R[MAX_MPCC]; \ 288 uint32_t MPCC_MCM_SHAPER_OFFSET_G[MAX_MPCC]; \ 289 uint32_t MPCC_MCM_SHAPER_OFFSET_B[MAX_MPCC]; \ 290 uint32_t MPCC_MCM_SHAPER_SCALE_R[MAX_MPCC]; \ 291 uint32_t MPCC_MCM_SHAPER_SCALE_G_B[MAX_MPCC]; \ 292 uint32_t MPCC_MCM_SHAPER_LUT_INDEX[MAX_MPCC]; \ 293 uint32_t MPCC_MCM_SHAPER_LUT_DATA[MAX_MPCC]; \ 294 uint32_t MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK[MAX_MPCC]; \ 295 uint32_t MPCC_MCM_SHAPER_RAMA_START_CNTL_B[MAX_MPCC]; \ 296 uint32_t MPCC_MCM_SHAPER_RAMA_START_CNTL_G[MAX_MPCC]; \ 297 uint32_t MPCC_MCM_SHAPER_RAMA_START_CNTL_R[MAX_MPCC]; \ 298 uint32_t MPCC_MCM_SHAPER_RAMA_END_CNTL_B[MAX_MPCC]; \ 299 uint32_t MPCC_MCM_SHAPER_RAMA_END_CNTL_G[MAX_MPCC]; \ 300 uint32_t MPCC_MCM_SHAPER_RAMA_END_CNTL_R[MAX_MPCC]; \ 301 uint32_t MPCC_MCM_SHAPER_RAMA_REGION_0_1[MAX_MPCC]; \ 302 uint32_t MPCC_MCM_SHAPER_RAMA_REGION_2_3[MAX_MPCC]; \ 303 uint32_t MPCC_MCM_SHAPER_RAMA_REGION_4_5[MAX_MPCC]; \ 304 uint32_t MPCC_MCM_SHAPER_RAMA_REGION_6_7[MAX_MPCC]; \ 305 uint32_t MPCC_MCM_SHAPER_RAMA_REGION_8_9[MAX_MPCC]; \ 306 uint32_t MPCC_MCM_SHAPER_RAMA_REGION_10_11[MAX_MPCC]; \ 307 uint32_t MPCC_MCM_SHAPER_RAMA_REGION_12_13[MAX_MPCC]; \ 308 uint32_t MPCC_MCM_SHAPER_RAMA_REGION_14_15[MAX_MPCC]; \ 309 uint32_t MPCC_MCM_SHAPER_RAMA_REGION_16_17[MAX_MPCC]; \ 310 uint32_t MPCC_MCM_SHAPER_RAMA_REGION_18_19[MAX_MPCC]; \ 311 uint32_t MPCC_MCM_SHAPER_RAMA_REGION_20_21[MAX_MPCC]; \ 312 uint32_t MPCC_MCM_SHAPER_RAMA_REGION_22_23[MAX_MPCC]; \ 313 uint32_t MPCC_MCM_SHAPER_RAMA_REGION_24_25[MAX_MPCC]; \ 314 uint32_t MPCC_MCM_SHAPER_RAMA_REGION_26_27[MAX_MPCC]; \ 315 uint32_t MPCC_MCM_SHAPER_RAMA_REGION_28_29[MAX_MPCC]; \ 316 uint32_t MPCC_MCM_SHAPER_RAMA_REGION_30_31[MAX_MPCC]; \ 317 uint32_t MPCC_MCM_SHAPER_RAMA_REGION_32_33[MAX_MPCC]; \ 318 uint32_t MPCC_MCM_SHAPER_RAMB_START_CNTL_B[MAX_MPCC]; \ 319 uint32_t MPCC_MCM_SHAPER_RAMB_START_CNTL_G[MAX_MPCC]; \ 320 uint32_t MPCC_MCM_SHAPER_RAMB_START_CNTL_R[MAX_MPCC]; \ 321 uint32_t MPCC_MCM_SHAPER_RAMB_END_CNTL_B[MAX_MPCC]; \ 322 uint32_t MPCC_MCM_SHAPER_RAMB_END_CNTL_G[MAX_MPCC]; \ 323 uint32_t MPCC_MCM_SHAPER_RAMB_END_CNTL_R[MAX_MPCC]; \ 324 uint32_t MPCC_MCM_SHAPER_RAMB_REGION_0_1[MAX_MPCC]; \ 325 uint32_t MPCC_MCM_SHAPER_RAMB_REGION_2_3[MAX_MPCC]; \ 326 uint32_t MPCC_MCM_SHAPER_RAMB_REGION_4_5[MAX_MPCC]; \ 327 uint32_t MPCC_MCM_SHAPER_RAMB_REGION_6_7[MAX_MPCC]; \ 328 uint32_t MPCC_MCM_SHAPER_RAMB_REGION_8_9[MAX_MPCC]; \ 329 uint32_t MPCC_MCM_SHAPER_RAMB_REGION_10_11[MAX_MPCC]; \ 330 uint32_t MPCC_MCM_SHAPER_RAMB_REGION_12_13[MAX_MPCC]; \ 331 uint32_t MPCC_MCM_SHAPER_RAMB_REGION_14_15[MAX_MPCC]; \ 332 uint32_t MPCC_MCM_SHAPER_RAMB_REGION_16_17[MAX_MPCC]; \ 333 uint32_t MPCC_MCM_SHAPER_RAMB_REGION_18_19[MAX_MPCC]; \ 334 uint32_t MPCC_MCM_SHAPER_RAMB_REGION_20_21[MAX_MPCC]; \ 335 uint32_t MPCC_MCM_SHAPER_RAMB_REGION_22_23[MAX_MPCC]; \ 336 uint32_t MPCC_MCM_SHAPER_RAMB_REGION_24_25[MAX_MPCC]; \ 337 uint32_t MPCC_MCM_SHAPER_RAMB_REGION_26_27[MAX_MPCC]; \ 338 uint32_t MPCC_MCM_SHAPER_RAMB_REGION_28_29[MAX_MPCC]; \ 339 uint32_t MPCC_MCM_SHAPER_RAMB_REGION_30_31[MAX_MPCC]; \ 340 uint32_t MPCC_MCM_SHAPER_RAMB_REGION_32_33[MAX_MPCC]; \ 341 uint32_t MPCC_MCM_3DLUT_MODE[MAX_MPCC]; \ 342 uint32_t MPCC_MCM_3DLUT_INDEX[MAX_MPCC]; \ 343 uint32_t MPCC_MCM_3DLUT_DATA[MAX_MPCC]; \ 344 uint32_t MPCC_MCM_3DLUT_DATA_30BIT[MAX_MPCC]; \ 345 uint32_t MPCC_MCM_3DLUT_READ_WRITE_CONTROL[MAX_MPCC]; \ 346 uint32_t MPCC_MCM_3DLUT_OUT_NORM_FACTOR[MAX_MPCC]; \ 347 uint32_t MPCC_MCM_3DLUT_OUT_OFFSET_R[MAX_MPCC]; \ 348 uint32_t MPCC_MCM_3DLUT_OUT_OFFSET_G[MAX_MPCC]; \ 349 uint32_t MPCC_MCM_3DLUT_OUT_OFFSET_B[MAX_MPCC]; \ 350 uint32_t MPCC_MCM_MEM_PWR_CTRL[MAX_MPCC] 351 352 #define MPC_COMMON_MASK_SH_LIST_DCN3_0(mask_sh) \ 353 MPC_COMMON_MASK_SH_LIST_DCN1_0(mask_sh),\ 354 SF(MPCC0_MPCC_CONTROL, MPCC_BG_BPC, mask_sh),\ 355 SF(MPCC0_MPCC_CONTROL, MPCC_BOT_GAIN_MODE, mask_sh),\ 356 SF(MPCC0_MPCC_TOP_GAIN, MPCC_TOP_GAIN, mask_sh),\ 357 SF(MPCC0_MPCC_BOT_GAIN_INSIDE, MPCC_BOT_GAIN_INSIDE, mask_sh),\ 358 SF(MPCC0_MPCC_BOT_GAIN_OUTSIDE, MPCC_BOT_GAIN_OUTSIDE, mask_sh),\ 359 SF(MPC_OUT0_CSC_MODE, MPC_OCSC_MODE, mask_sh),\ 360 SF(MPC_OUT0_CSC_C11_C12_A, MPC_OCSC_C11_A, mask_sh),\ 361 SF(MPC_OUT0_CSC_C11_C12_A, MPC_OCSC_C12_A, mask_sh),\ 362 SF(MPCC0_MPCC_STATUS, MPCC_DISABLED, mask_sh),\ 363 SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_FORCE, mask_sh),\ 364 SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_DIS, mask_sh),\ 365 SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_STATE, mask_sh),\ 366 SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_MODE, mask_sh),\ 367 SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_CLAMP_MAX_R_CR, mask_sh),\ 368 SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_CLAMP_MIN_R_CR, mask_sh),\ 369 SF(MPC_OUT0_DENORM_CLAMP_G_Y, MPC_OUT_DENORM_CLAMP_MAX_G_Y, mask_sh),\ 370 SF(MPC_OUT0_DENORM_CLAMP_G_Y, MPC_OUT_DENORM_CLAMP_MIN_G_Y, mask_sh),\ 371 SF(MPC_OUT0_DENORM_CLAMP_B_CB, MPC_OUT_DENORM_CLAMP_MAX_B_CB, mask_sh),\ 372 SF(MPC_OUT0_DENORM_CLAMP_B_CB, MPC_OUT_DENORM_CLAMP_MIN_B_CB, mask_sh),\ 373 SF(MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE, MPCC_GAMUT_REMAP_MODE, mask_sh),\ 374 SF(MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE, MPCC_GAMUT_REMAP_MODE_CURRENT, mask_sh),\ 375 SF(MPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT, MPCC_GAMUT_REMAP_COEF_FORMAT, mask_sh),\ 376 SF(MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A, MPCC_GAMUT_REMAP_C11_A, mask_sh),\ 377 SF(MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A, MPCC_GAMUT_REMAP_C12_A, mask_sh),\ 378 SF(MPC_DWB0_MUX, MPC_DWB0_MUX, mask_sh),\ 379 SF(MPC_DWB0_MUX, MPC_DWB0_MUX_STATUS, mask_sh),\ 380 SF(MPC_OUT0_MUX, MPC_OUT_RATE_CONTROL, mask_sh),\ 381 SF(MPC_OUT0_MUX, MPC_OUT_RATE_CONTROL_DISABLE, mask_sh),\ 382 SF(MPC_OUT0_MUX, MPC_OUT_FLOW_CONTROL_MODE, mask_sh),\ 383 SF(MPC_OUT0_MUX, MPC_OUT_FLOW_CONTROL_COUNT, mask_sh), \ 384 SF(MPC_RMU_CONTROL, MPC_RMU0_MUX, mask_sh), \ 385 SF(MPC_RMU_CONTROL, MPC_RMU1_MUX, mask_sh), \ 386 SF(MPC_RMU_CONTROL, MPC_RMU0_MUX_STATUS, mask_sh), \ 387 SF(MPC_RMU_CONTROL, MPC_RMU1_MUX_STATUS, mask_sh), \ 388 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh),\ 389 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\ 390 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh),\ 391 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\ 392 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B, MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B, mask_sh),\ 393 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B, MPCC_OGAM_RAMA_EXP_REGION_END_B, mask_sh),\ 394 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B, MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B, mask_sh),\ 395 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B, mask_sh),\ 396 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B, mask_sh),\ 397 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_B, mask_sh),\ 398 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh),\ 399 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B, MPCC_OGAM_RAMA_OFFSET_B, mask_sh),\ 400 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G, MPCC_OGAM_RAMA_OFFSET_G, mask_sh),\ 401 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R, MPCC_OGAM_RAMA_OFFSET_R, mask_sh),\ 402 SF(MPCC_OGAM0_MPCC_OGAM_LUT_INDEX, MPCC_OGAM_LUT_INDEX, mask_sh),\ 403 SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_MODE, mask_sh),\ 404 SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_SELECT, mask_sh),\ 405 SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_PWL_DISABLE, mask_sh),\ 406 SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_MODE_CURRENT, mask_sh),\ 407 SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_SELECT_CURRENT, mask_sh),\ 408 SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_WRITE_COLOR_MASK, mask_sh),\ 409 SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_READ_COLOR_SEL, mask_sh),\ 410 SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_READ_DBG, mask_sh),\ 411 SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_HOST_SEL, mask_sh),\ 412 SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_CONFIG_MODE, mask_sh),\ 413 SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_STATUS, mask_sh),\ 414 SF(MPCC_OGAM0_MPCC_OGAM_LUT_DATA, MPCC_OGAM_LUT_DATA, mask_sh),\ 415 SF(MPC_RMU0_3DLUT_MODE, MPC_RMU_3DLUT_MODE, mask_sh),\ 416 SF(MPC_RMU0_3DLUT_MODE, MPC_RMU_3DLUT_SIZE, mask_sh),\ 417 SF(MPC_RMU0_3DLUT_MODE, MPC_RMU_3DLUT_MODE_CURRENT, mask_sh),\ 418 SF(MPC_RMU0_3DLUT_READ_WRITE_CONTROL, MPC_RMU_3DLUT_WRITE_EN_MASK, mask_sh),\ 419 SF(MPC_RMU0_3DLUT_READ_WRITE_CONTROL, MPC_RMU_3DLUT_RAM_SEL, mask_sh),\ 420 SF(MPC_RMU0_3DLUT_READ_WRITE_CONTROL, MPC_RMU_3DLUT_30BIT_EN, mask_sh),\ 421 SF(MPC_RMU0_3DLUT_READ_WRITE_CONTROL, MPC_RMU_3DLUT_CONFIG_STATUS, mask_sh),\ 422 SF(MPC_RMU0_3DLUT_READ_WRITE_CONTROL, MPC_RMU_3DLUT_READ_SEL, mask_sh),\ 423 SF(MPC_RMU0_3DLUT_INDEX, MPC_RMU_3DLUT_INDEX, mask_sh),\ 424 SF(MPC_RMU0_3DLUT_DATA, MPC_RMU_3DLUT_DATA0, mask_sh),\ 425 SF(MPC_RMU0_3DLUT_DATA, MPC_RMU_3DLUT_DATA1, mask_sh),\ 426 SF(MPC_RMU0_3DLUT_DATA_30BIT, MPC_RMU_3DLUT_DATA_30BIT, mask_sh),\ 427 SF(MPC_RMU0_SHAPER_CONTROL, MPC_RMU_SHAPER_LUT_MODE, mask_sh),\ 428 SF(MPC_RMU0_SHAPER_CONTROL, MPC_RMU_SHAPER_LUT_MODE_CURRENT, mask_sh),\ 429 SF(MPC_RMU0_SHAPER_OFFSET_R, MPC_RMU_SHAPER_OFFSET_R, mask_sh),\ 430 SF(MPC_RMU0_SHAPER_OFFSET_G, MPC_RMU_SHAPER_OFFSET_G, mask_sh),\ 431 SF(MPC_RMU0_SHAPER_OFFSET_B, MPC_RMU_SHAPER_OFFSET_B, mask_sh),\ 432 SF(MPC_RMU0_SHAPER_SCALE_R, MPC_RMU_SHAPER_SCALE_R, mask_sh),\ 433 SF(MPC_RMU0_SHAPER_SCALE_G_B, MPC_RMU_SHAPER_SCALE_G, mask_sh),\ 434 SF(MPC_RMU0_SHAPER_SCALE_G_B, MPC_RMU_SHAPER_SCALE_B, mask_sh),\ 435 SF(MPC_RMU0_SHAPER_LUT_INDEX, MPC_RMU_SHAPER_LUT_INDEX, mask_sh),\ 436 SF(MPC_RMU0_SHAPER_LUT_DATA, MPC_RMU_SHAPER_LUT_DATA, mask_sh),\ 437 SF(MPC_RMU0_SHAPER_LUT_WRITE_EN_MASK, MPC_RMU_SHAPER_LUT_WRITE_EN_MASK, mask_sh),\ 438 SF(MPC_RMU0_SHAPER_LUT_WRITE_EN_MASK, MPC_RMU_SHAPER_LUT_WRITE_SEL, mask_sh),\ 439 SF(MPC_RMU0_SHAPER_LUT_WRITE_EN_MASK, MPC_RMU_SHAPER_CONFIG_STATUS, mask_sh),\ 440 SF(MPC_RMU0_SHAPER_RAMA_START_CNTL_B, MPC_RMU_SHAPER_RAMA_EXP_REGION_START_B, mask_sh),\ 441 SF(MPC_RMU0_SHAPER_RAMA_START_CNTL_B, MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh),\ 442 SF(MPC_RMU0_SHAPER_RAMA_END_CNTL_B, MPC_RMU_SHAPER_RAMA_EXP_REGION_END_B, mask_sh),\ 443 SF(MPC_RMU0_SHAPER_RAMA_END_CNTL_B, MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_B, mask_sh),\ 444 SF(MPC_RMU0_SHAPER_RAMA_REGION_0_1, MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh),\ 445 SF(MPC_RMU0_SHAPER_RAMA_REGION_0_1, MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\ 446 SF(MPC_RMU0_SHAPER_RAMA_REGION_0_1, MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh),\ 447 SF(MPC_RMU0_SHAPER_RAMA_REGION_0_1, MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\ 448 SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_MEM_PWR_FORCE, mask_sh),\ 449 SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_MEM_PWR_DIS, mask_sh),\ 450 SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_SHAPER_MEM_PWR_STATE, mask_sh),\ 451 SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_3DLUT_MEM_PWR_STATE, mask_sh),\ 452 SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU1_MEM_PWR_FORCE, mask_sh),\ 453 SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU1_MEM_PWR_DIS, mask_sh),\ 454 SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU1_SHAPER_MEM_PWR_STATE, mask_sh),\ 455 SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU1_3DLUT_MEM_PWR_STATE, mask_sh),\ 456 SF(CUR_VUPDATE_LOCK_SET0, CUR_VUPDATE_LOCK_SET, mask_sh) 457 458 459 #define MPC_COMMON_MASK_SH_LIST_DCN30(mask_sh) \ 460 MPC_COMMON_MASK_SH_LIST_DCN1_0(mask_sh),\ 461 SF(MPCC0_MPCC_CONTROL, MPCC_BG_BPC, mask_sh),\ 462 SF(MPCC0_MPCC_CONTROL, MPCC_BOT_GAIN_MODE, mask_sh),\ 463 SF(MPCC0_MPCC_TOP_GAIN, MPCC_TOP_GAIN, mask_sh),\ 464 SF(MPCC0_MPCC_BOT_GAIN_INSIDE, MPCC_BOT_GAIN_INSIDE, mask_sh),\ 465 SF(MPCC0_MPCC_BOT_GAIN_OUTSIDE, MPCC_BOT_GAIN_OUTSIDE, mask_sh),\ 466 SF(MPC_OUT0_CSC_MODE, MPC_OCSC_MODE, mask_sh),\ 467 SF(MPC_OUT0_CSC_C11_C12_A, MPC_OCSC_C11_A, mask_sh),\ 468 SF(MPC_OUT0_CSC_C11_C12_A, MPC_OCSC_C12_A, mask_sh),\ 469 SF(MPCC0_MPCC_STATUS, MPCC_DISABLED, mask_sh),\ 470 SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_FORCE, mask_sh),\ 471 SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_DIS, mask_sh),\ 472 SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_LOW_PWR_MODE, mask_sh),\ 473 SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_STATE, mask_sh),\ 474 SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_MODE, mask_sh),\ 475 SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_CLAMP_MAX_R_CR, mask_sh),\ 476 SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_CLAMP_MIN_R_CR, mask_sh),\ 477 SF(MPC_OUT0_DENORM_CLAMP_G_Y, MPC_OUT_DENORM_CLAMP_MAX_G_Y, mask_sh),\ 478 SF(MPC_OUT0_DENORM_CLAMP_G_Y, MPC_OUT_DENORM_CLAMP_MIN_G_Y, mask_sh),\ 479 SF(MPC_OUT0_DENORM_CLAMP_B_CB, MPC_OUT_DENORM_CLAMP_MAX_B_CB, mask_sh),\ 480 SF(MPC_OUT0_DENORM_CLAMP_B_CB, MPC_OUT_DENORM_CLAMP_MIN_B_CB, mask_sh),\ 481 SF(MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE, MPCC_GAMUT_REMAP_MODE, mask_sh),\ 482 SF(MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE, MPCC_GAMUT_REMAP_MODE_CURRENT, mask_sh),\ 483 SF(MPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT, MPCC_GAMUT_REMAP_COEF_FORMAT, mask_sh),\ 484 SF(MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A, MPCC_GAMUT_REMAP_C11_A, mask_sh),\ 485 SF(MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A, MPCC_GAMUT_REMAP_C12_A, mask_sh),\ 486 SF(MPC_DWB0_MUX, MPC_DWB0_MUX, mask_sh),\ 487 SF(MPC_DWB0_MUX, MPC_DWB0_MUX_STATUS, mask_sh),\ 488 SF(MPC_OUT0_MUX, MPC_OUT_RATE_CONTROL, mask_sh),\ 489 SF(MPC_OUT0_MUX, MPC_OUT_RATE_CONTROL_DISABLE, mask_sh),\ 490 SF(MPC_OUT0_MUX, MPC_OUT_FLOW_CONTROL_MODE, mask_sh),\ 491 SF(MPC_OUT0_MUX, MPC_OUT_FLOW_CONTROL_COUNT, mask_sh), \ 492 SF(MPC_RMU_CONTROL, MPC_RMU0_MUX, mask_sh), \ 493 SF(MPC_RMU_CONTROL, MPC_RMU1_MUX, mask_sh), \ 494 SF(MPC_RMU_CONTROL, MPC_RMU0_MUX_STATUS, mask_sh), \ 495 SF(MPC_RMU_CONTROL, MPC_RMU1_MUX_STATUS, mask_sh), \ 496 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh),\ 497 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\ 498 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh),\ 499 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\ 500 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B, MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B, mask_sh),\ 501 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B, MPCC_OGAM_RAMA_EXP_REGION_END_B, mask_sh),\ 502 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B, MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B, mask_sh),\ 503 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B, mask_sh),\ 504 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B, mask_sh),\ 505 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_B, mask_sh),\ 506 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh),\ 507 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B, MPCC_OGAM_RAMA_OFFSET_B, mask_sh),\ 508 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G, MPCC_OGAM_RAMA_OFFSET_G, mask_sh),\ 509 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R, MPCC_OGAM_RAMA_OFFSET_R, mask_sh),\ 510 SF(MPCC_OGAM0_MPCC_OGAM_LUT_INDEX, MPCC_OGAM_LUT_INDEX, mask_sh),\ 511 SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_MODE, mask_sh),\ 512 SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_SELECT, mask_sh),\ 513 SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_PWL_DISABLE, mask_sh),\ 514 SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_MODE_CURRENT, mask_sh),\ 515 SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_SELECT_CURRENT, mask_sh),\ 516 SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_WRITE_COLOR_MASK, mask_sh),\ 517 SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_READ_COLOR_SEL, mask_sh),\ 518 SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_READ_DBG, mask_sh),\ 519 SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_HOST_SEL, mask_sh),\ 520 SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_CONFIG_MODE, mask_sh),\ 521 /*SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_STATUS, mask_sh),*/\ 522 SF(MPCC_OGAM0_MPCC_OGAM_LUT_DATA, MPCC_OGAM_LUT_DATA, mask_sh),\ 523 SF(MPC_RMU0_3DLUT_MODE, MPC_RMU_3DLUT_MODE, mask_sh),\ 524 SF(MPC_RMU0_3DLUT_MODE, MPC_RMU_3DLUT_SIZE, mask_sh),\ 525 /*SF(MPC_RMU0_3DLUT_MODE, MPC_RMU_3DLUT_MODE_CURRENT, mask_sh),*/\ 526 SF(MPC_RMU0_3DLUT_READ_WRITE_CONTROL, MPC_RMU_3DLUT_WRITE_EN_MASK, mask_sh),\ 527 SF(MPC_RMU0_3DLUT_READ_WRITE_CONTROL, MPC_RMU_3DLUT_RAM_SEL, mask_sh),\ 528 SF(MPC_RMU0_3DLUT_READ_WRITE_CONTROL, MPC_RMU_3DLUT_30BIT_EN, mask_sh),\ 529 /*SF(MPC_RMU0_3DLUT_READ_WRITE_CONTROL, MPC_RMU_3DLUT_CONFIG_STATUS, mask_sh),*/\ 530 SF(MPC_RMU0_3DLUT_READ_WRITE_CONTROL, MPC_RMU_3DLUT_READ_SEL, mask_sh),\ 531 SF(MPC_RMU0_3DLUT_INDEX, MPC_RMU_3DLUT_INDEX, mask_sh),\ 532 SF(MPC_RMU0_3DLUT_DATA, MPC_RMU_3DLUT_DATA0, mask_sh),\ 533 SF(MPC_RMU0_3DLUT_DATA, MPC_RMU_3DLUT_DATA1, mask_sh),\ 534 SF(MPC_RMU0_3DLUT_DATA_30BIT, MPC_RMU_3DLUT_DATA_30BIT, mask_sh),\ 535 SF(MPC_RMU0_SHAPER_CONTROL, MPC_RMU_SHAPER_LUT_MODE, mask_sh),\ 536 /*SF(MPC_RMU0_SHAPER_CONTROL, MPC_RMU_SHAPER_LUT_MODE_CURRENT, mask_sh),*/\ 537 SF(MPC_RMU0_SHAPER_OFFSET_R, MPC_RMU_SHAPER_OFFSET_R, mask_sh),\ 538 SF(MPC_RMU0_SHAPER_OFFSET_G, MPC_RMU_SHAPER_OFFSET_G, mask_sh),\ 539 SF(MPC_RMU0_SHAPER_OFFSET_B, MPC_RMU_SHAPER_OFFSET_B, mask_sh),\ 540 SF(MPC_RMU0_SHAPER_SCALE_R, MPC_RMU_SHAPER_SCALE_R, mask_sh),\ 541 SF(MPC_RMU0_SHAPER_SCALE_G_B, MPC_RMU_SHAPER_SCALE_G, mask_sh),\ 542 SF(MPC_RMU0_SHAPER_SCALE_G_B, MPC_RMU_SHAPER_SCALE_B, mask_sh),\ 543 SF(MPC_RMU0_SHAPER_LUT_INDEX, MPC_RMU_SHAPER_LUT_INDEX, mask_sh),\ 544 SF(MPC_RMU0_SHAPER_LUT_DATA, MPC_RMU_SHAPER_LUT_DATA, mask_sh),\ 545 SF(MPC_RMU0_SHAPER_LUT_WRITE_EN_MASK, MPC_RMU_SHAPER_LUT_WRITE_EN_MASK, mask_sh),\ 546 SF(MPC_RMU0_SHAPER_LUT_WRITE_EN_MASK, MPC_RMU_SHAPER_LUT_WRITE_SEL, mask_sh),\ 547 /*SF(MPC_RMU0_SHAPER_LUT_WRITE_EN_MASK, MPC_RMU_SHAPER_CONFIG_STATUS, mask_sh),*/\ 548 SF(MPC_RMU0_SHAPER_RAMA_START_CNTL_B, MPC_RMU_SHAPER_RAMA_EXP_REGION_START_B, mask_sh),\ 549 SF(MPC_RMU0_SHAPER_RAMA_START_CNTL_B, MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh),\ 550 SF(MPC_RMU0_SHAPER_RAMA_END_CNTL_B, MPC_RMU_SHAPER_RAMA_EXP_REGION_END_B, mask_sh),\ 551 SF(MPC_RMU0_SHAPER_RAMA_END_CNTL_B, MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_B, mask_sh),\ 552 SF(MPC_RMU0_SHAPER_RAMA_REGION_0_1, MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh),\ 553 SF(MPC_RMU0_SHAPER_RAMA_REGION_0_1, MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\ 554 SF(MPC_RMU0_SHAPER_RAMA_REGION_0_1, MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh),\ 555 SF(MPC_RMU0_SHAPER_RAMA_REGION_0_1, MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\ 556 SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_MEM_PWR_FORCE, mask_sh),\ 557 SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_MEM_PWR_DIS, mask_sh),\ 558 SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_SHAPER_MEM_PWR_STATE, mask_sh),\ 559 SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_3DLUT_MEM_PWR_STATE, mask_sh),\ 560 SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_MEM_LOW_PWR_MODE, mask_sh),\ 561 SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU1_MEM_PWR_FORCE, mask_sh),\ 562 SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU1_MEM_PWR_DIS, mask_sh),\ 563 SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU1_SHAPER_MEM_PWR_STATE, mask_sh),\ 564 SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU1_3DLUT_MEM_PWR_STATE, mask_sh),\ 565 SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU1_MEM_LOW_PWR_MODE, mask_sh),\ 566 SF(MPC_RMU0_SHAPER_CONTROL, MPC_RMU_SHAPER_MODE_CURRENT, mask_sh),\ 567 SF(CUR_VUPDATE_LOCK_SET0, CUR_VUPDATE_LOCK_SET, mask_sh) 568 569 570 #define MPC_REG_FIELD_LIST_DCN3_0(type) \ 571 MPC_REG_FIELD_LIST_DCN2_0(type) \ 572 type MPC_DWB0_MUX;\ 573 type MPC_DWB0_MUX_STATUS;\ 574 type MPC_OUT_RATE_CONTROL;\ 575 type MPC_OUT_RATE_CONTROL_DISABLE;\ 576 type MPC_OUT_FLOW_CONTROL_MODE;\ 577 type MPC_OUT_FLOW_CONTROL_COUNT; \ 578 type MPCC_GAMUT_REMAP_MODE; \ 579 type MPCC_GAMUT_REMAP_MODE_CURRENT;\ 580 type MPCC_GAMUT_REMAP_COEF_FORMAT; \ 581 type MPCC_GAMUT_REMAP_C11_A; \ 582 type MPCC_GAMUT_REMAP_C12_A; \ 583 type MPC_RMU0_MUX; \ 584 type MPC_RMU1_MUX; \ 585 type MPC_RMU0_MUX_STATUS; \ 586 type MPC_RMU1_MUX_STATUS; \ 587 type MPC_RMU0_MEM_PWR_FORCE;\ 588 type MPC_RMU0_MEM_PWR_DIS;\ 589 type MPC_RMU0_MEM_LOW_PWR_MODE;\ 590 type MPC_RMU0_SHAPER_MEM_PWR_STATE;\ 591 type MPC_RMU0_3DLUT_MEM_PWR_STATE;\ 592 type MPC_RMU1_MEM_PWR_FORCE;\ 593 type MPC_RMU1_MEM_PWR_DIS;\ 594 type MPC_RMU1_MEM_LOW_PWR_MODE;\ 595 type MPC_RMU1_SHAPER_MEM_PWR_STATE;\ 596 type MPC_RMU1_3DLUT_MEM_PWR_STATE;\ 597 type MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B; \ 598 type MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B;\ 599 type MPCC_OGAM_RAMA_OFFSET_B;\ 600 type MPCC_OGAM_RAMA_OFFSET_G;\ 601 type MPCC_OGAM_RAMA_OFFSET_R;\ 602 type MPCC_OGAM_SELECT; \ 603 type MPCC_OGAM_PWL_DISABLE; \ 604 type MPCC_OGAM_MODE_CURRENT; \ 605 type MPCC_OGAM_SELECT_CURRENT; \ 606 type MPCC_OGAM_LUT_WRITE_COLOR_MASK; \ 607 type MPCC_OGAM_LUT_READ_COLOR_SEL; \ 608 type MPCC_OGAM_LUT_READ_DBG; \ 609 type MPCC_OGAM_LUT_HOST_SEL; \ 610 type MPCC_OGAM_LUT_CONFIG_MODE; \ 611 type MPCC_OGAM_LUT_STATUS; \ 612 type MPCC_OGAM_RAMA_START_BASE_CNTL_B;\ 613 type MPCC_OGAM_MEM_LOW_PWR_MODE;\ 614 type MPCC_OGAM_MEM_PWR_STATE;\ 615 type MPC_RMU_3DLUT_MODE; \ 616 type MPC_RMU_3DLUT_SIZE; \ 617 type MPC_RMU_3DLUT_MODE_CURRENT; \ 618 type MPC_RMU_3DLUT_WRITE_EN_MASK;\ 619 type MPC_RMU_3DLUT_RAM_SEL;\ 620 type MPC_RMU_3DLUT_30BIT_EN;\ 621 type MPC_RMU_3DLUT_CONFIG_STATUS;\ 622 type MPC_RMU_3DLUT_READ_SEL;\ 623 type MPC_RMU_3DLUT_INDEX;\ 624 type MPC_RMU_3DLUT_DATA0;\ 625 type MPC_RMU_3DLUT_DATA1;\ 626 type MPC_RMU_3DLUT_DATA_30BIT;\ 627 type MPC_RMU_SHAPER_LUT_MODE;\ 628 type MPC_RMU_SHAPER_LUT_MODE_CURRENT;\ 629 type MPC_RMU_SHAPER_OFFSET_R;\ 630 type MPC_RMU_SHAPER_OFFSET_G;\ 631 type MPC_RMU_SHAPER_OFFSET_B;\ 632 type MPC_RMU_SHAPER_SCALE_R;\ 633 type MPC_RMU_SHAPER_SCALE_G;\ 634 type MPC_RMU_SHAPER_SCALE_B;\ 635 type MPC_RMU_SHAPER_LUT_INDEX;\ 636 type MPC_RMU_SHAPER_LUT_DATA;\ 637 type MPC_RMU_SHAPER_LUT_WRITE_EN_MASK;\ 638 type MPC_RMU_SHAPER_LUT_WRITE_SEL;\ 639 type MPC_RMU_SHAPER_CONFIG_STATUS;\ 640 type MPC_RMU_SHAPER_RAMA_EXP_REGION_START_B;\ 641 type MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B;\ 642 type MPC_RMU_SHAPER_RAMA_EXP_REGION_END_B;\ 643 type MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_B;\ 644 type MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET;\ 645 type MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS;\ 646 type MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET;\ 647 type MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS;\ 648 type MPC_RMU_SHAPER_MODE_CURRENT 649 650 #define MPC_REG_FIELD_LIST_DCN32(type) \ 651 type MPCC_MCM_SHAPER_MEM_PWR_FORCE;\ 652 type MPCC_MCM_SHAPER_MEM_PWR_DIS;\ 653 type MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE;\ 654 type MPCC_MCM_3DLUT_MEM_PWR_FORCE;\ 655 type MPCC_MCM_3DLUT_MEM_PWR_DIS;\ 656 type MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE;\ 657 type MPCC_MCM_1DLUT_MEM_PWR_FORCE;\ 658 type MPCC_MCM_1DLUT_MEM_PWR_DIS;\ 659 type MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE;\ 660 type MPCC_MCM_SHAPER_MEM_PWR_STATE;\ 661 type MPCC_MCM_3DLUT_MEM_PWR_STATE;\ 662 type MPCC_MCM_1DLUT_MEM_PWR_STATE;\ 663 type MPCC_MCM_3DLUT_MODE; \ 664 type MPCC_MCM_3DLUT_SIZE; \ 665 type MPCC_MCM_3DLUT_MODE_CURRENT; \ 666 type MPCC_MCM_3DLUT_WRITE_EN_MASK;\ 667 type MPCC_MCM_3DLUT_RAM_SEL;\ 668 type MPCC_MCM_3DLUT_30BIT_EN;\ 669 type MPCC_MCM_3DLUT_CONFIG_STATUS;\ 670 type MPCC_MCM_3DLUT_READ_SEL;\ 671 type MPCC_MCM_3DLUT_INDEX;\ 672 type MPCC_MCM_3DLUT_DATA0;\ 673 type MPCC_MCM_3DLUT_DATA1;\ 674 type MPCC_MCM_3DLUT_DATA_30BIT;\ 675 type MPCC_MCM_SHAPER_LUT_MODE;\ 676 type MPCC_MCM_SHAPER_MODE_CURRENT;\ 677 type MPCC_MCM_SHAPER_OFFSET_R;\ 678 type MPCC_MCM_SHAPER_OFFSET_G;\ 679 type MPCC_MCM_SHAPER_OFFSET_B;\ 680 type MPCC_MCM_SHAPER_SCALE_R;\ 681 type MPCC_MCM_SHAPER_SCALE_G;\ 682 type MPCC_MCM_SHAPER_SCALE_B;\ 683 type MPCC_MCM_SHAPER_LUT_INDEX;\ 684 type MPCC_MCM_SHAPER_LUT_DATA;\ 685 type MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK;\ 686 type MPCC_MCM_SHAPER_LUT_WRITE_SEL;\ 687 type MPCC_MCM_SHAPER_CONFIG_STATUS;\ 688 type MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B;\ 689 type MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B;\ 690 type MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B;\ 691 type MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B;\ 692 type MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET;\ 693 type MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS;\ 694 type MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET;\ 695 type MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS 696 697 #define MPC_COMMON_MASK_SH_LIST_DCN303(mask_sh) \ 698 MPC_COMMON_MASK_SH_LIST_DCN1_0(mask_sh),\ 699 SF(MPCC0_MPCC_CONTROL, MPCC_BG_BPC, mask_sh),\ 700 SF(MPCC0_MPCC_CONTROL, MPCC_BOT_GAIN_MODE, mask_sh),\ 701 SF(MPCC0_MPCC_TOP_GAIN, MPCC_TOP_GAIN, mask_sh),\ 702 SF(MPCC0_MPCC_BOT_GAIN_INSIDE, MPCC_BOT_GAIN_INSIDE, mask_sh),\ 703 SF(MPCC0_MPCC_BOT_GAIN_OUTSIDE, MPCC_BOT_GAIN_OUTSIDE, mask_sh),\ 704 SF(MPC_OUT0_CSC_MODE, MPC_OCSC_MODE, mask_sh),\ 705 SF(MPC_OUT0_CSC_C11_C12_A, MPC_OCSC_C11_A, mask_sh),\ 706 SF(MPC_OUT0_CSC_C11_C12_A, MPC_OCSC_C12_A, mask_sh),\ 707 SF(MPCC0_MPCC_STATUS, MPCC_DISABLED, mask_sh),\ 708 SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_FORCE, mask_sh),\ 709 SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_DIS, mask_sh),\ 710 SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_LOW_PWR_MODE, mask_sh),\ 711 SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_STATE, mask_sh),\ 712 SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_MODE, mask_sh),\ 713 SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_CLAMP_MAX_R_CR, mask_sh),\ 714 SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_CLAMP_MIN_R_CR, mask_sh),\ 715 SF(MPC_OUT0_DENORM_CLAMP_G_Y, MPC_OUT_DENORM_CLAMP_MAX_G_Y, mask_sh),\ 716 SF(MPC_OUT0_DENORM_CLAMP_G_Y, MPC_OUT_DENORM_CLAMP_MIN_G_Y, mask_sh),\ 717 SF(MPC_OUT0_DENORM_CLAMP_B_CB, MPC_OUT_DENORM_CLAMP_MAX_B_CB, mask_sh),\ 718 SF(MPC_OUT0_DENORM_CLAMP_B_CB, MPC_OUT_DENORM_CLAMP_MIN_B_CB, mask_sh),\ 719 SF(MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE, MPCC_GAMUT_REMAP_MODE, mask_sh),\ 720 SF(MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE, MPCC_GAMUT_REMAP_MODE_CURRENT, mask_sh),\ 721 SF(MPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT, MPCC_GAMUT_REMAP_COEF_FORMAT, mask_sh),\ 722 SF(MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A, MPCC_GAMUT_REMAP_C11_A, mask_sh),\ 723 SF(MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A, MPCC_GAMUT_REMAP_C12_A, mask_sh),\ 724 SF(MPC_DWB0_MUX, MPC_DWB0_MUX, mask_sh),\ 725 SF(MPC_DWB0_MUX, MPC_DWB0_MUX_STATUS, mask_sh),\ 726 SF(MPC_OUT0_MUX, MPC_OUT_RATE_CONTROL, mask_sh),\ 727 SF(MPC_OUT0_MUX, MPC_OUT_RATE_CONTROL_DISABLE, mask_sh),\ 728 SF(MPC_OUT0_MUX, MPC_OUT_FLOW_CONTROL_MODE, mask_sh),\ 729 SF(MPC_OUT0_MUX, MPC_OUT_FLOW_CONTROL_COUNT, mask_sh), \ 730 SF(MPC_RMU_CONTROL, MPC_RMU0_MUX, mask_sh), \ 731 SF(MPC_RMU_CONTROL, MPC_RMU0_MUX_STATUS, mask_sh), \ 732 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh),\ 733 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\ 734 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh),\ 735 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\ 736 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B, MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B, mask_sh),\ 737 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B, MPCC_OGAM_RAMA_EXP_REGION_END_B, mask_sh),\ 738 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B, MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B, mask_sh),\ 739 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B, mask_sh),\ 740 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B, mask_sh),\ 741 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_B, mask_sh),\ 742 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh),\ 743 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B, MPCC_OGAM_RAMA_OFFSET_B, mask_sh),\ 744 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G, MPCC_OGAM_RAMA_OFFSET_G, mask_sh),\ 745 SF(MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R, MPCC_OGAM_RAMA_OFFSET_R, mask_sh),\ 746 SF(MPCC_OGAM0_MPCC_OGAM_LUT_INDEX, MPCC_OGAM_LUT_INDEX, mask_sh),\ 747 SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_MODE, mask_sh),\ 748 SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_SELECT, mask_sh),\ 749 SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_PWL_DISABLE, mask_sh),\ 750 SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_MODE_CURRENT, mask_sh),\ 751 SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_SELECT_CURRENT, mask_sh),\ 752 SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_WRITE_COLOR_MASK, mask_sh),\ 753 SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_READ_COLOR_SEL, mask_sh),\ 754 SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_READ_DBG, mask_sh),\ 755 SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_HOST_SEL, mask_sh),\ 756 SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_CONFIG_MODE, mask_sh),\ 757 /*SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_STATUS, mask_sh),*/\ 758 SF(MPCC_OGAM0_MPCC_OGAM_LUT_DATA, MPCC_OGAM_LUT_DATA, mask_sh),\ 759 SF(MPC_RMU0_3DLUT_MODE, MPC_RMU_3DLUT_MODE, mask_sh),\ 760 SF(MPC_RMU0_3DLUT_MODE, MPC_RMU_3DLUT_SIZE, mask_sh),\ 761 /*SF(MPC_RMU0_3DLUT_MODE, MPC_RMU_3DLUT_MODE_CURRENT, mask_sh),*/\ 762 SF(MPC_RMU0_3DLUT_READ_WRITE_CONTROL, MPC_RMU_3DLUT_WRITE_EN_MASK, mask_sh),\ 763 SF(MPC_RMU0_3DLUT_READ_WRITE_CONTROL, MPC_RMU_3DLUT_RAM_SEL, mask_sh),\ 764 SF(MPC_RMU0_3DLUT_READ_WRITE_CONTROL, MPC_RMU_3DLUT_30BIT_EN, mask_sh),\ 765 /*SF(MPC_RMU0_3DLUT_READ_WRITE_CONTROL, MPC_RMU_3DLUT_CONFIG_STATUS, mask_sh),*/\ 766 SF(MPC_RMU0_3DLUT_READ_WRITE_CONTROL, MPC_RMU_3DLUT_READ_SEL, mask_sh),\ 767 SF(MPC_RMU0_3DLUT_INDEX, MPC_RMU_3DLUT_INDEX, mask_sh),\ 768 SF(MPC_RMU0_3DLUT_DATA, MPC_RMU_3DLUT_DATA0, mask_sh),\ 769 SF(MPC_RMU0_3DLUT_DATA, MPC_RMU_3DLUT_DATA1, mask_sh),\ 770 SF(MPC_RMU0_3DLUT_DATA_30BIT, MPC_RMU_3DLUT_DATA_30BIT, mask_sh),\ 771 SF(MPC_RMU0_SHAPER_CONTROL, MPC_RMU_SHAPER_LUT_MODE, mask_sh),\ 772 /*SF(MPC_RMU0_SHAPER_CONTROL, MPC_RMU_SHAPER_LUT_MODE_CURRENT, mask_sh),*/\ 773 SF(MPC_RMU0_SHAPER_OFFSET_R, MPC_RMU_SHAPER_OFFSET_R, mask_sh),\ 774 SF(MPC_RMU0_SHAPER_OFFSET_G, MPC_RMU_SHAPER_OFFSET_G, mask_sh),\ 775 SF(MPC_RMU0_SHAPER_OFFSET_B, MPC_RMU_SHAPER_OFFSET_B, mask_sh),\ 776 SF(MPC_RMU0_SHAPER_SCALE_R, MPC_RMU_SHAPER_SCALE_R, mask_sh),\ 777 SF(MPC_RMU0_SHAPER_SCALE_G_B, MPC_RMU_SHAPER_SCALE_G, mask_sh),\ 778 SF(MPC_RMU0_SHAPER_SCALE_G_B, MPC_RMU_SHAPER_SCALE_B, mask_sh),\ 779 SF(MPC_RMU0_SHAPER_LUT_INDEX, MPC_RMU_SHAPER_LUT_INDEX, mask_sh),\ 780 SF(MPC_RMU0_SHAPER_LUT_DATA, MPC_RMU_SHAPER_LUT_DATA, mask_sh),\ 781 SF(MPC_RMU0_SHAPER_LUT_WRITE_EN_MASK, MPC_RMU_SHAPER_LUT_WRITE_EN_MASK, mask_sh),\ 782 SF(MPC_RMU0_SHAPER_LUT_WRITE_EN_MASK, MPC_RMU_SHAPER_LUT_WRITE_SEL, mask_sh),\ 783 /*SF(MPC_RMU0_SHAPER_LUT_WRITE_EN_MASK, MPC_RMU_SHAPER_CONFIG_STATUS, mask_sh),*/\ 784 SF(MPC_RMU0_SHAPER_RAMA_START_CNTL_B, MPC_RMU_SHAPER_RAMA_EXP_REGION_START_B, mask_sh),\ 785 SF(MPC_RMU0_SHAPER_RAMA_START_CNTL_B, MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh),\ 786 SF(MPC_RMU0_SHAPER_RAMA_END_CNTL_B, MPC_RMU_SHAPER_RAMA_EXP_REGION_END_B, mask_sh),\ 787 SF(MPC_RMU0_SHAPER_RAMA_END_CNTL_B, MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_B, mask_sh),\ 788 SF(MPC_RMU0_SHAPER_RAMA_REGION_0_1, MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh),\ 789 SF(MPC_RMU0_SHAPER_RAMA_REGION_0_1, MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\ 790 SF(MPC_RMU0_SHAPER_RAMA_REGION_0_1, MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh),\ 791 SF(MPC_RMU0_SHAPER_RAMA_REGION_0_1, MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\ 792 SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_MEM_PWR_FORCE, mask_sh),\ 793 SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_MEM_PWR_DIS, mask_sh),\ 794 SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_SHAPER_MEM_PWR_STATE, mask_sh),\ 795 SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_3DLUT_MEM_PWR_STATE, mask_sh),\ 796 SF(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_MEM_LOW_PWR_MODE, mask_sh),\ 797 SF(MPC_RMU0_SHAPER_CONTROL, MPC_RMU_SHAPER_MODE_CURRENT, mask_sh),\ 798 SF(CUR_VUPDATE_LOCK_SET0, CUR_VUPDATE_LOCK_SET, mask_sh) 799 800 #define MPC_REG_FIELD_LIST_DCN3_03(type) \ 801 MPC_REG_FIELD_LIST_DCN2_0(type) \ 802 type MPC_DWB0_MUX;\ 803 type MPC_DWB0_MUX_STATUS;\ 804 type MPC_OUT_RATE_CONTROL;\ 805 type MPC_OUT_RATE_CONTROL_DISABLE;\ 806 type MPC_OUT_FLOW_CONTROL_MODE;\ 807 type MPC_OUT_FLOW_CONTROL_COUNT; \ 808 type MPCC_GAMUT_REMAP_MODE; \ 809 type MPCC_GAMUT_REMAP_MODE_CURRENT;\ 810 type MPCC_GAMUT_REMAP_COEF_FORMAT; \ 811 type MPCC_GAMUT_REMAP_C11_A; \ 812 type MPCC_GAMUT_REMAP_C12_A; \ 813 type MPC_RMU0_MUX; \ 814 type MPC_RMU0_MUX_STATUS; \ 815 type MPC_RMU0_MEM_PWR_FORCE;\ 816 type MPC_RMU0_MEM_PWR_DIS;\ 817 type MPC_RMU0_MEM_LOW_PWR_MODE;\ 818 type MPC_RMU0_SHAPER_MEM_PWR_STATE;\ 819 type MPC_RMU0_3DLUT_MEM_PWR_STATE;\ 820 type MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B; \ 821 type MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B;\ 822 type MPCC_OGAM_RAMA_OFFSET_B;\ 823 type MPCC_OGAM_RAMA_OFFSET_G;\ 824 type MPCC_OGAM_RAMA_OFFSET_R;\ 825 type MPCC_OGAM_SELECT; \ 826 type MPCC_OGAM_PWL_DISABLE; \ 827 type MPCC_OGAM_MODE_CURRENT; \ 828 type MPCC_OGAM_SELECT_CURRENT; \ 829 type MPCC_OGAM_LUT_WRITE_COLOR_MASK; \ 830 type MPCC_OGAM_LUT_READ_COLOR_SEL; \ 831 type MPCC_OGAM_LUT_READ_DBG; \ 832 type MPCC_OGAM_LUT_HOST_SEL; \ 833 type MPCC_OGAM_LUT_CONFIG_MODE; \ 834 type MPCC_OGAM_LUT_STATUS; \ 835 type MPCC_OGAM_RAMA_START_BASE_CNTL_B;\ 836 type MPCC_OGAM_MEM_LOW_PWR_MODE;\ 837 type MPCC_OGAM_MEM_PWR_STATE;\ 838 type MPC_RMU_3DLUT_MODE; \ 839 type MPC_RMU_3DLUT_SIZE; \ 840 type MPC_RMU_3DLUT_MODE_CURRENT; \ 841 type MPC_RMU_3DLUT_WRITE_EN_MASK;\ 842 type MPC_RMU_3DLUT_RAM_SEL;\ 843 type MPC_RMU_3DLUT_30BIT_EN;\ 844 type MPC_RMU_3DLUT_CONFIG_STATUS;\ 845 type MPC_RMU_3DLUT_READ_SEL;\ 846 type MPC_RMU_3DLUT_INDEX;\ 847 type MPC_RMU_3DLUT_DATA0;\ 848 type MPC_RMU_3DLUT_DATA1;\ 849 type MPC_RMU_3DLUT_DATA_30BIT;\ 850 type MPC_RMU_SHAPER_LUT_MODE;\ 851 type MPC_RMU_SHAPER_LUT_MODE_CURRENT;\ 852 type MPC_RMU_SHAPER_OFFSET_R;\ 853 type MPC_RMU_SHAPER_OFFSET_G;\ 854 type MPC_RMU_SHAPER_OFFSET_B;\ 855 type MPC_RMU_SHAPER_SCALE_R;\ 856 type MPC_RMU_SHAPER_SCALE_G;\ 857 type MPC_RMU_SHAPER_SCALE_B;\ 858 type MPC_RMU_SHAPER_LUT_INDEX;\ 859 type MPC_RMU_SHAPER_LUT_DATA;\ 860 type MPC_RMU_SHAPER_LUT_WRITE_EN_MASK;\ 861 type MPC_RMU_SHAPER_LUT_WRITE_SEL;\ 862 type MPC_RMU_SHAPER_CONFIG_STATUS;\ 863 type MPC_RMU_SHAPER_RAMA_EXP_REGION_START_B;\ 864 type MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B;\ 865 type MPC_RMU_SHAPER_RAMA_EXP_REGION_END_B;\ 866 type MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_B;\ 867 type MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET;\ 868 type MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS;\ 869 type MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET;\ 870 type MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS;\ 871 type MPC_RMU_SHAPER_MODE_CURRENT 872 873 struct dcn30_mpc_registers { 874 MPC_REG_VARIABLE_LIST_DCN3_0; 875 MPC_REG_VARIABLE_LIST_DCN32; 876 }; 877 878 struct dcn30_mpc_shift { 879 MPC_REG_FIELD_LIST_DCN3_0(uint8_t); 880 MPC_REG_FIELD_LIST_DCN32(uint8_t); 881 }; 882 883 struct dcn30_mpc_mask { 884 MPC_REG_FIELD_LIST_DCN3_0(uint32_t); 885 MPC_REG_FIELD_LIST_DCN32(uint32_t); 886 }; 887 888 struct dcn30_mpc { 889 struct mpc base; 890 891 int mpcc_in_use_mask; 892 int num_mpcc; 893 const struct dcn30_mpc_registers *mpc_regs; 894 const struct dcn30_mpc_shift *mpc_shift; 895 const struct dcn30_mpc_mask *mpc_mask; 896 int num_rmu; 897 }; 898 899 void dcn30_mpc_construct(struct dcn30_mpc *mpc30, 900 struct dc_context *ctx, 901 const struct dcn30_mpc_registers *mpc_regs, 902 const struct dcn30_mpc_shift *mpc_shift, 903 const struct dcn30_mpc_mask *mpc_mask, 904 int num_mpcc, 905 int num_rmu); 906 907 bool mpc3_program_shaper( 908 struct mpc *mpc, 909 const struct pwl_params *params, 910 uint32_t rmu_idx); 911 912 bool mpc3_program_3dlut( 913 struct mpc *mpc, 914 const struct tetrahedral_params *params, 915 int rmu_idx); 916 917 uint32_t mpcc3_acquire_rmu(struct mpc *mpc, 918 int mpcc_id, int rmu_idx); 919 920 void mpc3_set_denorm( 921 struct mpc *mpc, 922 int opp_id, 923 enum dc_color_depth output_depth); 924 925 void mpc3_set_denorm_clamp( 926 struct mpc *mpc, 927 int opp_id, 928 struct mpc_denorm_clamp denorm_clamp); 929 930 void mpc3_set_output_csc( 931 struct mpc *mpc, 932 int opp_id, 933 const uint16_t *regval, 934 enum mpc_output_csc_mode ocsc_mode); 935 936 void mpc3_set_ocsc_default( 937 struct mpc *mpc, 938 int opp_id, 939 enum dc_color_space color_space, 940 enum mpc_output_csc_mode ocsc_mode); 941 942 void mpc3_set_output_gamma( 943 struct mpc *mpc, 944 int mpcc_id, 945 const struct pwl_params *params); 946 947 uint32_t mpc3_get_rmu_mux_status( 948 struct mpc *mpc, 949 int rmu_idx); 950 951 void mpc3_set_gamut_remap( 952 struct mpc *mpc, 953 int mpcc_id, 954 const struct mpc_grph_gamut_adjustment *adjust); 955 956 void mpc3_set_rmu_mux( 957 struct mpc *mpc, 958 int rmu_idx, 959 int value); 960 961 void mpc3_set_dwb_mux( 962 struct mpc *mpc, 963 int dwb_id, 964 int mpcc_id); 965 966 void mpc3_disable_dwb_mux( 967 struct mpc *mpc, 968 int dwb_id); 969 970 bool mpc3_is_dwb_idle( 971 struct mpc *mpc, 972 int dwb_id); 973 974 void mpc3_set_out_rate_control( 975 struct mpc *mpc, 976 int opp_id, 977 bool enable, 978 bool rate_2x_mode, 979 struct mpc_dwb_flow_control *flow_control); 980 981 void mpc3_power_on_ogam_lut( 982 struct mpc *mpc, int mpcc_id, 983 bool power_on); 984 985 void mpc3_init_mpcc(struct mpcc *mpcc, int mpcc_inst); 986 987 enum dc_lut_mode mpc3_get_ogam_current( 988 struct mpc *mpc, 989 int mpcc_id); 990 991 #endif 992