1b708205fSBhawanpreet Lakha /* 2b708205fSBhawanpreet Lakha * Copyright 2020 Advanced Micro Devices, Inc. 3b708205fSBhawanpreet Lakha * 4b708205fSBhawanpreet Lakha * Permission is hereby granted, free of charge, to any person obtaining a 5b708205fSBhawanpreet Lakha * copy of this software and associated documentation files (the "Software"), 6b708205fSBhawanpreet Lakha * to deal in the Software without restriction, including without limitation 7b708205fSBhawanpreet Lakha * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8b708205fSBhawanpreet Lakha * and/or sell copies of the Software, and to permit persons to whom the 9b708205fSBhawanpreet Lakha * Software is furnished to do so, subject to the following conditions: 10b708205fSBhawanpreet Lakha * 11b708205fSBhawanpreet Lakha * The above copyright notice and this permission notice shall be included in 12b708205fSBhawanpreet Lakha * all copies or substantial portions of the Software. 13b708205fSBhawanpreet Lakha * 14b708205fSBhawanpreet Lakha * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15b708205fSBhawanpreet Lakha * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16b708205fSBhawanpreet Lakha * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17b708205fSBhawanpreet Lakha * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18b708205fSBhawanpreet Lakha * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19b708205fSBhawanpreet Lakha * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20b708205fSBhawanpreet Lakha * OTHER DEALINGS IN THE SOFTWARE. 21b708205fSBhawanpreet Lakha * 22b708205fSBhawanpreet Lakha * Authors: AMD 23b708205fSBhawanpreet Lakha * 24b708205fSBhawanpreet Lakha */ 25b708205fSBhawanpreet Lakha 26b708205fSBhawanpreet Lakha #include "reg_helper.h" 27b708205fSBhawanpreet Lakha #include "dcn30_mpc.h" 28b708205fSBhawanpreet Lakha #include "dcn30_cm_common.h" 29b708205fSBhawanpreet Lakha #include "basics/conversion.h" 30b708205fSBhawanpreet Lakha #include "dcn10/dcn10_cm_common.h" 31b708205fSBhawanpreet Lakha #include "dc.h" 32b708205fSBhawanpreet Lakha 33b708205fSBhawanpreet Lakha #define REG(reg)\ 34b708205fSBhawanpreet Lakha mpc30->mpc_regs->reg 35b708205fSBhawanpreet Lakha 36b708205fSBhawanpreet Lakha #define CTX \ 37b708205fSBhawanpreet Lakha mpc30->base.ctx 38b708205fSBhawanpreet Lakha 39b708205fSBhawanpreet Lakha #undef FN 40b708205fSBhawanpreet Lakha #define FN(reg_name, field_name) \ 41b708205fSBhawanpreet Lakha mpc30->mpc_shift->field_name, mpc30->mpc_mask->field_name 42b708205fSBhawanpreet Lakha 43b708205fSBhawanpreet Lakha 44b708205fSBhawanpreet Lakha #define NUM_ELEMENTS(a) (sizeof(a) / sizeof((a)[0])) 45b708205fSBhawanpreet Lakha 46b708205fSBhawanpreet Lakha 47b708205fSBhawanpreet Lakha static bool mpc3_is_dwb_idle( 48b708205fSBhawanpreet Lakha struct mpc *mpc, 49b708205fSBhawanpreet Lakha int dwb_id) 50b708205fSBhawanpreet Lakha { 51b708205fSBhawanpreet Lakha struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc); 52b708205fSBhawanpreet Lakha unsigned int status; 53b708205fSBhawanpreet Lakha 54b708205fSBhawanpreet Lakha REG_GET(DWB_MUX[dwb_id], MPC_DWB0_MUX_STATUS, &status); 55b708205fSBhawanpreet Lakha 56b708205fSBhawanpreet Lakha if (status == 0xf) 57b708205fSBhawanpreet Lakha return true; 58b708205fSBhawanpreet Lakha else 59b708205fSBhawanpreet Lakha return false; 60b708205fSBhawanpreet Lakha } 61b708205fSBhawanpreet Lakha 62b708205fSBhawanpreet Lakha static void mpc3_set_dwb_mux( 63b708205fSBhawanpreet Lakha struct mpc *mpc, 64b708205fSBhawanpreet Lakha int dwb_id, 65b708205fSBhawanpreet Lakha int mpcc_id) 66b708205fSBhawanpreet Lakha { 67b708205fSBhawanpreet Lakha struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc); 68b708205fSBhawanpreet Lakha 69b708205fSBhawanpreet Lakha REG_SET(DWB_MUX[dwb_id], 0, 70b708205fSBhawanpreet Lakha MPC_DWB0_MUX, mpcc_id); 71b708205fSBhawanpreet Lakha } 72b708205fSBhawanpreet Lakha 73b708205fSBhawanpreet Lakha static void mpc3_disable_dwb_mux( 74b708205fSBhawanpreet Lakha struct mpc *mpc, 75b708205fSBhawanpreet Lakha int dwb_id) 76b708205fSBhawanpreet Lakha { 77b708205fSBhawanpreet Lakha struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc); 78b708205fSBhawanpreet Lakha 79b708205fSBhawanpreet Lakha REG_SET(DWB_MUX[dwb_id], 0, 80b708205fSBhawanpreet Lakha MPC_DWB0_MUX, 0xf); 81b708205fSBhawanpreet Lakha } 82b708205fSBhawanpreet Lakha 83b708205fSBhawanpreet Lakha static void mpc3_set_out_rate_control( 84b708205fSBhawanpreet Lakha struct mpc *mpc, 85b708205fSBhawanpreet Lakha int opp_id, 86b708205fSBhawanpreet Lakha bool enable, 87b708205fSBhawanpreet Lakha bool rate_2x_mode, 88b708205fSBhawanpreet Lakha struct mpc_dwb_flow_control *flow_control) 89b708205fSBhawanpreet Lakha { 90b708205fSBhawanpreet Lakha struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc); 91b708205fSBhawanpreet Lakha 92b708205fSBhawanpreet Lakha REG_UPDATE_2(MUX[opp_id], 93b708205fSBhawanpreet Lakha MPC_OUT_RATE_CONTROL_DISABLE, !enable, 94b708205fSBhawanpreet Lakha MPC_OUT_RATE_CONTROL, rate_2x_mode); 95b708205fSBhawanpreet Lakha 96b708205fSBhawanpreet Lakha if (flow_control) 97b708205fSBhawanpreet Lakha REG_UPDATE_2(MUX[opp_id], 98b708205fSBhawanpreet Lakha MPC_OUT_FLOW_CONTROL_MODE, flow_control->flow_ctrl_mode, 99b708205fSBhawanpreet Lakha MPC_OUT_FLOW_CONTROL_COUNT, flow_control->flow_ctrl_cnt1); 100b708205fSBhawanpreet Lakha } 101b708205fSBhawanpreet Lakha 102b708205fSBhawanpreet Lakha static enum dc_lut_mode mpc3_get_ogam_current(struct mpc *mpc, int mpcc_id) 103b708205fSBhawanpreet Lakha { 104b708205fSBhawanpreet Lakha /*Contrary to DCN2 and DCN1 wherein a single status register field holds this info; 105b708205fSBhawanpreet Lakha *in DCN3/3AG, we need to read two separate fields to retrieve the same info 106b708205fSBhawanpreet Lakha */ 107b708205fSBhawanpreet Lakha enum dc_lut_mode mode; 108b708205fSBhawanpreet Lakha uint32_t state_mode; 109b708205fSBhawanpreet Lakha uint32_t state_ram_lut_in_use; 110b708205fSBhawanpreet Lakha struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc); 111b708205fSBhawanpreet Lakha 112b708205fSBhawanpreet Lakha REG_GET_2(MPCC_OGAM_CONTROL[mpcc_id], 113b708205fSBhawanpreet Lakha MPCC_OGAM_MODE_CURRENT, &state_mode, 114b708205fSBhawanpreet Lakha MPCC_OGAM_SELECT_CURRENT, &state_ram_lut_in_use); 115b708205fSBhawanpreet Lakha 116b708205fSBhawanpreet Lakha switch (state_mode) { 117b708205fSBhawanpreet Lakha case 0: 118b708205fSBhawanpreet Lakha mode = LUT_BYPASS; 119b708205fSBhawanpreet Lakha break; 120b708205fSBhawanpreet Lakha case 2: 121b708205fSBhawanpreet Lakha switch (state_ram_lut_in_use) { 122b708205fSBhawanpreet Lakha case 0: 123b708205fSBhawanpreet Lakha mode = LUT_RAM_A; 124b708205fSBhawanpreet Lakha break; 125b708205fSBhawanpreet Lakha case 1: 126b708205fSBhawanpreet Lakha mode = LUT_RAM_B; 127b708205fSBhawanpreet Lakha break; 128b708205fSBhawanpreet Lakha default: 129b708205fSBhawanpreet Lakha mode = LUT_BYPASS; 130b708205fSBhawanpreet Lakha break; 131b708205fSBhawanpreet Lakha } 132b708205fSBhawanpreet Lakha break; 133b708205fSBhawanpreet Lakha default: 134b708205fSBhawanpreet Lakha mode = LUT_BYPASS; 135b708205fSBhawanpreet Lakha break; 136b708205fSBhawanpreet Lakha } 137b708205fSBhawanpreet Lakha return mode; 138b708205fSBhawanpreet Lakha } 139b708205fSBhawanpreet Lakha 140b708205fSBhawanpreet Lakha static void mpc3_power_on_ogam_lut( 141b708205fSBhawanpreet Lakha struct mpc *mpc, int mpcc_id, 142b708205fSBhawanpreet Lakha bool power_on) 143b708205fSBhawanpreet Lakha { 144b708205fSBhawanpreet Lakha struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc); 145b708205fSBhawanpreet Lakha 146737b2b53SNicholas Kazlauskas /* 147737b2b53SNicholas Kazlauskas * Powering on: force memory active so the LUT can be updated. 148737b2b53SNicholas Kazlauskas * Powering off: allow entering memory low power mode 149737b2b53SNicholas Kazlauskas * 150737b2b53SNicholas Kazlauskas * Memory low power mode is controlled during MPC OGAM LUT init. 151737b2b53SNicholas Kazlauskas */ 152737b2b53SNicholas Kazlauskas REG_UPDATE(MPCC_MEM_PWR_CTRL[mpcc_id], 153737b2b53SNicholas Kazlauskas MPCC_OGAM_MEM_PWR_DIS, power_on != 0); 154737b2b53SNicholas Kazlauskas 155737b2b53SNicholas Kazlauskas /* Wait for memory to be powered on - we won't be able to write to it otherwise. */ 1563e5b4cdfSJacky Liao if (power_on) 1573e5b4cdfSJacky Liao REG_WAIT(MPCC_MEM_PWR_CTRL[mpcc_id], MPCC_OGAM_MEM_PWR_STATE, 0, 10, 10); 1583e5b4cdfSJacky Liao } 159b708205fSBhawanpreet Lakha 160b708205fSBhawanpreet Lakha static void mpc3_configure_ogam_lut( 161b708205fSBhawanpreet Lakha struct mpc *mpc, int mpcc_id, 162b708205fSBhawanpreet Lakha bool is_ram_a) 163b708205fSBhawanpreet Lakha { 164b708205fSBhawanpreet Lakha struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc); 165b708205fSBhawanpreet Lakha 166b708205fSBhawanpreet Lakha REG_UPDATE_2(MPCC_OGAM_LUT_CONTROL[mpcc_id], 167b708205fSBhawanpreet Lakha MPCC_OGAM_LUT_WRITE_COLOR_MASK, 7, 168b708205fSBhawanpreet Lakha MPCC_OGAM_LUT_HOST_SEL, is_ram_a == true ? 0:1); 169b708205fSBhawanpreet Lakha 170b708205fSBhawanpreet Lakha REG_SET(MPCC_OGAM_LUT_INDEX[mpcc_id], 0, MPCC_OGAM_LUT_INDEX, 0); 171b708205fSBhawanpreet Lakha } 172b708205fSBhawanpreet Lakha 173b708205fSBhawanpreet Lakha static void mpc3_ogam_get_reg_field( 174b708205fSBhawanpreet Lakha struct mpc *mpc, 175b708205fSBhawanpreet Lakha struct dcn3_xfer_func_reg *reg) 176b708205fSBhawanpreet Lakha { 177b708205fSBhawanpreet Lakha struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc); 178b708205fSBhawanpreet Lakha 179b708205fSBhawanpreet Lakha reg->shifts.field_region_start_base = mpc30->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B; 180b708205fSBhawanpreet Lakha reg->masks.field_region_start_base = mpc30->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B; 181b708205fSBhawanpreet Lakha reg->shifts.field_offset = mpc30->mpc_shift->MPCC_OGAM_RAMA_OFFSET_B; 182b708205fSBhawanpreet Lakha reg->masks.field_offset = mpc30->mpc_mask->MPCC_OGAM_RAMA_OFFSET_B; 183b708205fSBhawanpreet Lakha 184b708205fSBhawanpreet Lakha reg->shifts.exp_region0_lut_offset = mpc30->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET; 185b708205fSBhawanpreet Lakha reg->masks.exp_region0_lut_offset = mpc30->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET; 186b708205fSBhawanpreet Lakha reg->shifts.exp_region0_num_segments = mpc30->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; 187b708205fSBhawanpreet Lakha reg->masks.exp_region0_num_segments = mpc30->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; 188b708205fSBhawanpreet Lakha reg->shifts.exp_region1_lut_offset = mpc30->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET; 189b708205fSBhawanpreet Lakha reg->masks.exp_region1_lut_offset = mpc30->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET; 190b708205fSBhawanpreet Lakha reg->shifts.exp_region1_num_segments = mpc30->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; 191b708205fSBhawanpreet Lakha reg->masks.exp_region1_num_segments = mpc30->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; 192b708205fSBhawanpreet Lakha 193b708205fSBhawanpreet Lakha reg->shifts.field_region_end = mpc30->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_END_B; 194b708205fSBhawanpreet Lakha reg->masks.field_region_end = mpc30->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_END_B; 195b708205fSBhawanpreet Lakha reg->shifts.field_region_end_slope = mpc30->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B; 196b708205fSBhawanpreet Lakha reg->masks.field_region_end_slope = mpc30->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B; 197b708205fSBhawanpreet Lakha reg->shifts.field_region_end_base = mpc30->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B; 198b708205fSBhawanpreet Lakha reg->masks.field_region_end_base = mpc30->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B; 199b708205fSBhawanpreet Lakha reg->shifts.field_region_linear_slope = mpc30->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B; 200b708205fSBhawanpreet Lakha reg->masks.field_region_linear_slope = mpc30->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B; 201b708205fSBhawanpreet Lakha reg->shifts.exp_region_start = mpc30->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_START_B; 202b708205fSBhawanpreet Lakha reg->masks.exp_region_start = mpc30->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_START_B; 203b708205fSBhawanpreet Lakha reg->shifts.exp_resion_start_segment = mpc30->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B; 204b708205fSBhawanpreet Lakha reg->masks.exp_resion_start_segment = mpc30->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B; 205b708205fSBhawanpreet Lakha } 206b708205fSBhawanpreet Lakha 207b708205fSBhawanpreet Lakha static void mpc3_program_luta(struct mpc *mpc, int mpcc_id, 208b708205fSBhawanpreet Lakha const struct pwl_params *params) 209b708205fSBhawanpreet Lakha { 210b708205fSBhawanpreet Lakha struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc); 211b708205fSBhawanpreet Lakha struct dcn3_xfer_func_reg gam_regs; 212b708205fSBhawanpreet Lakha 213b708205fSBhawanpreet Lakha mpc3_ogam_get_reg_field(mpc, &gam_regs); 214b708205fSBhawanpreet Lakha 215b708205fSBhawanpreet Lakha gam_regs.start_cntl_b = REG(MPCC_OGAM_RAMA_START_CNTL_B[mpcc_id]); 216b708205fSBhawanpreet Lakha gam_regs.start_cntl_g = REG(MPCC_OGAM_RAMA_START_CNTL_G[mpcc_id]); 217b708205fSBhawanpreet Lakha gam_regs.start_cntl_r = REG(MPCC_OGAM_RAMA_START_CNTL_R[mpcc_id]); 218b708205fSBhawanpreet Lakha gam_regs.start_slope_cntl_b = REG(MPCC_OGAM_RAMA_START_SLOPE_CNTL_B[mpcc_id]); 219b708205fSBhawanpreet Lakha gam_regs.start_slope_cntl_g = REG(MPCC_OGAM_RAMA_START_SLOPE_CNTL_G[mpcc_id]); 220b708205fSBhawanpreet Lakha gam_regs.start_slope_cntl_r = REG(MPCC_OGAM_RAMA_START_SLOPE_CNTL_R[mpcc_id]); 221b708205fSBhawanpreet Lakha gam_regs.start_end_cntl1_b = REG(MPCC_OGAM_RAMA_END_CNTL1_B[mpcc_id]); 222b708205fSBhawanpreet Lakha gam_regs.start_end_cntl2_b = REG(MPCC_OGAM_RAMA_END_CNTL2_B[mpcc_id]); 223b708205fSBhawanpreet Lakha gam_regs.start_end_cntl1_g = REG(MPCC_OGAM_RAMA_END_CNTL1_G[mpcc_id]); 224b708205fSBhawanpreet Lakha gam_regs.start_end_cntl2_g = REG(MPCC_OGAM_RAMA_END_CNTL2_G[mpcc_id]); 225b708205fSBhawanpreet Lakha gam_regs.start_end_cntl1_r = REG(MPCC_OGAM_RAMA_END_CNTL1_R[mpcc_id]); 226b708205fSBhawanpreet Lakha gam_regs.start_end_cntl2_r = REG(MPCC_OGAM_RAMA_END_CNTL2_R[mpcc_id]); 227b708205fSBhawanpreet Lakha gam_regs.region_start = REG(MPCC_OGAM_RAMA_REGION_0_1[mpcc_id]); 228b708205fSBhawanpreet Lakha gam_regs.region_end = REG(MPCC_OGAM_RAMA_REGION_32_33[mpcc_id]); 229b708205fSBhawanpreet Lakha //New registers in DCN3AG/DCN OGAM block 230b708205fSBhawanpreet Lakha gam_regs.offset_b = REG(MPCC_OGAM_RAMA_OFFSET_B[mpcc_id]); 231b708205fSBhawanpreet Lakha gam_regs.offset_g = REG(MPCC_OGAM_RAMA_OFFSET_G[mpcc_id]); 232b708205fSBhawanpreet Lakha gam_regs.offset_r = REG(MPCC_OGAM_RAMA_OFFSET_R[mpcc_id]); 233b708205fSBhawanpreet Lakha gam_regs.start_base_cntl_b = REG(MPCC_OGAM_RAMA_START_BASE_CNTL_B[mpcc_id]); 234b708205fSBhawanpreet Lakha gam_regs.start_base_cntl_g = REG(MPCC_OGAM_RAMA_START_BASE_CNTL_G[mpcc_id]); 235b708205fSBhawanpreet Lakha gam_regs.start_base_cntl_r = REG(MPCC_OGAM_RAMA_START_BASE_CNTL_R[mpcc_id]); 236b708205fSBhawanpreet Lakha 237b708205fSBhawanpreet Lakha cm_helper_program_gamcor_xfer_func(mpc30->base.ctx, params, &gam_regs); 238b708205fSBhawanpreet Lakha } 239b708205fSBhawanpreet Lakha 240b708205fSBhawanpreet Lakha static void mpc3_program_lutb(struct mpc *mpc, int mpcc_id, 241b708205fSBhawanpreet Lakha const struct pwl_params *params) 242b708205fSBhawanpreet Lakha { 243b708205fSBhawanpreet Lakha struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc); 244b708205fSBhawanpreet Lakha struct dcn3_xfer_func_reg gam_regs; 245b708205fSBhawanpreet Lakha 246b708205fSBhawanpreet Lakha mpc3_ogam_get_reg_field(mpc, &gam_regs); 247b708205fSBhawanpreet Lakha 248b708205fSBhawanpreet Lakha gam_regs.start_cntl_b = REG(MPCC_OGAM_RAMB_START_CNTL_B[mpcc_id]); 249b708205fSBhawanpreet Lakha gam_regs.start_cntl_g = REG(MPCC_OGAM_RAMB_START_CNTL_G[mpcc_id]); 250b708205fSBhawanpreet Lakha gam_regs.start_cntl_r = REG(MPCC_OGAM_RAMB_START_CNTL_R[mpcc_id]); 251b708205fSBhawanpreet Lakha gam_regs.start_slope_cntl_b = REG(MPCC_OGAM_RAMB_START_SLOPE_CNTL_B[mpcc_id]); 252b708205fSBhawanpreet Lakha gam_regs.start_slope_cntl_g = REG(MPCC_OGAM_RAMB_START_SLOPE_CNTL_G[mpcc_id]); 253b708205fSBhawanpreet Lakha gam_regs.start_slope_cntl_r = REG(MPCC_OGAM_RAMB_START_SLOPE_CNTL_R[mpcc_id]); 254b708205fSBhawanpreet Lakha gam_regs.start_end_cntl1_b = REG(MPCC_OGAM_RAMB_END_CNTL1_B[mpcc_id]); 255b708205fSBhawanpreet Lakha gam_regs.start_end_cntl2_b = REG(MPCC_OGAM_RAMB_END_CNTL2_B[mpcc_id]); 256b708205fSBhawanpreet Lakha gam_regs.start_end_cntl1_g = REG(MPCC_OGAM_RAMB_END_CNTL1_G[mpcc_id]); 257b708205fSBhawanpreet Lakha gam_regs.start_end_cntl2_g = REG(MPCC_OGAM_RAMB_END_CNTL2_G[mpcc_id]); 258b708205fSBhawanpreet Lakha gam_regs.start_end_cntl1_r = REG(MPCC_OGAM_RAMB_END_CNTL1_R[mpcc_id]); 259b708205fSBhawanpreet Lakha gam_regs.start_end_cntl2_r = REG(MPCC_OGAM_RAMB_END_CNTL2_R[mpcc_id]); 260b708205fSBhawanpreet Lakha gam_regs.region_start = REG(MPCC_OGAM_RAMB_REGION_0_1[mpcc_id]); 261b708205fSBhawanpreet Lakha gam_regs.region_end = REG(MPCC_OGAM_RAMB_REGION_32_33[mpcc_id]); 262b708205fSBhawanpreet Lakha //New registers in DCN3AG/DCN OGAM block 263b708205fSBhawanpreet Lakha gam_regs.offset_b = REG(MPCC_OGAM_RAMB_OFFSET_B[mpcc_id]); 264b708205fSBhawanpreet Lakha gam_regs.offset_g = REG(MPCC_OGAM_RAMB_OFFSET_G[mpcc_id]); 265b708205fSBhawanpreet Lakha gam_regs.offset_r = REG(MPCC_OGAM_RAMB_OFFSET_R[mpcc_id]); 266b708205fSBhawanpreet Lakha gam_regs.start_base_cntl_b = REG(MPCC_OGAM_RAMB_START_BASE_CNTL_B[mpcc_id]); 267b708205fSBhawanpreet Lakha gam_regs.start_base_cntl_g = REG(MPCC_OGAM_RAMB_START_BASE_CNTL_G[mpcc_id]); 268b708205fSBhawanpreet Lakha gam_regs.start_base_cntl_r = REG(MPCC_OGAM_RAMB_START_BASE_CNTL_R[mpcc_id]); 269b708205fSBhawanpreet Lakha 270b708205fSBhawanpreet Lakha cm_helper_program_gamcor_xfer_func(mpc30->base.ctx, params, &gam_regs); 271b708205fSBhawanpreet Lakha } 272b708205fSBhawanpreet Lakha 273b708205fSBhawanpreet Lakha 274b708205fSBhawanpreet Lakha static void mpc3_program_ogam_pwl( 275b708205fSBhawanpreet Lakha struct mpc *mpc, int mpcc_id, 276b708205fSBhawanpreet Lakha const struct pwl_result_data *rgb, 277b708205fSBhawanpreet Lakha uint32_t num) 278b708205fSBhawanpreet Lakha { 279b708205fSBhawanpreet Lakha uint32_t i; 280b708205fSBhawanpreet Lakha struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc); 281b708205fSBhawanpreet Lakha uint32_t last_base_value_red = rgb[num-1].red_reg + rgb[num-1].delta_red_reg; 282b708205fSBhawanpreet Lakha uint32_t last_base_value_green = rgb[num-1].green_reg + rgb[num-1].delta_green_reg; 283b708205fSBhawanpreet Lakha uint32_t last_base_value_blue = rgb[num-1].blue_reg + rgb[num-1].delta_blue_reg; 284b708205fSBhawanpreet Lakha 285b708205fSBhawanpreet Lakha /*the entries of DCN3AG gamma LUTs take 18bit base values as opposed to 286b708205fSBhawanpreet Lakha *38 base+delta values per entry in earlier DCN architectures 287b708205fSBhawanpreet Lakha *last base value for our lut is compute by adding the last base value 288b708205fSBhawanpreet Lakha *in our data + last delta 289b708205fSBhawanpreet Lakha */ 290b708205fSBhawanpreet Lakha 291b708205fSBhawanpreet Lakha if (is_rgb_equal(rgb, num)) { 292b708205fSBhawanpreet Lakha for (i = 0 ; i < num; i++) 293b708205fSBhawanpreet Lakha REG_SET(MPCC_OGAM_LUT_DATA[mpcc_id], 0, MPCC_OGAM_LUT_DATA, rgb[i].red_reg); 294b708205fSBhawanpreet Lakha 295b708205fSBhawanpreet Lakha REG_SET(MPCC_OGAM_LUT_DATA[mpcc_id], 0, MPCC_OGAM_LUT_DATA, last_base_value_red); 296b708205fSBhawanpreet Lakha 297b708205fSBhawanpreet Lakha } else { 298b708205fSBhawanpreet Lakha 299b708205fSBhawanpreet Lakha REG_UPDATE(MPCC_OGAM_LUT_CONTROL[mpcc_id], 300b708205fSBhawanpreet Lakha MPCC_OGAM_LUT_WRITE_COLOR_MASK, 4); 301b708205fSBhawanpreet Lakha 302b708205fSBhawanpreet Lakha for (i = 0 ; i < num; i++) 303b708205fSBhawanpreet Lakha REG_SET(MPCC_OGAM_LUT_DATA[mpcc_id], 0, MPCC_OGAM_LUT_DATA, rgb[i].red_reg); 304b708205fSBhawanpreet Lakha 305b708205fSBhawanpreet Lakha REG_SET(MPCC_OGAM_LUT_DATA[mpcc_id], 0, MPCC_OGAM_LUT_DATA, last_base_value_red); 306b708205fSBhawanpreet Lakha 307b708205fSBhawanpreet Lakha REG_SET(MPCC_OGAM_LUT_INDEX[mpcc_id], 0, MPCC_OGAM_LUT_INDEX, 0); 308b708205fSBhawanpreet Lakha 309b708205fSBhawanpreet Lakha REG_UPDATE(MPCC_OGAM_LUT_CONTROL[mpcc_id], 310b708205fSBhawanpreet Lakha MPCC_OGAM_LUT_WRITE_COLOR_MASK, 2); 311b708205fSBhawanpreet Lakha 312b708205fSBhawanpreet Lakha for (i = 0 ; i < num; i++) 313b708205fSBhawanpreet Lakha REG_SET(MPCC_OGAM_LUT_DATA[mpcc_id], 0, MPCC_OGAM_LUT_DATA, rgb[i].green_reg); 314b708205fSBhawanpreet Lakha 315b708205fSBhawanpreet Lakha REG_SET(MPCC_OGAM_LUT_DATA[mpcc_id], 0, MPCC_OGAM_LUT_DATA, last_base_value_green); 316b708205fSBhawanpreet Lakha 317b708205fSBhawanpreet Lakha REG_SET(MPCC_OGAM_LUT_INDEX[mpcc_id], 0, MPCC_OGAM_LUT_INDEX, 0); 318b708205fSBhawanpreet Lakha 319b708205fSBhawanpreet Lakha REG_UPDATE(MPCC_OGAM_LUT_CONTROL[mpcc_id], 320b708205fSBhawanpreet Lakha MPCC_OGAM_LUT_WRITE_COLOR_MASK, 1); 321b708205fSBhawanpreet Lakha 322b708205fSBhawanpreet Lakha for (i = 0 ; i < num; i++) 323b708205fSBhawanpreet Lakha REG_SET(MPCC_OGAM_LUT_DATA[mpcc_id], 0, MPCC_OGAM_LUT_DATA, rgb[i].blue_reg); 324b708205fSBhawanpreet Lakha 325b708205fSBhawanpreet Lakha REG_SET(MPCC_OGAM_LUT_DATA[mpcc_id], 0, MPCC_OGAM_LUT_DATA, last_base_value_blue); 326b708205fSBhawanpreet Lakha } 327b708205fSBhawanpreet Lakha 328b708205fSBhawanpreet Lakha } 329b708205fSBhawanpreet Lakha 330b708205fSBhawanpreet Lakha void mpc3_set_output_gamma( 331b708205fSBhawanpreet Lakha struct mpc *mpc, 332b708205fSBhawanpreet Lakha int mpcc_id, 333b708205fSBhawanpreet Lakha const struct pwl_params *params) 334b708205fSBhawanpreet Lakha { 335b708205fSBhawanpreet Lakha enum dc_lut_mode current_mode; 336b708205fSBhawanpreet Lakha enum dc_lut_mode next_mode; 337b708205fSBhawanpreet Lakha struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc); 338b708205fSBhawanpreet Lakha 339b708205fSBhawanpreet Lakha if (mpc->ctx->dc->debug.cm_in_bypass) { 340b708205fSBhawanpreet Lakha REG_SET(MPCC_OGAM_MODE[mpcc_id], 0, MPCC_OGAM_MODE, 0); 341b708205fSBhawanpreet Lakha return; 342b708205fSBhawanpreet Lakha } 343b708205fSBhawanpreet Lakha 344b708205fSBhawanpreet Lakha if (params == NULL) { //disable OGAM 345b708205fSBhawanpreet Lakha REG_SET(MPCC_OGAM_CONTROL[mpcc_id], 0, MPCC_OGAM_MODE, 0); 346b708205fSBhawanpreet Lakha return; 347b708205fSBhawanpreet Lakha } 348b708205fSBhawanpreet Lakha //enable OGAM 349b708205fSBhawanpreet Lakha REG_SET(MPCC_OGAM_CONTROL[mpcc_id], 0, MPCC_OGAM_MODE, 2); 350b708205fSBhawanpreet Lakha 351b708205fSBhawanpreet Lakha current_mode = mpc3_get_ogam_current(mpc, mpcc_id); 352b708205fSBhawanpreet Lakha if (current_mode == LUT_BYPASS) 353b708205fSBhawanpreet Lakha next_mode = LUT_RAM_A; 354b708205fSBhawanpreet Lakha else if (current_mode == LUT_RAM_A) 355b708205fSBhawanpreet Lakha next_mode = LUT_RAM_B; 356b708205fSBhawanpreet Lakha else 357b708205fSBhawanpreet Lakha next_mode = LUT_RAM_A; 358b708205fSBhawanpreet Lakha 359b708205fSBhawanpreet Lakha mpc3_power_on_ogam_lut(mpc, mpcc_id, true); 3605a613586SJiapeng Chong mpc3_configure_ogam_lut(mpc, mpcc_id, next_mode == LUT_RAM_A); 361b708205fSBhawanpreet Lakha 362b708205fSBhawanpreet Lakha if (next_mode == LUT_RAM_A) 363b708205fSBhawanpreet Lakha mpc3_program_luta(mpc, mpcc_id, params); 364b708205fSBhawanpreet Lakha else 365b708205fSBhawanpreet Lakha mpc3_program_lutb(mpc, mpcc_id, params); 366b708205fSBhawanpreet Lakha 367b708205fSBhawanpreet Lakha mpc3_program_ogam_pwl( 368b708205fSBhawanpreet Lakha mpc, mpcc_id, params->rgb_resulted, params->hw_points_num); 369b708205fSBhawanpreet Lakha 370b708205fSBhawanpreet Lakha /*we need to program 2 fields here as apposed to 1*/ 371b708205fSBhawanpreet Lakha REG_UPDATE(MPCC_OGAM_CONTROL[mpcc_id], 372b708205fSBhawanpreet Lakha MPCC_OGAM_SELECT, next_mode == LUT_RAM_A ? 0:1); 3733e5b4cdfSJacky Liao 374cae78e03SJacky Liao if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc) 3753e5b4cdfSJacky Liao mpc3_power_on_ogam_lut(mpc, mpcc_id, false); 376b708205fSBhawanpreet Lakha } 377b708205fSBhawanpreet Lakha 378b708205fSBhawanpreet Lakha void mpc3_set_denorm( 379b708205fSBhawanpreet Lakha struct mpc *mpc, 380b708205fSBhawanpreet Lakha int opp_id, 381b708205fSBhawanpreet Lakha enum dc_color_depth output_depth) 382b708205fSBhawanpreet Lakha { 383b708205fSBhawanpreet Lakha struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc); 384b708205fSBhawanpreet Lakha /* De-normalize Fixed U1.13 color data to different target bit depths. 0 is bypass*/ 385b708205fSBhawanpreet Lakha int denorm_mode = 0; 386b708205fSBhawanpreet Lakha 387b708205fSBhawanpreet Lakha switch (output_depth) { 388b708205fSBhawanpreet Lakha case COLOR_DEPTH_666: 389b708205fSBhawanpreet Lakha denorm_mode = 1; 390b708205fSBhawanpreet Lakha break; 391b708205fSBhawanpreet Lakha case COLOR_DEPTH_888: 392b708205fSBhawanpreet Lakha denorm_mode = 2; 393b708205fSBhawanpreet Lakha break; 394b708205fSBhawanpreet Lakha case COLOR_DEPTH_999: 395b708205fSBhawanpreet Lakha denorm_mode = 3; 396b708205fSBhawanpreet Lakha break; 397b708205fSBhawanpreet Lakha case COLOR_DEPTH_101010: 398b708205fSBhawanpreet Lakha denorm_mode = 4; 399b708205fSBhawanpreet Lakha break; 400b708205fSBhawanpreet Lakha case COLOR_DEPTH_111111: 401b708205fSBhawanpreet Lakha denorm_mode = 5; 402b708205fSBhawanpreet Lakha break; 403b708205fSBhawanpreet Lakha case COLOR_DEPTH_121212: 404b708205fSBhawanpreet Lakha denorm_mode = 6; 405b708205fSBhawanpreet Lakha break; 406b708205fSBhawanpreet Lakha case COLOR_DEPTH_141414: 407b708205fSBhawanpreet Lakha case COLOR_DEPTH_161616: 408b708205fSBhawanpreet Lakha default: 409b708205fSBhawanpreet Lakha /* not valid used case! */ 410b708205fSBhawanpreet Lakha break; 411b708205fSBhawanpreet Lakha } 412b708205fSBhawanpreet Lakha 413b708205fSBhawanpreet Lakha REG_UPDATE(DENORM_CONTROL[opp_id], 414b708205fSBhawanpreet Lakha MPC_OUT_DENORM_MODE, denorm_mode); 415b708205fSBhawanpreet Lakha } 416b708205fSBhawanpreet Lakha 417b708205fSBhawanpreet Lakha void mpc3_set_denorm_clamp( 418b708205fSBhawanpreet Lakha struct mpc *mpc, 419b708205fSBhawanpreet Lakha int opp_id, 420b708205fSBhawanpreet Lakha struct mpc_denorm_clamp denorm_clamp) 421b708205fSBhawanpreet Lakha { 422b708205fSBhawanpreet Lakha struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc); 423b708205fSBhawanpreet Lakha 424b708205fSBhawanpreet Lakha /*program min and max clamp values for the pixel components*/ 425b708205fSBhawanpreet Lakha REG_UPDATE_2(DENORM_CONTROL[opp_id], 426b708205fSBhawanpreet Lakha MPC_OUT_DENORM_CLAMP_MAX_R_CR, denorm_clamp.clamp_max_r_cr, 427b708205fSBhawanpreet Lakha MPC_OUT_DENORM_CLAMP_MIN_R_CR, denorm_clamp.clamp_min_r_cr); 428b708205fSBhawanpreet Lakha REG_UPDATE_2(DENORM_CLAMP_G_Y[opp_id], 429b708205fSBhawanpreet Lakha MPC_OUT_DENORM_CLAMP_MAX_G_Y, denorm_clamp.clamp_max_g_y, 430b708205fSBhawanpreet Lakha MPC_OUT_DENORM_CLAMP_MIN_G_Y, denorm_clamp.clamp_min_g_y); 431b708205fSBhawanpreet Lakha REG_UPDATE_2(DENORM_CLAMP_B_CB[opp_id], 432b708205fSBhawanpreet Lakha MPC_OUT_DENORM_CLAMP_MAX_B_CB, denorm_clamp.clamp_max_b_cb, 433b708205fSBhawanpreet Lakha MPC_OUT_DENORM_CLAMP_MIN_B_CB, denorm_clamp.clamp_min_b_cb); 434b708205fSBhawanpreet Lakha } 435b708205fSBhawanpreet Lakha 436b708205fSBhawanpreet Lakha static enum dc_lut_mode mpc3_get_shaper_current(struct mpc *mpc, uint32_t rmu_idx) 437b708205fSBhawanpreet Lakha { 438b708205fSBhawanpreet Lakha enum dc_lut_mode mode; 439b708205fSBhawanpreet Lakha uint32_t state_mode; 440b708205fSBhawanpreet Lakha struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc); 441b708205fSBhawanpreet Lakha 442b708205fSBhawanpreet Lakha REG_GET(SHAPER_CONTROL[rmu_idx], 443b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_LUT_MODE_CURRENT, &state_mode); 444b708205fSBhawanpreet Lakha 445b708205fSBhawanpreet Lakha switch (state_mode) { 446b708205fSBhawanpreet Lakha case 0: 447b708205fSBhawanpreet Lakha mode = LUT_BYPASS; 448b708205fSBhawanpreet Lakha break; 449b708205fSBhawanpreet Lakha case 1: 450b708205fSBhawanpreet Lakha mode = LUT_RAM_A; 451b708205fSBhawanpreet Lakha break; 452b708205fSBhawanpreet Lakha case 2: 453b708205fSBhawanpreet Lakha mode = LUT_RAM_B; 454b708205fSBhawanpreet Lakha break; 455b708205fSBhawanpreet Lakha default: 456b708205fSBhawanpreet Lakha mode = LUT_BYPASS; 457b708205fSBhawanpreet Lakha break; 458b708205fSBhawanpreet Lakha } 459b708205fSBhawanpreet Lakha return mode; 460b708205fSBhawanpreet Lakha } 461b708205fSBhawanpreet Lakha 462b708205fSBhawanpreet Lakha static void mpc3_configure_shaper_lut( 463b708205fSBhawanpreet Lakha struct mpc *mpc, 464b708205fSBhawanpreet Lakha bool is_ram_a, 465b708205fSBhawanpreet Lakha uint32_t rmu_idx) 466b708205fSBhawanpreet Lakha { 467b708205fSBhawanpreet Lakha struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc); 468b708205fSBhawanpreet Lakha 469b708205fSBhawanpreet Lakha REG_UPDATE(SHAPER_LUT_WRITE_EN_MASK[rmu_idx], 470b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_LUT_WRITE_EN_MASK, 7); 471b708205fSBhawanpreet Lakha REG_UPDATE(SHAPER_LUT_WRITE_EN_MASK[rmu_idx], 472b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_LUT_WRITE_SEL, is_ram_a == true ? 0:1); 473b708205fSBhawanpreet Lakha REG_SET(SHAPER_LUT_INDEX[rmu_idx], 0, MPC_RMU_SHAPER_LUT_INDEX, 0); 474b708205fSBhawanpreet Lakha } 475b708205fSBhawanpreet Lakha 476b708205fSBhawanpreet Lakha static void mpc3_program_shaper_luta_settings( 477b708205fSBhawanpreet Lakha struct mpc *mpc, 478b708205fSBhawanpreet Lakha const struct pwl_params *params, 479b708205fSBhawanpreet Lakha uint32_t rmu_idx) 480b708205fSBhawanpreet Lakha { 481b708205fSBhawanpreet Lakha const struct gamma_curve *curve; 482b708205fSBhawanpreet Lakha struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc); 483b708205fSBhawanpreet Lakha 484b708205fSBhawanpreet Lakha REG_SET_2(SHAPER_RAMA_START_CNTL_B[rmu_idx], 0, 485b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION_START_B, params->corner_points[0].blue.custom_float_x, 486b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0); 487b708205fSBhawanpreet Lakha REG_SET_2(SHAPER_RAMA_START_CNTL_G[rmu_idx], 0, 488b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION_START_B, params->corner_points[0].green.custom_float_x, 489b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0); 490b708205fSBhawanpreet Lakha REG_SET_2(SHAPER_RAMA_START_CNTL_R[rmu_idx], 0, 491b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION_START_B, params->corner_points[0].red.custom_float_x, 492b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0); 493b708205fSBhawanpreet Lakha 494b708205fSBhawanpreet Lakha REG_SET_2(SHAPER_RAMA_END_CNTL_B[rmu_idx], 0, 495b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION_END_B, params->corner_points[1].blue.custom_float_x, 496b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_B, params->corner_points[1].blue.custom_float_y); 497b708205fSBhawanpreet Lakha REG_SET_2(SHAPER_RAMA_END_CNTL_G[rmu_idx], 0, 498b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION_END_B, params->corner_points[1].green.custom_float_x, 499b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_B, params->corner_points[1].green.custom_float_y); 500b708205fSBhawanpreet Lakha REG_SET_2(SHAPER_RAMA_END_CNTL_R[rmu_idx], 0, 501b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION_END_B, params->corner_points[1].red.custom_float_x, 502b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_B, params->corner_points[1].red.custom_float_y); 503b708205fSBhawanpreet Lakha 504b708205fSBhawanpreet Lakha curve = params->arr_curve_points; 505b708205fSBhawanpreet Lakha REG_SET_4(SHAPER_RAMA_REGION_0_1[rmu_idx], 0, 506b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, 507b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 508b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, 509b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 510b708205fSBhawanpreet Lakha 511b708205fSBhawanpreet Lakha curve += 2; 512b708205fSBhawanpreet Lakha REG_SET_4(SHAPER_RAMA_REGION_2_3[rmu_idx], 0, 513b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, 514b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 515b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, 516b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 517b708205fSBhawanpreet Lakha 518b708205fSBhawanpreet Lakha curve += 2; 519b708205fSBhawanpreet Lakha REG_SET_4(SHAPER_RAMA_REGION_4_5[rmu_idx], 0, 520b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, 521b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 522b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, 523b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 524b708205fSBhawanpreet Lakha 525b708205fSBhawanpreet Lakha curve += 2; 526b708205fSBhawanpreet Lakha REG_SET_4(SHAPER_RAMA_REGION_6_7[rmu_idx], 0, 527b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, 528b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 529b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, 530b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 531b708205fSBhawanpreet Lakha 532b708205fSBhawanpreet Lakha curve += 2; 533b708205fSBhawanpreet Lakha REG_SET_4(SHAPER_RAMA_REGION_8_9[rmu_idx], 0, 534b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, 535b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 536b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, 537b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 538b708205fSBhawanpreet Lakha 539b708205fSBhawanpreet Lakha curve += 2; 540b708205fSBhawanpreet Lakha REG_SET_4(SHAPER_RAMA_REGION_10_11[rmu_idx], 0, 541b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, 542b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 543b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, 544b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 545b708205fSBhawanpreet Lakha 546b708205fSBhawanpreet Lakha curve += 2; 547b708205fSBhawanpreet Lakha REG_SET_4(SHAPER_RAMA_REGION_12_13[rmu_idx], 0, 548b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, 549b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 550b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, 551b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 552b708205fSBhawanpreet Lakha 553b708205fSBhawanpreet Lakha curve += 2; 554b708205fSBhawanpreet Lakha REG_SET_4(SHAPER_RAMA_REGION_14_15[rmu_idx], 0, 555b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, 556b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 557b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, 558b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 559b708205fSBhawanpreet Lakha 560b708205fSBhawanpreet Lakha 561b708205fSBhawanpreet Lakha curve += 2; 562b708205fSBhawanpreet Lakha REG_SET_4(SHAPER_RAMA_REGION_16_17[rmu_idx], 0, 563b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, 564b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 565b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, 566b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 567b708205fSBhawanpreet Lakha 568b708205fSBhawanpreet Lakha curve += 2; 569b708205fSBhawanpreet Lakha REG_SET_4(SHAPER_RAMA_REGION_18_19[rmu_idx], 0, 570b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, 571b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 572b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, 573b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 574b708205fSBhawanpreet Lakha 575b708205fSBhawanpreet Lakha curve += 2; 576b708205fSBhawanpreet Lakha REG_SET_4(SHAPER_RAMA_REGION_20_21[rmu_idx], 0, 577b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, 578b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 579b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, 580b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 581b708205fSBhawanpreet Lakha 582b708205fSBhawanpreet Lakha curve += 2; 583b708205fSBhawanpreet Lakha REG_SET_4(SHAPER_RAMA_REGION_22_23[rmu_idx], 0, 584b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, 585b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 586b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, 587b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 588b708205fSBhawanpreet Lakha 589b708205fSBhawanpreet Lakha curve += 2; 590b708205fSBhawanpreet Lakha REG_SET_4(SHAPER_RAMA_REGION_24_25[rmu_idx], 0, 591b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, 592b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 593b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, 594b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 595b708205fSBhawanpreet Lakha 596b708205fSBhawanpreet Lakha curve += 2; 597b708205fSBhawanpreet Lakha REG_SET_4(SHAPER_RAMA_REGION_26_27[rmu_idx], 0, 598b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, 599b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 600b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, 601b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 602b708205fSBhawanpreet Lakha 603b708205fSBhawanpreet Lakha curve += 2; 604b708205fSBhawanpreet Lakha REG_SET_4(SHAPER_RAMA_REGION_28_29[rmu_idx], 0, 605b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, 606b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 607b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, 608b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 609b708205fSBhawanpreet Lakha 610b708205fSBhawanpreet Lakha curve += 2; 611b708205fSBhawanpreet Lakha REG_SET_4(SHAPER_RAMA_REGION_30_31[rmu_idx], 0, 612b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, 613b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 614b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, 615b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 616b708205fSBhawanpreet Lakha 617b708205fSBhawanpreet Lakha curve += 2; 618b708205fSBhawanpreet Lakha REG_SET_4(SHAPER_RAMA_REGION_32_33[rmu_idx], 0, 619b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, 620b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 621b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, 622b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 623b708205fSBhawanpreet Lakha } 624b708205fSBhawanpreet Lakha 625b708205fSBhawanpreet Lakha static void mpc3_program_shaper_lutb_settings( 626b708205fSBhawanpreet Lakha struct mpc *mpc, 627b708205fSBhawanpreet Lakha const struct pwl_params *params, 628b708205fSBhawanpreet Lakha uint32_t rmu_idx) 629b708205fSBhawanpreet Lakha { 630b708205fSBhawanpreet Lakha const struct gamma_curve *curve; 631b708205fSBhawanpreet Lakha struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc); 632b708205fSBhawanpreet Lakha 633b708205fSBhawanpreet Lakha REG_SET_2(SHAPER_RAMB_START_CNTL_B[rmu_idx], 0, 634b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION_START_B, params->corner_points[0].blue.custom_float_x, 635b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0); 636b708205fSBhawanpreet Lakha REG_SET_2(SHAPER_RAMB_START_CNTL_G[rmu_idx], 0, 637b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION_START_B, params->corner_points[0].green.custom_float_x, 638b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0); 639b708205fSBhawanpreet Lakha REG_SET_2(SHAPER_RAMB_START_CNTL_R[rmu_idx], 0, 640b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION_START_B, params->corner_points[0].red.custom_float_x, 641b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0); 642b708205fSBhawanpreet Lakha 643b708205fSBhawanpreet Lakha REG_SET_2(SHAPER_RAMB_END_CNTL_B[rmu_idx], 0, 644b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION_END_B, params->corner_points[1].blue.custom_float_x, 645b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_B, params->corner_points[1].blue.custom_float_y); 646b708205fSBhawanpreet Lakha REG_SET_2(SHAPER_RAMB_END_CNTL_G[rmu_idx], 0, 647b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION_END_B, params->corner_points[1].green.custom_float_x, 648b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_B, params->corner_points[1].green.custom_float_y); 649b708205fSBhawanpreet Lakha REG_SET_2(SHAPER_RAMB_END_CNTL_R[rmu_idx], 0, 650b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION_END_B, params->corner_points[1].red.custom_float_x, 651b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_B, params->corner_points[1].red.custom_float_y); 652b708205fSBhawanpreet Lakha 653b708205fSBhawanpreet Lakha curve = params->arr_curve_points; 654b708205fSBhawanpreet Lakha REG_SET_4(SHAPER_RAMB_REGION_0_1[rmu_idx], 0, 655b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, 656b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 657b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, 658b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 659b708205fSBhawanpreet Lakha 660b708205fSBhawanpreet Lakha curve += 2; 661b708205fSBhawanpreet Lakha REG_SET_4(SHAPER_RAMB_REGION_2_3[rmu_idx], 0, 662b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, 663b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 664b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, 665b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 666b708205fSBhawanpreet Lakha 667b708205fSBhawanpreet Lakha 668b708205fSBhawanpreet Lakha curve += 2; 669b708205fSBhawanpreet Lakha REG_SET_4(SHAPER_RAMB_REGION_4_5[rmu_idx], 0, 670b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, 671b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 672b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, 673b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 674b708205fSBhawanpreet Lakha 675b708205fSBhawanpreet Lakha curve += 2; 676b708205fSBhawanpreet Lakha REG_SET_4(SHAPER_RAMB_REGION_6_7[rmu_idx], 0, 677b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, 678b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 679b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, 680b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 681b708205fSBhawanpreet Lakha 682b708205fSBhawanpreet Lakha curve += 2; 683b708205fSBhawanpreet Lakha REG_SET_4(SHAPER_RAMB_REGION_8_9[rmu_idx], 0, 684b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, 685b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 686b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, 687b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 688b708205fSBhawanpreet Lakha 689b708205fSBhawanpreet Lakha curve += 2; 690b708205fSBhawanpreet Lakha REG_SET_4(SHAPER_RAMB_REGION_10_11[rmu_idx], 0, 691b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, 692b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 693b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, 694b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 695b708205fSBhawanpreet Lakha 696b708205fSBhawanpreet Lakha curve += 2; 697b708205fSBhawanpreet Lakha REG_SET_4(SHAPER_RAMB_REGION_12_13[rmu_idx], 0, 698b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, 699b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 700b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, 701b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 702b708205fSBhawanpreet Lakha 703b708205fSBhawanpreet Lakha curve += 2; 704b708205fSBhawanpreet Lakha REG_SET_4(SHAPER_RAMB_REGION_14_15[rmu_idx], 0, 705b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, 706b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 707b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, 708b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 709b708205fSBhawanpreet Lakha 710b708205fSBhawanpreet Lakha 711b708205fSBhawanpreet Lakha curve += 2; 712b708205fSBhawanpreet Lakha REG_SET_4(SHAPER_RAMB_REGION_16_17[rmu_idx], 0, 713b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, 714b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 715b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, 716b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 717b708205fSBhawanpreet Lakha 718b708205fSBhawanpreet Lakha curve += 2; 719b708205fSBhawanpreet Lakha REG_SET_4(SHAPER_RAMB_REGION_18_19[rmu_idx], 0, 720b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, 721b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 722b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, 723b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 724b708205fSBhawanpreet Lakha 725b708205fSBhawanpreet Lakha curve += 2; 726b708205fSBhawanpreet Lakha REG_SET_4(SHAPER_RAMB_REGION_20_21[rmu_idx], 0, 727b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, 728b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 729b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, 730b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 731b708205fSBhawanpreet Lakha 732b708205fSBhawanpreet Lakha curve += 2; 733b708205fSBhawanpreet Lakha REG_SET_4(SHAPER_RAMB_REGION_22_23[rmu_idx], 0, 734b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, 735b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 736b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, 737b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 738b708205fSBhawanpreet Lakha 739b708205fSBhawanpreet Lakha curve += 2; 740b708205fSBhawanpreet Lakha REG_SET_4(SHAPER_RAMB_REGION_24_25[rmu_idx], 0, 741b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, 742b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 743b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, 744b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 745b708205fSBhawanpreet Lakha 746b708205fSBhawanpreet Lakha curve += 2; 747b708205fSBhawanpreet Lakha REG_SET_4(SHAPER_RAMB_REGION_26_27[rmu_idx], 0, 748b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, 749b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 750b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, 751b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 752b708205fSBhawanpreet Lakha 753b708205fSBhawanpreet Lakha curve += 2; 754b708205fSBhawanpreet Lakha REG_SET_4(SHAPER_RAMB_REGION_28_29[rmu_idx], 0, 755b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, 756b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 757b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, 758b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 759b708205fSBhawanpreet Lakha 760b708205fSBhawanpreet Lakha curve += 2; 761b708205fSBhawanpreet Lakha REG_SET_4(SHAPER_RAMB_REGION_30_31[rmu_idx], 0, 762b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, 763b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 764b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, 765b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 766b708205fSBhawanpreet Lakha 767b708205fSBhawanpreet Lakha curve += 2; 768b708205fSBhawanpreet Lakha REG_SET_4(SHAPER_RAMB_REGION_32_33[rmu_idx], 0, 769b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, 770b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, 771b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, 772b708205fSBhawanpreet Lakha MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); 773b708205fSBhawanpreet Lakha } 774b708205fSBhawanpreet Lakha 775b708205fSBhawanpreet Lakha 776b708205fSBhawanpreet Lakha static void mpc3_program_shaper_lut( 777b708205fSBhawanpreet Lakha struct mpc *mpc, 778b708205fSBhawanpreet Lakha const struct pwl_result_data *rgb, 779b708205fSBhawanpreet Lakha uint32_t num, 780b708205fSBhawanpreet Lakha uint32_t rmu_idx) 781b708205fSBhawanpreet Lakha { 782b708205fSBhawanpreet Lakha uint32_t i, red, green, blue; 783b708205fSBhawanpreet Lakha uint32_t red_delta, green_delta, blue_delta; 784b708205fSBhawanpreet Lakha uint32_t red_value, green_value, blue_value; 785b708205fSBhawanpreet Lakha 786b708205fSBhawanpreet Lakha struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc); 787b708205fSBhawanpreet Lakha 788b708205fSBhawanpreet Lakha for (i = 0 ; i < num; i++) { 789b708205fSBhawanpreet Lakha 790b708205fSBhawanpreet Lakha red = rgb[i].red_reg; 791b708205fSBhawanpreet Lakha green = rgb[i].green_reg; 792b708205fSBhawanpreet Lakha blue = rgb[i].blue_reg; 793b708205fSBhawanpreet Lakha 794b708205fSBhawanpreet Lakha red_delta = rgb[i].delta_red_reg; 795b708205fSBhawanpreet Lakha green_delta = rgb[i].delta_green_reg; 796b708205fSBhawanpreet Lakha blue_delta = rgb[i].delta_blue_reg; 797b708205fSBhawanpreet Lakha 798b708205fSBhawanpreet Lakha red_value = ((red_delta & 0x3ff) << 14) | (red & 0x3fff); 799b708205fSBhawanpreet Lakha green_value = ((green_delta & 0x3ff) << 14) | (green & 0x3fff); 800b708205fSBhawanpreet Lakha blue_value = ((blue_delta & 0x3ff) << 14) | (blue & 0x3fff); 801b708205fSBhawanpreet Lakha 802b708205fSBhawanpreet Lakha REG_SET(SHAPER_LUT_DATA[rmu_idx], 0, MPC_RMU_SHAPER_LUT_DATA, red_value); 803b708205fSBhawanpreet Lakha REG_SET(SHAPER_LUT_DATA[rmu_idx], 0, MPC_RMU_SHAPER_LUT_DATA, green_value); 804b708205fSBhawanpreet Lakha REG_SET(SHAPER_LUT_DATA[rmu_idx], 0, MPC_RMU_SHAPER_LUT_DATA, blue_value); 805b708205fSBhawanpreet Lakha } 806b708205fSBhawanpreet Lakha 807b708205fSBhawanpreet Lakha } 808b708205fSBhawanpreet Lakha 809b708205fSBhawanpreet Lakha static void mpc3_power_on_shaper_3dlut( 810b708205fSBhawanpreet Lakha struct mpc *mpc, 811b708205fSBhawanpreet Lakha uint32_t rmu_idx, 812b708205fSBhawanpreet Lakha bool power_on) 813b708205fSBhawanpreet Lakha { 814b708205fSBhawanpreet Lakha uint32_t power_status_shaper = 2; 815b708205fSBhawanpreet Lakha uint32_t power_status_3dlut = 2; 816b708205fSBhawanpreet Lakha struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc); 8173e5b4cdfSJacky Liao int max_retries = 10; 818b708205fSBhawanpreet Lakha 819b708205fSBhawanpreet Lakha if (rmu_idx == 0) { 820b708205fSBhawanpreet Lakha REG_SET(MPC_RMU_MEM_PWR_CTRL, 0, 821b708205fSBhawanpreet Lakha MPC_RMU0_MEM_PWR_DIS, power_on == true ? 1:0); 8223e5b4cdfSJacky Liao /* wait for memory to fully power up */ 823cae78e03SJacky Liao if (power_on && mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc) { 8243e5b4cdfSJacky Liao REG_WAIT(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_SHAPER_MEM_PWR_STATE, 0, 1, max_retries); 8253e5b4cdfSJacky Liao REG_WAIT(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_3DLUT_MEM_PWR_STATE, 0, 1, max_retries); 8263e5b4cdfSJacky Liao } 8273e5b4cdfSJacky Liao 828b708205fSBhawanpreet Lakha /*read status is not mandatory, it is just for debugging*/ 829b708205fSBhawanpreet Lakha REG_GET(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_SHAPER_MEM_PWR_STATE, &power_status_shaper); 830b708205fSBhawanpreet Lakha REG_GET(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_3DLUT_MEM_PWR_STATE, &power_status_3dlut); 831b708205fSBhawanpreet Lakha } else if (rmu_idx == 1) { 832b708205fSBhawanpreet Lakha REG_SET(MPC_RMU_MEM_PWR_CTRL, 0, 833b708205fSBhawanpreet Lakha MPC_RMU1_MEM_PWR_DIS, power_on == true ? 1:0); 834cae78e03SJacky Liao if (power_on && mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc) { 8353e5b4cdfSJacky Liao REG_WAIT(MPC_RMU_MEM_PWR_CTRL, MPC_RMU1_SHAPER_MEM_PWR_STATE, 0, 1, max_retries); 8363e5b4cdfSJacky Liao REG_WAIT(MPC_RMU_MEM_PWR_CTRL, MPC_RMU1_3DLUT_MEM_PWR_STATE, 0, 1, max_retries); 8373e5b4cdfSJacky Liao } 8383e5b4cdfSJacky Liao 839b708205fSBhawanpreet Lakha REG_GET(MPC_RMU_MEM_PWR_CTRL, MPC_RMU1_SHAPER_MEM_PWR_STATE, &power_status_shaper); 840b708205fSBhawanpreet Lakha REG_GET(MPC_RMU_MEM_PWR_CTRL, MPC_RMU1_3DLUT_MEM_PWR_STATE, &power_status_3dlut); 841b708205fSBhawanpreet Lakha } 842b708205fSBhawanpreet Lakha /*TODO Add rmu_idx == 2 for SIENNA_CICHLID */ 843b708205fSBhawanpreet Lakha if (power_status_shaper != 0 && power_on == true) 844b708205fSBhawanpreet Lakha BREAK_TO_DEBUGGER(); 845b708205fSBhawanpreet Lakha 846b708205fSBhawanpreet Lakha if (power_status_3dlut != 0 && power_on == true) 847b708205fSBhawanpreet Lakha BREAK_TO_DEBUGGER(); 848b708205fSBhawanpreet Lakha } 849b708205fSBhawanpreet Lakha 850b708205fSBhawanpreet Lakha 851b708205fSBhawanpreet Lakha 852b708205fSBhawanpreet Lakha bool mpc3_program_shaper( 853b708205fSBhawanpreet Lakha struct mpc *mpc, 854b708205fSBhawanpreet Lakha const struct pwl_params *params, 855b708205fSBhawanpreet Lakha uint32_t rmu_idx) 856b708205fSBhawanpreet Lakha { 857b708205fSBhawanpreet Lakha enum dc_lut_mode current_mode; 858b708205fSBhawanpreet Lakha enum dc_lut_mode next_mode; 859b708205fSBhawanpreet Lakha 860b708205fSBhawanpreet Lakha struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc); 861b708205fSBhawanpreet Lakha 862b708205fSBhawanpreet Lakha if (params == NULL) { 863b708205fSBhawanpreet Lakha REG_SET(SHAPER_CONTROL[rmu_idx], 0, MPC_RMU_SHAPER_LUT_MODE, 0); 864b708205fSBhawanpreet Lakha return false; 865b708205fSBhawanpreet Lakha } 8663e5b4cdfSJacky Liao 867cae78e03SJacky Liao if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc) 8683e5b4cdfSJacky Liao mpc3_power_on_shaper_3dlut(mpc, rmu_idx, true); 8693e5b4cdfSJacky Liao 870b708205fSBhawanpreet Lakha current_mode = mpc3_get_shaper_current(mpc, rmu_idx); 871b708205fSBhawanpreet Lakha 872b708205fSBhawanpreet Lakha if (current_mode == LUT_BYPASS || current_mode == LUT_RAM_A) 873b708205fSBhawanpreet Lakha next_mode = LUT_RAM_B; 874b708205fSBhawanpreet Lakha else 875b708205fSBhawanpreet Lakha next_mode = LUT_RAM_A; 876b708205fSBhawanpreet Lakha 877ea23ff02SZhen Lei mpc3_configure_shaper_lut(mpc, next_mode == LUT_RAM_A, rmu_idx); 878b708205fSBhawanpreet Lakha 879b708205fSBhawanpreet Lakha if (next_mode == LUT_RAM_A) 880b708205fSBhawanpreet Lakha mpc3_program_shaper_luta_settings(mpc, params, rmu_idx); 881b708205fSBhawanpreet Lakha else 882b708205fSBhawanpreet Lakha mpc3_program_shaper_lutb_settings(mpc, params, rmu_idx); 883b708205fSBhawanpreet Lakha 884b708205fSBhawanpreet Lakha mpc3_program_shaper_lut( 885b708205fSBhawanpreet Lakha mpc, params->rgb_resulted, params->hw_points_num, rmu_idx); 886b708205fSBhawanpreet Lakha 887b708205fSBhawanpreet Lakha REG_SET(SHAPER_CONTROL[rmu_idx], 0, MPC_RMU_SHAPER_LUT_MODE, next_mode == LUT_RAM_A ? 1:2); 888b708205fSBhawanpreet Lakha mpc3_power_on_shaper_3dlut(mpc, rmu_idx, false); 889b708205fSBhawanpreet Lakha 890b708205fSBhawanpreet Lakha return true; 891b708205fSBhawanpreet Lakha } 892b708205fSBhawanpreet Lakha 893b708205fSBhawanpreet Lakha static void mpc3_set_3dlut_mode( 894b708205fSBhawanpreet Lakha struct mpc *mpc, 895b708205fSBhawanpreet Lakha enum dc_lut_mode mode, 896b708205fSBhawanpreet Lakha bool is_color_channel_12bits, 897b708205fSBhawanpreet Lakha bool is_lut_size17x17x17, 898b708205fSBhawanpreet Lakha uint32_t rmu_idx) 899b708205fSBhawanpreet Lakha { 900b708205fSBhawanpreet Lakha uint32_t lut_mode; 901b708205fSBhawanpreet Lakha struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc); 902b708205fSBhawanpreet Lakha 903b708205fSBhawanpreet Lakha if (mode == LUT_BYPASS) 904b708205fSBhawanpreet Lakha lut_mode = 0; 905b708205fSBhawanpreet Lakha else if (mode == LUT_RAM_A) 906b708205fSBhawanpreet Lakha lut_mode = 1; 907b708205fSBhawanpreet Lakha else 908b708205fSBhawanpreet Lakha lut_mode = 2; 909b708205fSBhawanpreet Lakha 910b708205fSBhawanpreet Lakha REG_UPDATE_2(RMU_3DLUT_MODE[rmu_idx], 911b708205fSBhawanpreet Lakha MPC_RMU_3DLUT_MODE, lut_mode, 912b708205fSBhawanpreet Lakha MPC_RMU_3DLUT_SIZE, is_lut_size17x17x17 == true ? 0 : 1); 913b708205fSBhawanpreet Lakha } 914b708205fSBhawanpreet Lakha 915b708205fSBhawanpreet Lakha static enum dc_lut_mode get3dlut_config( 916b708205fSBhawanpreet Lakha struct mpc *mpc, 917b708205fSBhawanpreet Lakha bool *is_17x17x17, 918b708205fSBhawanpreet Lakha bool *is_12bits_color_channel, 919b708205fSBhawanpreet Lakha int rmu_idx) 920b708205fSBhawanpreet Lakha { 921b708205fSBhawanpreet Lakha uint32_t i_mode, i_enable_10bits, lut_size; 922b708205fSBhawanpreet Lakha enum dc_lut_mode mode; 923b708205fSBhawanpreet Lakha struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc); 924b708205fSBhawanpreet Lakha 925b708205fSBhawanpreet Lakha REG_GET(RMU_3DLUT_MODE[rmu_idx], 926b708205fSBhawanpreet Lakha MPC_RMU_3DLUT_MODE_CURRENT, &i_mode); 927b708205fSBhawanpreet Lakha 928b708205fSBhawanpreet Lakha REG_GET(RMU_3DLUT_READ_WRITE_CONTROL[rmu_idx], 929b708205fSBhawanpreet Lakha MPC_RMU_3DLUT_30BIT_EN, &i_enable_10bits); 930b708205fSBhawanpreet Lakha 931b708205fSBhawanpreet Lakha switch (i_mode) { 932b708205fSBhawanpreet Lakha case 0: 933b708205fSBhawanpreet Lakha mode = LUT_BYPASS; 934b708205fSBhawanpreet Lakha break; 935b708205fSBhawanpreet Lakha case 1: 936b708205fSBhawanpreet Lakha mode = LUT_RAM_A; 937b708205fSBhawanpreet Lakha break; 938b708205fSBhawanpreet Lakha case 2: 939b708205fSBhawanpreet Lakha mode = LUT_RAM_B; 940b708205fSBhawanpreet Lakha break; 941b708205fSBhawanpreet Lakha default: 942b708205fSBhawanpreet Lakha mode = LUT_BYPASS; 943b708205fSBhawanpreet Lakha break; 944b708205fSBhawanpreet Lakha } 945b708205fSBhawanpreet Lakha if (i_enable_10bits > 0) 946b708205fSBhawanpreet Lakha *is_12bits_color_channel = false; 947b708205fSBhawanpreet Lakha else 948b708205fSBhawanpreet Lakha *is_12bits_color_channel = true; 949b708205fSBhawanpreet Lakha 950b708205fSBhawanpreet Lakha REG_GET(RMU_3DLUT_MODE[rmu_idx], MPC_RMU_3DLUT_SIZE, &lut_size); 951b708205fSBhawanpreet Lakha 952b708205fSBhawanpreet Lakha if (lut_size == 0) 953b708205fSBhawanpreet Lakha *is_17x17x17 = true; 954b708205fSBhawanpreet Lakha else 955b708205fSBhawanpreet Lakha *is_17x17x17 = false; 956b708205fSBhawanpreet Lakha 957b708205fSBhawanpreet Lakha return mode; 958b708205fSBhawanpreet Lakha } 959b708205fSBhawanpreet Lakha 960b708205fSBhawanpreet Lakha static void mpc3_select_3dlut_ram( 961b708205fSBhawanpreet Lakha struct mpc *mpc, 962b708205fSBhawanpreet Lakha enum dc_lut_mode mode, 963b708205fSBhawanpreet Lakha bool is_color_channel_12bits, 964b708205fSBhawanpreet Lakha uint32_t rmu_idx) 965b708205fSBhawanpreet Lakha { 966b708205fSBhawanpreet Lakha struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc); 967b708205fSBhawanpreet Lakha 968b708205fSBhawanpreet Lakha REG_UPDATE_2(RMU_3DLUT_READ_WRITE_CONTROL[rmu_idx], 969b708205fSBhawanpreet Lakha MPC_RMU_3DLUT_RAM_SEL, mode == LUT_RAM_A ? 0 : 1, 970b708205fSBhawanpreet Lakha MPC_RMU_3DLUT_30BIT_EN, is_color_channel_12bits == true ? 0:1); 971b708205fSBhawanpreet Lakha } 972b708205fSBhawanpreet Lakha 973b708205fSBhawanpreet Lakha static void mpc3_select_3dlut_ram_mask( 974b708205fSBhawanpreet Lakha struct mpc *mpc, 975b708205fSBhawanpreet Lakha uint32_t ram_selection_mask, 976b708205fSBhawanpreet Lakha uint32_t rmu_idx) 977b708205fSBhawanpreet Lakha { 978b708205fSBhawanpreet Lakha struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc); 979b708205fSBhawanpreet Lakha 980b708205fSBhawanpreet Lakha REG_UPDATE(RMU_3DLUT_READ_WRITE_CONTROL[rmu_idx], MPC_RMU_3DLUT_WRITE_EN_MASK, 981b708205fSBhawanpreet Lakha ram_selection_mask); 982b708205fSBhawanpreet Lakha REG_SET(RMU_3DLUT_INDEX[rmu_idx], 0, MPC_RMU_3DLUT_INDEX, 0); 983b708205fSBhawanpreet Lakha } 984b708205fSBhawanpreet Lakha 985b708205fSBhawanpreet Lakha static void mpc3_set3dlut_ram12( 986b708205fSBhawanpreet Lakha struct mpc *mpc, 987b708205fSBhawanpreet Lakha const struct dc_rgb *lut, 988b708205fSBhawanpreet Lakha uint32_t entries, 989b708205fSBhawanpreet Lakha uint32_t rmu_idx) 990b708205fSBhawanpreet Lakha { 991b708205fSBhawanpreet Lakha uint32_t i, red, green, blue, red1, green1, blue1; 992b708205fSBhawanpreet Lakha struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc); 993b708205fSBhawanpreet Lakha 994b708205fSBhawanpreet Lakha for (i = 0 ; i < entries; i += 2) { 995b708205fSBhawanpreet Lakha red = lut[i].red<<4; 996b708205fSBhawanpreet Lakha green = lut[i].green<<4; 997b708205fSBhawanpreet Lakha blue = lut[i].blue<<4; 998b708205fSBhawanpreet Lakha red1 = lut[i+1].red<<4; 999b708205fSBhawanpreet Lakha green1 = lut[i+1].green<<4; 1000b708205fSBhawanpreet Lakha blue1 = lut[i+1].blue<<4; 1001b708205fSBhawanpreet Lakha 1002b708205fSBhawanpreet Lakha REG_SET_2(RMU_3DLUT_DATA[rmu_idx], 0, 1003b708205fSBhawanpreet Lakha MPC_RMU_3DLUT_DATA0, red, 1004b708205fSBhawanpreet Lakha MPC_RMU_3DLUT_DATA1, red1); 1005b708205fSBhawanpreet Lakha 1006b708205fSBhawanpreet Lakha REG_SET_2(RMU_3DLUT_DATA[rmu_idx], 0, 1007b708205fSBhawanpreet Lakha MPC_RMU_3DLUT_DATA0, green, 1008b708205fSBhawanpreet Lakha MPC_RMU_3DLUT_DATA1, green1); 1009b708205fSBhawanpreet Lakha 1010b708205fSBhawanpreet Lakha REG_SET_2(RMU_3DLUT_DATA[rmu_idx], 0, 1011b708205fSBhawanpreet Lakha MPC_RMU_3DLUT_DATA0, blue, 1012b708205fSBhawanpreet Lakha MPC_RMU_3DLUT_DATA1, blue1); 1013b708205fSBhawanpreet Lakha } 1014b708205fSBhawanpreet Lakha } 1015b708205fSBhawanpreet Lakha 1016b708205fSBhawanpreet Lakha static void mpc3_set3dlut_ram10( 1017b708205fSBhawanpreet Lakha struct mpc *mpc, 1018b708205fSBhawanpreet Lakha const struct dc_rgb *lut, 1019b708205fSBhawanpreet Lakha uint32_t entries, 1020b708205fSBhawanpreet Lakha uint32_t rmu_idx) 1021b708205fSBhawanpreet Lakha { 1022b708205fSBhawanpreet Lakha uint32_t i, red, green, blue, value; 1023b708205fSBhawanpreet Lakha struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc); 1024b708205fSBhawanpreet Lakha 1025b708205fSBhawanpreet Lakha for (i = 0; i < entries; i++) { 1026b708205fSBhawanpreet Lakha red = lut[i].red; 1027b708205fSBhawanpreet Lakha green = lut[i].green; 1028b708205fSBhawanpreet Lakha blue = lut[i].blue; 1029b708205fSBhawanpreet Lakha //should we shift red 22bit and green 12? ask Nvenko 1030b708205fSBhawanpreet Lakha value = (red<<20) | (green<<10) | blue; 1031b708205fSBhawanpreet Lakha 1032b708205fSBhawanpreet Lakha REG_SET(RMU_3DLUT_DATA_30BIT[rmu_idx], 0, MPC_RMU_3DLUT_DATA_30BIT, value); 1033b708205fSBhawanpreet Lakha } 1034b708205fSBhawanpreet Lakha 1035b708205fSBhawanpreet Lakha } 1036b708205fSBhawanpreet Lakha 1037b708205fSBhawanpreet Lakha 1038b708205fSBhawanpreet Lakha static void mpc3_init_mpcc(struct mpcc *mpcc, int mpcc_inst) 1039b708205fSBhawanpreet Lakha { 1040b708205fSBhawanpreet Lakha mpcc->mpcc_id = mpcc_inst; 1041b708205fSBhawanpreet Lakha mpcc->dpp_id = 0xf; 1042b708205fSBhawanpreet Lakha mpcc->mpcc_bot = NULL; 1043b708205fSBhawanpreet Lakha mpcc->blnd_cfg.overlap_only = false; 1044b708205fSBhawanpreet Lakha mpcc->blnd_cfg.global_alpha = 0xff; 1045b708205fSBhawanpreet Lakha mpcc->blnd_cfg.global_gain = 0xff; 1046b708205fSBhawanpreet Lakha mpcc->blnd_cfg.background_color_bpc = 4; 1047b708205fSBhawanpreet Lakha mpcc->blnd_cfg.bottom_gain_mode = 0; 1048b708205fSBhawanpreet Lakha mpcc->blnd_cfg.top_gain = 0x1f000; 1049b708205fSBhawanpreet Lakha mpcc->blnd_cfg.bottom_inside_gain = 0x1f000; 1050b708205fSBhawanpreet Lakha mpcc->blnd_cfg.bottom_outside_gain = 0x1f000; 1051b708205fSBhawanpreet Lakha mpcc->sm_cfg.enable = false; 1052b708205fSBhawanpreet Lakha mpcc->shared_bottom = false; 1053b708205fSBhawanpreet Lakha } 1054b708205fSBhawanpreet Lakha 1055b708205fSBhawanpreet Lakha static void program_gamut_remap( 1056b708205fSBhawanpreet Lakha struct dcn30_mpc *mpc30, 1057b708205fSBhawanpreet Lakha int mpcc_id, 1058b708205fSBhawanpreet Lakha const uint16_t *regval, 1059b708205fSBhawanpreet Lakha int select) 1060b708205fSBhawanpreet Lakha { 1061b708205fSBhawanpreet Lakha uint16_t selection = 0; 1062b708205fSBhawanpreet Lakha struct color_matrices_reg gam_regs; 1063b708205fSBhawanpreet Lakha 1064b708205fSBhawanpreet Lakha if (regval == NULL || select == GAMUT_REMAP_BYPASS) { 1065b708205fSBhawanpreet Lakha REG_SET(MPCC_GAMUT_REMAP_MODE[mpcc_id], 0, 1066b708205fSBhawanpreet Lakha MPCC_GAMUT_REMAP_MODE, GAMUT_REMAP_BYPASS); 1067b708205fSBhawanpreet Lakha return; 1068b708205fSBhawanpreet Lakha } 1069b708205fSBhawanpreet Lakha switch (select) { 1070b708205fSBhawanpreet Lakha case GAMUT_REMAP_COEFF: 1071b708205fSBhawanpreet Lakha selection = 1; 1072b708205fSBhawanpreet Lakha break; 1073b708205fSBhawanpreet Lakha /*this corresponds to GAMUT_REMAP coefficients set B 1074b708205fSBhawanpreet Lakha * we don't have common coefficient sets in dcn3ag/dcn3 1075b708205fSBhawanpreet Lakha */ 1076b708205fSBhawanpreet Lakha case GAMUT_REMAP_COMA_COEFF: 1077b708205fSBhawanpreet Lakha selection = 2; 1078b708205fSBhawanpreet Lakha break; 1079b708205fSBhawanpreet Lakha default: 1080b708205fSBhawanpreet Lakha break; 1081b708205fSBhawanpreet Lakha } 1082b708205fSBhawanpreet Lakha 1083b708205fSBhawanpreet Lakha gam_regs.shifts.csc_c11 = mpc30->mpc_shift->MPCC_GAMUT_REMAP_C11_A; 1084b708205fSBhawanpreet Lakha gam_regs.masks.csc_c11 = mpc30->mpc_mask->MPCC_GAMUT_REMAP_C11_A; 1085b708205fSBhawanpreet Lakha gam_regs.shifts.csc_c12 = mpc30->mpc_shift->MPCC_GAMUT_REMAP_C12_A; 1086b708205fSBhawanpreet Lakha gam_regs.masks.csc_c12 = mpc30->mpc_mask->MPCC_GAMUT_REMAP_C12_A; 1087b708205fSBhawanpreet Lakha 1088b708205fSBhawanpreet Lakha 1089b708205fSBhawanpreet Lakha if (select == GAMUT_REMAP_COEFF) { 1090b708205fSBhawanpreet Lakha gam_regs.csc_c11_c12 = REG(MPC_GAMUT_REMAP_C11_C12_A[mpcc_id]); 1091b708205fSBhawanpreet Lakha gam_regs.csc_c33_c34 = REG(MPC_GAMUT_REMAP_C33_C34_A[mpcc_id]); 1092b708205fSBhawanpreet Lakha 1093b708205fSBhawanpreet Lakha cm_helper_program_color_matrices( 1094b708205fSBhawanpreet Lakha mpc30->base.ctx, 1095b708205fSBhawanpreet Lakha regval, 1096b708205fSBhawanpreet Lakha &gam_regs); 1097b708205fSBhawanpreet Lakha 1098b708205fSBhawanpreet Lakha } else if (select == GAMUT_REMAP_COMA_COEFF) { 1099b708205fSBhawanpreet Lakha 1100b708205fSBhawanpreet Lakha gam_regs.csc_c11_c12 = REG(MPC_GAMUT_REMAP_C11_C12_B[mpcc_id]); 1101b708205fSBhawanpreet Lakha gam_regs.csc_c33_c34 = REG(MPC_GAMUT_REMAP_C33_C34_B[mpcc_id]); 1102b708205fSBhawanpreet Lakha 1103b708205fSBhawanpreet Lakha cm_helper_program_color_matrices( 1104b708205fSBhawanpreet Lakha mpc30->base.ctx, 1105b708205fSBhawanpreet Lakha regval, 1106b708205fSBhawanpreet Lakha &gam_regs); 1107b708205fSBhawanpreet Lakha 1108b708205fSBhawanpreet Lakha } 1109b708205fSBhawanpreet Lakha //select coefficient set to use 1110b708205fSBhawanpreet Lakha REG_SET(MPCC_GAMUT_REMAP_MODE[mpcc_id], 0, 1111b708205fSBhawanpreet Lakha MPCC_GAMUT_REMAP_MODE, selection); 1112b708205fSBhawanpreet Lakha } 1113b708205fSBhawanpreet Lakha 1114b708205fSBhawanpreet Lakha void mpc3_set_gamut_remap( 1115b708205fSBhawanpreet Lakha struct mpc *mpc, 1116b708205fSBhawanpreet Lakha int mpcc_id, 1117b708205fSBhawanpreet Lakha const struct mpc_grph_gamut_adjustment *adjust) 1118b708205fSBhawanpreet Lakha { 1119b708205fSBhawanpreet Lakha struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc); 1120b708205fSBhawanpreet Lakha int i = 0; 1121b708205fSBhawanpreet Lakha int gamut_mode; 1122b708205fSBhawanpreet Lakha 1123b708205fSBhawanpreet Lakha if (adjust->gamut_adjust_type != GRAPHICS_GAMUT_ADJUST_TYPE_SW) 1124b708205fSBhawanpreet Lakha program_gamut_remap(mpc30, mpcc_id, NULL, GAMUT_REMAP_BYPASS); 1125b708205fSBhawanpreet Lakha else { 1126b708205fSBhawanpreet Lakha struct fixed31_32 arr_matrix[12]; 1127b708205fSBhawanpreet Lakha uint16_t arr_reg_val[12]; 1128b708205fSBhawanpreet Lakha 1129b708205fSBhawanpreet Lakha for (i = 0; i < 12; i++) 1130b708205fSBhawanpreet Lakha arr_matrix[i] = adjust->temperature_matrix[i]; 1131b708205fSBhawanpreet Lakha 1132b708205fSBhawanpreet Lakha convert_float_matrix( 1133b708205fSBhawanpreet Lakha arr_reg_val, arr_matrix, 12); 1134b708205fSBhawanpreet Lakha 1135b708205fSBhawanpreet Lakha //current coefficient set in use 1136b708205fSBhawanpreet Lakha REG_GET(MPCC_GAMUT_REMAP_MODE[mpcc_id], MPCC_GAMUT_REMAP_MODE_CURRENT, &gamut_mode); 1137b708205fSBhawanpreet Lakha 1138b708205fSBhawanpreet Lakha if (gamut_mode == 0) 1139b708205fSBhawanpreet Lakha gamut_mode = 1; //use coefficient set A 1140b708205fSBhawanpreet Lakha else if (gamut_mode == 1) 1141b708205fSBhawanpreet Lakha gamut_mode = 2; 1142b708205fSBhawanpreet Lakha else 1143b708205fSBhawanpreet Lakha gamut_mode = 1; 1144b708205fSBhawanpreet Lakha 1145b708205fSBhawanpreet Lakha program_gamut_remap(mpc30, mpcc_id, arr_reg_val, gamut_mode); 1146b708205fSBhawanpreet Lakha } 1147b708205fSBhawanpreet Lakha } 1148b708205fSBhawanpreet Lakha 1149b708205fSBhawanpreet Lakha bool mpc3_program_3dlut( 1150b708205fSBhawanpreet Lakha struct mpc *mpc, 1151b708205fSBhawanpreet Lakha const struct tetrahedral_params *params, 1152b708205fSBhawanpreet Lakha int rmu_idx) 1153b708205fSBhawanpreet Lakha { 1154b708205fSBhawanpreet Lakha enum dc_lut_mode mode; 1155b708205fSBhawanpreet Lakha bool is_17x17x17; 1156b708205fSBhawanpreet Lakha bool is_12bits_color_channel; 1157b708205fSBhawanpreet Lakha const struct dc_rgb *lut0; 1158b708205fSBhawanpreet Lakha const struct dc_rgb *lut1; 1159b708205fSBhawanpreet Lakha const struct dc_rgb *lut2; 1160b708205fSBhawanpreet Lakha const struct dc_rgb *lut3; 1161b708205fSBhawanpreet Lakha int lut_size0; 1162b708205fSBhawanpreet Lakha int lut_size; 1163b708205fSBhawanpreet Lakha 1164b708205fSBhawanpreet Lakha if (params == NULL) { 1165b708205fSBhawanpreet Lakha mpc3_set_3dlut_mode(mpc, LUT_BYPASS, false, false, rmu_idx); 1166b708205fSBhawanpreet Lakha return false; 1167b708205fSBhawanpreet Lakha } 1168b708205fSBhawanpreet Lakha mpc3_power_on_shaper_3dlut(mpc, rmu_idx, true); 1169b708205fSBhawanpreet Lakha 1170b708205fSBhawanpreet Lakha mode = get3dlut_config(mpc, &is_17x17x17, &is_12bits_color_channel, rmu_idx); 1171b708205fSBhawanpreet Lakha 1172b708205fSBhawanpreet Lakha if (mode == LUT_BYPASS || mode == LUT_RAM_B) 1173b708205fSBhawanpreet Lakha mode = LUT_RAM_A; 1174b708205fSBhawanpreet Lakha else 1175b708205fSBhawanpreet Lakha mode = LUT_RAM_B; 1176b708205fSBhawanpreet Lakha 1177b708205fSBhawanpreet Lakha is_17x17x17 = !params->use_tetrahedral_9; 1178b708205fSBhawanpreet Lakha is_12bits_color_channel = params->use_12bits; 1179b708205fSBhawanpreet Lakha if (is_17x17x17) { 1180b708205fSBhawanpreet Lakha lut0 = params->tetrahedral_17.lut0; 1181b708205fSBhawanpreet Lakha lut1 = params->tetrahedral_17.lut1; 1182b708205fSBhawanpreet Lakha lut2 = params->tetrahedral_17.lut2; 1183b708205fSBhawanpreet Lakha lut3 = params->tetrahedral_17.lut3; 1184b708205fSBhawanpreet Lakha lut_size0 = sizeof(params->tetrahedral_17.lut0)/ 1185b708205fSBhawanpreet Lakha sizeof(params->tetrahedral_17.lut0[0]); 1186b708205fSBhawanpreet Lakha lut_size = sizeof(params->tetrahedral_17.lut1)/ 1187b708205fSBhawanpreet Lakha sizeof(params->tetrahedral_17.lut1[0]); 1188b708205fSBhawanpreet Lakha } else { 1189b708205fSBhawanpreet Lakha lut0 = params->tetrahedral_9.lut0; 1190b708205fSBhawanpreet Lakha lut1 = params->tetrahedral_9.lut1; 1191b708205fSBhawanpreet Lakha lut2 = params->tetrahedral_9.lut2; 1192b708205fSBhawanpreet Lakha lut3 = params->tetrahedral_9.lut3; 1193b708205fSBhawanpreet Lakha lut_size0 = sizeof(params->tetrahedral_9.lut0)/ 1194b708205fSBhawanpreet Lakha sizeof(params->tetrahedral_9.lut0[0]); 1195b708205fSBhawanpreet Lakha lut_size = sizeof(params->tetrahedral_9.lut1)/ 1196b708205fSBhawanpreet Lakha sizeof(params->tetrahedral_9.lut1[0]); 1197b708205fSBhawanpreet Lakha } 1198b708205fSBhawanpreet Lakha 1199b708205fSBhawanpreet Lakha mpc3_select_3dlut_ram(mpc, mode, 1200b708205fSBhawanpreet Lakha is_12bits_color_channel, rmu_idx); 1201b708205fSBhawanpreet Lakha mpc3_select_3dlut_ram_mask(mpc, 0x1, rmu_idx); 1202b708205fSBhawanpreet Lakha if (is_12bits_color_channel) 1203b708205fSBhawanpreet Lakha mpc3_set3dlut_ram12(mpc, lut0, lut_size0, rmu_idx); 1204b708205fSBhawanpreet Lakha else 1205b708205fSBhawanpreet Lakha mpc3_set3dlut_ram10(mpc, lut0, lut_size0, rmu_idx); 1206b708205fSBhawanpreet Lakha 1207b708205fSBhawanpreet Lakha mpc3_select_3dlut_ram_mask(mpc, 0x2, rmu_idx); 1208b708205fSBhawanpreet Lakha if (is_12bits_color_channel) 1209b708205fSBhawanpreet Lakha mpc3_set3dlut_ram12(mpc, lut1, lut_size, rmu_idx); 1210b708205fSBhawanpreet Lakha else 1211b708205fSBhawanpreet Lakha mpc3_set3dlut_ram10(mpc, lut1, lut_size, rmu_idx); 1212b708205fSBhawanpreet Lakha 1213b708205fSBhawanpreet Lakha mpc3_select_3dlut_ram_mask(mpc, 0x4, rmu_idx); 1214b708205fSBhawanpreet Lakha if (is_12bits_color_channel) 1215b708205fSBhawanpreet Lakha mpc3_set3dlut_ram12(mpc, lut2, lut_size, rmu_idx); 1216b708205fSBhawanpreet Lakha else 1217b708205fSBhawanpreet Lakha mpc3_set3dlut_ram10(mpc, lut2, lut_size, rmu_idx); 1218b708205fSBhawanpreet Lakha 1219b708205fSBhawanpreet Lakha mpc3_select_3dlut_ram_mask(mpc, 0x8, rmu_idx); 1220b708205fSBhawanpreet Lakha if (is_12bits_color_channel) 1221b708205fSBhawanpreet Lakha mpc3_set3dlut_ram12(mpc, lut3, lut_size, rmu_idx); 1222b708205fSBhawanpreet Lakha else 1223b708205fSBhawanpreet Lakha mpc3_set3dlut_ram10(mpc, lut3, lut_size, rmu_idx); 1224b708205fSBhawanpreet Lakha 1225b708205fSBhawanpreet Lakha mpc3_set_3dlut_mode(mpc, mode, is_12bits_color_channel, 1226b708205fSBhawanpreet Lakha is_17x17x17, rmu_idx); 1227b708205fSBhawanpreet Lakha 1228cae78e03SJacky Liao if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc) 12293e5b4cdfSJacky Liao mpc3_power_on_shaper_3dlut(mpc, rmu_idx, false); 12303e5b4cdfSJacky Liao 1231b708205fSBhawanpreet Lakha return true; 1232b708205fSBhawanpreet Lakha } 1233b708205fSBhawanpreet Lakha 1234b708205fSBhawanpreet Lakha void mpc3_set_output_csc( 1235b708205fSBhawanpreet Lakha struct mpc *mpc, 1236b708205fSBhawanpreet Lakha int opp_id, 1237b708205fSBhawanpreet Lakha const uint16_t *regval, 1238b708205fSBhawanpreet Lakha enum mpc_output_csc_mode ocsc_mode) 1239b708205fSBhawanpreet Lakha { 1240b708205fSBhawanpreet Lakha struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc); 1241b708205fSBhawanpreet Lakha struct color_matrices_reg ocsc_regs; 1242b708205fSBhawanpreet Lakha 1243b708205fSBhawanpreet Lakha REG_WRITE(MPC_OUT_CSC_COEF_FORMAT, 0); 1244b708205fSBhawanpreet Lakha 1245b708205fSBhawanpreet Lakha REG_SET(CSC_MODE[opp_id], 0, MPC_OCSC_MODE, ocsc_mode); 1246b708205fSBhawanpreet Lakha 1247b708205fSBhawanpreet Lakha if (ocsc_mode == MPC_OUTPUT_CSC_DISABLE) 1248b708205fSBhawanpreet Lakha return; 1249b708205fSBhawanpreet Lakha 1250b708205fSBhawanpreet Lakha if (regval == NULL) { 1251b708205fSBhawanpreet Lakha BREAK_TO_DEBUGGER(); 1252b708205fSBhawanpreet Lakha return; 1253b708205fSBhawanpreet Lakha } 1254b708205fSBhawanpreet Lakha 1255b708205fSBhawanpreet Lakha ocsc_regs.shifts.csc_c11 = mpc30->mpc_shift->MPC_OCSC_C11_A; 1256b708205fSBhawanpreet Lakha ocsc_regs.masks.csc_c11 = mpc30->mpc_mask->MPC_OCSC_C11_A; 1257b708205fSBhawanpreet Lakha ocsc_regs.shifts.csc_c12 = mpc30->mpc_shift->MPC_OCSC_C12_A; 1258b708205fSBhawanpreet Lakha ocsc_regs.masks.csc_c12 = mpc30->mpc_mask->MPC_OCSC_C12_A; 1259b708205fSBhawanpreet Lakha 1260b708205fSBhawanpreet Lakha if (ocsc_mode == MPC_OUTPUT_CSC_COEF_A) { 1261b708205fSBhawanpreet Lakha ocsc_regs.csc_c11_c12 = REG(CSC_C11_C12_A[opp_id]); 1262b708205fSBhawanpreet Lakha ocsc_regs.csc_c33_c34 = REG(CSC_C33_C34_A[opp_id]); 1263b708205fSBhawanpreet Lakha } else { 1264b708205fSBhawanpreet Lakha ocsc_regs.csc_c11_c12 = REG(CSC_C11_C12_B[opp_id]); 1265b708205fSBhawanpreet Lakha ocsc_regs.csc_c33_c34 = REG(CSC_C33_C34_B[opp_id]); 1266b708205fSBhawanpreet Lakha } 1267b708205fSBhawanpreet Lakha cm_helper_program_color_matrices( 1268b708205fSBhawanpreet Lakha mpc30->base.ctx, 1269b708205fSBhawanpreet Lakha regval, 1270b708205fSBhawanpreet Lakha &ocsc_regs); 1271b708205fSBhawanpreet Lakha } 1272b708205fSBhawanpreet Lakha 1273b708205fSBhawanpreet Lakha void mpc3_set_ocsc_default( 1274b708205fSBhawanpreet Lakha struct mpc *mpc, 1275b708205fSBhawanpreet Lakha int opp_id, 1276b708205fSBhawanpreet Lakha enum dc_color_space color_space, 1277b708205fSBhawanpreet Lakha enum mpc_output_csc_mode ocsc_mode) 1278b708205fSBhawanpreet Lakha { 1279b708205fSBhawanpreet Lakha struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc); 1280b708205fSBhawanpreet Lakha uint32_t arr_size; 1281b708205fSBhawanpreet Lakha struct color_matrices_reg ocsc_regs; 1282b708205fSBhawanpreet Lakha const uint16_t *regval = NULL; 1283b708205fSBhawanpreet Lakha 1284b708205fSBhawanpreet Lakha REG_WRITE(MPC_OUT_CSC_COEF_FORMAT, 0); 1285b708205fSBhawanpreet Lakha 1286b708205fSBhawanpreet Lakha REG_SET(CSC_MODE[opp_id], 0, MPC_OCSC_MODE, ocsc_mode); 1287b708205fSBhawanpreet Lakha if (ocsc_mode == MPC_OUTPUT_CSC_DISABLE) 1288b708205fSBhawanpreet Lakha return; 1289b708205fSBhawanpreet Lakha 1290b708205fSBhawanpreet Lakha regval = find_color_matrix(color_space, &arr_size); 1291b708205fSBhawanpreet Lakha 1292b708205fSBhawanpreet Lakha if (regval == NULL) { 1293b708205fSBhawanpreet Lakha BREAK_TO_DEBUGGER(); 1294b708205fSBhawanpreet Lakha return; 1295b708205fSBhawanpreet Lakha } 1296b708205fSBhawanpreet Lakha 1297b708205fSBhawanpreet Lakha ocsc_regs.shifts.csc_c11 = mpc30->mpc_shift->MPC_OCSC_C11_A; 1298b708205fSBhawanpreet Lakha ocsc_regs.masks.csc_c11 = mpc30->mpc_mask->MPC_OCSC_C11_A; 1299b708205fSBhawanpreet Lakha ocsc_regs.shifts.csc_c12 = mpc30->mpc_shift->MPC_OCSC_C12_A; 1300b708205fSBhawanpreet Lakha ocsc_regs.masks.csc_c12 = mpc30->mpc_mask->MPC_OCSC_C12_A; 1301b708205fSBhawanpreet Lakha 1302b708205fSBhawanpreet Lakha 1303b708205fSBhawanpreet Lakha if (ocsc_mode == MPC_OUTPUT_CSC_COEF_A) { 1304b708205fSBhawanpreet Lakha ocsc_regs.csc_c11_c12 = REG(CSC_C11_C12_A[opp_id]); 1305b708205fSBhawanpreet Lakha ocsc_regs.csc_c33_c34 = REG(CSC_C33_C34_A[opp_id]); 1306b708205fSBhawanpreet Lakha } else { 1307b708205fSBhawanpreet Lakha ocsc_regs.csc_c11_c12 = REG(CSC_C11_C12_B[opp_id]); 1308b708205fSBhawanpreet Lakha ocsc_regs.csc_c33_c34 = REG(CSC_C33_C34_B[opp_id]); 1309b708205fSBhawanpreet Lakha } 1310b708205fSBhawanpreet Lakha 1311b708205fSBhawanpreet Lakha cm_helper_program_color_matrices( 1312b708205fSBhawanpreet Lakha mpc30->base.ctx, 1313b708205fSBhawanpreet Lakha regval, 1314b708205fSBhawanpreet Lakha &ocsc_regs); 1315b708205fSBhawanpreet Lakha } 1316b708205fSBhawanpreet Lakha 1317b708205fSBhawanpreet Lakha void mpc3_set_rmu_mux( 1318b708205fSBhawanpreet Lakha struct mpc *mpc, 1319b708205fSBhawanpreet Lakha int rmu_idx, 1320b708205fSBhawanpreet Lakha int value) 1321b708205fSBhawanpreet Lakha { 1322b708205fSBhawanpreet Lakha struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc); 1323b708205fSBhawanpreet Lakha 1324b708205fSBhawanpreet Lakha if (rmu_idx == 0) 1325b708205fSBhawanpreet Lakha REG_UPDATE(MPC_RMU_CONTROL, MPC_RMU0_MUX, value); 1326b708205fSBhawanpreet Lakha else if (rmu_idx == 1) 1327b708205fSBhawanpreet Lakha REG_UPDATE(MPC_RMU_CONTROL, MPC_RMU1_MUX, value); 1328b708205fSBhawanpreet Lakha 1329b708205fSBhawanpreet Lakha } 1330b708205fSBhawanpreet Lakha 1331b708205fSBhawanpreet Lakha uint32_t mpc3_get_rmu_mux_status( 1332b708205fSBhawanpreet Lakha struct mpc *mpc, 1333b708205fSBhawanpreet Lakha int rmu_idx) 1334b708205fSBhawanpreet Lakha { 1335b708205fSBhawanpreet Lakha uint32_t status = 0xf; 1336b708205fSBhawanpreet Lakha struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc); 1337b708205fSBhawanpreet Lakha 1338b708205fSBhawanpreet Lakha if (rmu_idx == 0) 1339b708205fSBhawanpreet Lakha REG_GET(MPC_RMU_CONTROL, MPC_RMU0_MUX_STATUS, &status); 1340b708205fSBhawanpreet Lakha else if (rmu_idx == 1) 1341b708205fSBhawanpreet Lakha REG_GET(MPC_RMU_CONTROL, MPC_RMU1_MUX_STATUS, &status); 1342b708205fSBhawanpreet Lakha 1343b708205fSBhawanpreet Lakha return status; 1344b708205fSBhawanpreet Lakha } 1345b708205fSBhawanpreet Lakha 1346b708205fSBhawanpreet Lakha uint32_t mpcc3_acquire_rmu(struct mpc *mpc, int mpcc_id, int rmu_idx) 1347b708205fSBhawanpreet Lakha { 1348b708205fSBhawanpreet Lakha uint32_t rmu_status; 1349b708205fSBhawanpreet Lakha 1350b708205fSBhawanpreet Lakha //determine if this mpcc is already multiplexed to an RMU unit 1351b708205fSBhawanpreet Lakha rmu_status = mpc3_get_rmu_mux_status(mpc, rmu_idx); 1352b708205fSBhawanpreet Lakha if (rmu_status == mpcc_id) 1353b708205fSBhawanpreet Lakha //return rmu_idx of pre_acquired rmu unit 1354b708205fSBhawanpreet Lakha return rmu_idx; 1355b708205fSBhawanpreet Lakha 1356b708205fSBhawanpreet Lakha if (rmu_status == 0xf) {//rmu unit is disabled 1357b708205fSBhawanpreet Lakha mpc3_set_rmu_mux(mpc, rmu_idx, mpcc_id); 1358b708205fSBhawanpreet Lakha return rmu_idx; 1359b708205fSBhawanpreet Lakha } 1360b708205fSBhawanpreet Lakha 1361b708205fSBhawanpreet Lakha //no vacant RMU units or invalid parameters acquire_post_bldn_3dlut 1362b708205fSBhawanpreet Lakha return -1; 1363b708205fSBhawanpreet Lakha } 1364b708205fSBhawanpreet Lakha 1365b708205fSBhawanpreet Lakha int mpcc3_release_rmu(struct mpc *mpc, int mpcc_id) 1366b708205fSBhawanpreet Lakha { 1367b708205fSBhawanpreet Lakha struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc); 1368b708205fSBhawanpreet Lakha int rmu_idx; 1369b708205fSBhawanpreet Lakha uint32_t rmu_status; 1370b708205fSBhawanpreet Lakha int released_rmu = -1; 1371b708205fSBhawanpreet Lakha 1372b708205fSBhawanpreet Lakha for (rmu_idx = 0; rmu_idx < mpc30->num_rmu; rmu_idx++) { 1373b708205fSBhawanpreet Lakha rmu_status = mpc3_get_rmu_mux_status(mpc, rmu_idx); 1374b708205fSBhawanpreet Lakha if (rmu_status == mpcc_id) { 1375b708205fSBhawanpreet Lakha mpc3_set_rmu_mux(mpc, rmu_idx, 0xf); 1376b708205fSBhawanpreet Lakha released_rmu = rmu_idx; 1377b708205fSBhawanpreet Lakha break; 1378b708205fSBhawanpreet Lakha } 1379b708205fSBhawanpreet Lakha } 1380b708205fSBhawanpreet Lakha return released_rmu; 1381b708205fSBhawanpreet Lakha 1382b708205fSBhawanpreet Lakha } 1383b708205fSBhawanpreet Lakha 1384*9959125aSJake Wang static void mpc3_set_mpc_mem_lp_mode(struct mpc *mpc) 13853e5b4cdfSJacky Liao { 13863e5b4cdfSJacky Liao struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc); 13873e5b4cdfSJacky Liao int mpcc_id; 13883e5b4cdfSJacky Liao 1389cae78e03SJacky Liao if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc) { 13903e5b4cdfSJacky Liao if (mpc30->mpc_mask->MPC_RMU0_MEM_LOW_PWR_MODE && mpc30->mpc_mask->MPC_RMU1_MEM_LOW_PWR_MODE) { 13913e5b4cdfSJacky Liao REG_UPDATE(MPC_RMU_MEM_PWR_CTRL, MPC_RMU0_MEM_LOW_PWR_MODE, 3); 13923e5b4cdfSJacky Liao REG_UPDATE(MPC_RMU_MEM_PWR_CTRL, MPC_RMU1_MEM_LOW_PWR_MODE, 3); 13933e5b4cdfSJacky Liao } 13943e5b4cdfSJacky Liao 13953e5b4cdfSJacky Liao if (mpc30->mpc_mask->MPCC_OGAM_MEM_LOW_PWR_MODE) { 13963e5b4cdfSJacky Liao for (mpcc_id = 0; mpcc_id < mpc30->num_mpcc; mpcc_id++) 13973e5b4cdfSJacky Liao REG_UPDATE(MPCC_MEM_PWR_CTRL[mpcc_id], MPCC_OGAM_MEM_LOW_PWR_MODE, 3); 13983e5b4cdfSJacky Liao } 13993e5b4cdfSJacky Liao } 14003e5b4cdfSJacky Liao } 14013e5b4cdfSJacky Liao 1402b708205fSBhawanpreet Lakha const struct mpc_funcs dcn30_mpc_funcs = { 1403b708205fSBhawanpreet Lakha .read_mpcc_state = mpc1_read_mpcc_state, 1404b708205fSBhawanpreet Lakha .insert_plane = mpc1_insert_plane, 1405b708205fSBhawanpreet Lakha .remove_mpcc = mpc1_remove_mpcc, 1406*9959125aSJake Wang .mpc_init = mpc1_mpc_init, 1407b708205fSBhawanpreet Lakha .mpc_init_single_inst = mpc1_mpc_init_single_inst, 1408b708205fSBhawanpreet Lakha .update_blending = mpc2_update_blending, 1409b708205fSBhawanpreet Lakha .cursor_lock = mpc1_cursor_lock, 1410b708205fSBhawanpreet Lakha .get_mpcc_for_dpp = mpc1_get_mpcc_for_dpp, 1411b708205fSBhawanpreet Lakha .wait_for_idle = mpc2_assert_idle_mpcc, 1412b708205fSBhawanpreet Lakha .assert_mpcc_idle_before_connect = mpc2_assert_mpcc_idle_before_connect, 1413b708205fSBhawanpreet Lakha .init_mpcc_list_from_hw = mpc1_init_mpcc_list_from_hw, 1414b708205fSBhawanpreet Lakha .set_denorm = mpc3_set_denorm, 1415b708205fSBhawanpreet Lakha .set_denorm_clamp = mpc3_set_denorm_clamp, 1416b708205fSBhawanpreet Lakha .set_output_csc = mpc3_set_output_csc, 1417b708205fSBhawanpreet Lakha .set_ocsc_default = mpc3_set_ocsc_default, 1418b708205fSBhawanpreet Lakha .set_output_gamma = mpc3_set_output_gamma, 1419b708205fSBhawanpreet Lakha .insert_plane_to_secondary = NULL, 1420b708205fSBhawanpreet Lakha .remove_mpcc_from_secondary = NULL, 1421b708205fSBhawanpreet Lakha .set_dwb_mux = mpc3_set_dwb_mux, 1422b708205fSBhawanpreet Lakha .disable_dwb_mux = mpc3_disable_dwb_mux, 1423b708205fSBhawanpreet Lakha .is_dwb_idle = mpc3_is_dwb_idle, 1424b708205fSBhawanpreet Lakha .set_out_rate_control = mpc3_set_out_rate_control, 1425b708205fSBhawanpreet Lakha .set_gamut_remap = mpc3_set_gamut_remap, 1426b708205fSBhawanpreet Lakha .program_shaper = mpc3_program_shaper, 1427b708205fSBhawanpreet Lakha .acquire_rmu = mpcc3_acquire_rmu, 1428b708205fSBhawanpreet Lakha .program_3dlut = mpc3_program_3dlut, 1429b708205fSBhawanpreet Lakha .release_rmu = mpcc3_release_rmu, 1430737b2b53SNicholas Kazlauskas .power_on_mpc_mem_pwr = mpc3_power_on_ogam_lut, 1431110b055bSJosip Pavic .get_mpc_out_mux = mpc1_get_mpc_out_mux, 143260df8441SWyatt Wood .set_bg_color = mpc1_set_bg_color, 1433*9959125aSJake Wang .set_mpc_mem_lp_mode = mpc3_set_mpc_mem_lp_mode, 1434b708205fSBhawanpreet Lakha }; 1435b708205fSBhawanpreet Lakha 1436b708205fSBhawanpreet Lakha void dcn30_mpc_construct(struct dcn30_mpc *mpc30, 1437b708205fSBhawanpreet Lakha struct dc_context *ctx, 1438b708205fSBhawanpreet Lakha const struct dcn30_mpc_registers *mpc_regs, 1439b708205fSBhawanpreet Lakha const struct dcn30_mpc_shift *mpc_shift, 1440b708205fSBhawanpreet Lakha const struct dcn30_mpc_mask *mpc_mask, 1441b708205fSBhawanpreet Lakha int num_mpcc, 1442b708205fSBhawanpreet Lakha int num_rmu) 1443b708205fSBhawanpreet Lakha { 1444b708205fSBhawanpreet Lakha int i; 1445b708205fSBhawanpreet Lakha 1446b708205fSBhawanpreet Lakha mpc30->base.ctx = ctx; 1447b708205fSBhawanpreet Lakha 1448b708205fSBhawanpreet Lakha mpc30->base.funcs = &dcn30_mpc_funcs; 1449b708205fSBhawanpreet Lakha 1450b708205fSBhawanpreet Lakha mpc30->mpc_regs = mpc_regs; 1451b708205fSBhawanpreet Lakha mpc30->mpc_shift = mpc_shift; 1452b708205fSBhawanpreet Lakha mpc30->mpc_mask = mpc_mask; 1453b708205fSBhawanpreet Lakha 1454b708205fSBhawanpreet Lakha mpc30->mpcc_in_use_mask = 0; 1455b708205fSBhawanpreet Lakha mpc30->num_mpcc = num_mpcc; 1456b708205fSBhawanpreet Lakha mpc30->num_rmu = num_rmu; 1457b708205fSBhawanpreet Lakha 1458b708205fSBhawanpreet Lakha for (i = 0; i < MAX_MPCC; i++) 1459b708205fSBhawanpreet Lakha mpc3_init_mpcc(&mpc30->base.mpcc_array[i], i); 1460b708205fSBhawanpreet Lakha } 1461b708205fSBhawanpreet Lakha 1462