1 /*
2  * Copyright 2020 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 #include "dce110/dce110_hw_sequencer.h"
27 #include "dcn10/dcn10_hw_sequencer.h"
28 #include "dcn20/dcn20_hwseq.h"
29 #include "dcn21/dcn21_hwseq.h"
30 #include "dcn30_hwseq.h"
31 
32 static const struct hw_sequencer_funcs dcn30_funcs = {
33 	.program_gamut_remap = dcn10_program_gamut_remap,
34 	.init_hw = dcn30_init_hw,
35 	.apply_ctx_to_hw = dce110_apply_ctx_to_hw,
36 	.apply_ctx_for_surface = NULL,
37 	.program_front_end_for_ctx = dcn20_program_front_end_for_ctx,
38 	.disconnect_pipes = dcn10_disconnect_pipes,
39 	.wait_for_pending_cleared = dcn10_wait_for_pending_cleared,
40 	.post_unlock_program_front_end = dcn20_post_unlock_program_front_end,
41 	.update_plane_addr = dcn20_update_plane_addr,
42 	.update_dchub = dcn10_update_dchub,
43 	.update_pending_status = dcn10_update_pending_status,
44 	.program_output_csc = dcn20_program_output_csc,
45 	.enable_accelerated_mode = dce110_enable_accelerated_mode,
46 	.enable_timing_synchronization = dcn10_enable_timing_synchronization,
47 	.enable_per_frame_crtc_position_reset = dcn10_enable_per_frame_crtc_position_reset,
48 	.update_info_frame = dcn30_update_info_frame,
49 	.send_immediate_sdp_message = dcn10_send_immediate_sdp_message,
50 	.enable_stream = dcn20_enable_stream,
51 	.disable_stream = dce110_disable_stream,
52 	.unblank_stream = dcn20_unblank_stream,
53 	.blank_stream = dce110_blank_stream,
54 	.enable_audio_stream = dce110_enable_audio_stream,
55 	.disable_audio_stream = dce110_disable_audio_stream,
56 	.disable_plane = dcn20_disable_plane,
57 	.pipe_control_lock = dcn20_pipe_control_lock,
58 	.interdependent_update_lock = dcn10_lock_all_pipes,
59 	.cursor_lock = dcn10_cursor_lock,
60 	.prepare_bandwidth = dcn20_prepare_bandwidth,
61 	.optimize_bandwidth = dcn20_optimize_bandwidth,
62 	.update_bandwidth = dcn20_update_bandwidth,
63 	.set_drr = dcn10_set_drr,
64 	.get_position = dcn10_get_position,
65 	.set_static_screen_control = dcn10_set_static_screen_control,
66 	.setup_stereo = dcn10_setup_stereo,
67 	.set_avmute = dcn30_set_avmute,
68 	.log_hw_state = dcn10_log_hw_state,
69 	.get_hw_state = dcn10_get_hw_state,
70 	.clear_status_bits = dcn10_clear_status_bits,
71 	.wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect,
72 	.edp_backlight_control = dce110_edp_backlight_control,
73 	.edp_power_control = dce110_edp_power_control,
74 	.edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready,
75 	.set_cursor_position = dcn10_set_cursor_position,
76 	.set_cursor_attribute = dcn10_set_cursor_attribute,
77 	.set_cursor_sdr_white_level = dcn10_set_cursor_sdr_white_level,
78 	.setup_periodic_interrupt = dcn10_setup_periodic_interrupt,
79 	.set_clock = dcn10_set_clock,
80 	.get_clock = dcn10_get_clock,
81 	.program_triplebuffer = dcn20_program_triple_buffer,
82 	.enable_writeback = dcn30_enable_writeback,
83 	.disable_writeback = dcn30_disable_writeback,
84 	.update_writeback = dcn30_update_writeback,
85 	.mmhubbub_warmup = dcn30_mmhubbub_warmup,
86 	.dmdata_status_done = dcn20_dmdata_status_done,
87 	.program_dmdata_engine = dcn30_program_dmdata_engine,
88 	.set_dmdata_attributes = dcn20_set_dmdata_attributes,
89 	.init_sys_ctx = dcn20_init_sys_ctx,
90 	.init_vm_ctx = dcn20_init_vm_ctx,
91 	.set_flip_control_gsl = dcn20_set_flip_control_gsl,
92 	.get_vupdate_offset_from_vsync = dcn10_get_vupdate_offset_from_vsync,
93 	.apply_idle_power_optimizations = dcn30_apply_idle_power_optimizations,
94 	.set_backlight_level = dcn21_set_backlight_level,
95 	.set_abm_immediate_disable = dcn21_set_abm_immediate_disable,
96 };
97 
98 static const struct hwseq_private_funcs dcn30_private_funcs = {
99 	.init_pipes = dcn10_init_pipes,
100 	.update_plane_addr = dcn20_update_plane_addr,
101 	.plane_atomic_disconnect = dcn10_plane_atomic_disconnect,
102 	.update_mpcc = dcn20_update_mpcc,
103 	.set_input_transfer_func = dcn30_set_input_transfer_func,
104 	.set_output_transfer_func = dcn30_set_output_transfer_func,
105 	.power_down = dce110_power_down,
106 	.enable_display_power_gating = dcn10_dummy_display_power_gating,
107 	.blank_pixel_data = dcn20_blank_pixel_data,
108 	.reset_hw_ctx_wrap = dcn20_reset_hw_ctx_wrap,
109 	.enable_stream_timing = dcn20_enable_stream_timing,
110 	.edp_backlight_control = dce110_edp_backlight_control,
111 	.disable_stream_gating = dcn20_disable_stream_gating,
112 	.enable_stream_gating = dcn20_enable_stream_gating,
113 	.setup_vupdate_interrupt = dcn20_setup_vupdate_interrupt,
114 	.did_underflow_occur = dcn10_did_underflow_occur,
115 	.init_blank = dcn20_init_blank,
116 	.disable_vga = dcn20_disable_vga,
117 	.bios_golden_init = dcn10_bios_golden_init,
118 	.plane_atomic_disable = dcn20_plane_atomic_disable,
119 	.plane_atomic_power_down = dcn10_plane_atomic_power_down,
120 	.enable_power_gating_plane = dcn20_enable_power_gating_plane,
121 	.dpp_pg_control = dcn20_dpp_pg_control,
122 	.hubp_pg_control = dcn20_hubp_pg_control,
123 	.program_all_writeback_pipes_in_tree = dcn30_program_all_writeback_pipes_in_tree,
124 	.update_odm = dcn20_update_odm,
125 	.dsc_pg_control = dcn20_dsc_pg_control,
126 	.get_surface_visual_confirm_color = dcn10_get_surface_visual_confirm_color,
127 	.get_hdr_visual_confirm_color = dcn10_get_hdr_visual_confirm_color,
128 	.set_hdr_multiplier = dcn10_set_hdr_multiplier,
129 	.verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high,
130 	.wait_for_blank_complete = dcn20_wait_for_blank_complete,
131 	.dccg_init = dcn20_dccg_init,
132 	.set_blend_lut = dcn30_set_blend_lut,
133 	.set_shaper_3dlut = dcn20_set_shaper_3dlut,
134 };
135 
136 void dcn30_hw_sequencer_construct(struct dc *dc)
137 {
138 	dc->hwss = dcn30_funcs;
139 	dc->hwseq->funcs = dcn30_private_funcs;
140 
141 	if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
142 		dc->hwss.init_hw = dcn20_fpga_init_hw;
143 		dc->hwseq->funcs.init_pipes = NULL;
144 	}
145 }
146