1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 27 #include "dm_services.h" 28 #include "dm_helpers.h" 29 #include "core_types.h" 30 #include "resource.h" 31 #include "dcn30_hwseq.h" 32 #include "dccg.h" 33 #include "dce/dce_hwseq.h" 34 #include "dcn30_mpc.h" 35 #include "dcn30_dpp.h" 36 #include "dcn10/dcn10_cm_common.h" 37 #include "dcn30_cm_common.h" 38 #include "reg_helper.h" 39 #include "abm.h" 40 #include "clk_mgr.h" 41 #include "hubp.h" 42 #include "dchubbub.h" 43 #include "timing_generator.h" 44 #include "opp.h" 45 #include "ipp.h" 46 #include "mpc.h" 47 #include "mcif_wb.h" 48 #include "dc_dmub_srv.h" 49 #include "link_hwss.h" 50 #include "dpcd_defs.h" 51 #include "../dcn20/dcn20_hwseq.h" 52 #include "dcn30_resource.h" 53 #include "link.h" 54 55 56 57 58 #define DC_LOGGER_INIT(logger) 59 60 #define CTX \ 61 hws->ctx 62 #define REG(reg)\ 63 hws->regs->reg 64 #define DC_LOGGER \ 65 dc->ctx->logger 66 67 68 #undef FN 69 #define FN(reg_name, field_name) \ 70 hws->shifts->field_name, hws->masks->field_name 71 72 bool dcn30_set_blend_lut( 73 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state) 74 { 75 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; 76 bool result = true; 77 struct pwl_params *blend_lut = NULL; 78 79 if (plane_state->blend_tf) { 80 if (plane_state->blend_tf->type == TF_TYPE_HWPWL) 81 blend_lut = &plane_state->blend_tf->pwl; 82 else if (plane_state->blend_tf->type == TF_TYPE_DISTRIBUTED_POINTS) { 83 cm3_helper_translate_curve_to_hw_format( 84 plane_state->blend_tf, &dpp_base->regamma_params, false); 85 blend_lut = &dpp_base->regamma_params; 86 } 87 } 88 result = dpp_base->funcs->dpp_program_blnd_lut(dpp_base, blend_lut); 89 90 return result; 91 } 92 93 static bool dcn30_set_mpc_shaper_3dlut(struct pipe_ctx *pipe_ctx, 94 const struct dc_stream_state *stream) 95 { 96 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; 97 int mpcc_id = pipe_ctx->plane_res.hubp->inst; 98 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; 99 bool result = false; 100 int acquired_rmu = 0; 101 int mpcc_id_projected = 0; 102 103 const struct pwl_params *shaper_lut = NULL; 104 //get the shaper lut params 105 if (stream->func_shaper) { 106 if (stream->func_shaper->type == TF_TYPE_HWPWL) { 107 shaper_lut = &stream->func_shaper->pwl; 108 } else if (stream->func_shaper->type == TF_TYPE_DISTRIBUTED_POINTS) { 109 cm_helper_translate_curve_to_hw_format(stream->ctx, stream->func_shaper, 110 &dpp_base->shaper_params, true); 111 shaper_lut = &dpp_base->shaper_params; 112 } 113 } 114 115 if (stream->lut3d_func && 116 stream->lut3d_func->state.bits.initialized == 1 && 117 stream->lut3d_func->state.bits.rmu_idx_valid == 1) { 118 if (stream->lut3d_func->state.bits.rmu_mux_num == 0) 119 mpcc_id_projected = stream->lut3d_func->state.bits.mpc_rmu0_mux; 120 else if (stream->lut3d_func->state.bits.rmu_mux_num == 1) 121 mpcc_id_projected = stream->lut3d_func->state.bits.mpc_rmu1_mux; 122 else if (stream->lut3d_func->state.bits.rmu_mux_num == 2) 123 mpcc_id_projected = stream->lut3d_func->state.bits.mpc_rmu2_mux; 124 if (mpcc_id_projected != mpcc_id) 125 BREAK_TO_DEBUGGER(); 126 /* find the reason why logical layer assigned a different 127 * mpcc_id into acquire_post_bldn_3dlut 128 */ 129 acquired_rmu = mpc->funcs->acquire_rmu(mpc, mpcc_id, 130 stream->lut3d_func->state.bits.rmu_mux_num); 131 if (acquired_rmu != stream->lut3d_func->state.bits.rmu_mux_num) 132 BREAK_TO_DEBUGGER(); 133 134 result = mpc->funcs->program_3dlut(mpc, &stream->lut3d_func->lut_3d, 135 stream->lut3d_func->state.bits.rmu_mux_num); 136 result = mpc->funcs->program_shaper(mpc, shaper_lut, 137 stream->lut3d_func->state.bits.rmu_mux_num); 138 } else { 139 // loop through the available mux and release the requested mpcc_id 140 mpc->funcs->release_rmu(mpc, mpcc_id); 141 } 142 143 return result; 144 } 145 146 bool dcn30_set_input_transfer_func(struct dc *dc, 147 struct pipe_ctx *pipe_ctx, 148 const struct dc_plane_state *plane_state) 149 { 150 struct dce_hwseq *hws = dc->hwseq; 151 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; 152 enum dc_transfer_func_predefined tf; 153 bool result = true; 154 struct pwl_params *params = NULL; 155 156 if (dpp_base == NULL || plane_state == NULL) 157 return false; 158 159 tf = TRANSFER_FUNCTION_UNITY; 160 161 if (plane_state->in_transfer_func && 162 plane_state->in_transfer_func->type == TF_TYPE_PREDEFINED) 163 tf = plane_state->in_transfer_func->tf; 164 165 dpp_base->funcs->dpp_set_pre_degam(dpp_base, tf); 166 167 if (plane_state->in_transfer_func) { 168 if (plane_state->in_transfer_func->type == TF_TYPE_HWPWL) 169 params = &plane_state->in_transfer_func->pwl; 170 else if (plane_state->in_transfer_func->type == TF_TYPE_DISTRIBUTED_POINTS && 171 cm3_helper_translate_curve_to_hw_format(plane_state->in_transfer_func, 172 &dpp_base->degamma_params, false)) 173 params = &dpp_base->degamma_params; 174 } 175 176 result = dpp_base->funcs->dpp_program_gamcor_lut(dpp_base, params); 177 178 if (pipe_ctx->stream_res.opp && pipe_ctx->stream_res.opp->ctx) { 179 if (dpp_base->funcs->dpp_program_blnd_lut) 180 hws->funcs.set_blend_lut(pipe_ctx, plane_state); 181 if (dpp_base->funcs->dpp_program_shaper_lut && 182 dpp_base->funcs->dpp_program_3dlut) 183 hws->funcs.set_shaper_3dlut(pipe_ctx, plane_state); 184 } 185 186 return result; 187 } 188 189 bool dcn30_set_output_transfer_func(struct dc *dc, 190 struct pipe_ctx *pipe_ctx, 191 const struct dc_stream_state *stream) 192 { 193 int mpcc_id = pipe_ctx->plane_res.hubp->inst; 194 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; 195 struct pwl_params *params = NULL; 196 bool ret = false; 197 198 /* program OGAM or 3DLUT only for the top pipe*/ 199 if (pipe_ctx->top_pipe == NULL) { 200 /*program rmu shaper and 3dlut in MPC*/ 201 ret = dcn30_set_mpc_shaper_3dlut(pipe_ctx, stream); 202 if (ret == false && mpc->funcs->set_output_gamma && stream->out_transfer_func) { 203 if (stream->out_transfer_func->type == TF_TYPE_HWPWL) 204 params = &stream->out_transfer_func->pwl; 205 else if (pipe_ctx->stream->out_transfer_func->type == 206 TF_TYPE_DISTRIBUTED_POINTS && 207 cm3_helper_translate_curve_to_hw_format( 208 stream->out_transfer_func, 209 &mpc->blender_params, false)) 210 params = &mpc->blender_params; 211 /* there are no ROM LUTs in OUTGAM */ 212 if (stream->out_transfer_func->type == TF_TYPE_PREDEFINED) 213 BREAK_TO_DEBUGGER(); 214 } 215 } 216 217 mpc->funcs->set_output_gamma(mpc, mpcc_id, params); 218 return ret; 219 } 220 221 static void dcn30_set_writeback( 222 struct dc *dc, 223 struct dc_writeback_info *wb_info, 224 struct dc_state *context) 225 { 226 struct mcif_wb *mcif_wb; 227 struct mcif_buf_params *mcif_buf_params; 228 229 ASSERT(wb_info->dwb_pipe_inst < MAX_DWB_PIPES); 230 ASSERT(wb_info->wb_enabled); 231 ASSERT(wb_info->mpcc_inst >= 0); 232 ASSERT(wb_info->mpcc_inst < dc->res_pool->mpcc_count); 233 mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst]; 234 mcif_buf_params = &wb_info->mcif_buf_params; 235 236 /* set DWB MPC mux */ 237 dc->res_pool->mpc->funcs->set_dwb_mux(dc->res_pool->mpc, 238 wb_info->dwb_pipe_inst, wb_info->mpcc_inst); 239 /* set MCIF_WB buffer and arbitration configuration */ 240 mcif_wb->funcs->config_mcif_buf(mcif_wb, mcif_buf_params, wb_info->dwb_params.dest_height); 241 mcif_wb->funcs->config_mcif_arb(mcif_wb, &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[wb_info->dwb_pipe_inst]); 242 } 243 244 void dcn30_update_writeback( 245 struct dc *dc, 246 struct dc_writeback_info *wb_info, 247 struct dc_state *context) 248 { 249 struct dwbc *dwb; 250 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; 251 DC_LOG_DWB("%s dwb_pipe_inst = %d, mpcc_inst = %d",\ 252 __func__, wb_info->dwb_pipe_inst,\ 253 wb_info->mpcc_inst); 254 255 dcn30_set_writeback(dc, wb_info, context); 256 257 /* update DWB */ 258 dwb->funcs->update(dwb, &wb_info->dwb_params); 259 } 260 261 bool dcn30_mmhubbub_warmup( 262 struct dc *dc, 263 unsigned int num_dwb, 264 struct dc_writeback_info *wb_info) 265 { 266 struct dwbc *dwb; 267 struct mcif_wb *mcif_wb; 268 struct mcif_warmup_params warmup_params = {0}; 269 unsigned int i, i_buf; 270 /*make sure there is no active DWB eanbled */ 271 for (i = 0; i < num_dwb; i++) { 272 dwb = dc->res_pool->dwbc[wb_info[i].dwb_pipe_inst]; 273 if (dwb->dwb_is_efc_transition || dwb->dwb_is_drc) { 274 /*can not do warmup while any dwb enabled*/ 275 return false; 276 } 277 } 278 279 if (wb_info->mcif_warmup_params.p_vmid == 0) 280 return false; 281 282 /*check whether this is new interface: warmup big buffer once*/ 283 if (wb_info->mcif_warmup_params.start_address.quad_part != 0 && 284 wb_info->mcif_warmup_params.region_size != 0) { 285 /*mmhubbub is shared, so it does not matter which MCIF*/ 286 mcif_wb = dc->res_pool->mcif_wb[0]; 287 /*warmup a big chunk of VM buffer at once*/ 288 warmup_params.start_address.quad_part = wb_info->mcif_warmup_params.start_address.quad_part; 289 warmup_params.address_increment = wb_info->mcif_warmup_params.region_size; 290 warmup_params.region_size = wb_info->mcif_warmup_params.region_size; 291 warmup_params.p_vmid = wb_info->mcif_warmup_params.p_vmid; 292 293 if (warmup_params.address_increment == 0) 294 warmup_params.address_increment = dc->dml.soc.vmm_page_size_bytes; 295 296 mcif_wb->funcs->warmup_mcif(mcif_wb, &warmup_params); 297 return true; 298 } 299 /*following is the original: warmup each DWB's mcif buffer*/ 300 for (i = 0; i < num_dwb; i++) { 301 dwb = dc->res_pool->dwbc[wb_info[i].dwb_pipe_inst]; 302 mcif_wb = dc->res_pool->mcif_wb[wb_info[i].dwb_pipe_inst]; 303 /*warmup is for VM mode only*/ 304 if (wb_info[i].mcif_buf_params.p_vmid == 0) 305 return false; 306 307 /* Warmup MCIF_WB */ 308 for (i_buf = 0; i_buf < MCIF_BUF_COUNT; i_buf++) { 309 warmup_params.start_address.quad_part = wb_info[i].mcif_buf_params.luma_address[i_buf]; 310 warmup_params.address_increment = dc->dml.soc.vmm_page_size_bytes; 311 warmup_params.region_size = wb_info[i].mcif_buf_params.luma_pitch * wb_info[i].dwb_params.dest_height; 312 warmup_params.p_vmid = wb_info[i].mcif_buf_params.p_vmid; 313 mcif_wb->funcs->warmup_mcif(mcif_wb, &warmup_params); 314 } 315 } 316 return true; 317 } 318 319 void dcn30_enable_writeback( 320 struct dc *dc, 321 struct dc_writeback_info *wb_info, 322 struct dc_state *context) 323 { 324 struct dwbc *dwb; 325 struct mcif_wb *mcif_wb; 326 327 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; 328 mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst]; 329 330 DC_LOG_DWB("%s dwb_pipe_inst = %d, mpcc_inst = %d",\ 331 __func__, wb_info->dwb_pipe_inst,\ 332 wb_info->mpcc_inst); 333 /* Update writeback pipe */ 334 dcn30_set_writeback(dc, wb_info, context); 335 336 /* Enable MCIF_WB */ 337 mcif_wb->funcs->enable_mcif(mcif_wb); 338 /* Enable DWB */ 339 dwb->funcs->enable(dwb, &wb_info->dwb_params); 340 } 341 342 void dcn30_disable_writeback( 343 struct dc *dc, 344 unsigned int dwb_pipe_inst) 345 { 346 struct dwbc *dwb; 347 struct mcif_wb *mcif_wb; 348 349 ASSERT(dwb_pipe_inst < MAX_DWB_PIPES); 350 dwb = dc->res_pool->dwbc[dwb_pipe_inst]; 351 mcif_wb = dc->res_pool->mcif_wb[dwb_pipe_inst]; 352 DC_LOG_DWB("%s dwb_pipe_inst = %d",\ 353 __func__, dwb_pipe_inst); 354 355 /* disable DWB */ 356 dwb->funcs->disable(dwb); 357 /* disable MCIF */ 358 mcif_wb->funcs->disable_mcif(mcif_wb); 359 /* disable MPC DWB mux */ 360 dc->res_pool->mpc->funcs->disable_dwb_mux(dc->res_pool->mpc, dwb_pipe_inst); 361 } 362 363 void dcn30_program_all_writeback_pipes_in_tree( 364 struct dc *dc, 365 const struct dc_stream_state *stream, 366 struct dc_state *context) 367 { 368 struct dc_writeback_info wb_info; 369 struct dwbc *dwb; 370 struct dc_stream_status *stream_status = NULL; 371 int i_wb, i_pipe, i_stream; 372 DC_LOG_DWB("%s", __func__); 373 374 ASSERT(stream); 375 for (i_stream = 0; i_stream < context->stream_count; i_stream++) { 376 if (context->streams[i_stream] == stream) { 377 stream_status = &context->stream_status[i_stream]; 378 break; 379 } 380 } 381 ASSERT(stream_status); 382 383 ASSERT(stream->num_wb_info <= dc->res_pool->res_cap->num_dwb); 384 /* For each writeback pipe */ 385 for (i_wb = 0; i_wb < stream->num_wb_info; i_wb++) { 386 387 /* copy writeback info to local non-const so mpcc_inst can be set */ 388 wb_info = stream->writeback_info[i_wb]; 389 if (wb_info.wb_enabled) { 390 391 /* get the MPCC instance for writeback_source_plane */ 392 wb_info.mpcc_inst = -1; 393 for (i_pipe = 0; i_pipe < dc->res_pool->pipe_count; i_pipe++) { 394 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i_pipe]; 395 396 if (!pipe_ctx->plane_state) 397 continue; 398 399 if (pipe_ctx->plane_state == wb_info.writeback_source_plane) { 400 wb_info.mpcc_inst = pipe_ctx->plane_res.mpcc_inst; 401 break; 402 } 403 } 404 405 if (wb_info.mpcc_inst == -1) { 406 /* Disable writeback pipe and disconnect from MPCC 407 * if source plane has been removed 408 */ 409 dc->hwss.disable_writeback(dc, wb_info.dwb_pipe_inst); 410 continue; 411 } 412 413 ASSERT(wb_info.dwb_pipe_inst < dc->res_pool->res_cap->num_dwb); 414 dwb = dc->res_pool->dwbc[wb_info.dwb_pipe_inst]; 415 if (dwb->funcs->is_enabled(dwb)) { 416 /* writeback pipe already enabled, only need to update */ 417 dc->hwss.update_writeback(dc, &wb_info, context); 418 } else { 419 /* Enable writeback pipe and connect to MPCC */ 420 dc->hwss.enable_writeback(dc, &wb_info, context); 421 } 422 } else { 423 /* Disable writeback pipe and disconnect from MPCC */ 424 dc->hwss.disable_writeback(dc, wb_info.dwb_pipe_inst); 425 } 426 } 427 } 428 429 void dcn30_init_hw(struct dc *dc) 430 { 431 struct abm **abms = dc->res_pool->multiple_abms; 432 struct dce_hwseq *hws = dc->hwseq; 433 struct dc_bios *dcb = dc->ctx->dc_bios; 434 struct resource_pool *res_pool = dc->res_pool; 435 int i; 436 int edp_num; 437 uint32_t backlight = MAX_BACKLIGHT_LEVEL; 438 439 if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks) 440 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr); 441 442 // Initialize the dccg 443 if (res_pool->dccg->funcs->dccg_init) 444 res_pool->dccg->funcs->dccg_init(res_pool->dccg); 445 446 if (!dcb->funcs->is_accelerated_mode(dcb)) { 447 hws->funcs.bios_golden_init(dc); 448 hws->funcs.disable_vga(dc->hwseq); 449 } 450 451 if (dc->debug.enable_mem_low_power.bits.dmcu) { 452 // Force ERAM to shutdown if DMCU is not enabled 453 if (dc->debug.disable_dmcu || dc->config.disable_dmcu) { 454 REG_UPDATE(DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, 3); 455 } 456 } 457 458 // Set default OPTC memory power states 459 if (dc->debug.enable_mem_low_power.bits.optc) { 460 // Shutdown when unassigned and light sleep in VBLANK 461 REG_SET_2(ODM_MEM_PWR_CTRL3, 0, ODM_MEM_UNASSIGNED_PWR_MODE, 3, ODM_MEM_VBLANK_PWR_MODE, 1); 462 } 463 464 if (dc->debug.enable_mem_low_power.bits.vga) { 465 // Power down VGA memory 466 REG_UPDATE(MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, 1); 467 } 468 469 if (dc->ctx->dc_bios->fw_info_valid) { 470 res_pool->ref_clocks.xtalin_clock_inKhz = 471 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency; 472 473 if (res_pool->dccg && res_pool->hubbub) { 474 475 (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg, 476 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency, 477 &res_pool->ref_clocks.dccg_ref_clock_inKhz); 478 479 (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub, 480 res_pool->ref_clocks.dccg_ref_clock_inKhz, 481 &res_pool->ref_clocks.dchub_ref_clock_inKhz); 482 } else { 483 // Not all ASICs have DCCG sw component 484 res_pool->ref_clocks.dccg_ref_clock_inKhz = 485 res_pool->ref_clocks.xtalin_clock_inKhz; 486 res_pool->ref_clocks.dchub_ref_clock_inKhz = 487 res_pool->ref_clocks.xtalin_clock_inKhz; 488 } 489 } else 490 ASSERT_CRITICAL(false); 491 492 for (i = 0; i < dc->link_count; i++) { 493 /* Power up AND update implementation according to the 494 * required signal (which may be different from the 495 * default signal on connector). 496 */ 497 struct dc_link *link = dc->links[i]; 498 499 link->link_enc->funcs->hw_init(link->link_enc); 500 501 /* Check for enabled DIG to identify enabled display */ 502 if (link->link_enc->funcs->is_dig_enabled && 503 link->link_enc->funcs->is_dig_enabled(link->link_enc)) { 504 link->link_status.link_active = true; 505 if (link->link_enc->funcs->fec_is_active && 506 link->link_enc->funcs->fec_is_active(link->link_enc)) 507 link->fec_state = dc_link_fec_enabled; 508 } 509 } 510 511 /* we want to turn off all dp displays before doing detection */ 512 dc->link_srv->blank_all_dp_displays(dc); 513 514 if (hws->funcs.enable_power_gating_plane) 515 hws->funcs.enable_power_gating_plane(dc->hwseq, true); 516 517 /* If taking control over from VBIOS, we may want to optimize our first 518 * mode set, so we need to skip powering down pipes until we know which 519 * pipes we want to use. 520 * Otherwise, if taking control is not possible, we need to power 521 * everything down. 522 */ 523 if (dcb->funcs->is_accelerated_mode(dcb) || !dc->config.seamless_boot_edp_requested) { 524 hws->funcs.init_pipes(dc, dc->current_state); 525 if (dc->res_pool->hubbub->funcs->allow_self_refresh_control) 526 dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, 527 !dc->res_pool->hubbub->ctx->dc->debug.disable_stutter); 528 } 529 530 /* In headless boot cases, DIG may be turned 531 * on which causes HW/SW discrepancies. 532 * To avoid this, power down hardware on boot 533 * if DIG is turned on and seamless boot not enabled 534 */ 535 if (!dc->config.seamless_boot_edp_requested) { 536 struct dc_link *edp_links[MAX_NUM_EDP]; 537 struct dc_link *edp_link = NULL; 538 539 dc_get_edp_links(dc, edp_links, &edp_num); 540 if (edp_num) 541 edp_link = edp_links[0]; 542 if (edp_link && edp_link->link_enc->funcs->is_dig_enabled && 543 edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc) && 544 dc->hwss.edp_backlight_control && 545 dc->hwss.power_down && 546 dc->hwss.edp_power_control) { 547 dc->hwss.edp_backlight_control(edp_link, false); 548 dc->hwss.power_down(dc); 549 dc->hwss.edp_power_control(edp_link, false); 550 } else { 551 for (i = 0; i < dc->link_count; i++) { 552 struct dc_link *link = dc->links[i]; 553 554 if (link->link_enc->funcs->is_dig_enabled && 555 link->link_enc->funcs->is_dig_enabled(link->link_enc) && 556 dc->hwss.power_down) { 557 dc->hwss.power_down(dc); 558 break; 559 } 560 561 } 562 } 563 } 564 565 for (i = 0; i < res_pool->audio_count; i++) { 566 struct audio *audio = res_pool->audios[i]; 567 568 audio->funcs->hw_init(audio); 569 } 570 571 for (i = 0; i < dc->link_count; i++) { 572 struct dc_link *link = dc->links[i]; 573 574 if (link->panel_cntl) 575 backlight = link->panel_cntl->funcs->hw_init(link->panel_cntl); 576 } 577 578 for (i = 0; i < dc->res_pool->pipe_count; i++) { 579 if (abms[i] != NULL) 580 abms[i]->funcs->abm_init(abms[i], backlight); 581 } 582 583 /* power AFMT HDMI memory TODO: may move to dis/en output save power*/ 584 REG_WRITE(DIO_MEM_PWR_CTRL, 0); 585 586 if (!dc->debug.disable_clock_gate) { 587 /* enable all DCN clock gating */ 588 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); 589 590 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); 591 592 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); 593 } 594 595 if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks) 596 dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub); 597 598 if (dc->clk_mgr->funcs->notify_wm_ranges) 599 dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr); 600 601 //if softmax is enabled then hardmax will be set by a different call 602 if (dc->clk_mgr->funcs->set_hard_max_memclk && !dc->clk_mgr->dc_mode_softmax_enabled) 603 dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr); 604 605 if (dc->res_pool->hubbub->funcs->force_pstate_change_control) 606 dc->res_pool->hubbub->funcs->force_pstate_change_control( 607 dc->res_pool->hubbub, false, false); 608 if (dc->res_pool->hubbub->funcs->init_crb) 609 dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub); 610 611 // Get DMCUB capabilities 612 dc_dmub_srv_query_caps_cmd(dc->ctx->dmub_srv); 613 dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr; 614 dc->caps.dmub_caps.mclk_sw = dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch; 615 } 616 617 void dcn30_set_avmute(struct pipe_ctx *pipe_ctx, bool enable) 618 { 619 if (pipe_ctx == NULL) 620 return; 621 622 if (dc_is_hdmi_signal(pipe_ctx->stream->signal) && pipe_ctx->stream_res.stream_enc != NULL) { 623 pipe_ctx->stream_res.stream_enc->funcs->set_avmute( 624 pipe_ctx->stream_res.stream_enc, 625 enable); 626 627 /* Wait for two frame to make sure AV mute is sent out */ 628 if (enable) { 629 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE); 630 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VBLANK); 631 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE); 632 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VBLANK); 633 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE); 634 } 635 } 636 } 637 638 void dcn30_update_info_frame(struct pipe_ctx *pipe_ctx) 639 { 640 bool is_hdmi_tmds; 641 bool is_dp; 642 643 ASSERT(pipe_ctx->stream); 644 645 if (pipe_ctx->stream_res.stream_enc == NULL) 646 return; /* this is not root pipe */ 647 648 is_hdmi_tmds = dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal); 649 is_dp = dc_is_dp_signal(pipe_ctx->stream->signal); 650 651 if (!is_hdmi_tmds && !is_dp) 652 return; 653 654 if (is_hdmi_tmds) 655 pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets( 656 pipe_ctx->stream_res.stream_enc, 657 &pipe_ctx->stream_res.encoder_info_frame); 658 else { 659 if (pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets_sdp_line_num) 660 pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets_sdp_line_num( 661 pipe_ctx->stream_res.stream_enc, 662 &pipe_ctx->stream_res.encoder_info_frame); 663 664 pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets( 665 pipe_ctx->stream_res.stream_enc, 666 &pipe_ctx->stream_res.encoder_info_frame); 667 } 668 } 669 670 void dcn30_program_dmdata_engine(struct pipe_ctx *pipe_ctx) 671 { 672 struct dc_stream_state *stream = pipe_ctx->stream; 673 struct hubp *hubp = pipe_ctx->plane_res.hubp; 674 bool enable = false; 675 struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc; 676 enum dynamic_metadata_mode mode = dc_is_dp_signal(stream->signal) 677 ? dmdata_dp 678 : dmdata_hdmi; 679 680 /* if using dynamic meta, don't set up generic infopackets */ 681 if (pipe_ctx->stream->dmdata_address.quad_part != 0) { 682 pipe_ctx->stream_res.encoder_info_frame.hdrsmd.valid = false; 683 enable = true; 684 } 685 686 if (!hubp) 687 return; 688 689 if (!stream_enc || !stream_enc->funcs->set_dynamic_metadata) 690 return; 691 692 stream_enc->funcs->set_dynamic_metadata(stream_enc, enable, 693 hubp->inst, mode); 694 } 695 696 bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable) 697 { 698 union dmub_rb_cmd cmd; 699 uint32_t tmr_delay = 0, tmr_scale = 0; 700 struct dc_cursor_attributes cursor_attr; 701 bool cursor_cache_enable = false; 702 struct dc_stream_state *stream = NULL; 703 struct dc_plane_state *plane = NULL; 704 705 if (!dc->ctx->dmub_srv) 706 return false; 707 708 if (enable) { 709 if (dc->current_state) { 710 int i; 711 712 /* First, check no-memory-requests case */ 713 for (i = 0; i < dc->current_state->stream_count; i++) { 714 if (dc->current_state->stream_status[i].plane_count) 715 /* Fail eligibility on a visible stream */ 716 break; 717 } 718 719 if (i == dc->current_state->stream_count) { 720 /* Enable no-memory-requests case */ 721 memset(&cmd, 0, sizeof(cmd)); 722 cmd.mall.header.type = DMUB_CMD__MALL; 723 cmd.mall.header.sub_type = DMUB_CMD__MALL_ACTION_NO_DF_REQ; 724 cmd.mall.header.payload_bytes = sizeof(cmd.mall) - sizeof(cmd.mall.header); 725 726 dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_NO_WAIT); 727 728 return true; 729 } 730 731 stream = dc->current_state->streams[0]; 732 plane = (stream ? dc->current_state->stream_status[0].plane_states[0] : NULL); 733 734 if (stream && plane) { 735 cursor_cache_enable = stream->cursor_position.enable && 736 plane->address.grph.cursor_cache_addr.quad_part; 737 cursor_attr = stream->cursor_attributes; 738 } 739 740 /* 741 * Second, check MALL eligibility 742 * 743 * single display only, single surface only, 8 and 16 bit formats only, no VM, 744 * do not use MALL for displays that support PSR as they use D0i3.2 in DMCUB FW 745 * 746 * TODO: When we implement multi-display, PSR displays will be allowed if there is 747 * a non-PSR display present, since in that case we can't do D0i3.2 748 */ 749 if (dc->current_state->stream_count == 1 && 750 stream->link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED && 751 dc->current_state->stream_status[0].plane_count == 1 && 752 plane->format <= SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F && 753 plane->format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB8888 && 754 plane->address.page_table_base.quad_part == 0 && 755 dc->hwss.does_plane_fit_in_mall && 756 dc->hwss.does_plane_fit_in_mall(dc, plane, 757 cursor_cache_enable ? &cursor_attr : NULL)) { 758 unsigned int v_total = stream->adjust.v_total_max ? 759 stream->adjust.v_total_max : stream->timing.v_total; 760 unsigned int refresh_hz = div_u64((unsigned long long) stream->timing.pix_clk_100hz * 761 100LL, (v_total * stream->timing.h_total)); 762 763 /* 764 * one frame time in microsec: 765 * Delay_Us = 1000000 / refresh 766 * dynamic_delay_us = 1000000 / refresh + 2 * stutter_period 767 * 768 * one frame time modified by 'additional timer percent' (p): 769 * Delay_Us_modified = dynamic_delay_us + dynamic_delay_us * p / 100 770 * = dynamic_delay_us * (1 + p / 100) 771 * = (1000000 / refresh + 2 * stutter_period) * (100 + p) / 100 772 * = (1000000 + 2 * stutter_period * refresh) * (100 + p) / (100 * refresh) 773 * 774 * formula for timer duration based on parameters, from regspec: 775 * dynamic_delay_us = 65.28 * (64 + MallFrameCacheTmrDly) * 2^MallFrameCacheTmrScale 776 * 777 * dynamic_delay_us / 65.28 = (64 + MallFrameCacheTmrDly) * 2^MallFrameCacheTmrScale 778 * (dynamic_delay_us / 65.28) / 2^MallFrameCacheTmrScale = 64 + MallFrameCacheTmrDly 779 * MallFrameCacheTmrDly = ((dynamic_delay_us / 65.28) / 2^MallFrameCacheTmrScale) - 64 780 * = (1000000 + 2 * stutter_period * refresh) * (100 + p) / (100 * refresh) / 65.28 / 2^MallFrameCacheTmrScale - 64 781 * = (1000000 + 2 * stutter_period * refresh) * (100 + p) / (refresh * 6528 * 2^MallFrameCacheTmrScale) - 64 782 * 783 * need to round up the result of the division before the subtraction 784 */ 785 unsigned int denom = refresh_hz * 6528; 786 unsigned int stutter_period = dc->current_state->perf_params.stutter_period_us; 787 788 tmr_delay = div_u64(((1000000LL + 2 * stutter_period * refresh_hz) * 789 (100LL + dc->debug.mall_additional_timer_percent) + denom - 1), 790 denom) - 64LL; 791 792 /* In some cases the stutter period is really big (tiny modes) in these 793 * cases MALL cant be enabled, So skip these cases to avoid a ASSERT() 794 * 795 * We can check if stutter_period is more than 1/10th the frame time to 796 * consider if we can actually meet the range of hysteresis timer 797 */ 798 if (stutter_period > 100000/refresh_hz) 799 return false; 800 801 /* scale should be increased until it fits into 6 bits */ 802 while (tmr_delay & ~0x3F) { 803 tmr_scale++; 804 805 if (tmr_scale > 3) { 806 /* Delay exceeds range of hysteresis timer */ 807 ASSERT(false); 808 return false; 809 } 810 811 denom *= 2; 812 tmr_delay = div_u64(((1000000LL + 2 * stutter_period * refresh_hz) * 813 (100LL + dc->debug.mall_additional_timer_percent) + denom - 1), 814 denom) - 64LL; 815 } 816 817 /* Copy HW cursor */ 818 if (cursor_cache_enable) { 819 memset(&cmd, 0, sizeof(cmd)); 820 cmd.mall.header.type = DMUB_CMD__MALL; 821 cmd.mall.header.sub_type = DMUB_CMD__MALL_ACTION_COPY_CURSOR; 822 cmd.mall.header.payload_bytes = 823 sizeof(cmd.mall) - sizeof(cmd.mall.header); 824 825 switch (cursor_attr.color_format) { 826 case CURSOR_MODE_MONO: 827 cmd.mall.cursor_bpp = 2; 828 break; 829 case CURSOR_MODE_COLOR_1BIT_AND: 830 case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA: 831 case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA: 832 cmd.mall.cursor_bpp = 32; 833 break; 834 835 case CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED: 836 case CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED: 837 cmd.mall.cursor_bpp = 64; 838 break; 839 } 840 841 cmd.mall.cursor_copy_src.quad_part = cursor_attr.address.quad_part; 842 cmd.mall.cursor_copy_dst.quad_part = 843 (plane->address.grph.cursor_cache_addr.quad_part + 2047) & ~2047; 844 cmd.mall.cursor_width = cursor_attr.width; 845 cmd.mall.cursor_height = cursor_attr.height; 846 cmd.mall.cursor_pitch = cursor_attr.pitch; 847 848 dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT); 849 850 /* Use copied cursor, and it's okay to not switch back */ 851 cursor_attr.address.quad_part = cmd.mall.cursor_copy_dst.quad_part; 852 dc_stream_set_cursor_attributes(stream, &cursor_attr); 853 } 854 855 /* Enable MALL */ 856 memset(&cmd, 0, sizeof(cmd)); 857 cmd.mall.header.type = DMUB_CMD__MALL; 858 cmd.mall.header.sub_type = DMUB_CMD__MALL_ACTION_ALLOW; 859 cmd.mall.header.payload_bytes = sizeof(cmd.mall) - sizeof(cmd.mall.header); 860 cmd.mall.tmr_delay = tmr_delay; 861 cmd.mall.tmr_scale = tmr_scale; 862 cmd.mall.debug_bits = dc->debug.mall_error_as_fatal; 863 864 dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_NO_WAIT); 865 866 return true; 867 } 868 } 869 870 /* No applicable optimizations */ 871 return false; 872 } 873 874 /* Disable MALL */ 875 memset(&cmd, 0, sizeof(cmd)); 876 cmd.mall.header.type = DMUB_CMD__MALL; 877 cmd.mall.header.sub_type = DMUB_CMD__MALL_ACTION_DISALLOW; 878 cmd.mall.header.payload_bytes = 879 sizeof(cmd.mall) - sizeof(cmd.mall.header); 880 881 dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT); 882 883 return true; 884 } 885 886 bool dcn30_does_plane_fit_in_mall(struct dc *dc, struct dc_plane_state *plane, struct dc_cursor_attributes *cursor_attr) 887 { 888 // add meta size? 889 unsigned int surface_size = plane->plane_size.surface_pitch * plane->plane_size.surface_size.height * 890 (plane->format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616 ? 8 : 4); 891 unsigned int mall_size = dc->caps.mall_size_total; 892 unsigned int cursor_size = 0; 893 894 if (dc->debug.mall_size_override) 895 mall_size = 1024 * 1024 * dc->debug.mall_size_override; 896 897 if (cursor_attr) { 898 cursor_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size; 899 900 switch (cursor_attr->color_format) { 901 case CURSOR_MODE_MONO: 902 cursor_size /= 2; 903 break; 904 case CURSOR_MODE_COLOR_1BIT_AND: 905 case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA: 906 case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA: 907 cursor_size *= 4; 908 break; 909 910 case CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED: 911 case CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED: 912 cursor_size *= 8; 913 break; 914 } 915 } 916 917 return (surface_size + cursor_size) < mall_size; 918 } 919 920 void dcn30_hardware_release(struct dc *dc) 921 { 922 bool subvp_in_use = false; 923 uint32_t i; 924 925 dc_dmub_srv_p_state_delegate(dc, false, NULL); 926 dc_dmub_setup_subvp_dmub_command(dc, dc->current_state, false); 927 928 /* SubVP treated the same way as FPO. If driver disable and 929 * we are using a SubVP config, disable and force on DCN side 930 * to prevent P-State hang on driver enable. 931 */ 932 for (i = 0; i < dc->res_pool->pipe_count; i++) { 933 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i]; 934 935 if (!pipe->stream) 936 continue; 937 938 if (pipe->stream->mall_stream_config.type == SUBVP_MAIN) { 939 subvp_in_use = true; 940 break; 941 } 942 } 943 /* If pstate unsupported, or still supported 944 * by firmware, force it supported by dcn 945 */ 946 if (dc->current_state) 947 if ((!dc->clk_mgr->clks.p_state_change_support || subvp_in_use || 948 dc->current_state->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) && 949 dc->res_pool->hubbub->funcs->force_pstate_change_control) 950 dc->res_pool->hubbub->funcs->force_pstate_change_control( 951 dc->res_pool->hubbub, true, true); 952 } 953 954 void dcn30_set_disp_pattern_generator(const struct dc *dc, 955 struct pipe_ctx *pipe_ctx, 956 enum controller_dp_test_pattern test_pattern, 957 enum controller_dp_color_space color_space, 958 enum dc_color_depth color_depth, 959 const struct tg_color *solid_color, 960 int width, int height, int offset) 961 { 962 pipe_ctx->stream_res.opp->funcs->opp_set_disp_pattern_generator(pipe_ctx->stream_res.opp, test_pattern, 963 color_space, color_depth, solid_color, width, height, offset); 964 } 965 966 void dcn30_prepare_bandwidth(struct dc *dc, 967 struct dc_state *context) 968 { 969 bool p_state_change_support = context->bw_ctx.bw.dcn.clk.p_state_change_support; 970 /* Any transition into an FPO config should disable MCLK switching first to avoid 971 * driver and FW P-State synchronization issues. 972 */ 973 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching || dc->clk_mgr->clks.fw_based_mclk_switching) { 974 dc->optimized_required = true; 975 context->bw_ctx.bw.dcn.clk.p_state_change_support = false; 976 } 977 978 if (dc->clk_mgr->dc_mode_softmax_enabled) 979 if (dc->clk_mgr->clks.dramclk_khz <= dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000 && 980 context->bw_ctx.bw.dcn.clk.dramclk_khz > dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000) 981 dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, dc->clk_mgr->bw_params->clk_table.entries[dc->clk_mgr->bw_params->clk_table.num_entries - 1].memclk_mhz); 982 983 dcn20_prepare_bandwidth(dc, context); 984 /* 985 * enabled -> enabled: do not disable 986 * enabled -> disabled: disable 987 * disabled -> enabled: don't care 988 * disabled -> disabled: don't care 989 */ 990 if (!context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) 991 dc_dmub_srv_p_state_delegate(dc, false, context); 992 993 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching || dc->clk_mgr->clks.fw_based_mclk_switching) { 994 /* After disabling P-State, restore the original value to ensure we get the correct P-State 995 * on the next optimize. */ 996 context->bw_ctx.bw.dcn.clk.p_state_change_support = p_state_change_support; 997 } 998 } 999 1000 void dcn30_set_static_screen_control(struct pipe_ctx **pipe_ctx, 1001 int num_pipes, const struct dc_static_screen_params *params) 1002 { 1003 unsigned int i; 1004 unsigned int triggers = 0; 1005 1006 if (params->triggers.surface_update) 1007 triggers |= 0x100; 1008 if (params->triggers.cursor_update) 1009 triggers |= 0x8; 1010 if (params->triggers.force_trigger) 1011 triggers |= 0x1; 1012 1013 for (i = 0; i < num_pipes; i++) 1014 pipe_ctx[i]->stream_res.tg->funcs->set_static_screen_control(pipe_ctx[i]->stream_res.tg, 1015 triggers, params->num_frames); 1016 } 1017