1 /*
2  * Copyright 2020 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 
27 #include "dm_services.h"
28 #include "dm_helpers.h"
29 #include "core_types.h"
30 #include "resource.h"
31 #include "dcn30_hwseq.h"
32 #include "dccg.h"
33 #include "dce/dce_hwseq.h"
34 #include "dcn30_mpc.h"
35 #include "dcn30_dpp.h"
36 #include "dcn10/dcn10_cm_common.h"
37 #include "dcn30_cm_common.h"
38 #include "reg_helper.h"
39 #include "abm.h"
40 #include "clk_mgr.h"
41 #include "hubp.h"
42 #include "dchubbub.h"
43 #include "timing_generator.h"
44 #include "opp.h"
45 #include "ipp.h"
46 #include "mpc.h"
47 #include "mcif_wb.h"
48 #include "dc_dmub_srv.h"
49 #include "link_hwss.h"
50 #include "dpcd_defs.h"
51 
52 
53 
54 
55 #define DC_LOGGER_INIT(logger)
56 
57 #define CTX \
58 	hws->ctx
59 #define REG(reg)\
60 	hws->regs->reg
61 #define DC_LOGGER \
62 		dc->ctx->logger
63 
64 
65 #undef FN
66 #define FN(reg_name, field_name) \
67 	hws->shifts->field_name, hws->masks->field_name
68 
69 bool dcn30_set_blend_lut(
70 	struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state)
71 {
72 	struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
73 	bool result = true;
74 	struct pwl_params *blend_lut = NULL;
75 
76 	if (plane_state->blend_tf) {
77 		if (plane_state->blend_tf->type == TF_TYPE_HWPWL)
78 			blend_lut = &plane_state->blend_tf->pwl;
79 		else if (plane_state->blend_tf->type == TF_TYPE_DISTRIBUTED_POINTS) {
80 			cm3_helper_translate_curve_to_hw_format(
81 					plane_state->blend_tf, &dpp_base->regamma_params, false);
82 			blend_lut = &dpp_base->regamma_params;
83 		}
84 	}
85 	result = dpp_base->funcs->dpp_program_blnd_lut(dpp_base, blend_lut);
86 
87 	return result;
88 }
89 
90 static bool dcn30_set_mpc_shaper_3dlut(
91 	struct pipe_ctx *pipe_ctx, const struct dc_stream_state *stream)
92 {
93 	struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
94 	int mpcc_id = pipe_ctx->plane_res.hubp->inst;
95 	struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
96 	bool result = false;
97 	int acquired_rmu = 0;
98 	int mpcc_id_projected = 0;
99 
100 	const struct pwl_params *shaper_lut = NULL;
101 	//get the shaper lut params
102 	if (stream->func_shaper) {
103 		if (stream->func_shaper->type == TF_TYPE_HWPWL)
104 			shaper_lut = &stream->func_shaper->pwl;
105 		else if (stream->func_shaper->type == TF_TYPE_DISTRIBUTED_POINTS) {
106 			cm_helper_translate_curve_to_hw_format(
107 					stream->func_shaper,
108 					&dpp_base->shaper_params, true);
109 			shaper_lut = &dpp_base->shaper_params;
110 		}
111 	}
112 
113 	if (stream->lut3d_func &&
114 		stream->lut3d_func->state.bits.initialized == 1 &&
115 		stream->lut3d_func->state.bits.rmu_idx_valid == 1) {
116 		if (stream->lut3d_func->state.bits.rmu_mux_num == 0)
117 			mpcc_id_projected = stream->lut3d_func->state.bits.mpc_rmu0_mux;
118 		else if (stream->lut3d_func->state.bits.rmu_mux_num == 1)
119 			mpcc_id_projected = stream->lut3d_func->state.bits.mpc_rmu1_mux;
120 		else if (stream->lut3d_func->state.bits.rmu_mux_num == 2)
121 			mpcc_id_projected = stream->lut3d_func->state.bits.mpc_rmu2_mux;
122 		if (mpcc_id_projected != mpcc_id)
123 			BREAK_TO_DEBUGGER();
124 		/*find the reason why logical layer assigned a differant mpcc_id into acquire_post_bldn_3dlut*/
125 		acquired_rmu = mpc->funcs->acquire_rmu(mpc, mpcc_id,
126 				stream->lut3d_func->state.bits.rmu_mux_num);
127 		if (acquired_rmu != stream->lut3d_func->state.bits.rmu_mux_num)
128 			BREAK_TO_DEBUGGER();
129 		result = mpc->funcs->program_3dlut(mpc,
130 								&stream->lut3d_func->lut_3d,
131 								stream->lut3d_func->state.bits.rmu_mux_num);
132 		result = mpc->funcs->program_shaper(mpc, shaper_lut,
133 				stream->lut3d_func->state.bits.rmu_mux_num);
134 	} else
135 		/*loop through the available mux and release the requested mpcc_id*/
136 		mpc->funcs->release_rmu(mpc, mpcc_id);
137 
138 
139 	return result;
140 }
141 
142 bool dcn30_set_input_transfer_func(struct dc *dc,
143 				struct pipe_ctx *pipe_ctx,
144 				const struct dc_plane_state *plane_state)
145 {
146 	struct dce_hwseq *hws = dc->hwseq;
147 	struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
148 	enum dc_transfer_func_predefined tf;
149 	bool result = true;
150 	struct pwl_params *params = NULL;
151 
152 	if (dpp_base == NULL || plane_state == NULL)
153 		return false;
154 
155 	tf = TRANSFER_FUNCTION_UNITY;
156 
157 	if (plane_state->in_transfer_func &&
158 		plane_state->in_transfer_func->type == TF_TYPE_PREDEFINED)
159 		tf = plane_state->in_transfer_func->tf;
160 
161 	dpp_base->funcs->dpp_set_pre_degam(dpp_base, tf);
162 
163 	if (plane_state->in_transfer_func) {
164 		if (plane_state->in_transfer_func->type == TF_TYPE_HWPWL)
165 			params = &plane_state->in_transfer_func->pwl;
166 		else if (plane_state->in_transfer_func->type == TF_TYPE_DISTRIBUTED_POINTS &&
167 			cm3_helper_translate_curve_to_hw_format(plane_state->in_transfer_func,
168 					&dpp_base->degamma_params, false))
169 			params = &dpp_base->degamma_params;
170 	}
171 
172 	result = dpp_base->funcs->dpp_program_gamcor_lut(dpp_base, params);
173 
174 	if (pipe_ctx->stream_res.opp && pipe_ctx->stream_res.opp->ctx) {
175 		if (dpp_base->funcs->dpp_program_blnd_lut)
176 			hws->funcs.set_blend_lut(pipe_ctx, plane_state);
177 		if (dpp_base->funcs->dpp_program_shaper_lut &&
178 				dpp_base->funcs->dpp_program_3dlut)
179 			hws->funcs.set_shaper_3dlut(pipe_ctx, plane_state);
180 	}
181 
182 	return result;
183 }
184 
185 bool dcn30_set_output_transfer_func(struct dc *dc,
186 				struct pipe_ctx *pipe_ctx,
187 				const struct dc_stream_state *stream)
188 {
189 	int mpcc_id = pipe_ctx->plane_res.hubp->inst;
190 	struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
191 	struct pwl_params *params = NULL;
192 	bool ret = false;
193 
194 	/* program OGAM or 3DLUT only for the top pipe*/
195 	if (pipe_ctx->top_pipe == NULL) {
196 		/*program rmu shaper and 3dlut in MPC*/
197 		ret = dcn30_set_mpc_shaper_3dlut(pipe_ctx, stream);
198 		if (ret == false && mpc->funcs->set_output_gamma && stream->out_transfer_func) {
199 			if (stream->out_transfer_func->type == TF_TYPE_HWPWL)
200 				params = &stream->out_transfer_func->pwl;
201 			else if (pipe_ctx->stream->out_transfer_func->type ==
202 					TF_TYPE_DISTRIBUTED_POINTS &&
203 					cm3_helper_translate_curve_to_hw_format(
204 					stream->out_transfer_func,
205 					&mpc->blender_params, false))
206 				params = &mpc->blender_params;
207 			 /* there are no ROM LUTs in OUTGAM */
208 			if (stream->out_transfer_func->type == TF_TYPE_PREDEFINED)
209 				BREAK_TO_DEBUGGER();
210 		}
211 	}
212 
213 	mpc->funcs->set_output_gamma(mpc, mpcc_id, params);
214 	return ret;
215 }
216 
217 static void dcn30_set_writeback(
218 		struct dc *dc,
219 		struct dc_writeback_info *wb_info,
220 		struct dc_state *context)
221 {
222 	struct mcif_wb *mcif_wb;
223 	struct mcif_buf_params *mcif_buf_params;
224 
225 	ASSERT(wb_info->dwb_pipe_inst < MAX_DWB_PIPES);
226 	ASSERT(wb_info->wb_enabled);
227 	ASSERT(wb_info->mpcc_inst >= 0);
228 	ASSERT(wb_info->mpcc_inst < dc->res_pool->mpcc_count);
229 	mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst];
230 	mcif_buf_params = &wb_info->mcif_buf_params;
231 
232 	/* set DWB MPC mux */
233 	dc->res_pool->mpc->funcs->set_dwb_mux(dc->res_pool->mpc,
234 			wb_info->dwb_pipe_inst, wb_info->mpcc_inst);
235 	/* set MCIF_WB buffer and arbitration configuration */
236 	mcif_wb->funcs->config_mcif_buf(mcif_wb, mcif_buf_params, wb_info->dwb_params.dest_height);
237 	mcif_wb->funcs->config_mcif_arb(mcif_wb, &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[wb_info->dwb_pipe_inst]);
238 }
239 
240 void dcn30_update_writeback(
241 		struct dc *dc,
242 		struct dc_writeback_info *wb_info,
243 		struct dc_state *context)
244 {
245 	struct dwbc *dwb;
246 	dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
247 	DC_LOG_DWB("%s dwb_pipe_inst = %d, mpcc_inst = %d",\
248 		__func__, wb_info->dwb_pipe_inst,\
249 		wb_info->mpcc_inst);
250 
251 	dcn30_set_writeback(dc, wb_info, context);
252 
253 	/* update DWB */
254 	dwb->funcs->update(dwb, &wb_info->dwb_params);
255 }
256 
257 bool dcn30_mmhubbub_warmup(
258 	struct dc *dc,
259 	unsigned int num_dwb,
260 	struct dc_writeback_info *wb_info)
261 {
262 	struct dwbc *dwb;
263 	struct mcif_wb *mcif_wb;
264 	struct mcif_warmup_params warmup_params = {0};
265 	unsigned int  i, i_buf;
266 	/*make sure there is no active DWB eanbled */
267 	for (i = 0; i < num_dwb; i++) {
268 		dwb = dc->res_pool->dwbc[wb_info[i].dwb_pipe_inst];
269 		if (dwb->dwb_is_efc_transition || dwb->dwb_is_drc) {
270 			/*can not do warmup while any dwb enabled*/
271 			return false;
272 		}
273 	}
274 
275 	if (wb_info->mcif_warmup_params.p_vmid == 0)
276 		return false;
277 
278 	/*check whether this is new interface: warmup big buffer once*/
279 	if (wb_info->mcif_warmup_params.start_address.quad_part != 0 &&
280 		wb_info->mcif_warmup_params.region_size != 0) {
281 		/*mmhubbub is shared, so it does not matter which MCIF*/
282 		mcif_wb = dc->res_pool->mcif_wb[0];
283 		/*warmup a big chunk of VM buffer at once*/
284 		warmup_params.start_address.quad_part = wb_info->mcif_warmup_params.start_address.quad_part;
285 		warmup_params.address_increment =  wb_info->mcif_warmup_params.region_size;
286 		warmup_params.region_size = wb_info->mcif_warmup_params.region_size;
287 		warmup_params.p_vmid = wb_info->mcif_warmup_params.p_vmid;
288 
289 		if (warmup_params.address_increment == 0)
290 			warmup_params.address_increment = dc->dml.soc.vmm_page_size_bytes;
291 
292 		mcif_wb->funcs->warmup_mcif(mcif_wb, &warmup_params);
293 		return true;
294 	}
295 	/*following is the original: warmup each DWB's mcif buffer*/
296 	for (i = 0; i < num_dwb; i++) {
297 		dwb = dc->res_pool->dwbc[wb_info[i].dwb_pipe_inst];
298 		mcif_wb = dc->res_pool->mcif_wb[wb_info[i].dwb_pipe_inst];
299 		/*warmup is for VM mode only*/
300 		if (wb_info[i].mcif_buf_params.p_vmid == 0)
301 			return false;
302 
303 		/* Warmup MCIF_WB */
304 		for (i_buf = 0; i_buf < MCIF_BUF_COUNT; i_buf++) {
305 			warmup_params.start_address.quad_part = wb_info[i].mcif_buf_params.luma_address[i_buf];
306 			warmup_params.address_increment = dc->dml.soc.vmm_page_size_bytes;
307 			warmup_params.region_size = wb_info[i].mcif_buf_params.luma_pitch * wb_info[i].dwb_params.dest_height;
308 			warmup_params.p_vmid = wb_info[i].mcif_buf_params.p_vmid;
309 			mcif_wb->funcs->warmup_mcif(mcif_wb, &warmup_params);
310 		}
311 	}
312 	return true;
313 }
314 
315 void dcn30_enable_writeback(
316 		struct dc *dc,
317 		struct dc_writeback_info *wb_info,
318 		struct dc_state *context)
319 {
320 	struct dwbc *dwb;
321 	struct mcif_wb *mcif_wb;
322 	struct timing_generator *optc;
323 
324 	dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
325 	mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst];
326 
327 	/* set the OPTC source mux */
328 	optc = dc->res_pool->timing_generators[dwb->otg_inst];
329 	DC_LOG_DWB("%s dwb_pipe_inst = %d, mpcc_inst = %d",\
330 		__func__, wb_info->dwb_pipe_inst,\
331 		wb_info->mpcc_inst);
332 	if (IS_DIAG_DC(dc->ctx->dce_environment)) {
333 		/*till diags switch to warmup interface*/
334 		dcn30_mmhubbub_warmup(dc, 1, wb_info);
335 	}
336 	/* Update writeback pipe */
337 	dcn30_set_writeback(dc, wb_info, context);
338 
339 	/* Enable MCIF_WB */
340 	mcif_wb->funcs->enable_mcif(mcif_wb);
341 	/* Enable DWB */
342 	dwb->funcs->enable(dwb, &wb_info->dwb_params);
343 }
344 
345 void dcn30_disable_writeback(
346 		struct dc *dc,
347 		unsigned int dwb_pipe_inst)
348 {
349 	struct dwbc *dwb;
350 	struct mcif_wb *mcif_wb;
351 
352 	ASSERT(dwb_pipe_inst < MAX_DWB_PIPES);
353 	dwb = dc->res_pool->dwbc[dwb_pipe_inst];
354 	mcif_wb = dc->res_pool->mcif_wb[dwb_pipe_inst];
355 	DC_LOG_DWB("%s dwb_pipe_inst = %d",\
356 		__func__, dwb_pipe_inst);
357 
358 	/* disable DWB */
359 	dwb->funcs->disable(dwb);
360 	/* disable MCIF */
361 	mcif_wb->funcs->disable_mcif(mcif_wb);
362 	/* disable MPC DWB mux */
363 	dc->res_pool->mpc->funcs->disable_dwb_mux(dc->res_pool->mpc, dwb_pipe_inst);
364 }
365 
366 void dcn30_program_all_writeback_pipes_in_tree(
367 		struct dc *dc,
368 		const struct dc_stream_state *stream,
369 		struct dc_state *context)
370 {
371 	struct dc_writeback_info wb_info;
372 	struct dwbc *dwb;
373 	struct dc_stream_status *stream_status = NULL;
374 	int i_wb, i_pipe, i_stream;
375 	DC_LOG_DWB("%s", __func__);
376 
377 	ASSERT(stream);
378 	for (i_stream = 0; i_stream < context->stream_count; i_stream++) {
379 		if (context->streams[i_stream] == stream) {
380 			stream_status = &context->stream_status[i_stream];
381 			break;
382 		}
383 	}
384 	ASSERT(stream_status);
385 
386 	ASSERT(stream->num_wb_info <= dc->res_pool->res_cap->num_dwb);
387 	/* For each writeback pipe */
388 	for (i_wb = 0; i_wb < stream->num_wb_info; i_wb++) {
389 
390 		/* copy writeback info to local non-const so mpcc_inst can be set */
391 		wb_info = stream->writeback_info[i_wb];
392 		if (wb_info.wb_enabled) {
393 
394 			/* get the MPCC instance for writeback_source_plane */
395 			wb_info.mpcc_inst = -1;
396 			for (i_pipe = 0; i_pipe < dc->res_pool->pipe_count; i_pipe++) {
397 				struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i_pipe];
398 
399 				if (pipe_ctx->plane_state == wb_info.writeback_source_plane) {
400 					wb_info.mpcc_inst = pipe_ctx->plane_res.mpcc_inst;
401 					break;
402 				}
403 			}
404 			ASSERT(wb_info.mpcc_inst != -1);
405 
406 			ASSERT(wb_info.dwb_pipe_inst < dc->res_pool->res_cap->num_dwb);
407 			dwb = dc->res_pool->dwbc[wb_info.dwb_pipe_inst];
408 			if (dwb->funcs->is_enabled(dwb)) {
409 				/* writeback pipe already enabled, only need to update */
410 				dc->hwss.update_writeback(dc, &wb_info, context);
411 			} else {
412 				/* Enable writeback pipe and connect to MPCC */
413 				dc->hwss.enable_writeback(dc, &wb_info, context);
414 			}
415 		} else {
416 			/* Disable writeback pipe and disconnect from MPCC */
417 			dc->hwss.disable_writeback(dc, wb_info.dwb_pipe_inst);
418 		}
419 	}
420 }
421 
422 void dcn30_init_hw(struct dc *dc)
423 {
424 	int i, j;
425 	struct abm **abms = dc->res_pool->multiple_abms;
426 	struct dce_hwseq *hws = dc->hwseq;
427 	struct dc_bios *dcb = dc->ctx->dc_bios;
428 	struct resource_pool *res_pool = dc->res_pool;
429 	uint32_t backlight = MAX_BACKLIGHT_LEVEL;
430 
431 	if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)
432 		dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);
433 
434 	// Initialize the dccg
435 	if (res_pool->dccg->funcs->dccg_init)
436 		res_pool->dccg->funcs->dccg_init(res_pool->dccg);
437 
438 	if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
439 
440 		REG_WRITE(REFCLK_CNTL, 0);
441 		REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1);
442 		REG_WRITE(DIO_MEM_PWR_CTRL, 0);
443 
444 		if (!dc->debug.disable_clock_gate) {
445 			/* enable all DCN clock gating */
446 			REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
447 
448 			REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
449 
450 			REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
451 		}
452 
453 		//Enable ability to power gate / don't force power on permanently
454 		if (hws->funcs.enable_power_gating_plane)
455 			hws->funcs.enable_power_gating_plane(hws, true);
456 
457 		return;
458 	}
459 
460 	if (!dcb->funcs->is_accelerated_mode(dcb)) {
461 		hws->funcs.bios_golden_init(dc);
462 		hws->funcs.disable_vga(dc->hwseq);
463 	}
464 
465 	if (dc->ctx->dc_bios->fw_info_valid) {
466 		res_pool->ref_clocks.xtalin_clock_inKhz =
467 				dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
468 
469 		if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
470 			if (res_pool->dccg && res_pool->hubbub) {
471 
472 				(res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,
473 						dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,
474 						&res_pool->ref_clocks.dccg_ref_clock_inKhz);
475 
476 				(res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub,
477 						res_pool->ref_clocks.dccg_ref_clock_inKhz,
478 						&res_pool->ref_clocks.dchub_ref_clock_inKhz);
479 			} else {
480 				// Not all ASICs have DCCG sw component
481 				res_pool->ref_clocks.dccg_ref_clock_inKhz =
482 						res_pool->ref_clocks.xtalin_clock_inKhz;
483 				res_pool->ref_clocks.dchub_ref_clock_inKhz =
484 						res_pool->ref_clocks.xtalin_clock_inKhz;
485 			}
486 		}
487 	} else
488 		ASSERT_CRITICAL(false);
489 
490 	for (i = 0; i < dc->link_count; i++) {
491 		/* Power up AND update implementation according to the
492 		 * required signal (which may be different from the
493 		 * default signal on connector).
494 		 */
495 		struct dc_link *link = dc->links[i];
496 
497 		link->link_enc->funcs->hw_init(link->link_enc);
498 
499 		/* Check for enabled DIG to identify enabled display */
500 		if (link->link_enc->funcs->is_dig_enabled &&
501 			link->link_enc->funcs->is_dig_enabled(link->link_enc))
502 			link->link_status.link_active = true;
503 	}
504 
505 	/* Power gate DSCs */
506 	for (i = 0; i < res_pool->res_cap->num_dsc; i++)
507 		if (hws->funcs.dsc_pg_control != NULL)
508 			hws->funcs.dsc_pg_control(hws, res_pool->dscs[i]->inst, false);
509 
510 	/* we want to turn off all dp displays before doing detection */
511 	if (dc->config.power_down_display_on_boot) {
512 		uint8_t dpcd_power_state = '\0';
513 		enum dc_status status = DC_ERROR_UNEXPECTED;
514 
515 		for (i = 0; i < dc->link_count; i++) {
516 			if (dc->links[i]->connector_signal != SIGNAL_TYPE_DISPLAY_PORT)
517 				continue;
518 
519 			/* if any of the displays are lit up turn them off */
520 			status = core_link_read_dpcd(dc->links[i], DP_SET_POWER,
521 						     &dpcd_power_state, sizeof(dpcd_power_state));
522 			if (status == DC_OK && dpcd_power_state == DP_POWER_STATE_D0) {
523 				/* blank dp stream before power off receiver*/
524 				if (dc->links[i]->link_enc->funcs->get_dig_frontend) {
525 					unsigned int fe;
526 
527 					fe = dc->links[i]->link_enc->funcs->get_dig_frontend(
528 										dc->links[i]->link_enc);
529 
530 					for (j = 0; j < dc->res_pool->stream_enc_count; j++) {
531 						if (fe == dc->res_pool->stream_enc[j]->id) {
532 							dc->res_pool->stream_enc[j]->funcs->dp_blank(
533 										dc->res_pool->stream_enc[j]);
534 							break;
535 						}
536 					}
537 				}
538 				dp_receiver_power_ctrl(dc->links[i], false);
539 			}
540 		}
541 	}
542 
543 	/* If taking control over from VBIOS, we may want to optimize our first
544 	 * mode set, so we need to skip powering down pipes until we know which
545 	 * pipes we want to use.
546 	 * Otherwise, if taking control is not possible, we need to power
547 	 * everything down.
548 	 */
549 	if (dcb->funcs->is_accelerated_mode(dcb) || dc->config.power_down_display_on_boot) {
550 		hws->funcs.init_pipes(dc, dc->current_state);
551 		if (dc->res_pool->hubbub->funcs->allow_self_refresh_control)
552 			dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub,
553 					!dc->res_pool->hubbub->ctx->dc->debug.disable_stutter);
554 	}
555 
556 	/* In headless boot cases, DIG may be turned
557 	 * on which causes HW/SW discrepancies.
558 	 * To avoid this, power down hardware on boot
559 	 * if DIG is turned on and seamless boot not enabled
560 	 */
561 	if (dc->config.power_down_display_on_boot) {
562 		struct dc_link *edp_link = get_edp_link(dc);
563 
564 		if (edp_link &&
565 				edp_link->link_enc->funcs->is_dig_enabled &&
566 				edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc) &&
567 				dc->hwss.edp_backlight_control &&
568 				dc->hwss.power_down &&
569 				dc->hwss.edp_power_control) {
570 			dc->hwss.edp_backlight_control(edp_link, false);
571 			dc->hwss.power_down(dc);
572 			dc->hwss.edp_power_control(edp_link, false);
573 		} else {
574 			for (i = 0; i < dc->link_count; i++) {
575 				struct dc_link *link = dc->links[i];
576 
577 				if (link->link_enc->funcs->is_dig_enabled &&
578 						link->link_enc->funcs->is_dig_enabled(link->link_enc) &&
579 						dc->hwss.power_down) {
580 					dc->hwss.power_down(dc);
581 					break;
582 				}
583 
584 			}
585 		}
586 	}
587 
588 	for (i = 0; i < res_pool->audio_count; i++) {
589 		struct audio *audio = res_pool->audios[i];
590 
591 		audio->funcs->hw_init(audio);
592 	}
593 
594 	for (i = 0; i < dc->link_count; i++) {
595 		struct dc_link *link = dc->links[i];
596 
597 		if (link->panel_cntl)
598 			backlight = link->panel_cntl->funcs->hw_init(link->panel_cntl);
599 	}
600 
601 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
602 		if (abms[i] != NULL)
603 			abms[i]->funcs->abm_init(abms[i], backlight);
604 	}
605 
606 	/* power AFMT HDMI memory TODO: may move to dis/en output save power*/
607 	REG_WRITE(DIO_MEM_PWR_CTRL, 0);
608 
609 	if (!dc->debug.disable_clock_gate) {
610 		/* enable all DCN clock gating */
611 		REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
612 
613 		REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
614 
615 		REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
616 	}
617 	if (hws->funcs.enable_power_gating_plane)
618 		hws->funcs.enable_power_gating_plane(dc->hwseq, true);
619 
620 	if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks)
621 		dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub);
622 
623 	if (dc->clk_mgr->funcs->notify_wm_ranges)
624 		dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr);
625 
626 	if (dc->clk_mgr->funcs->set_hard_max_memclk)
627 		dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);
628 
629 	if (dc->res_pool->hubbub->funcs->force_pstate_change_control)
630 		dc->res_pool->hubbub->funcs->force_pstate_change_control(
631 				dc->res_pool->hubbub, false, false);
632 }
633 
634 void dcn30_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
635 {
636 	if (pipe_ctx == NULL)
637 		return;
638 
639 	if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal) && pipe_ctx->stream_res.stream_enc != NULL)
640 		pipe_ctx->stream_res.stream_enc->funcs->set_avmute(
641 				pipe_ctx->stream_res.stream_enc,
642 				enable);
643 }
644 
645 void dcn30_update_info_frame(struct pipe_ctx *pipe_ctx)
646 {
647 	bool is_hdmi_tmds;
648 	bool is_dp;
649 
650 	ASSERT(pipe_ctx->stream);
651 
652 	if (pipe_ctx->stream_res.stream_enc == NULL)
653 		return;  /* this is not root pipe */
654 
655 	is_hdmi_tmds = dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal);
656 	is_dp = dc_is_dp_signal(pipe_ctx->stream->signal);
657 
658 	if (!is_hdmi_tmds)
659 		return;
660 
661 	if (is_hdmi_tmds)
662 		pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets(
663 			pipe_ctx->stream_res.stream_enc,
664 			&pipe_ctx->stream_res.encoder_info_frame);
665 	else
666 		pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets(
667 			pipe_ctx->stream_res.stream_enc,
668 			&pipe_ctx->stream_res.encoder_info_frame);
669 }
670 
671 void dcn30_program_dmdata_engine(struct pipe_ctx *pipe_ctx)
672 {
673 	struct dc_stream_state    *stream     = pipe_ctx->stream;
674 	struct hubp               *hubp       = pipe_ctx->plane_res.hubp;
675 	bool                       enable     = false;
676 	struct stream_encoder     *stream_enc = pipe_ctx->stream_res.stream_enc;
677 	enum dynamic_metadata_mode mode       = dc_is_dp_signal(stream->signal)
678 							? dmdata_dp
679 							: dmdata_hdmi;
680 
681 	/* if using dynamic meta, don't set up generic infopackets */
682 	if (pipe_ctx->stream->dmdata_address.quad_part != 0) {
683 		pipe_ctx->stream_res.encoder_info_frame.hdrsmd.valid = false;
684 		enable = true;
685 	}
686 
687 	if (!hubp)
688 		return;
689 
690 	if (!stream_enc || !stream_enc->funcs->set_dynamic_metadata)
691 		return;
692 
693 	stream_enc->funcs->set_dynamic_metadata(stream_enc, enable,
694 							hubp->inst, mode);
695 }
696 
697 bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable)
698 {
699 	union dmub_rb_cmd cmd;
700 	unsigned int surface_size, refresh_hz, denom;
701 	uint32_t tmr_delay = 0, tmr_scale = 0;
702 
703 	if (!dc->ctx->dmub_srv)
704 		return false;
705 
706 	if (enable) {
707 		if (dc->current_state) {
708 			int i;
709 
710 			/* First, check no-memory-requests case */
711 			for (i = 0; i < dc->current_state->stream_count; i++) {
712 				if (dc->current_state->stream_status[i]
713 					    .plane_count)
714 					/* Fail eligibility on a visible stream */
715 					break;
716 			}
717 
718 			// TODO: remove hard code size
719 			if (surface_size < 128 * 1024 * 1024) {
720 				refresh_hz = div_u64((unsigned long long) dc->current_state->streams[0]->timing.pix_clk_100hz *
721 						     100LL,
722 						     (dc->current_state->streams[0]->timing.v_total *
723 						      dc->current_state->streams[0]->timing.h_total));
724 
725 				/*
726 				 * Delay_Us = 65.28 * (64 + MallFrameCacheTmrDly) * 2^MallFrameCacheTmrScale
727 				 * Delay_Us / 65.28 = (64 + MallFrameCacheTmrDly) * 2^MallFrameCacheTmrScale
728 				 * (Delay_Us / 65.28) / 2^MallFrameCacheTmrScale = 64 + MallFrameCacheTmrDly
729 				 * MallFrameCacheTmrDly = ((Delay_Us / 65.28) / 2^MallFrameCacheTmrScale) - 64
730 				 *                      = (1000000 / refresh) / 65.28 / 2^MallFrameCacheTmrScale - 64
731 				 *                      = 1000000 / (refresh * 65.28 * 2^MallFrameCacheTmrScale) - 64
732 				 *                      = (1000000 * 100) / (refresh * 6528 * 2^MallFrameCacheTmrScale) - 64
733 				 *
734 				 * need to round up the result of the division before the subtraction
735 				 */
736 				denom = refresh_hz * 6528;
737 				tmr_delay = div_u64((100000000LL + denom - 1), denom) - 64LL;
738 
739 				/* scale should be increased until it fits into 6 bits */
740 				while (tmr_delay & ~0x3F) {
741 					tmr_scale++;
742 
743 					if (tmr_scale > 3) {
744 						/* The delay exceeds the range of the hystersis timer */
745 						ASSERT(false);
746 						return false;
747 					}
748 
749 					denom *= 2;
750 					tmr_delay = div_u64((100000000LL + denom - 1), denom) - 64LL;
751 				}
752 
753 				/* Enable MALL */
754 				memset(&cmd, 0, sizeof(cmd));
755 				cmd.mall.header.type = DMUB_CMD__MALL;
756 				cmd.mall.header.sub_type =
757 					DMUB_CMD__MALL_ACTION_ALLOW;
758 				cmd.mall.header.payload_bytes =
759 					sizeof(cmd.mall) -
760 					sizeof(cmd.mall.header);
761 				cmd.mall.tmr_delay = tmr_delay;
762 				cmd.mall.tmr_scale = tmr_scale;
763 
764 				dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd);
765 				dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv);
766 
767 				return true;
768 			}
769 		}
770 
771 		/* No applicable optimizations */
772 		return false;
773 	}
774 
775 	/* Disable MALL */
776 	memset(&cmd, 0, sizeof(cmd));
777 	cmd.mall.header.type = DMUB_CMD__MALL;
778 	cmd.mall.header.sub_type = DMUB_CMD__MALL_ACTION_DISALLOW;
779 	cmd.mall.header.payload_bytes =
780 		sizeof(cmd.mall) - sizeof(cmd.mall.header);
781 
782 	dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd);
783 	dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv);
784 	dc_dmub_srv_wait_idle(dc->ctx->dmub_srv);
785 
786 	return true;
787 }
788 
789 void dcn30_hardware_release(struct dc *dc)
790 {
791 	/* if pstate unsupported, force it supported */
792 	if (!dc->clk_mgr->clks.p_state_change_support &&
793 			dc->res_pool->hubbub->funcs->force_pstate_change_control)
794 		dc->res_pool->hubbub->funcs->force_pstate_change_control(
795 				dc->res_pool->hubbub, true, true);
796 }
797