1 /*
2  * Copyright 2020 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 
27 #include "dm_services.h"
28 #include "dm_helpers.h"
29 #include "core_types.h"
30 #include "resource.h"
31 #include "dcn30_hwseq.h"
32 #include "dccg.h"
33 #include "dce/dce_hwseq.h"
34 #include "dcn30_mpc.h"
35 #include "dcn30_dpp.h"
36 #include "dcn10/dcn10_cm_common.h"
37 #include "dcn30_cm_common.h"
38 #include "reg_helper.h"
39 #include "abm.h"
40 #include "clk_mgr.h"
41 #include "hubp.h"
42 #include "dchubbub.h"
43 #include "timing_generator.h"
44 #include "opp.h"
45 #include "ipp.h"
46 #include "mpc.h"
47 #include "mcif_wb.h"
48 #include "dc_dmub_srv.h"
49 #include "link_hwss.h"
50 #include "dpcd_defs.h"
51 #include "../dcn20/dcn20_hwseq.h"
52 #include "dcn30_resource.h"
53 #include "inc/dc_link_dp.h"
54 
55 
56 
57 
58 #define DC_LOGGER_INIT(logger)
59 
60 #define CTX \
61 	hws->ctx
62 #define REG(reg)\
63 	hws->regs->reg
64 #define DC_LOGGER \
65 		dc->ctx->logger
66 
67 
68 #undef FN
69 #define FN(reg_name, field_name) \
70 	hws->shifts->field_name, hws->masks->field_name
71 
72 bool dcn30_set_blend_lut(
73 	struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state)
74 {
75 	struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
76 	bool result = true;
77 	struct pwl_params *blend_lut = NULL;
78 
79 	if (plane_state->blend_tf) {
80 		if (plane_state->blend_tf->type == TF_TYPE_HWPWL)
81 			blend_lut = &plane_state->blend_tf->pwl;
82 		else if (plane_state->blend_tf->type == TF_TYPE_DISTRIBUTED_POINTS) {
83 			cm3_helper_translate_curve_to_hw_format(
84 					plane_state->blend_tf, &dpp_base->regamma_params, false);
85 			blend_lut = &dpp_base->regamma_params;
86 		}
87 	}
88 	result = dpp_base->funcs->dpp_program_blnd_lut(dpp_base, blend_lut);
89 
90 	return result;
91 }
92 
93 static bool dcn30_set_mpc_shaper_3dlut(
94 	struct pipe_ctx *pipe_ctx, const struct dc_stream_state *stream)
95 {
96 	struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
97 	int mpcc_id = pipe_ctx->plane_res.hubp->inst;
98 	struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
99 	bool result = false;
100 	int acquired_rmu = 0;
101 	int mpcc_id_projected = 0;
102 
103 	const struct pwl_params *shaper_lut = NULL;
104 	//get the shaper lut params
105 	if (stream->func_shaper) {
106 		if (stream->func_shaper->type == TF_TYPE_HWPWL)
107 			shaper_lut = &stream->func_shaper->pwl;
108 		else if (stream->func_shaper->type == TF_TYPE_DISTRIBUTED_POINTS) {
109 			cm_helper_translate_curve_to_hw_format(
110 					stream->func_shaper,
111 					&dpp_base->shaper_params, true);
112 			shaper_lut = &dpp_base->shaper_params;
113 		}
114 	}
115 
116 	if (stream->lut3d_func &&
117 		stream->lut3d_func->state.bits.initialized == 1 &&
118 		stream->lut3d_func->state.bits.rmu_idx_valid == 1) {
119 		if (stream->lut3d_func->state.bits.rmu_mux_num == 0)
120 			mpcc_id_projected = stream->lut3d_func->state.bits.mpc_rmu0_mux;
121 		else if (stream->lut3d_func->state.bits.rmu_mux_num == 1)
122 			mpcc_id_projected = stream->lut3d_func->state.bits.mpc_rmu1_mux;
123 		else if (stream->lut3d_func->state.bits.rmu_mux_num == 2)
124 			mpcc_id_projected = stream->lut3d_func->state.bits.mpc_rmu2_mux;
125 		if (mpcc_id_projected != mpcc_id)
126 			BREAK_TO_DEBUGGER();
127 		/*find the reason why logical layer assigned a differant mpcc_id into acquire_post_bldn_3dlut*/
128 		acquired_rmu = mpc->funcs->acquire_rmu(mpc, mpcc_id,
129 				stream->lut3d_func->state.bits.rmu_mux_num);
130 		if (acquired_rmu != stream->lut3d_func->state.bits.rmu_mux_num)
131 			BREAK_TO_DEBUGGER();
132 		result = mpc->funcs->program_3dlut(mpc,
133 								&stream->lut3d_func->lut_3d,
134 								stream->lut3d_func->state.bits.rmu_mux_num);
135 		result = mpc->funcs->program_shaper(mpc, shaper_lut,
136 				stream->lut3d_func->state.bits.rmu_mux_num);
137 	} else
138 		/*loop through the available mux and release the requested mpcc_id*/
139 		mpc->funcs->release_rmu(mpc, mpcc_id);
140 
141 
142 	return result;
143 }
144 
145 bool dcn30_set_input_transfer_func(struct dc *dc,
146 				struct pipe_ctx *pipe_ctx,
147 				const struct dc_plane_state *plane_state)
148 {
149 	struct dce_hwseq *hws = dc->hwseq;
150 	struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
151 	enum dc_transfer_func_predefined tf;
152 	bool result = true;
153 	struct pwl_params *params = NULL;
154 
155 	if (dpp_base == NULL || plane_state == NULL)
156 		return false;
157 
158 	tf = TRANSFER_FUNCTION_UNITY;
159 
160 	if (plane_state->in_transfer_func &&
161 		plane_state->in_transfer_func->type == TF_TYPE_PREDEFINED)
162 		tf = plane_state->in_transfer_func->tf;
163 
164 	dpp_base->funcs->dpp_set_pre_degam(dpp_base, tf);
165 
166 	if (plane_state->in_transfer_func) {
167 		if (plane_state->in_transfer_func->type == TF_TYPE_HWPWL)
168 			params = &plane_state->in_transfer_func->pwl;
169 		else if (plane_state->in_transfer_func->type == TF_TYPE_DISTRIBUTED_POINTS &&
170 			cm3_helper_translate_curve_to_hw_format(plane_state->in_transfer_func,
171 					&dpp_base->degamma_params, false))
172 			params = &dpp_base->degamma_params;
173 	}
174 
175 	result = dpp_base->funcs->dpp_program_gamcor_lut(dpp_base, params);
176 
177 	if (pipe_ctx->stream_res.opp && pipe_ctx->stream_res.opp->ctx) {
178 		if (dpp_base->funcs->dpp_program_blnd_lut)
179 			hws->funcs.set_blend_lut(pipe_ctx, plane_state);
180 		if (dpp_base->funcs->dpp_program_shaper_lut &&
181 				dpp_base->funcs->dpp_program_3dlut)
182 			hws->funcs.set_shaper_3dlut(pipe_ctx, plane_state);
183 	}
184 
185 	return result;
186 }
187 
188 bool dcn30_set_output_transfer_func(struct dc *dc,
189 				struct pipe_ctx *pipe_ctx,
190 				const struct dc_stream_state *stream)
191 {
192 	int mpcc_id = pipe_ctx->plane_res.hubp->inst;
193 	struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
194 	struct pwl_params *params = NULL;
195 	bool ret = false;
196 
197 	/* program OGAM or 3DLUT only for the top pipe*/
198 	if (pipe_ctx->top_pipe == NULL) {
199 		/*program rmu shaper and 3dlut in MPC*/
200 		ret = dcn30_set_mpc_shaper_3dlut(pipe_ctx, stream);
201 		if (ret == false && mpc->funcs->set_output_gamma && stream->out_transfer_func) {
202 			if (stream->out_transfer_func->type == TF_TYPE_HWPWL)
203 				params = &stream->out_transfer_func->pwl;
204 			else if (pipe_ctx->stream->out_transfer_func->type ==
205 					TF_TYPE_DISTRIBUTED_POINTS &&
206 					cm3_helper_translate_curve_to_hw_format(
207 					stream->out_transfer_func,
208 					&mpc->blender_params, false))
209 				params = &mpc->blender_params;
210 			 /* there are no ROM LUTs in OUTGAM */
211 			if (stream->out_transfer_func->type == TF_TYPE_PREDEFINED)
212 				BREAK_TO_DEBUGGER();
213 		}
214 	}
215 
216 	mpc->funcs->set_output_gamma(mpc, mpcc_id, params);
217 	return ret;
218 }
219 
220 static void dcn30_set_writeback(
221 		struct dc *dc,
222 		struct dc_writeback_info *wb_info,
223 		struct dc_state *context)
224 {
225 	struct mcif_wb *mcif_wb;
226 	struct mcif_buf_params *mcif_buf_params;
227 
228 	ASSERT(wb_info->dwb_pipe_inst < MAX_DWB_PIPES);
229 	ASSERT(wb_info->wb_enabled);
230 	ASSERT(wb_info->mpcc_inst >= 0);
231 	ASSERT(wb_info->mpcc_inst < dc->res_pool->mpcc_count);
232 	mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst];
233 	mcif_buf_params = &wb_info->mcif_buf_params;
234 
235 	/* set DWB MPC mux */
236 	dc->res_pool->mpc->funcs->set_dwb_mux(dc->res_pool->mpc,
237 			wb_info->dwb_pipe_inst, wb_info->mpcc_inst);
238 	/* set MCIF_WB buffer and arbitration configuration */
239 	mcif_wb->funcs->config_mcif_buf(mcif_wb, mcif_buf_params, wb_info->dwb_params.dest_height);
240 	mcif_wb->funcs->config_mcif_arb(mcif_wb, &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[wb_info->dwb_pipe_inst]);
241 }
242 
243 void dcn30_update_writeback(
244 		struct dc *dc,
245 		struct dc_writeback_info *wb_info,
246 		struct dc_state *context)
247 {
248 	struct dwbc *dwb;
249 	dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
250 	DC_LOG_DWB("%s dwb_pipe_inst = %d, mpcc_inst = %d",\
251 		__func__, wb_info->dwb_pipe_inst,\
252 		wb_info->mpcc_inst);
253 
254 	dcn30_set_writeback(dc, wb_info, context);
255 
256 	/* update DWB */
257 	dwb->funcs->update(dwb, &wb_info->dwb_params);
258 }
259 
260 bool dcn30_mmhubbub_warmup(
261 	struct dc *dc,
262 	unsigned int num_dwb,
263 	struct dc_writeback_info *wb_info)
264 {
265 	struct dwbc *dwb;
266 	struct mcif_wb *mcif_wb;
267 	struct mcif_warmup_params warmup_params = {0};
268 	unsigned int  i, i_buf;
269 	/*make sure there is no active DWB eanbled */
270 	for (i = 0; i < num_dwb; i++) {
271 		dwb = dc->res_pool->dwbc[wb_info[i].dwb_pipe_inst];
272 		if (dwb->dwb_is_efc_transition || dwb->dwb_is_drc) {
273 			/*can not do warmup while any dwb enabled*/
274 			return false;
275 		}
276 	}
277 
278 	if (wb_info->mcif_warmup_params.p_vmid == 0)
279 		return false;
280 
281 	/*check whether this is new interface: warmup big buffer once*/
282 	if (wb_info->mcif_warmup_params.start_address.quad_part != 0 &&
283 		wb_info->mcif_warmup_params.region_size != 0) {
284 		/*mmhubbub is shared, so it does not matter which MCIF*/
285 		mcif_wb = dc->res_pool->mcif_wb[0];
286 		/*warmup a big chunk of VM buffer at once*/
287 		warmup_params.start_address.quad_part = wb_info->mcif_warmup_params.start_address.quad_part;
288 		warmup_params.address_increment =  wb_info->mcif_warmup_params.region_size;
289 		warmup_params.region_size = wb_info->mcif_warmup_params.region_size;
290 		warmup_params.p_vmid = wb_info->mcif_warmup_params.p_vmid;
291 
292 		if (warmup_params.address_increment == 0)
293 			warmup_params.address_increment = dc->dml.soc.vmm_page_size_bytes;
294 
295 		mcif_wb->funcs->warmup_mcif(mcif_wb, &warmup_params);
296 		return true;
297 	}
298 	/*following is the original: warmup each DWB's mcif buffer*/
299 	for (i = 0; i < num_dwb; i++) {
300 		dwb = dc->res_pool->dwbc[wb_info[i].dwb_pipe_inst];
301 		mcif_wb = dc->res_pool->mcif_wb[wb_info[i].dwb_pipe_inst];
302 		/*warmup is for VM mode only*/
303 		if (wb_info[i].mcif_buf_params.p_vmid == 0)
304 			return false;
305 
306 		/* Warmup MCIF_WB */
307 		for (i_buf = 0; i_buf < MCIF_BUF_COUNT; i_buf++) {
308 			warmup_params.start_address.quad_part = wb_info[i].mcif_buf_params.luma_address[i_buf];
309 			warmup_params.address_increment = dc->dml.soc.vmm_page_size_bytes;
310 			warmup_params.region_size = wb_info[i].mcif_buf_params.luma_pitch * wb_info[i].dwb_params.dest_height;
311 			warmup_params.p_vmid = wb_info[i].mcif_buf_params.p_vmid;
312 			mcif_wb->funcs->warmup_mcif(mcif_wb, &warmup_params);
313 		}
314 	}
315 	return true;
316 }
317 
318 void dcn30_enable_writeback(
319 		struct dc *dc,
320 		struct dc_writeback_info *wb_info,
321 		struct dc_state *context)
322 {
323 	struct dwbc *dwb;
324 	struct mcif_wb *mcif_wb;
325 	struct timing_generator *optc;
326 
327 	dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
328 	mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst];
329 
330 	/* set the OPTC source mux */
331 	optc = dc->res_pool->timing_generators[dwb->otg_inst];
332 	DC_LOG_DWB("%s dwb_pipe_inst = %d, mpcc_inst = %d",\
333 		__func__, wb_info->dwb_pipe_inst,\
334 		wb_info->mpcc_inst);
335 	if (IS_DIAG_DC(dc->ctx->dce_environment)) {
336 		/*till diags switch to warmup interface*/
337 		dcn30_mmhubbub_warmup(dc, 1, wb_info);
338 	}
339 	/* Update writeback pipe */
340 	dcn30_set_writeback(dc, wb_info, context);
341 
342 	/* Enable MCIF_WB */
343 	mcif_wb->funcs->enable_mcif(mcif_wb);
344 	/* Enable DWB */
345 	dwb->funcs->enable(dwb, &wb_info->dwb_params);
346 }
347 
348 void dcn30_disable_writeback(
349 		struct dc *dc,
350 		unsigned int dwb_pipe_inst)
351 {
352 	struct dwbc *dwb;
353 	struct mcif_wb *mcif_wb;
354 
355 	ASSERT(dwb_pipe_inst < MAX_DWB_PIPES);
356 	dwb = dc->res_pool->dwbc[dwb_pipe_inst];
357 	mcif_wb = dc->res_pool->mcif_wb[dwb_pipe_inst];
358 	DC_LOG_DWB("%s dwb_pipe_inst = %d",\
359 		__func__, dwb_pipe_inst);
360 
361 	/* disable DWB */
362 	dwb->funcs->disable(dwb);
363 	/* disable MCIF */
364 	mcif_wb->funcs->disable_mcif(mcif_wb);
365 	/* disable MPC DWB mux */
366 	dc->res_pool->mpc->funcs->disable_dwb_mux(dc->res_pool->mpc, dwb_pipe_inst);
367 }
368 
369 void dcn30_program_all_writeback_pipes_in_tree(
370 		struct dc *dc,
371 		const struct dc_stream_state *stream,
372 		struct dc_state *context)
373 {
374 	struct dc_writeback_info wb_info;
375 	struct dwbc *dwb;
376 	struct dc_stream_status *stream_status = NULL;
377 	int i_wb, i_pipe, i_stream;
378 	DC_LOG_DWB("%s", __func__);
379 
380 	ASSERT(stream);
381 	for (i_stream = 0; i_stream < context->stream_count; i_stream++) {
382 		if (context->streams[i_stream] == stream) {
383 			stream_status = &context->stream_status[i_stream];
384 			break;
385 		}
386 	}
387 	ASSERT(stream_status);
388 
389 	ASSERT(stream->num_wb_info <= dc->res_pool->res_cap->num_dwb);
390 	/* For each writeback pipe */
391 	for (i_wb = 0; i_wb < stream->num_wb_info; i_wb++) {
392 
393 		/* copy writeback info to local non-const so mpcc_inst can be set */
394 		wb_info = stream->writeback_info[i_wb];
395 		if (wb_info.wb_enabled) {
396 
397 			/* get the MPCC instance for writeback_source_plane */
398 			wb_info.mpcc_inst = -1;
399 			for (i_pipe = 0; i_pipe < dc->res_pool->pipe_count; i_pipe++) {
400 				struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i_pipe];
401 
402 				if (!pipe_ctx->plane_state)
403 					continue;
404 
405 				if (pipe_ctx->plane_state == wb_info.writeback_source_plane) {
406 					wb_info.mpcc_inst = pipe_ctx->plane_res.mpcc_inst;
407 					break;
408 				}
409 			}
410 
411 			if (wb_info.mpcc_inst == -1) {
412 				/* Disable writeback pipe and disconnect from MPCC
413 				 * if source plane has been removed
414 				 */
415 				dc->hwss.disable_writeback(dc, wb_info.dwb_pipe_inst);
416 				continue;
417 			}
418 
419 			ASSERT(wb_info.dwb_pipe_inst < dc->res_pool->res_cap->num_dwb);
420 			dwb = dc->res_pool->dwbc[wb_info.dwb_pipe_inst];
421 			if (dwb->funcs->is_enabled(dwb)) {
422 				/* writeback pipe already enabled, only need to update */
423 				dc->hwss.update_writeback(dc, &wb_info, context);
424 			} else {
425 				/* Enable writeback pipe and connect to MPCC */
426 				dc->hwss.enable_writeback(dc, &wb_info, context);
427 			}
428 		} else {
429 			/* Disable writeback pipe and disconnect from MPCC */
430 			dc->hwss.disable_writeback(dc, wb_info.dwb_pipe_inst);
431 		}
432 	}
433 }
434 
435 void dcn30_init_hw(struct dc *dc)
436 {
437 	struct abm **abms = dc->res_pool->multiple_abms;
438 	struct dce_hwseq *hws = dc->hwseq;
439 	struct dc_bios *dcb = dc->ctx->dc_bios;
440 	struct resource_pool *res_pool = dc->res_pool;
441 	int i;
442 	int edp_num;
443 	uint32_t backlight = MAX_BACKLIGHT_LEVEL;
444 
445 	if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)
446 		dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);
447 
448 	// Initialize the dccg
449 	if (res_pool->dccg->funcs->dccg_init)
450 		res_pool->dccg->funcs->dccg_init(res_pool->dccg);
451 
452 	if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
453 
454 		REG_WRITE(REFCLK_CNTL, 0);
455 		REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1);
456 		REG_WRITE(DIO_MEM_PWR_CTRL, 0);
457 
458 		if (!dc->debug.disable_clock_gate) {
459 			/* enable all DCN clock gating */
460 			REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
461 
462 			REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
463 
464 			REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
465 		}
466 
467 		//Enable ability to power gate / don't force power on permanently
468 		if (hws->funcs.enable_power_gating_plane)
469 			hws->funcs.enable_power_gating_plane(hws, true);
470 
471 		return;
472 	}
473 
474 	if (!dcb->funcs->is_accelerated_mode(dcb)) {
475 		hws->funcs.bios_golden_init(dc);
476 		hws->funcs.disable_vga(dc->hwseq);
477 	}
478 
479 	if (dc->debug.enable_mem_low_power.bits.dmcu) {
480 		// Force ERAM to shutdown if DMCU is not enabled
481 		if (dc->debug.disable_dmcu || dc->config.disable_dmcu) {
482 			REG_UPDATE(DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, 3);
483 		}
484 	}
485 
486 	// Set default OPTC memory power states
487 	if (dc->debug.enable_mem_low_power.bits.optc) {
488 		// Shutdown when unassigned and light sleep in VBLANK
489 		REG_SET_2(ODM_MEM_PWR_CTRL3, 0, ODM_MEM_UNASSIGNED_PWR_MODE, 3, ODM_MEM_VBLANK_PWR_MODE, 1);
490 	}
491 
492 	if (dc->ctx->dc_bios->fw_info_valid) {
493 		res_pool->ref_clocks.xtalin_clock_inKhz =
494 				dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
495 
496 		if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
497 			if (res_pool->dccg && res_pool->hubbub) {
498 
499 				(res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,
500 						dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,
501 						&res_pool->ref_clocks.dccg_ref_clock_inKhz);
502 
503 				(res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub,
504 						res_pool->ref_clocks.dccg_ref_clock_inKhz,
505 						&res_pool->ref_clocks.dchub_ref_clock_inKhz);
506 			} else {
507 				// Not all ASICs have DCCG sw component
508 				res_pool->ref_clocks.dccg_ref_clock_inKhz =
509 						res_pool->ref_clocks.xtalin_clock_inKhz;
510 				res_pool->ref_clocks.dchub_ref_clock_inKhz =
511 						res_pool->ref_clocks.xtalin_clock_inKhz;
512 			}
513 		}
514 	} else
515 		ASSERT_CRITICAL(false);
516 
517 	for (i = 0; i < dc->link_count; i++) {
518 		/* Power up AND update implementation according to the
519 		 * required signal (which may be different from the
520 		 * default signal on connector).
521 		 */
522 		struct dc_link *link = dc->links[i];
523 
524 		link->link_enc->funcs->hw_init(link->link_enc);
525 
526 		/* Check for enabled DIG to identify enabled display */
527 		if (link->link_enc->funcs->is_dig_enabled &&
528 			link->link_enc->funcs->is_dig_enabled(link->link_enc)) {
529 			link->link_status.link_active = true;
530 			if (link->link_enc->funcs->fec_is_active &&
531 					link->link_enc->funcs->fec_is_active(link->link_enc))
532 				link->fec_state = dc_link_fec_enabled;
533 		}
534 	}
535 
536 	/* Power gate DSCs */
537 	for (i = 0; i < res_pool->res_cap->num_dsc; i++)
538 		if (hws->funcs.dsc_pg_control != NULL)
539 			hws->funcs.dsc_pg_control(hws, res_pool->dscs[i]->inst, false);
540 
541 	/* we want to turn off all dp displays before doing detection */
542 	dc_link_blank_all_dp_displays(dc);
543 
544 	if (hws->funcs.enable_power_gating_plane)
545 		hws->funcs.enable_power_gating_plane(dc->hwseq, true);
546 
547 	/* If taking control over from VBIOS, we may want to optimize our first
548 	 * mode set, so we need to skip powering down pipes until we know which
549 	 * pipes we want to use.
550 	 * Otherwise, if taking control is not possible, we need to power
551 	 * everything down.
552 	 */
553 	if (dcb->funcs->is_accelerated_mode(dcb) || !dc->config.seamless_boot_edp_requested) {
554 		hws->funcs.init_pipes(dc, dc->current_state);
555 		if (dc->res_pool->hubbub->funcs->allow_self_refresh_control)
556 			dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub,
557 					!dc->res_pool->hubbub->ctx->dc->debug.disable_stutter);
558 	}
559 
560 	/* In headless boot cases, DIG may be turned
561 	 * on which causes HW/SW discrepancies.
562 	 * To avoid this, power down hardware on boot
563 	 * if DIG is turned on and seamless boot not enabled
564 	 */
565 	if (!dc->config.seamless_boot_edp_requested) {
566 		struct dc_link *edp_links[MAX_NUM_EDP];
567 		struct dc_link *edp_link = NULL;
568 
569 		get_edp_links(dc, edp_links, &edp_num);
570 		if (edp_num)
571 			edp_link = edp_links[0];
572 		if (edp_link && edp_link->link_enc->funcs->is_dig_enabled &&
573 				edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc) &&
574 				dc->hwss.edp_backlight_control &&
575 				dc->hwss.power_down &&
576 				dc->hwss.edp_power_control) {
577 			dc->hwss.edp_backlight_control(edp_link, false);
578 			dc->hwss.power_down(dc);
579 			dc->hwss.edp_power_control(edp_link, false);
580 		} else {
581 			for (i = 0; i < dc->link_count; i++) {
582 				struct dc_link *link = dc->links[i];
583 
584 				if (link->link_enc->funcs->is_dig_enabled &&
585 						link->link_enc->funcs->is_dig_enabled(link->link_enc) &&
586 						dc->hwss.power_down) {
587 					dc->hwss.power_down(dc);
588 					break;
589 				}
590 
591 			}
592 		}
593 	}
594 
595 	for (i = 0; i < res_pool->audio_count; i++) {
596 		struct audio *audio = res_pool->audios[i];
597 
598 		audio->funcs->hw_init(audio);
599 	}
600 
601 	for (i = 0; i < dc->link_count; i++) {
602 		struct dc_link *link = dc->links[i];
603 
604 		if (link->panel_cntl)
605 			backlight = link->panel_cntl->funcs->hw_init(link->panel_cntl);
606 	}
607 
608 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
609 		if (abms[i] != NULL)
610 			abms[i]->funcs->abm_init(abms[i], backlight);
611 	}
612 
613 	/* power AFMT HDMI memory TODO: may move to dis/en output save power*/
614 	REG_WRITE(DIO_MEM_PWR_CTRL, 0);
615 
616 	if (!dc->debug.disable_clock_gate) {
617 		/* enable all DCN clock gating */
618 		REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
619 
620 		REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
621 
622 		REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
623 	}
624 
625 	if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks)
626 		dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub);
627 
628 	if (dc->clk_mgr->funcs->notify_wm_ranges)
629 		dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr);
630 
631 	if (dc->clk_mgr->funcs->set_hard_max_memclk)
632 		dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);
633 
634 	if (dc->res_pool->hubbub->funcs->force_pstate_change_control)
635 		dc->res_pool->hubbub->funcs->force_pstate_change_control(
636 				dc->res_pool->hubbub, false, false);
637 	if (dc->res_pool->hubbub->funcs->init_crb)
638 		dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub);
639 
640 	// Get DMCUB capabilities
641 	dc_dmub_srv_query_caps_cmd(dc->ctx->dmub_srv->dmub);
642 	dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr;
643 	dc->caps.dmub_caps.mclk_sw = dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch;
644 }
645 
646 void dcn30_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
647 {
648 	if (pipe_ctx == NULL)
649 		return;
650 
651 	if (dc_is_hdmi_signal(pipe_ctx->stream->signal) && pipe_ctx->stream_res.stream_enc != NULL)
652 		pipe_ctx->stream_res.stream_enc->funcs->set_avmute(
653 				pipe_ctx->stream_res.stream_enc,
654 				enable);
655 }
656 
657 void dcn30_update_info_frame(struct pipe_ctx *pipe_ctx)
658 {
659 	bool is_hdmi_tmds;
660 	bool is_dp;
661 
662 	ASSERT(pipe_ctx->stream);
663 
664 	if (pipe_ctx->stream_res.stream_enc == NULL)
665 		return;  /* this is not root pipe */
666 
667 	is_hdmi_tmds = dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal);
668 	is_dp = dc_is_dp_signal(pipe_ctx->stream->signal);
669 
670 	if (!is_hdmi_tmds && !is_dp)
671 		return;
672 
673 	if (is_hdmi_tmds)
674 		pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets(
675 			pipe_ctx->stream_res.stream_enc,
676 			&pipe_ctx->stream_res.encoder_info_frame);
677 	else
678 		pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets(
679 			pipe_ctx->stream_res.stream_enc,
680 			&pipe_ctx->stream_res.encoder_info_frame);
681 }
682 
683 void dcn30_program_dmdata_engine(struct pipe_ctx *pipe_ctx)
684 {
685 	struct dc_stream_state    *stream     = pipe_ctx->stream;
686 	struct hubp               *hubp       = pipe_ctx->plane_res.hubp;
687 	bool                       enable     = false;
688 	struct stream_encoder     *stream_enc = pipe_ctx->stream_res.stream_enc;
689 	enum dynamic_metadata_mode mode       = dc_is_dp_signal(stream->signal)
690 							? dmdata_dp
691 							: dmdata_hdmi;
692 
693 	/* if using dynamic meta, don't set up generic infopackets */
694 	if (pipe_ctx->stream->dmdata_address.quad_part != 0) {
695 		pipe_ctx->stream_res.encoder_info_frame.hdrsmd.valid = false;
696 		enable = true;
697 	}
698 
699 	if (!hubp)
700 		return;
701 
702 	if (!stream_enc || !stream_enc->funcs->set_dynamic_metadata)
703 		return;
704 
705 	stream_enc->funcs->set_dynamic_metadata(stream_enc, enable,
706 							hubp->inst, mode);
707 }
708 
709 bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable)
710 {
711 	union dmub_rb_cmd cmd;
712 	uint32_t tmr_delay = 0, tmr_scale = 0;
713 	struct dc_cursor_attributes cursor_attr;
714 	bool cursor_cache_enable = false;
715 	struct dc_stream_state *stream = NULL;
716 	struct dc_plane_state *plane = NULL;
717 
718 	if (!dc->ctx->dmub_srv)
719 		return false;
720 
721 	if (enable) {
722 		if (dc->current_state) {
723 			int i;
724 
725 			/* First, check no-memory-requests case */
726 			for (i = 0; i < dc->current_state->stream_count; i++) {
727 				if (dc->current_state->stream_status[i].plane_count)
728 					/* Fail eligibility on a visible stream */
729 					break;
730 			}
731 
732 			if (i == dc->current_state->stream_count) {
733 				/* Enable no-memory-requests case */
734 				memset(&cmd, 0, sizeof(cmd));
735 				cmd.mall.header.type = DMUB_CMD__MALL;
736 				cmd.mall.header.sub_type = DMUB_CMD__MALL_ACTION_NO_DF_REQ;
737 				cmd.mall.header.payload_bytes = sizeof(cmd.mall) - sizeof(cmd.mall.header);
738 
739 				dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd);
740 				dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv);
741 
742 				return true;
743 			}
744 
745 			stream = dc->current_state->streams[0];
746 			plane = (stream ? dc->current_state->stream_status[0].plane_states[0] : NULL);
747 
748 			if (stream && plane) {
749 				cursor_cache_enable = stream->cursor_position.enable &&
750 						plane->address.grph.cursor_cache_addr.quad_part;
751 				cursor_attr = stream->cursor_attributes;
752 			}
753 
754 			/*
755 			 * Second, check MALL eligibility
756 			 *
757 			 * single display only, single surface only, 8 and 16 bit formats only, no VM,
758 			 * do not use MALL for displays that support PSR as they use D0i3.2 in DMCUB FW
759 			 *
760 			 * TODO: When we implement multi-display, PSR displays will be allowed if there is
761 			 * a non-PSR display present, since in that case we can't do D0i3.2
762 			 */
763 			if (dc->current_state->stream_count == 1 &&
764 					stream->link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED &&
765 					dc->current_state->stream_status[0].plane_count == 1 &&
766 					plane->format <= SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F &&
767 					plane->format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB8888 &&
768 					plane->address.page_table_base.quad_part == 0 &&
769 					dc->hwss.does_plane_fit_in_mall &&
770 					dc->hwss.does_plane_fit_in_mall(dc, plane,
771 							cursor_cache_enable ? &cursor_attr : NULL)) {
772 				unsigned int v_total = stream->adjust.v_total_max ?
773 						stream->adjust.v_total_max : stream->timing.v_total;
774 				unsigned int refresh_hz = div_u64((unsigned long long) stream->timing.pix_clk_100hz *
775 						100LL, (v_total * stream->timing.h_total));
776 
777 				/*
778 				 * one frame time in microsec:
779 				 * Delay_Us = 1000000 / refresh
780 				 * dynamic_delay_us = 1000000 / refresh + 2 * stutter_period
781 				 *
782 				 * one frame time modified by 'additional timer percent' (p):
783 				 * Delay_Us_modified = dynamic_delay_us + dynamic_delay_us * p / 100
784 				 *                   = dynamic_delay_us * (1 + p / 100)
785 				 *                   = (1000000 / refresh + 2 * stutter_period) * (100 + p) / 100
786 				 *                   = (1000000 + 2 * stutter_period * refresh) * (100 + p) / (100 * refresh)
787 				 *
788 				 * formula for timer duration based on parameters, from regspec:
789 				 * dynamic_delay_us = 65.28 * (64 + MallFrameCacheTmrDly) * 2^MallFrameCacheTmrScale
790 				 *
791 				 * dynamic_delay_us / 65.28 = (64 + MallFrameCacheTmrDly) * 2^MallFrameCacheTmrScale
792 				 * (dynamic_delay_us / 65.28) / 2^MallFrameCacheTmrScale = 64 + MallFrameCacheTmrDly
793 				 * MallFrameCacheTmrDly = ((dynamic_delay_us / 65.28) / 2^MallFrameCacheTmrScale) - 64
794 				 *                      = (1000000 + 2 * stutter_period * refresh) * (100 + p) / (100 * refresh) / 65.28 / 2^MallFrameCacheTmrScale - 64
795 				 *                      = (1000000 + 2 * stutter_period * refresh) * (100 + p) / (refresh * 6528 * 2^MallFrameCacheTmrScale) - 64
796 				 *
797 				 * need to round up the result of the division before the subtraction
798 				 */
799 				unsigned int denom = refresh_hz * 6528;
800 				unsigned int stutter_period = dc->current_state->perf_params.stutter_period_us;
801 
802 				tmr_delay = div_u64(((1000000LL + 2 * stutter_period * refresh_hz) *
803 						(100LL + dc->debug.mall_additional_timer_percent) + denom - 1),
804 						denom) - 64LL;
805 
806 				/* In some cases the stutter period is really big (tiny modes) in these
807 				 * cases MALL cant be enabled, So skip these cases to avoid a ASSERT()
808 				 *
809 				 * We can check if stutter_period is more than 1/10th the frame time to
810 				 * consider if we can actually meet the range of hysteresis timer
811 				 */
812 				if (stutter_period > 100000/refresh_hz)
813 					return false;
814 
815 				/* scale should be increased until it fits into 6 bits */
816 				while (tmr_delay & ~0x3F) {
817 					tmr_scale++;
818 
819 					if (tmr_scale > 3) {
820 						/* Delay exceeds range of hysteresis timer */
821 						ASSERT(false);
822 						return false;
823 					}
824 
825 					denom *= 2;
826 					tmr_delay = div_u64(((1000000LL + 2 * stutter_period * refresh_hz) *
827 							(100LL + dc->debug.mall_additional_timer_percent) + denom - 1),
828 							denom) - 64LL;
829 				}
830 
831 				/* Copy HW cursor */
832 				if (cursor_cache_enable) {
833 					memset(&cmd, 0, sizeof(cmd));
834 					cmd.mall.header.type = DMUB_CMD__MALL;
835 					cmd.mall.header.sub_type = DMUB_CMD__MALL_ACTION_COPY_CURSOR;
836 					cmd.mall.header.payload_bytes =
837 							sizeof(cmd.mall) - sizeof(cmd.mall.header);
838 
839 					switch (cursor_attr.color_format) {
840 					case CURSOR_MODE_MONO:
841 						cmd.mall.cursor_bpp = 2;
842 						break;
843 					case CURSOR_MODE_COLOR_1BIT_AND:
844 					case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA:
845 					case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA:
846 						cmd.mall.cursor_bpp = 32;
847 						break;
848 
849 					case CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED:
850 					case CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED:
851 						cmd.mall.cursor_bpp = 64;
852 						break;
853 					}
854 
855 					cmd.mall.cursor_copy_src.quad_part = cursor_attr.address.quad_part;
856 					cmd.mall.cursor_copy_dst.quad_part =
857 							(plane->address.grph.cursor_cache_addr.quad_part + 2047) & ~2047;
858 					cmd.mall.cursor_width = cursor_attr.width;
859 					cmd.mall.cursor_height = cursor_attr.height;
860 					cmd.mall.cursor_pitch = cursor_attr.pitch;
861 
862 					dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd);
863 					dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv);
864 					dc_dmub_srv_wait_idle(dc->ctx->dmub_srv);
865 
866 					/* Use copied cursor, and it's okay to not switch back */
867 					cursor_attr.address.quad_part = cmd.mall.cursor_copy_dst.quad_part;
868 					dc_stream_set_cursor_attributes(stream, &cursor_attr);
869 				}
870 
871 				/* Enable MALL */
872 				memset(&cmd, 0, sizeof(cmd));
873 				cmd.mall.header.type = DMUB_CMD__MALL;
874 				cmd.mall.header.sub_type = DMUB_CMD__MALL_ACTION_ALLOW;
875 				cmd.mall.header.payload_bytes = sizeof(cmd.mall) - sizeof(cmd.mall.header);
876 				cmd.mall.tmr_delay = tmr_delay;
877 				cmd.mall.tmr_scale = tmr_scale;
878 				cmd.mall.debug_bits = dc->debug.mall_error_as_fatal;
879 
880 				dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd);
881 				dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv);
882 
883 				return true;
884 			}
885 		}
886 
887 		/* No applicable optimizations */
888 		return false;
889 	}
890 
891 	/* Disable MALL */
892 	memset(&cmd, 0, sizeof(cmd));
893 	cmd.mall.header.type = DMUB_CMD__MALL;
894 	cmd.mall.header.sub_type = DMUB_CMD__MALL_ACTION_DISALLOW;
895 	cmd.mall.header.payload_bytes =
896 		sizeof(cmd.mall) - sizeof(cmd.mall.header);
897 
898 	dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd);
899 	dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv);
900 	dc_dmub_srv_wait_idle(dc->ctx->dmub_srv);
901 
902 	return true;
903 }
904 
905 bool dcn30_does_plane_fit_in_mall(struct dc *dc, struct dc_plane_state *plane, struct dc_cursor_attributes *cursor_attr)
906 {
907 	// add meta size?
908 	unsigned int surface_size = plane->plane_size.surface_pitch * plane->plane_size.surface_size.height *
909 			(plane->format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616 ? 8 : 4);
910 	unsigned int mall_size = dc->caps.mall_size_total;
911 	unsigned int cursor_size = 0;
912 
913 	if (dc->debug.mall_size_override)
914 		mall_size = 1024 * 1024 * dc->debug.mall_size_override;
915 
916 	if (cursor_attr) {
917 		cursor_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size;
918 
919 		switch (cursor_attr->color_format) {
920 		case CURSOR_MODE_MONO:
921 			cursor_size /= 2;
922 			break;
923 		case CURSOR_MODE_COLOR_1BIT_AND:
924 		case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA:
925 		case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA:
926 			cursor_size *= 4;
927 			break;
928 
929 		case CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED:
930 		case CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED:
931 			cursor_size *= 8;
932 			break;
933 		}
934 	}
935 
936 	return (surface_size + cursor_size) < mall_size;
937 }
938 
939 void dcn30_hardware_release(struct dc *dc)
940 {
941 	bool subvp_in_use = false;
942 	uint32_t i;
943 
944 	dc_dmub_srv_p_state_delegate(dc, false, NULL);
945 	dc_dmub_setup_subvp_dmub_command(dc, dc->current_state, false);
946 
947 	/* SubVP treated the same way as FPO. If driver disable and
948 	 * we are using a SubVP config, disable and force on DCN side
949 	 * to prevent P-State hang on driver enable.
950 	 */
951 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
952 		struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
953 
954 		if (!pipe->stream)
955 			continue;
956 
957 		if (pipe->stream->mall_stream_config.type == SUBVP_MAIN) {
958 			subvp_in_use = true;
959 			break;
960 		}
961 	}
962 	/* If pstate unsupported, or still supported
963 	 * by firmware, force it supported by dcn
964 	 */
965 	if (dc->current_state)
966 		if ((!dc->clk_mgr->clks.p_state_change_support || subvp_in_use ||
967 				dc->current_state->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) &&
968 				dc->res_pool->hubbub->funcs->force_pstate_change_control)
969 			dc->res_pool->hubbub->funcs->force_pstate_change_control(
970 					dc->res_pool->hubbub, true, true);
971 }
972 
973 void dcn30_set_disp_pattern_generator(const struct dc *dc,
974 		struct pipe_ctx *pipe_ctx,
975 		enum controller_dp_test_pattern test_pattern,
976 		enum controller_dp_color_space color_space,
977 		enum dc_color_depth color_depth,
978 		const struct tg_color *solid_color,
979 		int width, int height, int offset)
980 {
981 	pipe_ctx->stream_res.opp->funcs->opp_set_disp_pattern_generator(pipe_ctx->stream_res.opp, test_pattern,
982 			color_space, color_depth, solid_color, width, height, offset);
983 }
984 
985 void dcn30_prepare_bandwidth(struct dc *dc,
986  	struct dc_state *context)
987 {
988 	if (dc->clk_mgr->dc_mode_softmax_enabled)
989 		if (dc->clk_mgr->clks.dramclk_khz <= dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000 &&
990 				context->bw_ctx.bw.dcn.clk.dramclk_khz > dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000)
991 			dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, dc->clk_mgr->bw_params->clk_table.entries[dc->clk_mgr->bw_params->clk_table.num_entries - 1].memclk_mhz);
992 
993 	dcn20_prepare_bandwidth(dc, context);
994 
995 	dc_dmub_srv_p_state_delegate(dc,
996 		context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching, context);
997 }
998 
999