1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 27 #include "dm_services.h" 28 #include "dm_helpers.h" 29 #include "core_types.h" 30 #include "resource.h" 31 #include "dcn30_hwseq.h" 32 #include "dccg.h" 33 #include "dce/dce_hwseq.h" 34 #include "dcn30_mpc.h" 35 #include "dcn30_dpp.h" 36 #include "dcn10/dcn10_cm_common.h" 37 #include "dcn30_cm_common.h" 38 #include "reg_helper.h" 39 #include "abm.h" 40 #include "clk_mgr.h" 41 #include "hubp.h" 42 #include "dchubbub.h" 43 #include "timing_generator.h" 44 #include "opp.h" 45 #include "ipp.h" 46 #include "mpc.h" 47 #include "mcif_wb.h" 48 #include "dc_dmub_srv.h" 49 #include "link_hwss.h" 50 #include "dpcd_defs.h" 51 52 53 54 55 #define DC_LOGGER_INIT(logger) 56 57 #define CTX \ 58 hws->ctx 59 #define REG(reg)\ 60 hws->regs->reg 61 #define DC_LOGGER \ 62 dc->ctx->logger 63 64 65 #undef FN 66 #define FN(reg_name, field_name) \ 67 hws->shifts->field_name, hws->masks->field_name 68 69 bool dcn30_set_blend_lut( 70 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state) 71 { 72 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; 73 bool result = true; 74 struct pwl_params *blend_lut = NULL; 75 76 if (plane_state->blend_tf) { 77 if (plane_state->blend_tf->type == TF_TYPE_HWPWL) 78 blend_lut = &plane_state->blend_tf->pwl; 79 else if (plane_state->blend_tf->type == TF_TYPE_DISTRIBUTED_POINTS) { 80 cm3_helper_translate_curve_to_hw_format( 81 plane_state->blend_tf, &dpp_base->regamma_params, false); 82 blend_lut = &dpp_base->regamma_params; 83 } 84 } 85 result = dpp_base->funcs->dpp_program_blnd_lut(dpp_base, blend_lut); 86 87 return result; 88 } 89 90 static bool dcn30_set_mpc_shaper_3dlut( 91 struct pipe_ctx *pipe_ctx, const struct dc_stream_state *stream) 92 { 93 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; 94 int mpcc_id = pipe_ctx->plane_res.hubp->inst; 95 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; 96 bool result = false; 97 int acquired_rmu = 0; 98 int mpcc_id_projected = 0; 99 100 const struct pwl_params *shaper_lut = NULL; 101 //get the shaper lut params 102 if (stream->func_shaper) { 103 if (stream->func_shaper->type == TF_TYPE_HWPWL) 104 shaper_lut = &stream->func_shaper->pwl; 105 else if (stream->func_shaper->type == TF_TYPE_DISTRIBUTED_POINTS) { 106 cm_helper_translate_curve_to_hw_format( 107 stream->func_shaper, 108 &dpp_base->shaper_params, true); 109 shaper_lut = &dpp_base->shaper_params; 110 } 111 } 112 113 if (stream->lut3d_func && 114 stream->lut3d_func->state.bits.initialized == 1 && 115 stream->lut3d_func->state.bits.rmu_idx_valid == 1) { 116 if (stream->lut3d_func->state.bits.rmu_mux_num == 0) 117 mpcc_id_projected = stream->lut3d_func->state.bits.mpc_rmu0_mux; 118 else if (stream->lut3d_func->state.bits.rmu_mux_num == 1) 119 mpcc_id_projected = stream->lut3d_func->state.bits.mpc_rmu1_mux; 120 else if (stream->lut3d_func->state.bits.rmu_mux_num == 2) 121 mpcc_id_projected = stream->lut3d_func->state.bits.mpc_rmu2_mux; 122 if (mpcc_id_projected != mpcc_id) 123 BREAK_TO_DEBUGGER(); 124 /*find the reason why logical layer assigned a differant mpcc_id into acquire_post_bldn_3dlut*/ 125 acquired_rmu = mpc->funcs->acquire_rmu(mpc, mpcc_id, 126 stream->lut3d_func->state.bits.rmu_mux_num); 127 if (acquired_rmu != stream->lut3d_func->state.bits.rmu_mux_num) 128 BREAK_TO_DEBUGGER(); 129 result = mpc->funcs->program_3dlut(mpc, 130 &stream->lut3d_func->lut_3d, 131 stream->lut3d_func->state.bits.rmu_mux_num); 132 result = mpc->funcs->program_shaper(mpc, shaper_lut, 133 stream->lut3d_func->state.bits.rmu_mux_num); 134 } else 135 /*loop through the available mux and release the requested mpcc_id*/ 136 mpc->funcs->release_rmu(mpc, mpcc_id); 137 138 139 return result; 140 } 141 142 bool dcn30_set_input_transfer_func(struct dc *dc, 143 struct pipe_ctx *pipe_ctx, 144 const struct dc_plane_state *plane_state) 145 { 146 struct dce_hwseq *hws = dc->hwseq; 147 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; 148 enum dc_transfer_func_predefined tf; 149 bool result = true; 150 struct pwl_params *params = NULL; 151 152 if (dpp_base == NULL || plane_state == NULL) 153 return false; 154 155 tf = TRANSFER_FUNCTION_UNITY; 156 157 if (plane_state->in_transfer_func && 158 plane_state->in_transfer_func->type == TF_TYPE_PREDEFINED) 159 tf = plane_state->in_transfer_func->tf; 160 161 dpp_base->funcs->dpp_set_pre_degam(dpp_base, tf); 162 163 if (plane_state->in_transfer_func) { 164 if (plane_state->in_transfer_func->type == TF_TYPE_HWPWL) 165 params = &plane_state->in_transfer_func->pwl; 166 else if (plane_state->in_transfer_func->type == TF_TYPE_DISTRIBUTED_POINTS && 167 cm3_helper_translate_curve_to_hw_format(plane_state->in_transfer_func, 168 &dpp_base->degamma_params, false)) 169 params = &dpp_base->degamma_params; 170 } 171 172 result = dpp_base->funcs->dpp_program_gamcor_lut(dpp_base, params); 173 174 if (pipe_ctx->stream_res.opp && pipe_ctx->stream_res.opp->ctx) { 175 if (dpp_base->funcs->dpp_program_blnd_lut) 176 hws->funcs.set_blend_lut(pipe_ctx, plane_state); 177 if (dpp_base->funcs->dpp_program_shaper_lut && 178 dpp_base->funcs->dpp_program_3dlut) 179 hws->funcs.set_shaper_3dlut(pipe_ctx, plane_state); 180 } 181 182 return result; 183 } 184 185 bool dcn30_set_output_transfer_func(struct dc *dc, 186 struct pipe_ctx *pipe_ctx, 187 const struct dc_stream_state *stream) 188 { 189 int mpcc_id = pipe_ctx->plane_res.hubp->inst; 190 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; 191 struct pwl_params *params = NULL; 192 bool ret = false; 193 194 /* program OGAM or 3DLUT only for the top pipe*/ 195 if (pipe_ctx->top_pipe == NULL) { 196 /*program rmu shaper and 3dlut in MPC*/ 197 ret = dcn30_set_mpc_shaper_3dlut(pipe_ctx, stream); 198 if (ret == false && mpc->funcs->set_output_gamma && stream->out_transfer_func) { 199 if (stream->out_transfer_func->type == TF_TYPE_HWPWL) 200 params = &stream->out_transfer_func->pwl; 201 else if (pipe_ctx->stream->out_transfer_func->type == 202 TF_TYPE_DISTRIBUTED_POINTS && 203 cm3_helper_translate_curve_to_hw_format( 204 stream->out_transfer_func, 205 &mpc->blender_params, false)) 206 params = &mpc->blender_params; 207 /* there are no ROM LUTs in OUTGAM */ 208 if (stream->out_transfer_func->type == TF_TYPE_PREDEFINED) 209 BREAK_TO_DEBUGGER(); 210 } 211 } 212 213 mpc->funcs->set_output_gamma(mpc, mpcc_id, params); 214 return ret; 215 } 216 217 static void dcn30_set_writeback( 218 struct dc *dc, 219 struct dc_writeback_info *wb_info, 220 struct dc_state *context) 221 { 222 struct mcif_wb *mcif_wb; 223 struct mcif_buf_params *mcif_buf_params; 224 225 ASSERT(wb_info->dwb_pipe_inst < MAX_DWB_PIPES); 226 ASSERT(wb_info->wb_enabled); 227 ASSERT(wb_info->mpcc_inst >= 0); 228 ASSERT(wb_info->mpcc_inst < dc->res_pool->mpcc_count); 229 mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst]; 230 mcif_buf_params = &wb_info->mcif_buf_params; 231 232 /* set DWB MPC mux */ 233 dc->res_pool->mpc->funcs->set_dwb_mux(dc->res_pool->mpc, 234 wb_info->dwb_pipe_inst, wb_info->mpcc_inst); 235 /* set MCIF_WB buffer and arbitration configuration */ 236 mcif_wb->funcs->config_mcif_buf(mcif_wb, mcif_buf_params, wb_info->dwb_params.dest_height); 237 mcif_wb->funcs->config_mcif_arb(mcif_wb, &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[wb_info->dwb_pipe_inst]); 238 } 239 240 void dcn30_update_writeback( 241 struct dc *dc, 242 struct dc_writeback_info *wb_info, 243 struct dc_state *context) 244 { 245 struct dwbc *dwb; 246 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; 247 DC_LOG_DWB("%s dwb_pipe_inst = %d, mpcc_inst = %d",\ 248 __func__, wb_info->dwb_pipe_inst,\ 249 wb_info->mpcc_inst); 250 251 dcn30_set_writeback(dc, wb_info, context); 252 253 /* update DWB */ 254 dwb->funcs->update(dwb, &wb_info->dwb_params); 255 } 256 257 bool dcn30_mmhubbub_warmup( 258 struct dc *dc, 259 unsigned int num_dwb, 260 struct dc_writeback_info *wb_info) 261 { 262 struct dwbc *dwb; 263 struct mcif_wb *mcif_wb; 264 struct mcif_warmup_params warmup_params = {0}; 265 unsigned int i, i_buf; 266 /*make sure there is no active DWB eanbled */ 267 for (i = 0; i < num_dwb; i++) { 268 dwb = dc->res_pool->dwbc[wb_info[i].dwb_pipe_inst]; 269 if (dwb->dwb_is_efc_transition || dwb->dwb_is_drc) { 270 /*can not do warmup while any dwb enabled*/ 271 return false; 272 } 273 } 274 275 if (wb_info->mcif_warmup_params.p_vmid == 0) 276 return false; 277 278 /*check whether this is new interface: warmup big buffer once*/ 279 if (wb_info->mcif_warmup_params.start_address.quad_part != 0 && 280 wb_info->mcif_warmup_params.region_size != 0) { 281 /*mmhubbub is shared, so it does not matter which MCIF*/ 282 mcif_wb = dc->res_pool->mcif_wb[0]; 283 /*warmup a big chunk of VM buffer at once*/ 284 warmup_params.start_address.quad_part = wb_info->mcif_warmup_params.start_address.quad_part; 285 warmup_params.address_increment = wb_info->mcif_warmup_params.region_size; 286 warmup_params.region_size = wb_info->mcif_warmup_params.region_size; 287 warmup_params.p_vmid = wb_info->mcif_warmup_params.p_vmid; 288 289 if (warmup_params.address_increment == 0) 290 warmup_params.address_increment = dc->dml.soc.vmm_page_size_bytes; 291 292 mcif_wb->funcs->warmup_mcif(mcif_wb, &warmup_params); 293 return true; 294 } 295 /*following is the original: warmup each DWB's mcif buffer*/ 296 for (i = 0; i < num_dwb; i++) { 297 dwb = dc->res_pool->dwbc[wb_info[i].dwb_pipe_inst]; 298 mcif_wb = dc->res_pool->mcif_wb[wb_info[i].dwb_pipe_inst]; 299 /*warmup is for VM mode only*/ 300 if (wb_info[i].mcif_buf_params.p_vmid == 0) 301 return false; 302 303 /* Warmup MCIF_WB */ 304 for (i_buf = 0; i_buf < MCIF_BUF_COUNT; i_buf++) { 305 warmup_params.start_address.quad_part = wb_info[i].mcif_buf_params.luma_address[i_buf]; 306 warmup_params.address_increment = dc->dml.soc.vmm_page_size_bytes; 307 warmup_params.region_size = wb_info[i].mcif_buf_params.luma_pitch * wb_info[i].dwb_params.dest_height; 308 warmup_params.p_vmid = wb_info[i].mcif_buf_params.p_vmid; 309 mcif_wb->funcs->warmup_mcif(mcif_wb, &warmup_params); 310 } 311 } 312 return true; 313 } 314 315 void dcn30_enable_writeback( 316 struct dc *dc, 317 struct dc_writeback_info *wb_info, 318 struct dc_state *context) 319 { 320 struct dwbc *dwb; 321 struct mcif_wb *mcif_wb; 322 struct timing_generator *optc; 323 324 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; 325 mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst]; 326 327 /* set the OPTC source mux */ 328 optc = dc->res_pool->timing_generators[dwb->otg_inst]; 329 DC_LOG_DWB("%s dwb_pipe_inst = %d, mpcc_inst = %d",\ 330 __func__, wb_info->dwb_pipe_inst,\ 331 wb_info->mpcc_inst); 332 if (IS_DIAG_DC(dc->ctx->dce_environment)) { 333 /*till diags switch to warmup interface*/ 334 dcn30_mmhubbub_warmup(dc, 1, wb_info); 335 } 336 /* Update writeback pipe */ 337 dcn30_set_writeback(dc, wb_info, context); 338 339 /* Enable MCIF_WB */ 340 mcif_wb->funcs->enable_mcif(mcif_wb); 341 /* Enable DWB */ 342 dwb->funcs->enable(dwb, &wb_info->dwb_params); 343 } 344 345 void dcn30_disable_writeback( 346 struct dc *dc, 347 unsigned int dwb_pipe_inst) 348 { 349 struct dwbc *dwb; 350 struct mcif_wb *mcif_wb; 351 352 ASSERT(dwb_pipe_inst < MAX_DWB_PIPES); 353 dwb = dc->res_pool->dwbc[dwb_pipe_inst]; 354 mcif_wb = dc->res_pool->mcif_wb[dwb_pipe_inst]; 355 DC_LOG_DWB("%s dwb_pipe_inst = %d",\ 356 __func__, dwb_pipe_inst); 357 358 /* disable DWB */ 359 dwb->funcs->disable(dwb); 360 /* disable MCIF */ 361 mcif_wb->funcs->disable_mcif(mcif_wb); 362 /* disable MPC DWB mux */ 363 dc->res_pool->mpc->funcs->disable_dwb_mux(dc->res_pool->mpc, dwb_pipe_inst); 364 } 365 366 void dcn30_program_all_writeback_pipes_in_tree( 367 struct dc *dc, 368 const struct dc_stream_state *stream, 369 struct dc_state *context) 370 { 371 struct dc_writeback_info wb_info; 372 struct dwbc *dwb; 373 struct dc_stream_status *stream_status = NULL; 374 int i_wb, i_pipe, i_stream; 375 DC_LOG_DWB("%s", __func__); 376 377 ASSERT(stream); 378 for (i_stream = 0; i_stream < context->stream_count; i_stream++) { 379 if (context->streams[i_stream] == stream) { 380 stream_status = &context->stream_status[i_stream]; 381 break; 382 } 383 } 384 ASSERT(stream_status); 385 386 ASSERT(stream->num_wb_info <= dc->res_pool->res_cap->num_dwb); 387 /* For each writeback pipe */ 388 for (i_wb = 0; i_wb < stream->num_wb_info; i_wb++) { 389 390 /* copy writeback info to local non-const so mpcc_inst can be set */ 391 wb_info = stream->writeback_info[i_wb]; 392 if (wb_info.wb_enabled) { 393 394 /* get the MPCC instance for writeback_source_plane */ 395 wb_info.mpcc_inst = -1; 396 for (i_pipe = 0; i_pipe < dc->res_pool->pipe_count; i_pipe++) { 397 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i_pipe]; 398 399 if (pipe_ctx->plane_state == wb_info.writeback_source_plane) { 400 wb_info.mpcc_inst = pipe_ctx->plane_res.mpcc_inst; 401 break; 402 } 403 } 404 ASSERT(wb_info.mpcc_inst != -1); 405 406 ASSERT(wb_info.dwb_pipe_inst < dc->res_pool->res_cap->num_dwb); 407 dwb = dc->res_pool->dwbc[wb_info.dwb_pipe_inst]; 408 if (dwb->funcs->is_enabled(dwb)) { 409 /* writeback pipe already enabled, only need to update */ 410 dc->hwss.update_writeback(dc, &wb_info, context); 411 } else { 412 /* Enable writeback pipe and connect to MPCC */ 413 dc->hwss.enable_writeback(dc, &wb_info, context); 414 } 415 } else { 416 /* Disable writeback pipe and disconnect from MPCC */ 417 dc->hwss.disable_writeback(dc, wb_info.dwb_pipe_inst); 418 } 419 } 420 } 421 422 void dcn30_init_hw(struct dc *dc) 423 { 424 int i, j; 425 struct abm **abms = dc->res_pool->multiple_abms; 426 struct dce_hwseq *hws = dc->hwseq; 427 struct dc_bios *dcb = dc->ctx->dc_bios; 428 struct resource_pool *res_pool = dc->res_pool; 429 uint32_t backlight = MAX_BACKLIGHT_LEVEL; 430 431 if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks) 432 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr); 433 434 // Initialize the dccg 435 if (res_pool->dccg->funcs->dccg_init) 436 res_pool->dccg->funcs->dccg_init(res_pool->dccg); 437 438 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { 439 440 REG_WRITE(REFCLK_CNTL, 0); 441 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1); 442 REG_WRITE(DIO_MEM_PWR_CTRL, 0); 443 444 if (!dc->debug.disable_clock_gate) { 445 /* enable all DCN clock gating */ 446 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); 447 448 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); 449 450 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); 451 } 452 453 //Enable ability to power gate / don't force power on permanently 454 if (hws->funcs.enable_power_gating_plane) 455 hws->funcs.enable_power_gating_plane(hws, true); 456 457 return; 458 } 459 460 if (!dcb->funcs->is_accelerated_mode(dcb)) { 461 hws->funcs.bios_golden_init(dc); 462 hws->funcs.disable_vga(dc->hwseq); 463 } 464 465 if (dc->debug.enable_mem_low_power.bits.dmcu) { 466 // Force ERAM to shutdown if DMCU is not enabled 467 if (dc->debug.disable_dmcu || dc->config.disable_dmcu) { 468 REG_UPDATE(DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, 3); 469 } 470 } 471 472 // Set default OPTC memory power states 473 if (dc->debug.enable_mem_low_power.bits.optc) { 474 // Shutdown when unassigned and light sleep in VBLANK 475 REG_SET_2(ODM_MEM_PWR_CTRL3, 0, ODM_MEM_UNASSIGNED_PWR_MODE, 3, ODM_MEM_VBLANK_PWR_MODE, 1); 476 } 477 478 if (dc->ctx->dc_bios->fw_info_valid) { 479 res_pool->ref_clocks.xtalin_clock_inKhz = 480 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency; 481 482 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { 483 if (res_pool->dccg && res_pool->hubbub) { 484 485 (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg, 486 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency, 487 &res_pool->ref_clocks.dccg_ref_clock_inKhz); 488 489 (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub, 490 res_pool->ref_clocks.dccg_ref_clock_inKhz, 491 &res_pool->ref_clocks.dchub_ref_clock_inKhz); 492 } else { 493 // Not all ASICs have DCCG sw component 494 res_pool->ref_clocks.dccg_ref_clock_inKhz = 495 res_pool->ref_clocks.xtalin_clock_inKhz; 496 res_pool->ref_clocks.dchub_ref_clock_inKhz = 497 res_pool->ref_clocks.xtalin_clock_inKhz; 498 } 499 } 500 } else 501 ASSERT_CRITICAL(false); 502 503 for (i = 0; i < dc->link_count; i++) { 504 /* Power up AND update implementation according to the 505 * required signal (which may be different from the 506 * default signal on connector). 507 */ 508 struct dc_link *link = dc->links[i]; 509 510 link->link_enc->funcs->hw_init(link->link_enc); 511 512 /* Check for enabled DIG to identify enabled display */ 513 if (link->link_enc->funcs->is_dig_enabled && 514 link->link_enc->funcs->is_dig_enabled(link->link_enc)) 515 link->link_status.link_active = true; 516 } 517 518 /* Power gate DSCs */ 519 for (i = 0; i < res_pool->res_cap->num_dsc; i++) 520 if (hws->funcs.dsc_pg_control != NULL) 521 hws->funcs.dsc_pg_control(hws, res_pool->dscs[i]->inst, false); 522 523 /* we want to turn off all dp displays before doing detection */ 524 if (dc->config.power_down_display_on_boot) { 525 uint8_t dpcd_power_state = '\0'; 526 enum dc_status status = DC_ERROR_UNEXPECTED; 527 528 for (i = 0; i < dc->link_count; i++) { 529 if (dc->links[i]->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) 530 continue; 531 532 /* if any of the displays are lit up turn them off */ 533 status = core_link_read_dpcd(dc->links[i], DP_SET_POWER, 534 &dpcd_power_state, sizeof(dpcd_power_state)); 535 if (status == DC_OK && dpcd_power_state == DP_POWER_STATE_D0) { 536 /* blank dp stream before power off receiver*/ 537 if (dc->links[i]->link_enc->funcs->get_dig_frontend) { 538 unsigned int fe; 539 540 fe = dc->links[i]->link_enc->funcs->get_dig_frontend( 541 dc->links[i]->link_enc); 542 if (fe == ENGINE_ID_UNKNOWN) 543 continue; 544 545 for (j = 0; j < dc->res_pool->stream_enc_count; j++) { 546 if (fe == dc->res_pool->stream_enc[j]->id) { 547 dc->res_pool->stream_enc[j]->funcs->dp_blank( 548 dc->res_pool->stream_enc[j]); 549 break; 550 } 551 } 552 } 553 dp_receiver_power_ctrl(dc->links[i], false); 554 } 555 } 556 } 557 558 /* If taking control over from VBIOS, we may want to optimize our first 559 * mode set, so we need to skip powering down pipes until we know which 560 * pipes we want to use. 561 * Otherwise, if taking control is not possible, we need to power 562 * everything down. 563 */ 564 if (dcb->funcs->is_accelerated_mode(dcb) || dc->config.power_down_display_on_boot) { 565 hws->funcs.init_pipes(dc, dc->current_state); 566 if (dc->res_pool->hubbub->funcs->allow_self_refresh_control) 567 dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, 568 !dc->res_pool->hubbub->ctx->dc->debug.disable_stutter); 569 } 570 571 /* In headless boot cases, DIG may be turned 572 * on which causes HW/SW discrepancies. 573 * To avoid this, power down hardware on boot 574 * if DIG is turned on and seamless boot not enabled 575 */ 576 if (dc->config.power_down_display_on_boot) { 577 struct dc_link *edp_link = get_edp_link(dc); 578 579 if (edp_link && 580 edp_link->link_enc->funcs->is_dig_enabled && 581 edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc) && 582 dc->hwss.edp_backlight_control && 583 dc->hwss.power_down && 584 dc->hwss.edp_power_control) { 585 dc->hwss.edp_backlight_control(edp_link, false); 586 dc->hwss.power_down(dc); 587 dc->hwss.edp_power_control(edp_link, false); 588 } else { 589 for (i = 0; i < dc->link_count; i++) { 590 struct dc_link *link = dc->links[i]; 591 592 if (link->link_enc->funcs->is_dig_enabled && 593 link->link_enc->funcs->is_dig_enabled(link->link_enc) && 594 dc->hwss.power_down) { 595 dc->hwss.power_down(dc); 596 break; 597 } 598 599 } 600 } 601 } 602 603 for (i = 0; i < res_pool->audio_count; i++) { 604 struct audio *audio = res_pool->audios[i]; 605 606 audio->funcs->hw_init(audio); 607 } 608 609 for (i = 0; i < dc->link_count; i++) { 610 struct dc_link *link = dc->links[i]; 611 612 if (link->panel_cntl) 613 backlight = link->panel_cntl->funcs->hw_init(link->panel_cntl); 614 } 615 616 for (i = 0; i < dc->res_pool->pipe_count; i++) { 617 if (abms[i] != NULL) 618 abms[i]->funcs->abm_init(abms[i], backlight); 619 } 620 621 /* power AFMT HDMI memory TODO: may move to dis/en output save power*/ 622 REG_WRITE(DIO_MEM_PWR_CTRL, 0); 623 624 if (!dc->debug.disable_clock_gate) { 625 /* enable all DCN clock gating */ 626 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); 627 628 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); 629 630 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); 631 } 632 if (hws->funcs.enable_power_gating_plane) 633 hws->funcs.enable_power_gating_plane(dc->hwseq, true); 634 635 if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks) 636 dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub); 637 638 if (dc->clk_mgr->funcs->notify_wm_ranges) 639 dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr); 640 641 if (dc->clk_mgr->funcs->set_hard_max_memclk) 642 dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr); 643 644 if (dc->res_pool->hubbub->funcs->force_pstate_change_control) 645 dc->res_pool->hubbub->funcs->force_pstate_change_control( 646 dc->res_pool->hubbub, false, false); 647 } 648 649 void dcn30_set_avmute(struct pipe_ctx *pipe_ctx, bool enable) 650 { 651 if (pipe_ctx == NULL) 652 return; 653 654 if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal) && pipe_ctx->stream_res.stream_enc != NULL) 655 pipe_ctx->stream_res.stream_enc->funcs->set_avmute( 656 pipe_ctx->stream_res.stream_enc, 657 enable); 658 } 659 660 void dcn30_update_info_frame(struct pipe_ctx *pipe_ctx) 661 { 662 bool is_hdmi_tmds; 663 bool is_dp; 664 665 ASSERT(pipe_ctx->stream); 666 667 if (pipe_ctx->stream_res.stream_enc == NULL) 668 return; /* this is not root pipe */ 669 670 is_hdmi_tmds = dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal); 671 is_dp = dc_is_dp_signal(pipe_ctx->stream->signal); 672 673 if (!is_hdmi_tmds && !is_dp) 674 return; 675 676 if (is_hdmi_tmds) 677 pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets( 678 pipe_ctx->stream_res.stream_enc, 679 &pipe_ctx->stream_res.encoder_info_frame); 680 else 681 pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets( 682 pipe_ctx->stream_res.stream_enc, 683 &pipe_ctx->stream_res.encoder_info_frame); 684 } 685 686 void dcn30_program_dmdata_engine(struct pipe_ctx *pipe_ctx) 687 { 688 struct dc_stream_state *stream = pipe_ctx->stream; 689 struct hubp *hubp = pipe_ctx->plane_res.hubp; 690 bool enable = false; 691 struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc; 692 enum dynamic_metadata_mode mode = dc_is_dp_signal(stream->signal) 693 ? dmdata_dp 694 : dmdata_hdmi; 695 696 /* if using dynamic meta, don't set up generic infopackets */ 697 if (pipe_ctx->stream->dmdata_address.quad_part != 0) { 698 pipe_ctx->stream_res.encoder_info_frame.hdrsmd.valid = false; 699 enable = true; 700 } 701 702 if (!hubp) 703 return; 704 705 if (!stream_enc || !stream_enc->funcs->set_dynamic_metadata) 706 return; 707 708 stream_enc->funcs->set_dynamic_metadata(stream_enc, enable, 709 hubp->inst, mode); 710 } 711 712 bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable) 713 { 714 union dmub_rb_cmd cmd; 715 uint32_t tmr_delay = 0, tmr_scale = 0; 716 struct dc_cursor_attributes cursor_attr; 717 bool cursor_cache_enable = false; 718 struct dc_stream_state *stream = NULL; 719 struct dc_plane_state *plane = NULL; 720 721 if (!dc->ctx->dmub_srv) 722 return false; 723 724 if (enable) { 725 if (dc->current_state) { 726 int i; 727 728 /* First, check no-memory-requests case */ 729 for (i = 0; i < dc->current_state->stream_count; i++) { 730 if (dc->current_state->stream_status[i].plane_count) 731 /* Fail eligibility on a visible stream */ 732 break; 733 } 734 735 if (i == dc->current_state->stream_count) { 736 /* Enable no-memory-requests case */ 737 memset(&cmd, 0, sizeof(cmd)); 738 cmd.mall.header.type = DMUB_CMD__MALL; 739 cmd.mall.header.sub_type = DMUB_CMD__MALL_ACTION_NO_DF_REQ; 740 cmd.mall.header.payload_bytes = sizeof(cmd.mall) - sizeof(cmd.mall.header); 741 742 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd); 743 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv); 744 745 return true; 746 } 747 748 stream = dc->current_state->streams[0]; 749 plane = (stream ? dc->current_state->stream_status[0].plane_states[0] : NULL); 750 751 if (stream && plane) { 752 cursor_cache_enable = stream->cursor_position.enable && 753 plane->address.grph.cursor_cache_addr.quad_part; 754 cursor_attr = stream->cursor_attributes; 755 } 756 757 /* 758 * Second, check MALL eligibility 759 * 760 * single display only, single surface only, 8 and 16 bit formats only, no VM, 761 * do not use MALL for displays that support PSR as they use D0i3.2 in DMCUB FW 762 * 763 * TODO: When we implement multi-display, PSR displays will be allowed if there is 764 * a non-PSR display present, since in that case we can't do D0i3.2 765 */ 766 if (dc->current_state->stream_count == 1 && 767 stream->link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED && 768 dc->current_state->stream_status[0].plane_count == 1 && 769 plane->format <= SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F && 770 plane->format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB8888 && 771 plane->address.page_table_base.quad_part == 0 && 772 dc->hwss.does_plane_fit_in_mall && 773 dc->hwss.does_plane_fit_in_mall(dc, plane, 774 cursor_cache_enable ? &cursor_attr : NULL)) { 775 unsigned int v_total = stream->adjust.v_total_max ? 776 stream->adjust.v_total_max : stream->timing.v_total; 777 unsigned int refresh_hz = div_u64((unsigned long long) stream->timing.pix_clk_100hz * 778 100LL, (v_total * stream->timing.h_total)); 779 780 /* 781 * one frame time in microsec: 782 * Delay_Us = 1000000 / refresh 783 * dynamic_delay_us = 1000000 / refresh + 2 * stutter_period 784 * 785 * one frame time modified by 'additional timer percent' (p): 786 * Delay_Us_modified = dynamic_delay_us + dynamic_delay_us * p / 100 787 * = dynamic_delay_us * (1 + p / 100) 788 * = (1000000 / refresh + 2 * stutter_period) * (100 + p) / 100 789 * = (1000000 + 2 * stutter_period * refresh) * (100 + p) / (100 * refresh) 790 * 791 * formula for timer duration based on parameters, from regspec: 792 * dynamic_delay_us = 65.28 * (64 + MallFrameCacheTmrDly) * 2^MallFrameCacheTmrScale 793 * 794 * dynamic_delay_us / 65.28 = (64 + MallFrameCacheTmrDly) * 2^MallFrameCacheTmrScale 795 * (dynamic_delay_us / 65.28) / 2^MallFrameCacheTmrScale = 64 + MallFrameCacheTmrDly 796 * MallFrameCacheTmrDly = ((dynamic_delay_us / 65.28) / 2^MallFrameCacheTmrScale) - 64 797 * = (1000000 + 2 * stutter_period * refresh) * (100 + p) / (100 * refresh) / 65.28 / 2^MallFrameCacheTmrScale - 64 798 * = (1000000 + 2 * stutter_period * refresh) * (100 + p) / (refresh * 6528 * 2^MallFrameCacheTmrScale) - 64 799 * 800 * need to round up the result of the division before the subtraction 801 */ 802 unsigned int denom = refresh_hz * 6528; 803 unsigned int stutter_period = dc->current_state->perf_params.stutter_period_us; 804 805 tmr_delay = div_u64(((1000000LL + 2 * stutter_period * refresh_hz) * 806 (100LL + dc->debug.mall_additional_timer_percent) + denom - 1), 807 denom) - 64LL; 808 809 /* scale should be increased until it fits into 6 bits */ 810 while (tmr_delay & ~0x3F) { 811 tmr_scale++; 812 813 if (tmr_scale > 3) { 814 /* Delay exceeds range of hysteresis timer */ 815 ASSERT(false); 816 return false; 817 } 818 819 denom *= 2; 820 tmr_delay = div_u64(((1000000LL + 2 * stutter_period * refresh_hz) * 821 (100LL + dc->debug.mall_additional_timer_percent) + denom - 1), 822 denom) - 64LL; 823 } 824 825 /* Copy HW cursor */ 826 if (cursor_cache_enable) { 827 memset(&cmd, 0, sizeof(cmd)); 828 cmd.mall.header.type = DMUB_CMD__MALL; 829 cmd.mall.header.sub_type = DMUB_CMD__MALL_ACTION_COPY_CURSOR; 830 cmd.mall.header.payload_bytes = 831 sizeof(cmd.mall) - sizeof(cmd.mall.header); 832 833 switch (cursor_attr.color_format) { 834 case CURSOR_MODE_MONO: 835 cmd.mall.cursor_bpp = 2; 836 break; 837 case CURSOR_MODE_COLOR_1BIT_AND: 838 case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA: 839 case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA: 840 cmd.mall.cursor_bpp = 32; 841 break; 842 843 case CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED: 844 case CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED: 845 cmd.mall.cursor_bpp = 64; 846 break; 847 } 848 849 cmd.mall.cursor_copy_src.quad_part = cursor_attr.address.quad_part; 850 cmd.mall.cursor_copy_dst.quad_part = 851 plane->address.grph.cursor_cache_addr.quad_part; 852 cmd.mall.cursor_width = cursor_attr.width; 853 cmd.mall.cursor_height = cursor_attr.height; 854 cmd.mall.cursor_pitch = cursor_attr.pitch; 855 856 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd); 857 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv); 858 dc_dmub_srv_wait_idle(dc->ctx->dmub_srv); 859 860 /* Use copied cursor, and it's okay to not switch back */ 861 cursor_attr.address.quad_part = 862 plane->address.grph.cursor_cache_addr.quad_part; 863 dc_stream_set_cursor_attributes(stream, &cursor_attr); 864 } 865 866 /* Enable MALL */ 867 memset(&cmd, 0, sizeof(cmd)); 868 cmd.mall.header.type = DMUB_CMD__MALL; 869 cmd.mall.header.sub_type = DMUB_CMD__MALL_ACTION_ALLOW; 870 cmd.mall.header.payload_bytes = sizeof(cmd.mall) - sizeof(cmd.mall.header); 871 cmd.mall.tmr_delay = tmr_delay; 872 cmd.mall.tmr_scale = tmr_scale; 873 cmd.mall.debug_bits = dc->debug.mall_error_as_fatal; 874 875 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd); 876 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv); 877 878 return true; 879 } 880 } 881 882 /* No applicable optimizations */ 883 return false; 884 } 885 886 /* Disable MALL */ 887 memset(&cmd, 0, sizeof(cmd)); 888 cmd.mall.header.type = DMUB_CMD__MALL; 889 cmd.mall.header.sub_type = DMUB_CMD__MALL_ACTION_DISALLOW; 890 cmd.mall.header.payload_bytes = 891 sizeof(cmd.mall) - sizeof(cmd.mall.header); 892 893 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd); 894 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv); 895 dc_dmub_srv_wait_idle(dc->ctx->dmub_srv); 896 897 return true; 898 } 899 900 bool dcn30_does_plane_fit_in_mall(struct dc *dc, struct dc_plane_state *plane, struct dc_cursor_attributes *cursor_attr) 901 { 902 // add meta size? 903 unsigned int surface_size = plane->plane_size.surface_pitch * plane->plane_size.surface_size.height * 904 (plane->format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616 ? 8 : 4); 905 unsigned int mall_size = dc->caps.mall_size_total; 906 unsigned int cursor_size = 0; 907 908 if (dc->debug.mall_size_override) 909 mall_size = 1024 * 1024 * dc->debug.mall_size_override; 910 911 if (cursor_attr) { 912 cursor_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size; 913 914 switch (cursor_attr->color_format) { 915 case CURSOR_MODE_MONO: 916 cursor_size /= 2; 917 break; 918 case CURSOR_MODE_COLOR_1BIT_AND: 919 case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA: 920 case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA: 921 cursor_size *= 4; 922 break; 923 924 case CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED: 925 case CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED: 926 cursor_size *= 8; 927 break; 928 } 929 } 930 931 return (surface_size + cursor_size) < mall_size; 932 } 933 934 void dcn30_hardware_release(struct dc *dc) 935 { 936 /* if pstate unsupported, force it supported */ 937 if (!dc->clk_mgr->clks.p_state_change_support && 938 dc->res_pool->hubbub->funcs->force_pstate_change_control) 939 dc->res_pool->hubbub->funcs->force_pstate_change_control( 940 dc->res_pool->hubbub, true, true); 941 } 942 943 void dcn30_set_hubp_blank(const struct dc *dc, 944 struct pipe_ctx *pipe_ctx, 945 bool blank_enable) 946 { 947 struct pipe_ctx *mpcc_pipe; 948 struct pipe_ctx *odm_pipe; 949 950 if (blank_enable) { 951 struct plane_resource *plane_res = &pipe_ctx->plane_res; 952 struct stream_resource *stream_res = &pipe_ctx->stream_res; 953 954 /* Wait for enter vblank */ 955 stream_res->tg->funcs->wait_for_state(stream_res->tg, CRTC_STATE_VBLANK); 956 957 /* Blank HUBP to allow p-state during blank on all timings */ 958 pipe_ctx->plane_res.hubp->funcs->set_blank(pipe_ctx->plane_res.hubp, true); 959 /* Confirm hubp in blank */ 960 ASSERT(plane_res->hubp->funcs->hubp_in_blank(plane_res->hubp)); 961 /* Toggle HUBP_DISABLE */ 962 plane_res->hubp->funcs->hubp_soft_reset(plane_res->hubp, true); 963 plane_res->hubp->funcs->hubp_soft_reset(plane_res->hubp, false); 964 for (mpcc_pipe = pipe_ctx->bottom_pipe; mpcc_pipe; mpcc_pipe = mpcc_pipe->bottom_pipe) { 965 mpcc_pipe->plane_res.hubp->funcs->set_blank(mpcc_pipe->plane_res.hubp, true); 966 /* Confirm hubp in blank */ 967 ASSERT(mpcc_pipe->plane_res.hubp->funcs->hubp_in_blank(mpcc_pipe->plane_res.hubp)); 968 /* Toggle HUBP_DISABLE */ 969 mpcc_pipe->plane_res.hubp->funcs->hubp_soft_reset(mpcc_pipe->plane_res.hubp, true); 970 mpcc_pipe->plane_res.hubp->funcs->hubp_soft_reset(mpcc_pipe->plane_res.hubp, false); 971 972 } 973 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { 974 odm_pipe->plane_res.hubp->funcs->set_blank(odm_pipe->plane_res.hubp, true); 975 /* Confirm hubp in blank */ 976 ASSERT(odm_pipe->plane_res.hubp->funcs->hubp_in_blank(odm_pipe->plane_res.hubp)); 977 /* Toggle HUBP_DISABLE */ 978 odm_pipe->plane_res.hubp->funcs->hubp_soft_reset(odm_pipe->plane_res.hubp, true); 979 odm_pipe->plane_res.hubp->funcs->hubp_soft_reset(odm_pipe->plane_res.hubp, false); 980 } 981 } else { 982 pipe_ctx->plane_res.hubp->funcs->set_blank(pipe_ctx->plane_res.hubp, false); 983 for (mpcc_pipe = pipe_ctx->bottom_pipe; mpcc_pipe; mpcc_pipe = mpcc_pipe->bottom_pipe) 984 mpcc_pipe->plane_res.hubp->funcs->set_blank(mpcc_pipe->plane_res.hubp, false); 985 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 986 odm_pipe->plane_res.hubp->funcs->set_blank(odm_pipe->plane_res.hubp, false); 987 } 988 } 989 990 void dcn30_set_disp_pattern_generator(const struct dc *dc, 991 struct pipe_ctx *pipe_ctx, 992 enum controller_dp_test_pattern test_pattern, 993 enum controller_dp_color_space color_space, 994 enum dc_color_depth color_depth, 995 const struct tg_color *solid_color, 996 int width, int height, int offset) 997 { 998 struct stream_resource *stream_res = &pipe_ctx->stream_res; 999 1000 if (test_pattern != CONTROLLER_DP_TEST_PATTERN_VIDEOMODE) { 1001 pipe_ctx->vtp_locked = false; 1002 /* turning on DPG */ 1003 stream_res->opp->funcs->opp_set_disp_pattern_generator(stream_res->opp, test_pattern, color_space, 1004 color_depth, solid_color, width, height, offset); 1005 1006 /* Defer hubp blank if tg is locked */ 1007 if (stream_res->tg->funcs->is_tg_enabled(stream_res->tg)) { 1008 if (stream_res->tg->funcs->is_locked(stream_res->tg)) 1009 pipe_ctx->vtp_locked = true; 1010 else 1011 dc->hwss.set_hubp_blank(dc, pipe_ctx, true); 1012 } 1013 } else { 1014 dc->hwss.set_hubp_blank(dc, pipe_ctx, false); 1015 /* turning off DPG */ 1016 stream_res->opp->funcs->opp_set_disp_pattern_generator(stream_res->opp, test_pattern, color_space, 1017 color_depth, solid_color, width, height, offset); 1018 } 1019 } 1020