1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 27 #include "dm_services.h" 28 #include "dm_helpers.h" 29 #include "core_types.h" 30 #include "resource.h" 31 #include "dcn30_hwseq.h" 32 #include "dccg.h" 33 #include "dce/dce_hwseq.h" 34 #include "dcn30_mpc.h" 35 #include "dcn30_dpp.h" 36 #include "dcn10/dcn10_cm_common.h" 37 #include "dcn30_cm_common.h" 38 #include "reg_helper.h" 39 #include "abm.h" 40 #include "clk_mgr.h" 41 #include "hubp.h" 42 #include "dchubbub.h" 43 #include "timing_generator.h" 44 #include "opp.h" 45 #include "ipp.h" 46 #include "mpc.h" 47 #include "mcif_wb.h" 48 #include "dc_dmub_srv.h" 49 #include "link_hwss.h" 50 #include "dpcd_defs.h" 51 #include "../dcn20/dcn20_hwseq.h" 52 #include "dcn30_resource.h" 53 #include "link.h" 54 55 56 57 58 #define DC_LOGGER_INIT(logger) 59 60 #define CTX \ 61 hws->ctx 62 #define REG(reg)\ 63 hws->regs->reg 64 #define DC_LOGGER \ 65 dc->ctx->logger 66 67 68 #undef FN 69 #define FN(reg_name, field_name) \ 70 hws->shifts->field_name, hws->masks->field_name 71 72 bool dcn30_set_blend_lut( 73 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state) 74 { 75 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; 76 bool result = true; 77 struct pwl_params *blend_lut = NULL; 78 79 if (plane_state->blend_tf) { 80 if (plane_state->blend_tf->type == TF_TYPE_HWPWL) 81 blend_lut = &plane_state->blend_tf->pwl; 82 else if (plane_state->blend_tf->type == TF_TYPE_DISTRIBUTED_POINTS) { 83 cm3_helper_translate_curve_to_hw_format( 84 plane_state->blend_tf, &dpp_base->regamma_params, false); 85 blend_lut = &dpp_base->regamma_params; 86 } 87 } 88 result = dpp_base->funcs->dpp_program_blnd_lut(dpp_base, blend_lut); 89 90 return result; 91 } 92 93 static bool dcn30_set_mpc_shaper_3dlut(struct pipe_ctx *pipe_ctx, 94 const struct dc_stream_state *stream) 95 { 96 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; 97 int mpcc_id = pipe_ctx->plane_res.hubp->inst; 98 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; 99 bool result = false; 100 int acquired_rmu = 0; 101 int mpcc_id_projected = 0; 102 103 const struct pwl_params *shaper_lut = NULL; 104 //get the shaper lut params 105 if (stream->func_shaper) { 106 if (stream->func_shaper->type == TF_TYPE_HWPWL) { 107 shaper_lut = &stream->func_shaper->pwl; 108 } else if (stream->func_shaper->type == TF_TYPE_DISTRIBUTED_POINTS) { 109 cm_helper_translate_curve_to_hw_format(stream->ctx, stream->func_shaper, 110 &dpp_base->shaper_params, true); 111 shaper_lut = &dpp_base->shaper_params; 112 } 113 } 114 115 if (stream->lut3d_func && 116 stream->lut3d_func->state.bits.initialized == 1 && 117 stream->lut3d_func->state.bits.rmu_idx_valid == 1) { 118 if (stream->lut3d_func->state.bits.rmu_mux_num == 0) 119 mpcc_id_projected = stream->lut3d_func->state.bits.mpc_rmu0_mux; 120 else if (stream->lut3d_func->state.bits.rmu_mux_num == 1) 121 mpcc_id_projected = stream->lut3d_func->state.bits.mpc_rmu1_mux; 122 else if (stream->lut3d_func->state.bits.rmu_mux_num == 2) 123 mpcc_id_projected = stream->lut3d_func->state.bits.mpc_rmu2_mux; 124 if (mpcc_id_projected != mpcc_id) 125 BREAK_TO_DEBUGGER(); 126 /* find the reason why logical layer assigned a different 127 * mpcc_id into acquire_post_bldn_3dlut 128 */ 129 acquired_rmu = mpc->funcs->acquire_rmu(mpc, mpcc_id, 130 stream->lut3d_func->state.bits.rmu_mux_num); 131 if (acquired_rmu != stream->lut3d_func->state.bits.rmu_mux_num) 132 BREAK_TO_DEBUGGER(); 133 134 result = mpc->funcs->program_3dlut(mpc, &stream->lut3d_func->lut_3d, 135 stream->lut3d_func->state.bits.rmu_mux_num); 136 result = mpc->funcs->program_shaper(mpc, shaper_lut, 137 stream->lut3d_func->state.bits.rmu_mux_num); 138 } else { 139 // loop through the available mux and release the requested mpcc_id 140 mpc->funcs->release_rmu(mpc, mpcc_id); 141 } 142 143 return result; 144 } 145 146 bool dcn30_set_input_transfer_func(struct dc *dc, 147 struct pipe_ctx *pipe_ctx, 148 const struct dc_plane_state *plane_state) 149 { 150 struct dce_hwseq *hws = dc->hwseq; 151 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; 152 enum dc_transfer_func_predefined tf; 153 bool result = true; 154 struct pwl_params *params = NULL; 155 156 if (dpp_base == NULL || plane_state == NULL) 157 return false; 158 159 tf = TRANSFER_FUNCTION_UNITY; 160 161 if (plane_state->in_transfer_func && 162 plane_state->in_transfer_func->type == TF_TYPE_PREDEFINED) 163 tf = plane_state->in_transfer_func->tf; 164 165 dpp_base->funcs->dpp_set_pre_degam(dpp_base, tf); 166 167 if (plane_state->in_transfer_func) { 168 if (plane_state->in_transfer_func->type == TF_TYPE_HWPWL) 169 params = &plane_state->in_transfer_func->pwl; 170 else if (plane_state->in_transfer_func->type == TF_TYPE_DISTRIBUTED_POINTS && 171 cm3_helper_translate_curve_to_hw_format(plane_state->in_transfer_func, 172 &dpp_base->degamma_params, false)) 173 params = &dpp_base->degamma_params; 174 } 175 176 result = dpp_base->funcs->dpp_program_gamcor_lut(dpp_base, params); 177 178 if (pipe_ctx->stream_res.opp && pipe_ctx->stream_res.opp->ctx) { 179 if (dpp_base->funcs->dpp_program_blnd_lut) 180 hws->funcs.set_blend_lut(pipe_ctx, plane_state); 181 if (dpp_base->funcs->dpp_program_shaper_lut && 182 dpp_base->funcs->dpp_program_3dlut) 183 hws->funcs.set_shaper_3dlut(pipe_ctx, plane_state); 184 } 185 186 return result; 187 } 188 189 bool dcn30_set_output_transfer_func(struct dc *dc, 190 struct pipe_ctx *pipe_ctx, 191 const struct dc_stream_state *stream) 192 { 193 int mpcc_id = pipe_ctx->plane_res.hubp->inst; 194 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; 195 struct pwl_params *params = NULL; 196 bool ret = false; 197 198 /* program OGAM or 3DLUT only for the top pipe*/ 199 if (pipe_ctx->top_pipe == NULL) { 200 /*program rmu shaper and 3dlut in MPC*/ 201 ret = dcn30_set_mpc_shaper_3dlut(pipe_ctx, stream); 202 if (ret == false && mpc->funcs->set_output_gamma && stream->out_transfer_func) { 203 if (stream->out_transfer_func->type == TF_TYPE_HWPWL) 204 params = &stream->out_transfer_func->pwl; 205 else if (pipe_ctx->stream->out_transfer_func->type == 206 TF_TYPE_DISTRIBUTED_POINTS && 207 cm3_helper_translate_curve_to_hw_format( 208 stream->out_transfer_func, 209 &mpc->blender_params, false)) 210 params = &mpc->blender_params; 211 /* there are no ROM LUTs in OUTGAM */ 212 if (stream->out_transfer_func->type == TF_TYPE_PREDEFINED) 213 BREAK_TO_DEBUGGER(); 214 } 215 } 216 217 if (mpc->funcs->set_output_gamma) 218 mpc->funcs->set_output_gamma(mpc, mpcc_id, params); 219 else 220 DC_LOG_ERROR("%s: set_output_gamma function pointer is NULL.\n", __func__); 221 222 return ret; 223 } 224 225 static void dcn30_set_writeback( 226 struct dc *dc, 227 struct dc_writeback_info *wb_info, 228 struct dc_state *context) 229 { 230 struct mcif_wb *mcif_wb; 231 struct mcif_buf_params *mcif_buf_params; 232 233 ASSERT(wb_info->dwb_pipe_inst < MAX_DWB_PIPES); 234 ASSERT(wb_info->wb_enabled); 235 ASSERT(wb_info->mpcc_inst >= 0); 236 ASSERT(wb_info->mpcc_inst < dc->res_pool->mpcc_count); 237 mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst]; 238 mcif_buf_params = &wb_info->mcif_buf_params; 239 240 /* set DWB MPC mux */ 241 dc->res_pool->mpc->funcs->set_dwb_mux(dc->res_pool->mpc, 242 wb_info->dwb_pipe_inst, wb_info->mpcc_inst); 243 /* set MCIF_WB buffer and arbitration configuration */ 244 mcif_wb->funcs->config_mcif_buf(mcif_wb, mcif_buf_params, wb_info->dwb_params.dest_height); 245 mcif_wb->funcs->config_mcif_arb(mcif_wb, &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[wb_info->dwb_pipe_inst]); 246 } 247 248 void dcn30_update_writeback( 249 struct dc *dc, 250 struct dc_writeback_info *wb_info, 251 struct dc_state *context) 252 { 253 struct dwbc *dwb; 254 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; 255 DC_LOG_DWB("%s dwb_pipe_inst = %d, mpcc_inst = %d",\ 256 __func__, wb_info->dwb_pipe_inst,\ 257 wb_info->mpcc_inst); 258 259 dcn30_set_writeback(dc, wb_info, context); 260 261 /* update DWB */ 262 dwb->funcs->update(dwb, &wb_info->dwb_params); 263 } 264 265 bool dcn30_mmhubbub_warmup( 266 struct dc *dc, 267 unsigned int num_dwb, 268 struct dc_writeback_info *wb_info) 269 { 270 struct dwbc *dwb; 271 struct mcif_wb *mcif_wb; 272 struct mcif_warmup_params warmup_params = {0}; 273 unsigned int i, i_buf; 274 /*make sure there is no active DWB eanbled */ 275 for (i = 0; i < num_dwb; i++) { 276 dwb = dc->res_pool->dwbc[wb_info[i].dwb_pipe_inst]; 277 if (dwb->dwb_is_efc_transition || dwb->dwb_is_drc) { 278 /*can not do warmup while any dwb enabled*/ 279 return false; 280 } 281 } 282 283 if (wb_info->mcif_warmup_params.p_vmid == 0) 284 return false; 285 286 /*check whether this is new interface: warmup big buffer once*/ 287 if (wb_info->mcif_warmup_params.start_address.quad_part != 0 && 288 wb_info->mcif_warmup_params.region_size != 0) { 289 /*mmhubbub is shared, so it does not matter which MCIF*/ 290 mcif_wb = dc->res_pool->mcif_wb[0]; 291 /*warmup a big chunk of VM buffer at once*/ 292 warmup_params.start_address.quad_part = wb_info->mcif_warmup_params.start_address.quad_part; 293 warmup_params.address_increment = wb_info->mcif_warmup_params.region_size; 294 warmup_params.region_size = wb_info->mcif_warmup_params.region_size; 295 warmup_params.p_vmid = wb_info->mcif_warmup_params.p_vmid; 296 297 if (warmup_params.address_increment == 0) 298 warmup_params.address_increment = dc->dml.soc.vmm_page_size_bytes; 299 300 mcif_wb->funcs->warmup_mcif(mcif_wb, &warmup_params); 301 return true; 302 } 303 /*following is the original: warmup each DWB's mcif buffer*/ 304 for (i = 0; i < num_dwb; i++) { 305 dwb = dc->res_pool->dwbc[wb_info[i].dwb_pipe_inst]; 306 mcif_wb = dc->res_pool->mcif_wb[wb_info[i].dwb_pipe_inst]; 307 /*warmup is for VM mode only*/ 308 if (wb_info[i].mcif_buf_params.p_vmid == 0) 309 return false; 310 311 /* Warmup MCIF_WB */ 312 for (i_buf = 0; i_buf < MCIF_BUF_COUNT; i_buf++) { 313 warmup_params.start_address.quad_part = wb_info[i].mcif_buf_params.luma_address[i_buf]; 314 warmup_params.address_increment = dc->dml.soc.vmm_page_size_bytes; 315 warmup_params.region_size = wb_info[i].mcif_buf_params.luma_pitch * wb_info[i].dwb_params.dest_height; 316 warmup_params.p_vmid = wb_info[i].mcif_buf_params.p_vmid; 317 mcif_wb->funcs->warmup_mcif(mcif_wb, &warmup_params); 318 } 319 } 320 return true; 321 } 322 323 void dcn30_enable_writeback( 324 struct dc *dc, 325 struct dc_writeback_info *wb_info, 326 struct dc_state *context) 327 { 328 struct dwbc *dwb; 329 struct mcif_wb *mcif_wb; 330 331 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; 332 mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst]; 333 334 DC_LOG_DWB("%s dwb_pipe_inst = %d, mpcc_inst = %d",\ 335 __func__, wb_info->dwb_pipe_inst,\ 336 wb_info->mpcc_inst); 337 /* Update writeback pipe */ 338 dcn30_set_writeback(dc, wb_info, context); 339 340 /* Enable MCIF_WB */ 341 mcif_wb->funcs->enable_mcif(mcif_wb); 342 /* Enable DWB */ 343 dwb->funcs->enable(dwb, &wb_info->dwb_params); 344 } 345 346 void dcn30_disable_writeback( 347 struct dc *dc, 348 unsigned int dwb_pipe_inst) 349 { 350 struct dwbc *dwb; 351 struct mcif_wb *mcif_wb; 352 353 ASSERT(dwb_pipe_inst < MAX_DWB_PIPES); 354 dwb = dc->res_pool->dwbc[dwb_pipe_inst]; 355 mcif_wb = dc->res_pool->mcif_wb[dwb_pipe_inst]; 356 DC_LOG_DWB("%s dwb_pipe_inst = %d",\ 357 __func__, dwb_pipe_inst); 358 359 /* disable DWB */ 360 dwb->funcs->disable(dwb); 361 /* disable MCIF */ 362 mcif_wb->funcs->disable_mcif(mcif_wb); 363 /* disable MPC DWB mux */ 364 dc->res_pool->mpc->funcs->disable_dwb_mux(dc->res_pool->mpc, dwb_pipe_inst); 365 } 366 367 void dcn30_program_all_writeback_pipes_in_tree( 368 struct dc *dc, 369 const struct dc_stream_state *stream, 370 struct dc_state *context) 371 { 372 struct dc_writeback_info wb_info; 373 struct dwbc *dwb; 374 struct dc_stream_status *stream_status = NULL; 375 int i_wb, i_pipe, i_stream; 376 DC_LOG_DWB("%s", __func__); 377 378 ASSERT(stream); 379 for (i_stream = 0; i_stream < context->stream_count; i_stream++) { 380 if (context->streams[i_stream] == stream) { 381 stream_status = &context->stream_status[i_stream]; 382 break; 383 } 384 } 385 ASSERT(stream_status); 386 387 ASSERT(stream->num_wb_info <= dc->res_pool->res_cap->num_dwb); 388 /* For each writeback pipe */ 389 for (i_wb = 0; i_wb < stream->num_wb_info; i_wb++) { 390 391 /* copy writeback info to local non-const so mpcc_inst can be set */ 392 wb_info = stream->writeback_info[i_wb]; 393 if (wb_info.wb_enabled) { 394 395 /* get the MPCC instance for writeback_source_plane */ 396 wb_info.mpcc_inst = -1; 397 for (i_pipe = 0; i_pipe < dc->res_pool->pipe_count; i_pipe++) { 398 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i_pipe]; 399 400 if (!pipe_ctx->plane_state) 401 continue; 402 403 if (pipe_ctx->plane_state == wb_info.writeback_source_plane) { 404 wb_info.mpcc_inst = pipe_ctx->plane_res.mpcc_inst; 405 break; 406 } 407 } 408 409 if (wb_info.mpcc_inst == -1) { 410 /* Disable writeback pipe and disconnect from MPCC 411 * if source plane has been removed 412 */ 413 dc->hwss.disable_writeback(dc, wb_info.dwb_pipe_inst); 414 continue; 415 } 416 417 ASSERT(wb_info.dwb_pipe_inst < dc->res_pool->res_cap->num_dwb); 418 dwb = dc->res_pool->dwbc[wb_info.dwb_pipe_inst]; 419 if (dwb->funcs->is_enabled(dwb)) { 420 /* writeback pipe already enabled, only need to update */ 421 dc->hwss.update_writeback(dc, &wb_info, context); 422 } else { 423 /* Enable writeback pipe and connect to MPCC */ 424 dc->hwss.enable_writeback(dc, &wb_info, context); 425 } 426 } else { 427 /* Disable writeback pipe and disconnect from MPCC */ 428 dc->hwss.disable_writeback(dc, wb_info.dwb_pipe_inst); 429 } 430 } 431 } 432 433 void dcn30_init_hw(struct dc *dc) 434 { 435 struct abm **abms = dc->res_pool->multiple_abms; 436 struct dce_hwseq *hws = dc->hwseq; 437 struct dc_bios *dcb = dc->ctx->dc_bios; 438 struct resource_pool *res_pool = dc->res_pool; 439 int i; 440 int edp_num; 441 uint32_t backlight = MAX_BACKLIGHT_LEVEL; 442 443 if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks) 444 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr); 445 446 // Initialize the dccg 447 if (res_pool->dccg->funcs->dccg_init) 448 res_pool->dccg->funcs->dccg_init(res_pool->dccg); 449 450 if (!dcb->funcs->is_accelerated_mode(dcb)) { 451 hws->funcs.bios_golden_init(dc); 452 hws->funcs.disable_vga(dc->hwseq); 453 } 454 455 if (dc->debug.enable_mem_low_power.bits.dmcu) { 456 // Force ERAM to shutdown if DMCU is not enabled 457 if (dc->debug.disable_dmcu || dc->config.disable_dmcu) { 458 REG_UPDATE(DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, 3); 459 } 460 } 461 462 // Set default OPTC memory power states 463 if (dc->debug.enable_mem_low_power.bits.optc) { 464 // Shutdown when unassigned and light sleep in VBLANK 465 REG_SET_2(ODM_MEM_PWR_CTRL3, 0, ODM_MEM_UNASSIGNED_PWR_MODE, 3, ODM_MEM_VBLANK_PWR_MODE, 1); 466 } 467 468 if (dc->debug.enable_mem_low_power.bits.vga) { 469 // Power down VGA memory 470 REG_UPDATE(MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, 1); 471 } 472 473 if (dc->ctx->dc_bios->fw_info_valid) { 474 res_pool->ref_clocks.xtalin_clock_inKhz = 475 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency; 476 477 if (res_pool->dccg && res_pool->hubbub) { 478 479 (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg, 480 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency, 481 &res_pool->ref_clocks.dccg_ref_clock_inKhz); 482 483 (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub, 484 res_pool->ref_clocks.dccg_ref_clock_inKhz, 485 &res_pool->ref_clocks.dchub_ref_clock_inKhz); 486 } else { 487 // Not all ASICs have DCCG sw component 488 res_pool->ref_clocks.dccg_ref_clock_inKhz = 489 res_pool->ref_clocks.xtalin_clock_inKhz; 490 res_pool->ref_clocks.dchub_ref_clock_inKhz = 491 res_pool->ref_clocks.xtalin_clock_inKhz; 492 } 493 } else 494 ASSERT_CRITICAL(false); 495 496 for (i = 0; i < dc->link_count; i++) { 497 /* Power up AND update implementation according to the 498 * required signal (which may be different from the 499 * default signal on connector). 500 */ 501 struct dc_link *link = dc->links[i]; 502 503 link->link_enc->funcs->hw_init(link->link_enc); 504 505 /* Check for enabled DIG to identify enabled display */ 506 if (link->link_enc->funcs->is_dig_enabled && 507 link->link_enc->funcs->is_dig_enabled(link->link_enc)) { 508 link->link_status.link_active = true; 509 if (link->link_enc->funcs->fec_is_active && 510 link->link_enc->funcs->fec_is_active(link->link_enc)) 511 link->fec_state = dc_link_fec_enabled; 512 } 513 } 514 515 /* we want to turn off all dp displays before doing detection */ 516 dc->link_srv->blank_all_dp_displays(dc); 517 518 if (hws->funcs.enable_power_gating_plane) 519 hws->funcs.enable_power_gating_plane(dc->hwseq, true); 520 521 /* If taking control over from VBIOS, we may want to optimize our first 522 * mode set, so we need to skip powering down pipes until we know which 523 * pipes we want to use. 524 * Otherwise, if taking control is not possible, we need to power 525 * everything down. 526 */ 527 if (dcb->funcs->is_accelerated_mode(dcb) || !dc->config.seamless_boot_edp_requested) { 528 hws->funcs.init_pipes(dc, dc->current_state); 529 if (dc->res_pool->hubbub->funcs->allow_self_refresh_control) 530 dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, 531 !dc->res_pool->hubbub->ctx->dc->debug.disable_stutter); 532 } 533 534 /* In headless boot cases, DIG may be turned 535 * on which causes HW/SW discrepancies. 536 * To avoid this, power down hardware on boot 537 * if DIG is turned on and seamless boot not enabled 538 */ 539 if (!dc->config.seamless_boot_edp_requested) { 540 struct dc_link *edp_links[MAX_NUM_EDP]; 541 struct dc_link *edp_link = NULL; 542 543 dc_get_edp_links(dc, edp_links, &edp_num); 544 if (edp_num) 545 edp_link = edp_links[0]; 546 if (edp_link && edp_link->link_enc->funcs->is_dig_enabled && 547 edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc) && 548 dc->hwss.edp_backlight_control && 549 dc->hwss.power_down && 550 dc->hwss.edp_power_control) { 551 dc->hwss.edp_backlight_control(edp_link, false); 552 dc->hwss.power_down(dc); 553 dc->hwss.edp_power_control(edp_link, false); 554 } else { 555 for (i = 0; i < dc->link_count; i++) { 556 struct dc_link *link = dc->links[i]; 557 558 if (link->link_enc->funcs->is_dig_enabled && 559 link->link_enc->funcs->is_dig_enabled(link->link_enc) && 560 dc->hwss.power_down) { 561 dc->hwss.power_down(dc); 562 break; 563 } 564 565 } 566 } 567 } 568 569 for (i = 0; i < res_pool->audio_count; i++) { 570 struct audio *audio = res_pool->audios[i]; 571 572 audio->funcs->hw_init(audio); 573 } 574 575 for (i = 0; i < dc->link_count; i++) { 576 struct dc_link *link = dc->links[i]; 577 578 if (link->panel_cntl) 579 backlight = link->panel_cntl->funcs->hw_init(link->panel_cntl); 580 } 581 582 for (i = 0; i < dc->res_pool->pipe_count; i++) { 583 if (abms[i] != NULL) 584 abms[i]->funcs->abm_init(abms[i], backlight); 585 } 586 587 /* power AFMT HDMI memory TODO: may move to dis/en output save power*/ 588 REG_WRITE(DIO_MEM_PWR_CTRL, 0); 589 590 if (!dc->debug.disable_clock_gate) { 591 /* enable all DCN clock gating */ 592 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); 593 594 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); 595 596 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); 597 } 598 599 if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks) 600 dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub); 601 602 if (dc->clk_mgr->funcs->notify_wm_ranges) 603 dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr); 604 605 //if softmax is enabled then hardmax will be set by a different call 606 if (dc->clk_mgr->funcs->set_hard_max_memclk && !dc->clk_mgr->dc_mode_softmax_enabled) 607 dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr); 608 609 if (dc->res_pool->hubbub->funcs->force_pstate_change_control) 610 dc->res_pool->hubbub->funcs->force_pstate_change_control( 611 dc->res_pool->hubbub, false, false); 612 if (dc->res_pool->hubbub->funcs->init_crb) 613 dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub); 614 615 // Get DMCUB capabilities 616 dc_dmub_srv_query_caps_cmd(dc->ctx->dmub_srv); 617 dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr; 618 dc->caps.dmub_caps.mclk_sw = dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch; 619 } 620 621 void dcn30_set_avmute(struct pipe_ctx *pipe_ctx, bool enable) 622 { 623 if (pipe_ctx == NULL) 624 return; 625 626 if (dc_is_hdmi_signal(pipe_ctx->stream->signal) && pipe_ctx->stream_res.stream_enc != NULL) { 627 pipe_ctx->stream_res.stream_enc->funcs->set_avmute( 628 pipe_ctx->stream_res.stream_enc, 629 enable); 630 631 /* Wait for two frame to make sure AV mute is sent out */ 632 if (enable) { 633 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE); 634 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VBLANK); 635 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE); 636 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VBLANK); 637 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE); 638 } 639 } 640 } 641 642 void dcn30_update_info_frame(struct pipe_ctx *pipe_ctx) 643 { 644 bool is_hdmi_tmds; 645 bool is_dp; 646 647 ASSERT(pipe_ctx->stream); 648 649 if (pipe_ctx->stream_res.stream_enc == NULL) 650 return; /* this is not root pipe */ 651 652 is_hdmi_tmds = dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal); 653 is_dp = dc_is_dp_signal(pipe_ctx->stream->signal); 654 655 if (!is_hdmi_tmds && !is_dp) 656 return; 657 658 if (is_hdmi_tmds) 659 pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets( 660 pipe_ctx->stream_res.stream_enc, 661 &pipe_ctx->stream_res.encoder_info_frame); 662 else { 663 if (pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets_sdp_line_num) 664 pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets_sdp_line_num( 665 pipe_ctx->stream_res.stream_enc, 666 &pipe_ctx->stream_res.encoder_info_frame); 667 668 pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets( 669 pipe_ctx->stream_res.stream_enc, 670 &pipe_ctx->stream_res.encoder_info_frame); 671 } 672 } 673 674 void dcn30_program_dmdata_engine(struct pipe_ctx *pipe_ctx) 675 { 676 struct dc_stream_state *stream = pipe_ctx->stream; 677 struct hubp *hubp = pipe_ctx->plane_res.hubp; 678 bool enable = false; 679 struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc; 680 enum dynamic_metadata_mode mode = dc_is_dp_signal(stream->signal) 681 ? dmdata_dp 682 : dmdata_hdmi; 683 684 /* if using dynamic meta, don't set up generic infopackets */ 685 if (pipe_ctx->stream->dmdata_address.quad_part != 0) { 686 pipe_ctx->stream_res.encoder_info_frame.hdrsmd.valid = false; 687 enable = true; 688 } 689 690 if (!hubp) 691 return; 692 693 if (!stream_enc || !stream_enc->funcs->set_dynamic_metadata) 694 return; 695 696 stream_enc->funcs->set_dynamic_metadata(stream_enc, enable, 697 hubp->inst, mode); 698 } 699 700 bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable) 701 { 702 union dmub_rb_cmd cmd; 703 uint32_t tmr_delay = 0, tmr_scale = 0; 704 struct dc_cursor_attributes cursor_attr; 705 bool cursor_cache_enable = false; 706 struct dc_stream_state *stream = NULL; 707 struct dc_plane_state *plane = NULL; 708 709 if (!dc->ctx->dmub_srv) 710 return false; 711 712 if (enable) { 713 if (dc->current_state) { 714 int i; 715 716 /* First, check no-memory-requests case */ 717 for (i = 0; i < dc->current_state->stream_count; i++) { 718 if (dc->current_state->stream_status[i].plane_count) 719 /* Fail eligibility on a visible stream */ 720 break; 721 } 722 723 if (i == dc->current_state->stream_count) { 724 /* Enable no-memory-requests case */ 725 memset(&cmd, 0, sizeof(cmd)); 726 cmd.mall.header.type = DMUB_CMD__MALL; 727 cmd.mall.header.sub_type = DMUB_CMD__MALL_ACTION_NO_DF_REQ; 728 cmd.mall.header.payload_bytes = sizeof(cmd.mall) - sizeof(cmd.mall.header); 729 730 dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_NO_WAIT); 731 732 return true; 733 } 734 735 stream = dc->current_state->streams[0]; 736 plane = (stream ? dc->current_state->stream_status[0].plane_states[0] : NULL); 737 738 if (!stream || !plane) 739 return false; 740 741 if (stream && plane) { 742 cursor_cache_enable = stream->cursor_position.enable && 743 plane->address.grph.cursor_cache_addr.quad_part; 744 cursor_attr = stream->cursor_attributes; 745 } 746 747 /* 748 * Second, check MALL eligibility 749 * 750 * single display only, single surface only, 8 and 16 bit formats only, no VM, 751 * do not use MALL for displays that support PSR as they use D0i3.2 in DMCUB FW 752 * 753 * TODO: When we implement multi-display, PSR displays will be allowed if there is 754 * a non-PSR display present, since in that case we can't do D0i3.2 755 */ 756 if (dc->current_state->stream_count == 1 && 757 stream->link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED && 758 dc->current_state->stream_status[0].plane_count == 1 && 759 plane->format <= SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F && 760 plane->format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB8888 && 761 plane->address.page_table_base.quad_part == 0 && 762 dc->hwss.does_plane_fit_in_mall && 763 dc->hwss.does_plane_fit_in_mall(dc, plane, 764 cursor_cache_enable ? &cursor_attr : NULL)) { 765 unsigned int v_total = stream->adjust.v_total_max ? 766 stream->adjust.v_total_max : stream->timing.v_total; 767 unsigned int refresh_hz = div_u64((unsigned long long) stream->timing.pix_clk_100hz * 768 100LL, (v_total * stream->timing.h_total)); 769 770 /* 771 * one frame time in microsec: 772 * Delay_Us = 1000000 / refresh 773 * dynamic_delay_us = 1000000 / refresh + 2 * stutter_period 774 * 775 * one frame time modified by 'additional timer percent' (p): 776 * Delay_Us_modified = dynamic_delay_us + dynamic_delay_us * p / 100 777 * = dynamic_delay_us * (1 + p / 100) 778 * = (1000000 / refresh + 2 * stutter_period) * (100 + p) / 100 779 * = (1000000 + 2 * stutter_period * refresh) * (100 + p) / (100 * refresh) 780 * 781 * formula for timer duration based on parameters, from regspec: 782 * dynamic_delay_us = 65.28 * (64 + MallFrameCacheTmrDly) * 2^MallFrameCacheTmrScale 783 * 784 * dynamic_delay_us / 65.28 = (64 + MallFrameCacheTmrDly) * 2^MallFrameCacheTmrScale 785 * (dynamic_delay_us / 65.28) / 2^MallFrameCacheTmrScale = 64 + MallFrameCacheTmrDly 786 * MallFrameCacheTmrDly = ((dynamic_delay_us / 65.28) / 2^MallFrameCacheTmrScale) - 64 787 * = (1000000 + 2 * stutter_period * refresh) * (100 + p) / (100 * refresh) / 65.28 / 2^MallFrameCacheTmrScale - 64 788 * = (1000000 + 2 * stutter_period * refresh) * (100 + p) / (refresh * 6528 * 2^MallFrameCacheTmrScale) - 64 789 * 790 * need to round up the result of the division before the subtraction 791 */ 792 unsigned int denom = refresh_hz * 6528; 793 unsigned int stutter_period = dc->current_state->perf_params.stutter_period_us; 794 795 tmr_delay = div_u64(((1000000LL + 2 * stutter_period * refresh_hz) * 796 (100LL + dc->debug.mall_additional_timer_percent) + denom - 1), 797 denom) - 64LL; 798 799 /* In some cases the stutter period is really big (tiny modes) in these 800 * cases MALL cant be enabled, So skip these cases to avoid a ASSERT() 801 * 802 * We can check if stutter_period is more than 1/10th the frame time to 803 * consider if we can actually meet the range of hysteresis timer 804 */ 805 if (stutter_period > 100000/refresh_hz) 806 return false; 807 808 /* scale should be increased until it fits into 6 bits */ 809 while (tmr_delay & ~0x3F) { 810 tmr_scale++; 811 812 if (tmr_scale > 3) { 813 /* Delay exceeds range of hysteresis timer */ 814 ASSERT(false); 815 return false; 816 } 817 818 denom *= 2; 819 tmr_delay = div_u64(((1000000LL + 2 * stutter_period * refresh_hz) * 820 (100LL + dc->debug.mall_additional_timer_percent) + denom - 1), 821 denom) - 64LL; 822 } 823 824 /* Copy HW cursor */ 825 if (cursor_cache_enable) { 826 memset(&cmd, 0, sizeof(cmd)); 827 cmd.mall.header.type = DMUB_CMD__MALL; 828 cmd.mall.header.sub_type = DMUB_CMD__MALL_ACTION_COPY_CURSOR; 829 cmd.mall.header.payload_bytes = 830 sizeof(cmd.mall) - sizeof(cmd.mall.header); 831 832 switch (cursor_attr.color_format) { 833 case CURSOR_MODE_MONO: 834 cmd.mall.cursor_bpp = 2; 835 break; 836 case CURSOR_MODE_COLOR_1BIT_AND: 837 case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA: 838 case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA: 839 cmd.mall.cursor_bpp = 32; 840 break; 841 842 case CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED: 843 case CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED: 844 cmd.mall.cursor_bpp = 64; 845 break; 846 } 847 848 cmd.mall.cursor_copy_src.quad_part = cursor_attr.address.quad_part; 849 cmd.mall.cursor_copy_dst.quad_part = 850 (plane->address.grph.cursor_cache_addr.quad_part + 2047) & ~2047; 851 cmd.mall.cursor_width = cursor_attr.width; 852 cmd.mall.cursor_height = cursor_attr.height; 853 cmd.mall.cursor_pitch = cursor_attr.pitch; 854 855 dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT); 856 857 /* Use copied cursor, and it's okay to not switch back */ 858 cursor_attr.address.quad_part = cmd.mall.cursor_copy_dst.quad_part; 859 dc_stream_set_cursor_attributes(stream, &cursor_attr); 860 } 861 862 /* Enable MALL */ 863 memset(&cmd, 0, sizeof(cmd)); 864 cmd.mall.header.type = DMUB_CMD__MALL; 865 cmd.mall.header.sub_type = DMUB_CMD__MALL_ACTION_ALLOW; 866 cmd.mall.header.payload_bytes = sizeof(cmd.mall) - sizeof(cmd.mall.header); 867 cmd.mall.tmr_delay = tmr_delay; 868 cmd.mall.tmr_scale = tmr_scale; 869 cmd.mall.debug_bits = dc->debug.mall_error_as_fatal; 870 871 dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_NO_WAIT); 872 873 return true; 874 } 875 } 876 877 /* No applicable optimizations */ 878 return false; 879 } 880 881 /* Disable MALL */ 882 memset(&cmd, 0, sizeof(cmd)); 883 cmd.mall.header.type = DMUB_CMD__MALL; 884 cmd.mall.header.sub_type = DMUB_CMD__MALL_ACTION_DISALLOW; 885 cmd.mall.header.payload_bytes = 886 sizeof(cmd.mall) - sizeof(cmd.mall.header); 887 888 dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT); 889 890 return true; 891 } 892 893 bool dcn30_does_plane_fit_in_mall(struct dc *dc, struct dc_plane_state *plane, struct dc_cursor_attributes *cursor_attr) 894 { 895 // add meta size? 896 unsigned int surface_size = plane->plane_size.surface_pitch * plane->plane_size.surface_size.height * 897 (plane->format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616 ? 8 : 4); 898 unsigned int mall_size = dc->caps.mall_size_total; 899 unsigned int cursor_size = 0; 900 901 if (dc->debug.mall_size_override) 902 mall_size = 1024 * 1024 * dc->debug.mall_size_override; 903 904 if (cursor_attr) { 905 cursor_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size; 906 907 switch (cursor_attr->color_format) { 908 case CURSOR_MODE_MONO: 909 cursor_size /= 2; 910 break; 911 case CURSOR_MODE_COLOR_1BIT_AND: 912 case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA: 913 case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA: 914 cursor_size *= 4; 915 break; 916 917 case CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED: 918 case CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED: 919 cursor_size *= 8; 920 break; 921 } 922 } 923 924 return (surface_size + cursor_size) < mall_size; 925 } 926 927 void dcn30_hardware_release(struct dc *dc) 928 { 929 bool subvp_in_use = false; 930 uint32_t i; 931 932 dc_dmub_srv_p_state_delegate(dc, false, NULL); 933 dc_dmub_setup_subvp_dmub_command(dc, dc->current_state, false); 934 935 /* SubVP treated the same way as FPO. If driver disable and 936 * we are using a SubVP config, disable and force on DCN side 937 * to prevent P-State hang on driver enable. 938 */ 939 for (i = 0; i < dc->res_pool->pipe_count; i++) { 940 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i]; 941 942 if (!pipe->stream) 943 continue; 944 945 if (pipe->stream->mall_stream_config.type == SUBVP_MAIN) { 946 subvp_in_use = true; 947 break; 948 } 949 } 950 /* If pstate unsupported, or still supported 951 * by firmware, force it supported by dcn 952 */ 953 if (dc->current_state) 954 if ((!dc->clk_mgr->clks.p_state_change_support || subvp_in_use || 955 dc->current_state->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) && 956 dc->res_pool->hubbub->funcs->force_pstate_change_control) 957 dc->res_pool->hubbub->funcs->force_pstate_change_control( 958 dc->res_pool->hubbub, true, true); 959 } 960 961 void dcn30_set_disp_pattern_generator(const struct dc *dc, 962 struct pipe_ctx *pipe_ctx, 963 enum controller_dp_test_pattern test_pattern, 964 enum controller_dp_color_space color_space, 965 enum dc_color_depth color_depth, 966 const struct tg_color *solid_color, 967 int width, int height, int offset) 968 { 969 pipe_ctx->stream_res.opp->funcs->opp_set_disp_pattern_generator(pipe_ctx->stream_res.opp, test_pattern, 970 color_space, color_depth, solid_color, width, height, offset); 971 } 972 973 void dcn30_prepare_bandwidth(struct dc *dc, 974 struct dc_state *context) 975 { 976 bool p_state_change_support = context->bw_ctx.bw.dcn.clk.p_state_change_support; 977 /* Any transition into an FPO config should disable MCLK switching first to avoid 978 * driver and FW P-State synchronization issues. 979 */ 980 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching || dc->clk_mgr->clks.fw_based_mclk_switching) { 981 dc->optimized_required = true; 982 context->bw_ctx.bw.dcn.clk.p_state_change_support = false; 983 } 984 985 if (dc->clk_mgr->dc_mode_softmax_enabled) 986 if (dc->clk_mgr->clks.dramclk_khz <= dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000 && 987 context->bw_ctx.bw.dcn.clk.dramclk_khz > dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000) 988 dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, dc->clk_mgr->bw_params->clk_table.entries[dc->clk_mgr->bw_params->clk_table.num_entries - 1].memclk_mhz); 989 990 dcn20_prepare_bandwidth(dc, context); 991 /* 992 * enabled -> enabled: do not disable 993 * enabled -> disabled: disable 994 * disabled -> enabled: don't care 995 * disabled -> disabled: don't care 996 */ 997 if (!context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) 998 dc_dmub_srv_p_state_delegate(dc, false, context); 999 1000 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching || dc->clk_mgr->clks.fw_based_mclk_switching) { 1001 /* After disabling P-State, restore the original value to ensure we get the correct P-State 1002 * on the next optimize. */ 1003 context->bw_ctx.bw.dcn.clk.p_state_change_support = p_state_change_support; 1004 } 1005 } 1006 1007 void dcn30_set_static_screen_control(struct pipe_ctx **pipe_ctx, 1008 int num_pipes, const struct dc_static_screen_params *params) 1009 { 1010 unsigned int i; 1011 unsigned int triggers = 0; 1012 1013 if (params->triggers.surface_update) 1014 triggers |= 0x100; 1015 if (params->triggers.cursor_update) 1016 triggers |= 0x8; 1017 if (params->triggers.force_trigger) 1018 triggers |= 0x1; 1019 1020 for (i = 0; i < num_pipes; i++) 1021 pipe_ctx[i]->stream_res.tg->funcs->set_static_screen_control(pipe_ctx[i]->stream_res.tg, 1022 triggers, params->num_frames); 1023 } 1024