1 /* Copyright 2020 Advanced Micro Devices, Inc.
2  *
3  * Permission is hereby granted, free of charge, to any person obtaining a
4  * copy of this software and associated documentation files (the "Software"),
5  * to deal in the Software without restriction, including without limitation
6  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
7  * and/or sell copies of the Software, and to permit persons to whom the
8  * Software is furnished to do so, subject to the following conditions:
9  *
10  * The above copyright notice and this permission notice shall be included in
11  * all copies or substantial portions of the Software.
12  *
13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
16  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
17  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
18  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
19  * OTHER DEALINGS IN THE SOFTWARE.
20  *
21  * Authors: AMD
22  *
23  */
24 
25 #ifndef __DCN30_DPP_H__
26 #define __DCN30_DPP_H__
27 
28 #include "dcn20/dcn20_dpp.h"
29 
30 #define TO_DCN30_DPP(dpp)\
31 	container_of(dpp, struct dcn3_dpp, base)
32 
33 #define DPP_REG_LIST_DCN30_COMMON(id)\
34 	SRI(CM_DEALPHA, CM, id),\
35 	SRI(CM_MEM_PWR_STATUS, CM, id),\
36 	SRI(CM_BIAS_CR_R, CM, id),\
37 	SRI(CM_BIAS_Y_G_CB_B, CM, id),\
38 	SRI(PRE_DEGAM, CNVC_CFG, id),\
39 	SRI(CM_GAMCOR_CONTROL, CM, id),\
40 	SRI(CM_GAMCOR_LUT_CONTROL, CM, id),\
41 	SRI(CM_GAMCOR_LUT_INDEX, CM, id),\
42 	SRI(CM_GAMCOR_LUT_INDEX, CM, id),\
43 	SRI(CM_GAMCOR_LUT_DATA, CM, id),\
44 	SRI(CM_GAMCOR_RAMB_START_CNTL_B, CM, id),\
45 	SRI(CM_GAMCOR_RAMB_START_CNTL_G, CM, id),\
46 	SRI(CM_GAMCOR_RAMB_START_CNTL_R, CM, id),\
47 	SRI(CM_GAMCOR_RAMB_START_SLOPE_CNTL_B, CM, id),\
48 	SRI(CM_GAMCOR_RAMB_START_SLOPE_CNTL_G, CM, id),\
49 	SRI(CM_GAMCOR_RAMB_START_SLOPE_CNTL_R, CM, id),\
50 	SRI(CM_GAMCOR_RAMB_END_CNTL1_B, CM, id),\
51 	SRI(CM_GAMCOR_RAMB_END_CNTL2_B, CM, id),\
52 	SRI(CM_GAMCOR_RAMB_END_CNTL1_G, CM, id),\
53 	SRI(CM_GAMCOR_RAMB_END_CNTL2_G, CM, id),\
54 	SRI(CM_GAMCOR_RAMB_END_CNTL1_R, CM, id),\
55 	SRI(CM_GAMCOR_RAMB_END_CNTL2_R, CM, id),\
56 	SRI(CM_GAMCOR_RAMB_REGION_0_1, CM, id),\
57 	SRI(CM_GAMCOR_RAMB_REGION_32_33, CM, id),\
58 	SRI(CM_GAMCOR_RAMB_OFFSET_B, CM, id),\
59 	SRI(CM_GAMCOR_RAMB_OFFSET_G, CM, id),\
60 	SRI(CM_GAMCOR_RAMB_OFFSET_R, CM, id),\
61 	SRI(CM_GAMCOR_RAMB_START_BASE_CNTL_B, CM, id),\
62 	SRI(CM_GAMCOR_RAMB_START_BASE_CNTL_G, CM, id),\
63 	SRI(CM_GAMCOR_RAMB_START_BASE_CNTL_R, CM, id),\
64 	SRI(CM_GAMCOR_RAMA_START_CNTL_B, CM, id),\
65 	SRI(CM_GAMCOR_RAMA_START_CNTL_G, CM, id),\
66 	SRI(CM_GAMCOR_RAMA_START_CNTL_R, CM, id),\
67 	SRI(CM_GAMCOR_RAMA_START_SLOPE_CNTL_B, CM, id),\
68 	SRI(CM_GAMCOR_RAMA_START_SLOPE_CNTL_G, CM, id),\
69 	SRI(CM_GAMCOR_RAMA_START_SLOPE_CNTL_R, CM, id),\
70 	SRI(CM_GAMCOR_RAMA_END_CNTL1_B, CM, id),\
71 	SRI(CM_GAMCOR_RAMA_END_CNTL2_B, CM, id),\
72 	SRI(CM_GAMCOR_RAMA_END_CNTL1_G, CM, id),\
73 	SRI(CM_GAMCOR_RAMA_END_CNTL2_G, CM, id),\
74 	SRI(CM_GAMCOR_RAMA_END_CNTL1_R, CM, id),\
75 	SRI(CM_GAMCOR_RAMA_END_CNTL2_R, CM, id),\
76 	SRI(CM_GAMCOR_RAMA_REGION_0_1, CM, id),\
77 	SRI(CM_GAMCOR_RAMA_REGION_32_33, CM, id),\
78 	SRI(CM_GAMCOR_RAMA_OFFSET_B, CM, id),\
79 	SRI(CM_GAMCOR_RAMA_OFFSET_G, CM, id),\
80 	SRI(CM_GAMCOR_RAMA_OFFSET_R, CM, id),\
81 	SRI(CM_GAMCOR_RAMA_START_BASE_CNTL_B, CM, id),\
82 	SRI(CM_GAMCOR_RAMA_START_BASE_CNTL_G, CM, id),\
83 	SRI(CM_GAMCOR_RAMA_START_BASE_CNTL_R, CM, id),\
84 	SRI(CM_GAMUT_REMAP_CONTROL, CM, id),\
85 	SRI(CM_GAMUT_REMAP_C11_C12, CM, id),\
86 	SRI(CM_GAMUT_REMAP_C13_C14, CM, id),\
87 	SRI(CM_GAMUT_REMAP_C21_C22, CM, id),\
88 	SRI(CM_GAMUT_REMAP_C23_C24, CM, id),\
89 	SRI(CM_GAMUT_REMAP_C31_C32, CM, id),\
90 	SRI(CM_GAMUT_REMAP_C33_C34, CM, id),\
91 	SRI(CM_GAMUT_REMAP_B_C11_C12, CM, id),\
92 	SRI(CM_GAMUT_REMAP_B_C13_C14, CM, id),\
93 	SRI(CM_GAMUT_REMAP_B_C21_C22, CM, id),\
94 	SRI(CM_GAMUT_REMAP_B_C23_C24, CM, id),\
95 	SRI(CM_GAMUT_REMAP_B_C31_C32, CM, id),\
96 	SRI(CM_GAMUT_REMAP_B_C33_C34, CM, id),\
97 	SRI(DSCL_EXT_OVERSCAN_LEFT_RIGHT, DSCL, id), \
98 	SRI(DSCL_EXT_OVERSCAN_TOP_BOTTOM, DSCL, id), \
99 	SRI(OTG_H_BLANK, DSCL, id), \
100 	SRI(OTG_V_BLANK, DSCL, id), \
101 	SRI(SCL_MODE, DSCL, id), \
102 	SRI(LB_DATA_FORMAT, DSCL, id), \
103 	SRI(LB_MEMORY_CTRL, DSCL, id), \
104 	SRI(DSCL_AUTOCAL, DSCL, id), \
105 	SRI(SCL_TAP_CONTROL, DSCL, id), \
106 	SRI(SCL_COEF_RAM_TAP_SELECT, DSCL, id), \
107 	SRI(SCL_COEF_RAM_TAP_DATA, DSCL, id), \
108 	SRI(DSCL_2TAP_CONTROL, DSCL, id), \
109 	SRI(MPC_SIZE, DSCL, id), \
110 	SRI(SCL_HORZ_FILTER_SCALE_RATIO, DSCL, id), \
111 	SRI(SCL_VERT_FILTER_SCALE_RATIO, DSCL, id), \
112 	SRI(SCL_HORZ_FILTER_SCALE_RATIO_C, DSCL, id), \
113 	SRI(SCL_VERT_FILTER_SCALE_RATIO_C, DSCL, id), \
114 	SRI(SCL_HORZ_FILTER_INIT, DSCL, id), \
115 	SRI(SCL_HORZ_FILTER_INIT_C, DSCL, id), \
116 	SRI(SCL_VERT_FILTER_INIT, DSCL, id), \
117 	SRI(SCL_VERT_FILTER_INIT_C, DSCL, id), \
118 	SRI(RECOUT_START, DSCL, id), \
119 	SRI(RECOUT_SIZE, DSCL, id), \
120 	SRI(PRE_DEALPHA, CNVC_CFG, id), \
121 	SRI(PRE_REALPHA, CNVC_CFG, id), \
122 	SRI(PRE_CSC_MODE, CNVC_CFG, id), \
123 	SRI(PRE_CSC_C11_C12, CNVC_CFG, id), \
124 	SRI(PRE_CSC_C33_C34, CNVC_CFG, id), \
125 	SRI(PRE_CSC_B_C11_C12, CNVC_CFG, id), \
126 	SRI(PRE_CSC_B_C33_C34, CNVC_CFG, id), \
127 	SRI(CM_POST_CSC_CONTROL, CM, id), \
128 	SRI(CM_POST_CSC_C11_C12, CM, id), \
129 	SRI(CM_POST_CSC_C33_C34, CM, id), \
130 	SRI(CM_POST_CSC_B_C11_C12, CM, id), \
131 	SRI(CM_POST_CSC_B_C33_C34, CM, id), \
132 	SRI(CM_MEM_PWR_CTRL, CM, id), \
133 	SRI(CM_CONTROL, CM, id), \
134 	SRI(FORMAT_CONTROL, CNVC_CFG, id), \
135 	SRI(CNVC_SURFACE_PIXEL_FORMAT, CNVC_CFG, id), \
136 	SRI(CURSOR0_CONTROL, CNVC_CUR, id), \
137 	SRI(CURSOR0_COLOR0, CNVC_CUR, id), \
138 	SRI(CURSOR0_COLOR1, CNVC_CUR, id), \
139 	SRI(CURSOR0_FP_SCALE_BIAS, CNVC_CUR, id), \
140 	SRI(DPP_CONTROL, DPP_TOP, id), \
141 	SRI(CM_HDR_MULT_COEF, CM, id), \
142 	SRI(CURSOR_CONTROL, CURSOR0_, id), \
143 	SRI(ALPHA_2BIT_LUT, CNVC_CFG, id), \
144 	SRI(FCNV_FP_BIAS_R, CNVC_CFG, id), \
145 	SRI(FCNV_FP_BIAS_G, CNVC_CFG, id), \
146 	SRI(FCNV_FP_BIAS_B, CNVC_CFG, id), \
147 	SRI(FCNV_FP_SCALE_R, CNVC_CFG, id), \
148 	SRI(FCNV_FP_SCALE_G, CNVC_CFG, id), \
149 	SRI(FCNV_FP_SCALE_B, CNVC_CFG, id), \
150 	SRI(COLOR_KEYER_CONTROL, CNVC_CFG, id), \
151 	SRI(COLOR_KEYER_ALPHA, CNVC_CFG, id), \
152 	SRI(COLOR_KEYER_RED, CNVC_CFG, id), \
153 	SRI(COLOR_KEYER_GREEN, CNVC_CFG, id), \
154 	SRI(COLOR_KEYER_BLUE, CNVC_CFG, id), \
155 	SRI(CURSOR_CONTROL, CURSOR0_, id),\
156 	SRI(OBUF_MEM_PWR_CTRL, DSCL, id),\
157 	SRI(DSCL_MEM_PWR_STATUS, DSCL, id), \
158 	SRI(DSCL_MEM_PWR_CTRL, DSCL, id)
159 
160 #define DPP_REG_LIST_DCN30(id)\
161 	DPP_REG_LIST_DCN30_COMMON(id), \
162 	TF_REG_LIST_DCN20_COMMON(id), \
163 	SRI(CM_BLNDGAM_CONTROL, CM, id), \
164 	SRI(CM_SHAPER_LUT_DATA, CM, id),\
165 	SRI(CM_MEM_PWR_CTRL2, CM, id), \
166 	SRI(CM_MEM_PWR_STATUS2, CM, id), \
167 	SRI(CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B, CM, id),\
168 	SRI(CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G, CM, id),\
169 	SRI(CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R, CM, id),\
170 	SRI(CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B, CM, id),\
171 	SRI(CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G, CM, id),\
172 	SRI(CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R, CM, id),\
173 	SRI(CM_BLNDGAM_LUT_CONTROL, CM, id)
174 
175 
176 
177 #define DPP_REG_LIST_SH_MASK_DCN30_COMMON(mask_sh)\
178 	TF_SF(CM0_CM_MEM_PWR_STATUS, GAMCOR_MEM_PWR_STATE, mask_sh),\
179 	TF_SF(CM0_CM_DEALPHA, CM_DEALPHA_EN, mask_sh),\
180 	TF_SF(CM0_CM_DEALPHA, CM_DEALPHA_ABLND, mask_sh),\
181 	TF_SF(CM0_CM_BIAS_CR_R, CM_BIAS_CR_R, mask_sh),\
182 	TF_SF(CM0_CM_BIAS_Y_G_CB_B, CM_BIAS_Y_G, mask_sh),\
183 	TF_SF(CM0_CM_BIAS_Y_G_CB_B, CM_BIAS_CB_B, mask_sh),\
184 	TF_SF(CM0_CM_MEM_PWR_CTRL, GAMCOR_MEM_PWR_DIS, mask_sh),\
185 	TF_SF(CM0_CM_MEM_PWR_CTRL, GAMCOR_MEM_PWR_FORCE, mask_sh),\
186 	TF_SF(CNVC_CFG0_PRE_DEGAM, PRE_DEGAM_MODE, mask_sh),\
187 	TF_SF(CNVC_CFG0_PRE_DEGAM, PRE_DEGAM_SELECT, mask_sh),\
188 	TF_SF(CM0_CM_GAMCOR_CONTROL, CM_GAMCOR_MODE, mask_sh),\
189 	TF_SF(CM0_CM_GAMCOR_CONTROL, CM_GAMCOR_SELECT, mask_sh),\
190 	TF_SF(CM0_CM_GAMCOR_CONTROL, CM_GAMCOR_PWL_DISABLE, mask_sh),\
191 	TF_SF(CM0_CM_GAMCOR_CONTROL, CM_GAMCOR_MODE_CURRENT, mask_sh),\
192 	TF_SF(CM0_CM_GAMCOR_CONTROL, CM_GAMCOR_SELECT_CURRENT, mask_sh),\
193 	TF_SF(CM0_CM_GAMCOR_LUT_INDEX, CM_GAMCOR_LUT_INDEX, mask_sh),\
194 	TF_SF(CM0_CM_GAMCOR_LUT_DATA, CM_GAMCOR_LUT_DATA, mask_sh),\
195 	TF_SF(CM0_CM_GAMCOR_LUT_CONTROL, CM_GAMCOR_LUT_WRITE_COLOR_MASK, mask_sh),\
196 	TF_SF(CM0_CM_GAMCOR_LUT_CONTROL, CM_GAMCOR_LUT_READ_COLOR_SEL, mask_sh),\
197 	TF_SF(CM0_CM_GAMCOR_LUT_CONTROL, CM_GAMCOR_LUT_READ_DBG, mask_sh),\
198 	TF_SF(CM0_CM_GAMCOR_LUT_CONTROL, CM_GAMCOR_LUT_HOST_SEL, mask_sh),\
199 	TF_SF(CM0_CM_GAMCOR_LUT_CONTROL, CM_GAMCOR_LUT_CONFIG_MODE, mask_sh),\
200 	TF_SF(CM0_CM_GAMCOR_RAMA_START_CNTL_B, CM_GAMCOR_RAMA_EXP_REGION_START_B, mask_sh),\
201 	TF_SF(CM0_CM_GAMCOR_RAMA_START_CNTL_B, CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh),\
202 	TF_SF(CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B, CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B, mask_sh),\
203 	TF_SF(CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B, CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B, mask_sh),\
204 	TF_SF(CM0_CM_GAMCOR_RAMA_END_CNTL1_B, CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B, mask_sh),\
205 	TF_SF(CM0_CM_GAMCOR_RAMA_END_CNTL2_B, CM_GAMCOR_RAMA_EXP_REGION_END_B, mask_sh),\
206 	TF_SF(CM0_CM_GAMCOR_RAMA_END_CNTL2_B, CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B, mask_sh),\
207 	TF_SF(CM0_CM_GAMCOR_RAMA_OFFSET_B, CM_GAMCOR_RAMA_OFFSET_B, mask_sh),\
208 	TF_SF(CM0_CM_GAMCOR_RAMA_REGION_0_1, CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh),\
209 	TF_SF(CM0_CM_GAMCOR_RAMA_REGION_0_1, CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\
210 	TF_SF(CM0_CM_GAMCOR_RAMA_REGION_0_1, CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh),\
211 	TF_SF(CM0_CM_GAMCOR_RAMA_REGION_0_1, CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\
212 	TF_SF(CM0_CM_GAMUT_REMAP_CONTROL, CM_GAMUT_REMAP_MODE, mask_sh),\
213 	TF_SF(CM0_CM_GAMUT_REMAP_CONTROL, CM_GAMUT_REMAP_MODE_CURRENT, mask_sh),\
214 	TF_SF(CM0_CM_GAMUT_REMAP_C11_C12, CM_GAMUT_REMAP_C11, mask_sh),\
215 	TF_SF(CM0_CM_GAMUT_REMAP_C11_C12, CM_GAMUT_REMAP_C12, mask_sh),\
216 	TF_SF(CM0_CM_GAMUT_REMAP_C13_C14, CM_GAMUT_REMAP_C13, mask_sh),\
217 	TF_SF(CM0_CM_GAMUT_REMAP_C13_C14, CM_GAMUT_REMAP_C14, mask_sh),\
218 	TF_SF(CM0_CM_GAMUT_REMAP_C21_C22, CM_GAMUT_REMAP_C21, mask_sh),\
219 	TF_SF(CM0_CM_GAMUT_REMAP_C21_C22, CM_GAMUT_REMAP_C22, mask_sh),\
220 	TF_SF(CM0_CM_GAMUT_REMAP_C23_C24, CM_GAMUT_REMAP_C23, mask_sh),\
221 	TF_SF(CM0_CM_GAMUT_REMAP_C23_C24, CM_GAMUT_REMAP_C24, mask_sh),\
222 	TF_SF(CM0_CM_GAMUT_REMAP_C31_C32, CM_GAMUT_REMAP_C31, mask_sh),\
223 	TF_SF(CM0_CM_GAMUT_REMAP_C31_C32, CM_GAMUT_REMAP_C32, mask_sh),\
224 	TF_SF(CM0_CM_GAMUT_REMAP_C33_C34, CM_GAMUT_REMAP_C33, mask_sh),\
225 	TF_SF(CM0_CM_GAMUT_REMAP_C33_C34, CM_GAMUT_REMAP_C34, mask_sh),\
226 	TF_SF(DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_LEFT, mask_sh),\
227 	TF_SF(DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_RIGHT, mask_sh),\
228 	TF_SF(DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_BOTTOM, mask_sh),\
229 	TF_SF(DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_TOP, mask_sh),\
230 	TF_SF(DSCL0_OTG_H_BLANK, OTG_H_BLANK_START, mask_sh),\
231 	TF_SF(DSCL0_OTG_H_BLANK, OTG_H_BLANK_END, mask_sh),\
232 	TF_SF(DSCL0_OTG_V_BLANK, OTG_V_BLANK_START, mask_sh),\
233 	TF_SF(DSCL0_OTG_V_BLANK, OTG_V_BLANK_END, mask_sh),\
234 	TF_SF(DSCL0_LB_DATA_FORMAT, INTERLEAVE_EN, mask_sh),\
235 	TF2_SF(DSCL0, LB_DATA_FORMAT__ALPHA_EN, mask_sh),\
236 	TF_SF(DSCL0_LB_MEMORY_CTRL, MEMORY_CONFIG, mask_sh),\
237 	TF_SF(DSCL0_LB_MEMORY_CTRL, LB_MAX_PARTITIONS, mask_sh),\
238 	TF_SF(DSCL0_DSCL_AUTOCAL, AUTOCAL_MODE, mask_sh),\
239 	TF_SF(DSCL0_DSCL_AUTOCAL, AUTOCAL_NUM_PIPE, mask_sh),\
240 	TF_SF(DSCL0_DSCL_AUTOCAL, AUTOCAL_PIPE_ID, mask_sh),\
241 	TF_SF(DSCL0_SCL_TAP_CONTROL, SCL_V_NUM_TAPS, mask_sh),\
242 	TF_SF(DSCL0_SCL_TAP_CONTROL, SCL_H_NUM_TAPS, mask_sh),\
243 	TF_SF(DSCL0_SCL_TAP_CONTROL, SCL_V_NUM_TAPS_C, mask_sh),\
244 	TF_SF(DSCL0_SCL_TAP_CONTROL, SCL_H_NUM_TAPS_C, mask_sh),\
245 	TF_SF(DSCL0_SCL_COEF_RAM_TAP_SELECT, SCL_COEF_RAM_TAP_PAIR_IDX, mask_sh),\
246 	TF_SF(DSCL0_SCL_COEF_RAM_TAP_SELECT, SCL_COEF_RAM_PHASE, mask_sh),\
247 	TF_SF(DSCL0_SCL_COEF_RAM_TAP_SELECT, SCL_COEF_RAM_FILTER_TYPE, mask_sh),\
248 	TF_SF(DSCL0_SCL_COEF_RAM_TAP_DATA, SCL_COEF_RAM_EVEN_TAP_COEF, mask_sh),\
249 	TF_SF(DSCL0_SCL_COEF_RAM_TAP_DATA, SCL_COEF_RAM_EVEN_TAP_COEF_EN, mask_sh),\
250 	TF_SF(DSCL0_SCL_COEF_RAM_TAP_DATA, SCL_COEF_RAM_ODD_TAP_COEF, mask_sh),\
251 	TF_SF(DSCL0_SCL_COEF_RAM_TAP_DATA, SCL_COEF_RAM_ODD_TAP_COEF_EN, mask_sh),\
252 	TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_H_2TAP_HARDCODE_COEF_EN, mask_sh),\
253 	TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_H_2TAP_SHARP_EN, mask_sh),\
254 	TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_H_2TAP_SHARP_FACTOR, mask_sh),\
255 	TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_V_2TAP_HARDCODE_COEF_EN, mask_sh),\
256 	TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_V_2TAP_SHARP_EN, mask_sh),\
257 	TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_V_2TAP_SHARP_FACTOR, mask_sh),\
258 	TF_SF(DSCL0_SCL_MODE, SCL_COEF_RAM_SELECT, mask_sh),\
259 	TF_SF(DSCL0_SCL_MODE, DSCL_MODE, mask_sh),\
260 	TF_SF(DSCL0_RECOUT_START, RECOUT_START_X, mask_sh),\
261 	TF_SF(DSCL0_RECOUT_START, RECOUT_START_Y, mask_sh),\
262 	TF_SF(DSCL0_RECOUT_SIZE, RECOUT_WIDTH, mask_sh),\
263 	TF_SF(DSCL0_RECOUT_SIZE, RECOUT_HEIGHT, mask_sh),\
264 	TF_SF(DSCL0_MPC_SIZE, MPC_WIDTH, mask_sh),\
265 	TF_SF(DSCL0_MPC_SIZE, MPC_HEIGHT, mask_sh),\
266 	TF_SF(DSCL0_SCL_HORZ_FILTER_SCALE_RATIO, SCL_H_SCALE_RATIO, mask_sh),\
267 	TF_SF(DSCL0_SCL_VERT_FILTER_SCALE_RATIO, SCL_V_SCALE_RATIO, mask_sh),\
268 	TF_SF(DSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C, SCL_H_SCALE_RATIO_C, mask_sh),\
269 	TF_SF(DSCL0_SCL_VERT_FILTER_SCALE_RATIO_C, SCL_V_SCALE_RATIO_C, mask_sh),\
270 	TF_SF(DSCL0_SCL_HORZ_FILTER_INIT, SCL_H_INIT_FRAC, mask_sh),\
271 	TF_SF(DSCL0_SCL_HORZ_FILTER_INIT, SCL_H_INIT_INT, mask_sh),\
272 	TF_SF(DSCL0_SCL_HORZ_FILTER_INIT_C, SCL_H_INIT_FRAC_C, mask_sh),\
273 	TF_SF(DSCL0_SCL_HORZ_FILTER_INIT_C, SCL_H_INIT_INT_C, mask_sh),\
274 	TF_SF(DSCL0_SCL_VERT_FILTER_INIT, SCL_V_INIT_FRAC, mask_sh),\
275 	TF_SF(DSCL0_SCL_VERT_FILTER_INIT, SCL_V_INIT_INT, mask_sh),\
276 	TF_SF(DSCL0_SCL_VERT_FILTER_INIT_C, SCL_V_INIT_FRAC_C, mask_sh),\
277 	TF_SF(DSCL0_SCL_VERT_FILTER_INIT_C, SCL_V_INIT_INT_C, mask_sh),\
278 	TF_SF(DSCL0_SCL_MODE, SCL_CHROMA_COEF_MODE, mask_sh),\
279 	TF_SF(DSCL0_SCL_MODE, SCL_COEF_RAM_SELECT_CURRENT, mask_sh), \
280 	TF_SF(CNVC_CFG0_PRE_DEALPHA, PRE_DEALPHA_EN, mask_sh), \
281 	TF_SF(CNVC_CFG0_PRE_DEALPHA, PRE_DEALPHA_ABLND_EN, mask_sh), \
282 	TF_SF(CNVC_CFG0_PRE_REALPHA, PRE_REALPHA_EN, mask_sh), \
283 	TF_SF(CNVC_CFG0_PRE_REALPHA, PRE_REALPHA_ABLND_EN, mask_sh), \
284 	TF_SF(CNVC_CFG0_PRE_CSC_MODE, PRE_CSC_MODE, mask_sh), \
285 	TF_SF(CNVC_CFG0_PRE_CSC_MODE, PRE_CSC_MODE_CURRENT, mask_sh), \
286 	TF_SF(CNVC_CFG0_PRE_CSC_C11_C12, PRE_CSC_C11, mask_sh), \
287 	TF_SF(CNVC_CFG0_PRE_CSC_C11_C12, PRE_CSC_C12, mask_sh), \
288 	TF_SF(CNVC_CFG0_PRE_CSC_C33_C34, PRE_CSC_C33, mask_sh), \
289 	TF_SF(CNVC_CFG0_PRE_CSC_C33_C34, PRE_CSC_C34, mask_sh), \
290 	TF_SF(CM0_CM_POST_CSC_CONTROL, CM_POST_CSC_MODE, mask_sh), \
291 	TF_SF(CM0_CM_POST_CSC_CONTROL, CM_POST_CSC_MODE_CURRENT, mask_sh), \
292 	TF_SF(CM0_CM_POST_CSC_C11_C12, CM_POST_CSC_C11, mask_sh), \
293 	TF_SF(CM0_CM_POST_CSC_C11_C12, CM_POST_CSC_C12, mask_sh), \
294 	TF_SF(CM0_CM_POST_CSC_C33_C34, CM_POST_CSC_C33, mask_sh), \
295 	TF_SF(CM0_CM_POST_CSC_C33_C34, CM_POST_CSC_C34, mask_sh), \
296 	TF_SF(CNVC_CFG0_FORMAT_CONTROL, CNVC_BYPASS, mask_sh), \
297 	TF2_SF(CNVC_CFG0, FORMAT_CONTROL__ALPHA_EN, mask_sh), \
298 	TF_SF(CNVC_CFG0_FORMAT_CONTROL, FORMAT_EXPANSION_MODE, mask_sh), \
299 	TF_SF(CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT, CNVC_SURFACE_PIXEL_FORMAT, mask_sh), \
300 	TF_SF(CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT, CNVC_ALPHA_PLANE_ENABLE, mask_sh), \
301 	TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_MODE, mask_sh), \
302 	TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_EXPANSION_MODE, mask_sh), \
303 	TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_ENABLE, mask_sh), \
304 	TF_SF(CNVC_CUR0_CURSOR0_COLOR0, CUR0_COLOR0, mask_sh), \
305 	TF_SF(CNVC_CUR0_CURSOR0_COLOR1, CUR0_COLOR1, mask_sh), \
306 	TF_SF(CNVC_CUR0_CURSOR0_FP_SCALE_BIAS, CUR0_FP_BIAS, mask_sh), \
307 	TF_SF(CNVC_CUR0_CURSOR0_FP_SCALE_BIAS, CUR0_FP_SCALE, mask_sh), \
308 	TF_SF(DPP_TOP0_DPP_CONTROL, DPP_CLOCK_ENABLE, mask_sh), \
309 	TF_SF(CM0_CM_HDR_MULT_COEF, CM_HDR_MULT_COEF, mask_sh), \
310 	TF_SF(CM0_CM_CONTROL, CM_BYPASS, mask_sh), \
311 	TF_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_MODE, mask_sh), \
312 	TF_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_PITCH, mask_sh), \
313 	TF_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_LINES_PER_CHUNK, mask_sh), \
314 	TF_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_ENABLE, mask_sh), \
315 	TF_SF(CNVC_CFG0_FORMAT_CONTROL, FORMAT_CNV16, mask_sh), \
316 	TF_SF(CNVC_CFG0_FORMAT_CONTROL, CNVC_BYPASS_MSB_ALIGN, mask_sh), \
317 	TF_SF(CNVC_CFG0_FORMAT_CONTROL, CLAMP_POSITIVE, mask_sh), \
318 	TF_SF(CNVC_CFG0_FORMAT_CONTROL, CLAMP_POSITIVE_C, mask_sh), \
319 	TF_SF(CNVC_CFG0_FORMAT_CONTROL, FORMAT_CROSSBAR_R, mask_sh), \
320 	TF_SF(CNVC_CFG0_FORMAT_CONTROL, FORMAT_CROSSBAR_G, mask_sh), \
321 	TF_SF(CNVC_CFG0_FORMAT_CONTROL, FORMAT_CROSSBAR_B, mask_sh), \
322 	TF_SF(CNVC_CFG0_ALPHA_2BIT_LUT, ALPHA_2BIT_LUT0, mask_sh), \
323 	TF_SF(CNVC_CFG0_ALPHA_2BIT_LUT, ALPHA_2BIT_LUT1, mask_sh), \
324 	TF_SF(CNVC_CFG0_ALPHA_2BIT_LUT, ALPHA_2BIT_LUT2, mask_sh), \
325 	TF_SF(CNVC_CFG0_ALPHA_2BIT_LUT, ALPHA_2BIT_LUT3, mask_sh), \
326 	TF_SF(CNVC_CFG0_FCNV_FP_BIAS_R, FCNV_FP_BIAS_R, mask_sh), \
327 	TF_SF(CNVC_CFG0_FCNV_FP_BIAS_G, FCNV_FP_BIAS_G, mask_sh), \
328 	TF_SF(CNVC_CFG0_FCNV_FP_BIAS_B, FCNV_FP_BIAS_B, mask_sh), \
329 	TF_SF(CNVC_CFG0_FCNV_FP_SCALE_R, FCNV_FP_SCALE_R, mask_sh), \
330 	TF_SF(CNVC_CFG0_FCNV_FP_SCALE_G, FCNV_FP_SCALE_G, mask_sh), \
331 	TF_SF(CNVC_CFG0_FCNV_FP_SCALE_B, FCNV_FP_SCALE_B, mask_sh), \
332 	TF_SF(CNVC_CFG0_COLOR_KEYER_CONTROL, COLOR_KEYER_EN, mask_sh), \
333 	TF_SF(CNVC_CFG0_COLOR_KEYER_CONTROL, COLOR_KEYER_MODE, mask_sh), \
334 	TF_SF(CNVC_CFG0_COLOR_KEYER_ALPHA, COLOR_KEYER_ALPHA_LOW, mask_sh), \
335 	TF_SF(CNVC_CFG0_COLOR_KEYER_ALPHA, COLOR_KEYER_ALPHA_HIGH, mask_sh), \
336 	TF_SF(CNVC_CFG0_COLOR_KEYER_RED, COLOR_KEYER_RED_LOW, mask_sh), \
337 	TF_SF(CNVC_CFG0_COLOR_KEYER_RED, COLOR_KEYER_RED_HIGH, mask_sh), \
338 	TF_SF(CNVC_CFG0_COLOR_KEYER_GREEN, COLOR_KEYER_GREEN_LOW, mask_sh), \
339 	TF_SF(CNVC_CFG0_COLOR_KEYER_GREEN, COLOR_KEYER_GREEN_HIGH, mask_sh), \
340 	TF_SF(CNVC_CFG0_COLOR_KEYER_BLUE, COLOR_KEYER_BLUE_LOW, mask_sh), \
341 	TF_SF(CNVC_CFG0_COLOR_KEYER_BLUE, COLOR_KEYER_BLUE_HIGH, mask_sh), \
342 	TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_PIX_INV_MODE, mask_sh), \
343 	TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_PIXEL_ALPHA_MOD_EN, mask_sh), \
344 	TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_ROM_EN, mask_sh),\
345 	TF_SF(DSCL0_OBUF_MEM_PWR_CTRL, OBUF_MEM_PWR_FORCE, mask_sh),\
346 	TF_SF(DSCL0_DSCL_MEM_PWR_CTRL, LUT_MEM_PWR_FORCE, mask_sh),\
347 	TF_SF(DSCL0_DSCL_MEM_PWR_STATUS, LUT_MEM_PWR_STATE, mask_sh)
348 
349 #define DPP_REG_LIST_SH_MASK_DCN30_UPDATED(mask_sh)\
350 	TF_SF(CM0_CM_MEM_PWR_STATUS, BLNDGAM_MEM_PWR_STATE, mask_sh), \
351 	TF_SF(CM0_CM_MEM_PWR_CTRL2, HDR3DLUT_MEM_PWR_FORCE, mask_sh),\
352 	TF_SF(CM0_CM_MEM_PWR_CTRL2, SHAPER_MEM_PWR_FORCE, mask_sh),\
353 	TF_SF(CM0_CM_MEM_PWR_STATUS2, HDR3DLUT_MEM_PWR_STATE, mask_sh),\
354 	TF_SF(CM0_CM_MEM_PWR_STATUS2, SHAPER_MEM_PWR_STATE, mask_sh),\
355 	TF_SF(CM0_CM_BLNDGAM_CONTROL, CM_BLNDGAM_MODE, mask_sh), \
356 	TF_SF(CM0_CM_BLNDGAM_CONTROL, CM_BLNDGAM_MODE_CURRENT, mask_sh), \
357 	TF_SF(CM0_CM_BLNDGAM_CONTROL, CM_BLNDGAM_SELECT_CURRENT, mask_sh), \
358 	TF_SF(CM0_CM_BLNDGAM_CONTROL, CM_BLNDGAM_SELECT, mask_sh), \
359 	TF_SF(CM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B, CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_B, mask_sh), \
360 	TF_SF(CM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G, CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_G, mask_sh), \
361 	TF_SF(CM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R, CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_R, mask_sh), \
362 	TF_SF(CM0_CM_BLNDGAM_RAMB_END_CNTL1_B, CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B, mask_sh), \
363 	TF_SF(CM0_CM_BLNDGAM_RAMB_END_CNTL1_G, CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G, mask_sh), \
364 	TF_SF(CM0_CM_BLNDGAM_RAMB_END_CNTL1_R, CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R, mask_sh), \
365 	TF_SF(CM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B, CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_B, mask_sh), \
366 	TF_SF(CM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G, CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_G, mask_sh), \
367 	TF_SF(CM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R, CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_R, mask_sh), \
368 	TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL1_B, CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B, mask_sh), \
369 	TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL1_G, CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G, mask_sh), \
370 	TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL1_R, CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R, mask_sh), \
371 	TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL2_B, CM_BLNDGAM_RAMA_EXP_REGION_END_B, mask_sh), \
372 	TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL2_G, CM_BLNDGAM_RAMA_EXP_REGION_END_G, mask_sh), \
373 	TF_SF(CM0_CM_BLNDGAM_RAMA_END_CNTL2_R, CM_BLNDGAM_RAMA_EXP_REGION_END_R, mask_sh), \
374 	TF_SF(CM0_CM_BLNDGAM_LUT_CONTROL, CM_BLNDGAM_LUT_WRITE_COLOR_MASK, mask_sh), \
375 	TF_SF(CM0_CM_BLNDGAM_LUT_CONTROL, CM_BLNDGAM_LUT_HOST_SEL, mask_sh), \
376 	TF_SF(CM0_CM_BLNDGAM_LUT_CONTROL, CM_BLNDGAM_LUT_CONFIG_MODE, mask_sh), \
377 	TF_SF(CM0_CM_3DLUT_MODE, CM_3DLUT_MODE_CURRENT, mask_sh), \
378 	TF_SF(CM0_CM_SHAPER_CONTROL, CM_SHAPER_MODE_CURRENT, mask_sh)
379 
380 
381 #define DPP_REG_LIST_SH_MASK_DCN30(mask_sh)\
382 	DPP_REG_LIST_SH_MASK_DCN30_COMMON(mask_sh), \
383 	TF_REG_LIST_SH_MASK_DCN20_COMMON(mask_sh), \
384 	DPP_REG_LIST_SH_MASK_DCN30_UPDATED(mask_sh)
385 
386 #define DPP_REG_FIELD_LIST_DCN3(type) \
387 	TF_REG_FIELD_LIST_DCN2_0(type); \
388 	type FORMAT_CROSSBAR_R; \
389 	type FORMAT_CROSSBAR_G; \
390 	type FORMAT_CROSSBAR_B; \
391 	type CM_DEALPHA_EN;\
392 	type CM_DEALPHA_ABLND;\
393 	type CM_BIAS_Y_G;\
394 	type CM_BIAS_CB_B;\
395 	type CM_BIAS_CR_R;\
396 	type GAMCOR_MEM_PWR_DIS; \
397 	type GAMCOR_MEM_PWR_FORCE; \
398 	type HDR3DLUT_MEM_PWR_FORCE; \
399 	type SHAPER_MEM_PWR_FORCE; \
400 	type PRE_DEGAM_MODE;\
401 	type PRE_DEGAM_SELECT;\
402 	type CNVC_ALPHA_PLANE_ENABLE; \
403 	type PRE_DEALPHA_EN; \
404 	type PRE_DEALPHA_ABLND_EN; \
405 	type PRE_REALPHA_EN; \
406 	type PRE_REALPHA_ABLND_EN; \
407 	type PRE_CSC_MODE; \
408 	type PRE_CSC_MODE_CURRENT; \
409 	type PRE_CSC_C11; \
410 	type PRE_CSC_C12; \
411 	type PRE_CSC_C33; \
412 	type PRE_CSC_C34; \
413 	type CM_POST_CSC_MODE; \
414 	type CM_POST_CSC_MODE_CURRENT; \
415 	type CM_POST_CSC_C11; \
416 	type CM_POST_CSC_C12; \
417 	type CM_POST_CSC_C33; \
418 	type CM_POST_CSC_C34; \
419 	type CM_GAMCOR_MODE; \
420 	type CM_GAMCOR_SELECT; \
421 	type CM_GAMCOR_PWL_DISABLE; \
422 	type CM_GAMCOR_MODE_CURRENT; \
423 	type CM_GAMCOR_SELECT_CURRENT; \
424 	type CM_GAMCOR_LUT_INDEX; \
425 	type CM_GAMCOR_LUT_DATA; \
426 	type CM_GAMCOR_LUT_WRITE_COLOR_MASK; \
427 	type CM_GAMCOR_LUT_READ_COLOR_SEL; \
428 	type CM_GAMCOR_LUT_READ_DBG; \
429 	type CM_GAMCOR_LUT_HOST_SEL; \
430 	type CM_GAMCOR_LUT_CONFIG_MODE; \
431 	type CM_GAMCOR_LUT_STATUS; \
432 	type CM_GAMCOR_RAMA_EXP_REGION_START_B; \
433 	type CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B; \
434 	type CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B; \
435 	type CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B; \
436 	type CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B; \
437 	type CM_GAMCOR_RAMA_EXP_REGION_END_B; \
438 	type CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B; \
439 	type CM_GAMCOR_RAMA_OFFSET_B; \
440 	type CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET; \
441 	type CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS; \
442 	type CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET; \
443 	type CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS;\
444 	type CM_GAMUT_REMAP_MODE_CURRENT;\
445 	type CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_B; \
446 	type CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_G; \
447 	type CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_R; \
448 	type CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_B; \
449 	type CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_G; \
450 	type CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_R; \
451 	type CM_BLNDGAM_LUT_WRITE_COLOR_MASK; \
452 	type CM_BLNDGAM_LUT_HOST_SEL; \
453 	type CM_BLNDGAM_LUT_CONFIG_MODE; \
454 	type CM_3DLUT_MODE_CURRENT; \
455 	type CM_SHAPER_MODE_CURRENT; \
456 	type CM_BLNDGAM_MODE; \
457 	type CM_BLNDGAM_MODE_CURRENT; \
458 	type CM_BLNDGAM_SELECT_CURRENT; \
459 	type CM_BLNDGAM_SELECT; \
460 	type GAMCOR_MEM_PWR_STATE; \
461 	type BLNDGAM_MEM_PWR_STATE; \
462 	type HDR3DLUT_MEM_PWR_STATE; \
463 	type SHAPER_MEM_PWR_STATE
464 
465 struct dcn3_dpp_shift {
466 	DPP_REG_FIELD_LIST_DCN3(uint8_t);
467 };
468 
469 struct dcn3_dpp_mask {
470 	DPP_REG_FIELD_LIST_DCN3(uint32_t);
471 };
472 
473 #define DPP_DCN3_REG_VARIABLE_LIST_COMMON \
474 	DPP_DCN2_REG_VARIABLE_LIST; \
475 	uint32_t CM_MEM_PWR_STATUS;\
476 	uint32_t CM_MEM_PWR_STATUS2;\
477 	uint32_t CM_MEM_PWR_CTRL2;\
478 	uint32_t CM_DEALPHA;\
479 	uint32_t CM_BIAS_CR_R;\
480 	uint32_t CM_BIAS_Y_G_CB_B;\
481 	uint32_t PRE_DEGAM;\
482 	uint32_t PRE_DEALPHA; \
483 	uint32_t PRE_REALPHA; \
484 	uint32_t PRE_CSC_MODE; \
485 	uint32_t PRE_CSC_C11_C12; \
486 	uint32_t PRE_CSC_C33_C34; \
487 	uint32_t PRE_CSC_B_C11_C12; \
488 	uint32_t PRE_CSC_B_C33_C34; \
489 	uint32_t CM_POST_CSC_CONTROL; \
490 	uint32_t CM_POST_CSC_C11_C12; \
491 	uint32_t CM_POST_CSC_C33_C34; \
492 	uint32_t CM_POST_CSC_B_C11_C12; \
493 	uint32_t CM_POST_CSC_B_C33_C34; \
494 	uint32_t CM_GAMUT_REMAP_B_C11_C12; \
495 	uint32_t CM_GAMUT_REMAP_B_C13_C14; \
496 	uint32_t CM_GAMUT_REMAP_B_C21_C22; \
497 	uint32_t CM_GAMUT_REMAP_B_C23_C24; \
498 	uint32_t CM_GAMUT_REMAP_B_C31_C32; \
499 	uint32_t CM_GAMUT_REMAP_B_C33_C34; \
500 	uint32_t CM_GAMCOR_CONTROL; \
501 	uint32_t CM_GAMCOR_LUT_CONTROL; \
502 	uint32_t CM_GAMCOR_LUT_INDEX; \
503 	uint32_t CM_GAMCOR_LUT_DATA; \
504 	uint32_t CM_GAMCOR_RAMB_START_CNTL_B; \
505 	uint32_t CM_GAMCOR_RAMB_START_CNTL_G; \
506 	uint32_t CM_GAMCOR_RAMB_START_CNTL_R; \
507 	uint32_t CM_GAMCOR_RAMB_START_SLOPE_CNTL_B; \
508 	uint32_t CM_GAMCOR_RAMB_START_SLOPE_CNTL_G; \
509 	uint32_t CM_GAMCOR_RAMB_START_SLOPE_CNTL_R; \
510 	uint32_t CM_GAMCOR_RAMB_END_CNTL1_B; \
511 	uint32_t CM_GAMCOR_RAMB_END_CNTL2_B; \
512 	uint32_t CM_GAMCOR_RAMB_END_CNTL1_G; \
513 	uint32_t CM_GAMCOR_RAMB_END_CNTL2_G; \
514 	uint32_t CM_GAMCOR_RAMB_END_CNTL1_R; \
515 	uint32_t CM_GAMCOR_RAMB_END_CNTL2_R; \
516 	uint32_t CM_GAMCOR_RAMB_REGION_0_1; \
517 	uint32_t CM_GAMCOR_RAMB_REGION_32_33; \
518 	uint32_t CM_GAMCOR_RAMB_OFFSET_B; \
519 	uint32_t CM_GAMCOR_RAMB_OFFSET_G; \
520 	uint32_t CM_GAMCOR_RAMB_OFFSET_R; \
521 	uint32_t CM_GAMCOR_RAMB_START_BASE_CNTL_B; \
522 	uint32_t CM_GAMCOR_RAMB_START_BASE_CNTL_G; \
523 	uint32_t CM_GAMCOR_RAMB_START_BASE_CNTL_R; \
524 	uint32_t CM_GAMCOR_RAMA_START_CNTL_B; \
525 	uint32_t CM_GAMCOR_RAMA_START_CNTL_G; \
526 	uint32_t CM_GAMCOR_RAMA_START_CNTL_R; \
527 	uint32_t CM_GAMCOR_RAMA_START_SLOPE_CNTL_B; \
528 	uint32_t CM_GAMCOR_RAMA_START_SLOPE_CNTL_G; \
529 	uint32_t CM_GAMCOR_RAMA_START_SLOPE_CNTL_R; \
530 	uint32_t CM_GAMCOR_RAMA_END_CNTL1_B; \
531 	uint32_t CM_GAMCOR_RAMA_END_CNTL2_B; \
532 	uint32_t CM_GAMCOR_RAMA_END_CNTL1_G; \
533 	uint32_t CM_GAMCOR_RAMA_END_CNTL2_G; \
534 	uint32_t CM_GAMCOR_RAMA_END_CNTL1_R; \
535 	uint32_t CM_GAMCOR_RAMA_END_CNTL2_R; \
536 	uint32_t CM_GAMCOR_RAMA_REGION_0_1; \
537 	uint32_t CM_GAMCOR_RAMA_REGION_32_33; \
538 	uint32_t CM_GAMCOR_RAMA_OFFSET_B; \
539 	uint32_t CM_GAMCOR_RAMA_OFFSET_G; \
540 	uint32_t CM_GAMCOR_RAMA_OFFSET_R; \
541 	uint32_t CM_GAMCOR_RAMA_START_BASE_CNTL_B; \
542 	uint32_t CM_GAMCOR_RAMA_START_BASE_CNTL_G; \
543 	uint32_t CM_GAMCOR_RAMA_START_BASE_CNTL_R; \
544 	uint32_t CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B; \
545 	uint32_t CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G; \
546 	uint32_t CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R; \
547 	uint32_t CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B; \
548 	uint32_t CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G; \
549 	uint32_t CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R; \
550 	uint32_t CM_BLNDGAM_LUT_CONTROL
551 
552 
553 struct dcn3_dpp_registers {
554 	DPP_DCN3_REG_VARIABLE_LIST_COMMON;
555 };
556 
557 
558 struct dcn3_dpp {
559 	struct dpp base;
560 
561 	const struct dcn3_dpp_registers *tf_regs;
562 	const struct dcn3_dpp_shift *tf_shift;
563 	const struct dcn3_dpp_mask *tf_mask;
564 
565 	const uint16_t *filter_v;
566 	const uint16_t *filter_h;
567 	const uint16_t *filter_v_c;
568 	const uint16_t *filter_h_c;
569 	int lb_pixel_depth_supported;
570 	int lb_memory_size;
571 	int lb_bits_per_entry;
572 	bool is_write_to_ram_a_safe;
573 	struct scaler_data scl_data;
574 	struct pwl_params pwl_data;
575 };
576 
577 bool dpp3_construct(struct dcn3_dpp *dpp3,
578 	struct dc_context *ctx,
579 	uint32_t inst,
580 	const struct dcn3_dpp_registers *tf_regs,
581 	const struct dcn3_dpp_shift *tf_shift,
582 	const struct dcn3_dpp_mask *tf_mask);
583 
584 bool dpp3_program_gamcor_lut(
585 	struct dpp *dpp_base, const struct pwl_params *params);
586 
587 void dpp3_program_CM_dealpha(
588 		struct dpp *dpp_base,
589 		uint32_t enable, uint32_t additive_blending);
590 
591 void dpp30_read_state(struct dpp *dpp_base,
592 		struct dcn_dpp_state *s);
593 
594 bool dpp3_get_optimal_number_of_taps(
595 		struct dpp *dpp,
596 		struct scaler_data *scl_data,
597 		const struct scaling_taps *in_taps);
598 
599 void dpp3_cnv_setup (
600 		struct dpp *dpp_base,
601 		enum surface_pixel_format format,
602 		enum expansion_mode mode,
603 		struct dc_csc_transform input_csc_color_matrix,
604 		enum dc_color_space input_color_space,
605 		struct cnv_alpha_2bit_lut *alpha_2bit_lut);
606 
607 void dpp3_program_CM_bias(
608 		struct dpp *dpp_base,
609 		struct CM_bias_params *bias_params);
610 
611 void dpp3_set_hdr_multiplier(
612 		struct dpp *dpp_base,
613 		uint32_t multiplier);
614 
615 void dpp3_cm_set_gamut_remap(
616 		struct dpp *dpp_base,
617 		const struct dpp_grph_csc_adjustment *adjust);
618 
619 void dpp3_set_pre_degam(struct dpp *dpp_base,
620 		enum dc_transfer_func_predefined tr);
621 
622 void dpp3_set_cursor_attributes(
623 		struct dpp *dpp_base,
624 		struct dc_cursor_attributes *cursor_attributes);
625 
626 void dpp3_program_post_csc(
627 		struct dpp *dpp_base,
628 		enum dc_color_space color_space,
629 		enum dcn10_input_csc_select input_select,
630 		const struct out_csc_color_matrix *tbl_entry);
631 
632 void dpp3_program_cm_bias(
633 	struct dpp *dpp_base,
634 	struct CM_bias_params *bias_params);
635 
636 void dpp3_program_cm_dealpha(
637 		struct dpp *dpp_base,
638 	uint32_t enable, uint32_t additive_blending);
639 
640 #endif /* __DC_HWSS_DCN30_H__ */
641